Commit 035e0fe5 authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher

drm/amd/display: adding FCLK and DPPCLK clock types

Signed-off-by: default avatarCharlene Liu <charlene.liu@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 00d7930c
...@@ -71,7 +71,9 @@ enum dm_pp_clock_type { ...@@ -71,7 +71,9 @@ enum dm_pp_clock_type {
DM_PP_CLOCK_TYPE_DCFCLK, DM_PP_CLOCK_TYPE_DCFCLK,
DM_PP_CLOCK_TYPE_SOCCLK, DM_PP_CLOCK_TYPE_SOCCLK,
DM_PP_CLOCK_TYPE_PIXELCLK, DM_PP_CLOCK_TYPE_PIXELCLK,
DM_PP_CLOCK_TYPE_DISPLAYPHYCLK DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
DM_PP_CLOCK_TYPE_DPPCLK,
DM_PP_CLOCK_TYPE_FCLK,
}; };
#define DC_DECODE_PP_CLOCK_TYPE(clk_type) \ #define DC_DECODE_PP_CLOCK_TYPE(clk_type) \
......
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