Commit 06823925 authored by Xiaojie Yuan's avatar Xiaojie Yuan Committed by Alex Deucher

drm/amdgpu/sdma5: add placeholder for navi14 golden settings

To be filled in once they are available.
Signed-off-by: default avatarXiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarJack Xiao <Jack.Xiao@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6041f2a2
...@@ -85,6 +85,9 @@ static const struct soc15_reg_golden golden_settings_sdma_5[] = { ...@@ -85,6 +85,9 @@ static const struct soc15_reg_golden golden_settings_sdma_5[] = {
static const struct soc15_reg_golden golden_settings_sdma_nv10[] = { static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
}; };
static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
};
static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
{ {
u32 base; u32 base;
...@@ -114,6 +117,14 @@ static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev) ...@@ -114,6 +117,14 @@ static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_sdma_nv10, golden_settings_sdma_nv10,
(const u32)ARRAY_SIZE(golden_settings_sdma_nv10)); (const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
break; break;
case CHIP_NAVI14:
soc15_program_register_sequence(adev,
golden_settings_sdma_5,
(const u32)ARRAY_SIZE(golden_settings_sdma_5));
soc15_program_register_sequence(adev,
golden_settings_sdma_nv14,
(const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
break;
default: default:
break; break;
} }
......
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