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Commit 077d0b6b authored by David Francis's avatar David Francis Committed by Alex Deucher
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drm/amd/display: Remove i2caux folder 

[Why]
It is huge, unmaintainable, needlessly layered, and obsolete

[How]
Remove it.  All of it.  Also remove the i2caux struct in
dc_context and the code that created and destructed it
Signed-off-by: default avatarDavid Francis <David.Francis@amd.com>
Reviewed-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1877ccf6
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Showing with 4 additions and 5874 deletions
drivers/gpu/drm/amd/display/dc/Makefile
View file @ 077d0b6b
...@@ -23,7 +23,7 @@ ...@@ -23,7 +23,7 @@
# Makefile for Display Core (dc) component. # Makefile for Display Core (dc) component.
# #
DC_LIBS = basics bios calcs dce gpio i2caux irq virtual DC_LIBS = basics bios calcs dce gpio irq virtual
ifdef CONFIG_DRM_AMD_DC_DCN1_0 ifdef CONFIG_DRM_AMD_DC_DCN1_0
DC_LIBS += dcn10 dml DC_LIBS += dcn10 dml
......
drivers/gpu/drm/amd/display/dc/core/dc.c
View file @ 077d0b6b
...@@ -585,9 +585,6 @@ static void destruct(struct dc *dc) ...@@ -585,9 +585,6 @@ static void destruct(struct dc *dc)
if (dc->ctx->gpio_service) if (dc->ctx->gpio_service)
dal_gpio_service_destroy(&dc->ctx->gpio_service); dal_gpio_service_destroy(&dc->ctx->gpio_service);
if (dc->ctx->i2caux)
dal_i2caux_destroy(&dc->ctx->i2caux);
if (dc->ctx->created_bios) if (dc->ctx->created_bios)
dal_bios_parser_destroy(&dc->ctx->dc_bios); dal_bios_parser_destroy(&dc->ctx->dc_bios);
...@@ -709,14 +706,6 @@ static bool construct(struct dc *dc, ...@@ -709,14 +706,6 @@ static bool construct(struct dc *dc,
dc_ctx->created_bios = true; dc_ctx->created_bios = true;
} }
/* Create I2C AUX */
dc_ctx->i2caux = dal_i2caux_create(dc_ctx);
if (!dc_ctx->i2caux) {
ASSERT_CRITICAL(false);
goto fail;
}
dc_ctx->perf_trace = dc_perf_trace_create(); dc_ctx->perf_trace = dc_perf_trace_create();
if (!dc_ctx->perf_trace) { if (!dc_ctx->perf_trace) {
ASSERT_CRITICAL(false); ASSERT_CRITICAL(false);
......
drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
View file @ 077d0b6b
...@@ -33,7 +33,6 @@ ...@@ -33,7 +33,6 @@
#include "include/vector.h" #include "include/vector.h"
#include "core_types.h" #include "core_types.h"
#include "dc_link_ddc.h" #include "dc_link_ddc.h"
#include "aux_engine.h"
#include "dce/dce_aux.h" #include "dce/dce_aux.h"
#define AUX_POWER_UP_WA_DELAY 500 #define AUX_POWER_UP_WA_DELAY 500
......
drivers/gpu/drm/amd/display/dc/dc_types.h
View file @ 077d0b6b
...@@ -97,7 +97,6 @@ struct dc_context { ...@@ -97,7 +97,6 @@ struct dc_context {
struct dc_bios *dc_bios; struct dc_bios *dc_bios;
bool created_bios; bool created_bios;
struct gpio_service *gpio_service; struct gpio_service *gpio_service;
struct i2caux *i2caux;
uint32_t dc_sink_id_count; uint32_t dc_sink_id_count;
uint32_t dc_stream_id_count; uint32_t dc_stream_id_count;
uint64_t fbc_gpu_addr; uint64_t fbc_gpu_addr;
......
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
View file @ 077d0b6b
...@@ -25,7 +25,9 @@ ...@@ -25,7 +25,9 @@
#ifndef __DAL_AUX_ENGINE_DCE110_H__ #ifndef __DAL_AUX_ENGINE_DCE110_H__
#define __DAL_AUX_ENGINE_DCE110_H__ #define __DAL_AUX_ENGINE_DCE110_H__
#include "aux_engine.h"
#include "i2caux_interface.h"
#include "inc/hw/aux_engine.h"
#define AUX_COMMON_REG_LIST(id)\ #define AUX_COMMON_REG_LIST(id)\
SRI(AUX_CONTROL, DP_AUX, id), \ SRI(AUX_CONTROL, DP_AUX, id), \
......
drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c deleted 100644 → 0
View file @ 1877ccf6
This diff is collapsed.
drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h deleted 100644 → 0
View file @ 1877ccf6
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_AUX_ENGINE_H__
#define __DAL_AUX_ENGINE_H__
#include "dc_ddc_types.h"
struct aux_engine;
struct aux_engine_funcs {
void (*destroy)(
struct aux_engine **ptr);
bool (*acquire_engine)(
struct aux_engine *engine);
void (*configure)(
struct aux_engine *engine,
union aux_config cfg);
void (*submit_channel_request)(
struct aux_engine *engine,
struct aux_request_transaction_data *request);
void (*process_channel_reply)(
struct aux_engine *engine,
struct aux_reply_transaction_data *reply);
int (*read_channel_reply)(
struct aux_engine *engine,
uint32_t size,
uint8_t *buffer,
uint8_t *reply_result,
uint32_t *sw_status);
enum aux_channel_operation_result (*get_channel_status)(
struct aux_engine *engine,
uint8_t *returned_bytes);
bool (*is_engine_available) (
struct aux_engine *engine);
};
struct aux_engine {
struct engine base;
const struct aux_engine_funcs *funcs;
/* following values are expressed in milliseconds */
uint32_t delay;
uint32_t max_defer_write_retry;
bool acquire_reset;
};
void dal_aux_engine_construct(
struct aux_engine *engine,
struct dc_context *ctx);
void dal_aux_engine_destruct(
struct aux_engine *engine);
bool dal_aux_engine_submit_request(
struct engine *ptr,
struct i2caux_transaction_request *request,
bool middle_of_transaction);
bool dal_aux_engine_acquire(
struct engine *ptr,
struct ddc *ddc);
enum i2caux_engine_type dal_aux_engine_get_engine_type(
const struct engine *engine);
#endif
drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c deleted 100644 → 0
View file @ 1877ccf6
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "include/i2caux_interface.h"
#include "../i2caux.h"
#include "../engine.h"
#include "../i2c_engine.h"
#include "../i2c_sw_engine.h"
#include "../i2c_hw_engine.h"
#include "../dce110/aux_engine_dce110.h"
#include "../dce110/i2c_hw_engine_dce110.h"
#include "../dce110/i2caux_dce110.h"
#include "dce/dce_10_0_d.h"
#include "dce/dce_10_0_sh_mask.h"
/* set register offset */
#define SR(reg_name)\
.reg_name = mm ## reg_name
/* set register offset with instance */
#define SRI(reg_name, block, id)\
.reg_name = mm ## block ## id ## _ ## reg_name
#define aux_regs(id)\
[id] = {\
AUX_COMMON_REG_LIST(id), \
.AUX_RESET_MASK = 0 \
}
#define hw_engine_regs(id)\
{\
I2C_HW_ENGINE_COMMON_REG_LIST(id) \
}
static const struct dce110_aux_registers dce100_aux_regs[] = {
aux_regs(0),
aux_regs(1),
aux_regs(2),
aux_regs(3),
aux_regs(4),
aux_regs(5),
};
static const struct dce110_i2c_hw_engine_registers dce100_hw_engine_regs[] = {
hw_engine_regs(1),
hw_engine_regs(2),
hw_engine_regs(3),
hw_engine_regs(4),
hw_engine_regs(5),
hw_engine_regs(6)
};
static const struct dce110_i2c_hw_engine_shift i2c_shift = {
I2C_COMMON_MASK_SH_LIST_DCE100(__SHIFT)
};
static const struct dce110_i2c_hw_engine_mask i2c_mask = {
I2C_COMMON_MASK_SH_LIST_DCE100(_MASK)
};
struct i2caux *dal_i2caux_dce100_create(
struct dc_context *ctx)
{
struct i2caux_dce110 *i2caux_dce110 =
kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL);
if (!i2caux_dce110) {
ASSERT_CRITICAL(false);
return NULL;
}
dal_i2caux_dce110_construct(i2caux_dce110,
ctx,
ARRAY_SIZE(dce100_aux_regs),
dce100_aux_regs,
dce100_hw_engine_regs,
&i2c_shift,
&i2c_mask);
return &i2caux_dce110->base;
}
drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.h deleted 100644 → 0
View file @ 1877ccf6
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_I2C_AUX_DCE100_H__
#define __DAL_I2C_AUX_DCE100_H__
struct i2caux *dal_i2caux_dce100_create(
struct dc_context *ctx);
#endif /* __DAL_I2C_AUX_DCE100_H__ */
drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.h deleted 100644 → 0
View file @ 1877ccf6
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_AUX_ENGINE_DCE110_H__
#define __DAL_AUX_ENGINE_DCE110_H__
#include "../aux_engine.h"
#define AUX_COMMON_REG_LIST(id)\
SRI(AUX_CONTROL, DP_AUX, id), \
SRI(AUX_ARB_CONTROL, DP_AUX, id), \
SRI(AUX_SW_DATA, DP_AUX, id), \
SRI(AUX_SW_CONTROL, DP_AUX, id), \
SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \
SRI(AUX_SW_STATUS, DP_AUX, id), \
SR(AUXN_IMPCAL), \
SR(AUXP_IMPCAL)
struct dce110_aux_registers {
uint32_t AUX_CONTROL;
uint32_t AUX_ARB_CONTROL;
uint32_t AUX_SW_DATA;
uint32_t AUX_SW_CONTROL;
uint32_t AUX_INTERRUPT_CONTROL;
uint32_t AUX_SW_STATUS;
uint32_t AUXN_IMPCAL;
uint32_t AUXP_IMPCAL;
uint32_t AUX_RESET_MASK;
};
struct aux_engine_dce110 {
struct aux_engine base;
const struct dce110_aux_registers *regs;
struct {
uint32_t aux_control;
uint32_t aux_arb_control;
uint32_t aux_sw_data;
uint32_t aux_sw_control;
uint32_t aux_interrupt_control;
uint32_t aux_sw_status;
} addr;
uint32_t timeout_period;
};
struct aux_engine_dce110_init_data {
uint32_t engine_id;
uint32_t timeout_period;
struct dc_context *ctx;
const struct dce110_aux_registers *regs;
};
struct aux_engine *dal_aux_engine_dce110_create(
const struct aux_engine_dce110_init_data *aux_init_data);
#endif
drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.h deleted 100644 → 0
View file @ 1877ccf6
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_I2C_HW_ENGINE_DCE110_H__
#define __DAL_I2C_HW_ENGINE_DCE110_H__
#define I2C_HW_ENGINE_COMMON_REG_LIST(id)\
SRI(SETUP, DC_I2C_DDC, id),\
SRI(SPEED, DC_I2C_DDC, id),\
SR(DC_I2C_ARBITRATION),\
SR(DC_I2C_CONTROL),\
SR(DC_I2C_SW_STATUS),\
SR(DC_I2C_TRANSACTION0),\
SR(DC_I2C_TRANSACTION1),\
SR(DC_I2C_TRANSACTION2),\
SR(DC_I2C_TRANSACTION3),\
SR(DC_I2C_DATA),\
SR(MICROSECOND_TIME_BASE_DIV)
#define I2C_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
#define I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\
I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\
I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT, mask_sh),\
I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_EN, mask_sh),\
I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_CLK_DRIVE_EN, mask_sh),\
I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_SEL, mask_sh),\
I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_TRANSACTION_DELAY, mask_sh),\
I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_BYTE_DELAY, mask_sh),\
I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, mask_sh),\
I2C_SF(DC_I2C_ARBITRATION, DC_I2C_NO_QUEUED_SW_GO, mask_sh),\
I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_PRIORITY, mask_sh),\
I2C_SF(DC_I2C_CONTROL, DC_I2C_SOFT_RESET, mask_sh),\
I2C_SF(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, mask_sh),\
I2C_SF(DC_I2C_CONTROL, DC_I2C_GO, mask_sh),\
I2C_SF(DC_I2C_CONTROL, DC_I2C_SEND_RESET, mask_sh),\
I2C_SF(DC_I2C_CONTROL, DC_I2C_TRANSACTION_COUNT, mask_sh),\
I2C_SF(DC_I2C_CONTROL, DC_I2C_DDC_SELECT, mask_sh),\
I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE, mask_sh),\
I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD, mask_sh),\
I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_STOPPED_ON_NACK, mask_sh),\
I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_TIMEOUT, mask_sh),\
I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_ABORTED, mask_sh),\
I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_DONE, mask_sh),\
I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, mask_sh),\
I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_STOP_ON_NACK0, mask_sh),\
I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_START0, mask_sh),\
I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_RW0, mask_sh),\
I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_STOP0, mask_sh),\
I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_COUNT0, mask_sh),\
I2C_SF(DC_I2C_DATA, DC_I2C_DATA_RW, mask_sh),\
I2C_SF(DC_I2C_DATA, DC_I2C_DATA, mask_sh),\
I2C_SF(DC_I2C_DATA, DC_I2C_INDEX, mask_sh),\
I2C_SF(DC_I2C_DATA, DC_I2C_INDEX_WRITE, mask_sh),\
I2C_SF(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, mask_sh)
#define I2C_COMMON_MASK_SH_LIST_DCE100(mask_sh)\
I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)
#define I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh)\
I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_START_STOP_TIMING_CNTL, mask_sh)
struct dce110_i2c_hw_engine_shift {
uint8_t DC_I2C_DDC1_ENABLE;
uint8_t DC_I2C_DDC1_TIME_LIMIT;
uint8_t DC_I2C_DDC1_DATA_DRIVE_EN;
uint8_t DC_I2C_DDC1_CLK_DRIVE_EN;
uint8_t DC_I2C_DDC1_DATA_DRIVE_SEL;
uint8_t DC_I2C_DDC1_INTRA_TRANSACTION_DELAY;
uint8_t DC_I2C_DDC1_INTRA_BYTE_DELAY;
uint8_t DC_I2C_SW_DONE_USING_I2C_REG;
uint8_t DC_I2C_NO_QUEUED_SW_GO;
uint8_t DC_I2C_SW_PRIORITY;
uint8_t DC_I2C_SOFT_RESET;
uint8_t DC_I2C_SW_STATUS_RESET;
uint8_t DC_I2C_GO;
uint8_t DC_I2C_SEND_RESET;
uint8_t DC_I2C_TRANSACTION_COUNT;
uint8_t DC_I2C_DDC_SELECT;
uint8_t DC_I2C_DDC1_PRESCALE;
uint8_t DC_I2C_DDC1_THRESHOLD;
uint8_t DC_I2C_DDC1_START_STOP_TIMING_CNTL;
uint8_t DC_I2C_SW_STOPPED_ON_NACK;
uint8_t DC_I2C_SW_TIMEOUT;
uint8_t DC_I2C_SW_ABORTED;
uint8_t DC_I2C_SW_DONE;
uint8_t DC_I2C_SW_STATUS;
uint8_t DC_I2C_STOP_ON_NACK0;
uint8_t DC_I2C_START0;
uint8_t DC_I2C_RW0;
uint8_t DC_I2C_STOP0;
uint8_t DC_I2C_COUNT0;
uint8_t DC_I2C_DATA_RW;
uint8_t DC_I2C_DATA;
uint8_t DC_I2C_INDEX;
uint8_t DC_I2C_INDEX_WRITE;
uint8_t XTAL_REF_DIV;
};
struct dce110_i2c_hw_engine_mask {
uint32_t DC_I2C_DDC1_ENABLE;
uint32_t DC_I2C_DDC1_TIME_LIMIT;
uint32_t DC_I2C_DDC1_DATA_DRIVE_EN;
uint32_t DC_I2C_DDC1_CLK_DRIVE_EN;
uint32_t DC_I2C_DDC1_DATA_DRIVE_SEL;
uint32_t DC_I2C_DDC1_INTRA_TRANSACTION_DELAY;
uint32_t DC_I2C_DDC1_INTRA_BYTE_DELAY;
uint32_t DC_I2C_SW_DONE_USING_I2C_REG;
uint32_t DC_I2C_NO_QUEUED_SW_GO;
uint32_t DC_I2C_SW_PRIORITY;
uint32_t DC_I2C_SOFT_RESET;
uint32_t DC_I2C_SW_STATUS_RESET;
uint32_t DC_I2C_GO;
uint32_t DC_I2C_SEND_RESET;
uint32_t DC_I2C_TRANSACTION_COUNT;
uint32_t DC_I2C_DDC_SELECT;
uint32_t DC_I2C_DDC1_PRESCALE;
uint32_t DC_I2C_DDC1_THRESHOLD;
uint32_t DC_I2C_DDC1_START_STOP_TIMING_CNTL;
uint32_t DC_I2C_SW_STOPPED_ON_NACK;
uint32_t DC_I2C_SW_TIMEOUT;
uint32_t DC_I2C_SW_ABORTED;
uint32_t DC_I2C_SW_DONE;
uint32_t DC_I2C_SW_STATUS;
uint32_t DC_I2C_STOP_ON_NACK0;
uint32_t DC_I2C_START0;
uint32_t DC_I2C_RW0;
uint32_t DC_I2C_STOP0;
uint32_t DC_I2C_COUNT0;
uint32_t DC_I2C_DATA_RW;
uint32_t DC_I2C_DATA;
uint32_t DC_I2C_INDEX;
uint32_t DC_I2C_INDEX_WRITE;
uint32_t XTAL_REF_DIV;
};
struct dce110_i2c_hw_engine_registers {
uint32_t SETUP;
uint32_t SPEED;
uint32_t DC_I2C_ARBITRATION;
uint32_t DC_I2C_CONTROL;
uint32_t DC_I2C_SW_STATUS;
uint32_t DC_I2C_TRANSACTION0;
uint32_t DC_I2C_TRANSACTION1;
uint32_t DC_I2C_TRANSACTION2;
uint32_t DC_I2C_TRANSACTION3;
uint32_t DC_I2C_DATA;
uint32_t MICROSECOND_TIME_BASE_DIV;
};
struct i2c_hw_engine_dce110 {
struct i2c_hw_engine base;
const struct dce110_i2c_hw_engine_registers *regs;
const struct dce110_i2c_hw_engine_shift *i2c_shift;
const struct dce110_i2c_hw_engine_mask *i2c_mask;
struct {
uint32_t DC_I2C_DDCX_SETUP;
uint32_t DC_I2C_DDCX_SPEED;
} addr;
uint32_t engine_id;
/* expressed in kilohertz */
uint32_t reference_frequency;
/* number of bytes currently used in HW buffer */
uint32_t buffer_used_bytes;
/* number of bytes used for write transaction in HW buffer
* - this will be used as the index to read from*/
uint32_t buffer_used_write;
/* number of pending transactions (before GO) */
uint32_t transaction_count;
uint32_t engine_keep_power_up_count;
uint32_t i2_setup_time_limit;
};
struct i2c_hw_engine_dce110_create_arg {
uint32_t engine_id;
uint32_t reference_frequency;
uint32_t default_speed;
struct dc_context *ctx;
const struct dce110_i2c_hw_engine_registers *regs;
const struct dce110_i2c_hw_engine_shift *i2c_shift;
const struct dce110_i2c_hw_engine_mask *i2c_mask;
};
struct i2c_engine *dal_i2c_hw_engine_dce110_create(
const struct i2c_hw_engine_dce110_create_arg *arg);
enum {
I2C_SETUP_TIME_LIMIT_DCE = 255,
I2C_SETUP_TIME_LIMIT_DCN = 3,
I2C_HW_BUFFER_SIZE = 538,
I2C_SEND_RESET_LENGTH_9 = 9,
I2C_SEND_RESET_LENGTH_10 = 10,
};
#endif
drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c deleted 100644 → 0
View file @ 1877ccf6
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
/*
* Pre-requisites: headers required by header of this unit
*/
#include "include/i2caux_interface.h"
#include "../engine.h"
#include "../i2c_engine.h"
#include "../i2c_sw_engine.h"
/*
* Header of this unit
*/
#include "i2c_sw_engine_dce110.h"
/*
* Post-requisites: headers required by this unit
*/
/*
* This unit
*/
/*
* @brief
* Cast 'struct i2c_sw_engine *'
* to 'struct i2c_sw_engine_dce110 *'
*/
#define FROM_I2C_SW_ENGINE(ptr) \
container_of((ptr), struct i2c_sw_engine_dce110, base)
/*
* @brief
* Cast 'struct i2c_engine *'
* to 'struct i2c_sw_engine_dce80 *'
*/
#define FROM_I2C_ENGINE(ptr) \
FROM_I2C_SW_ENGINE(container_of((ptr), struct i2c_sw_engine, base))
/*
* @brief
* Cast 'struct engine *'
* to 'struct i2c_sw_engine_dce80 *'
*/
#define FROM_ENGINE(ptr) \
FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
static void release_engine(
struct engine *engine)
{
}
static void destruct(
struct i2c_sw_engine_dce110 *engine)
{
dal_i2c_sw_engine_destruct(&engine->base);
}
static void destroy(
struct i2c_engine **engine)
{
struct i2c_sw_engine_dce110 *sw_engine = FROM_I2C_ENGINE(*engine);
destruct(sw_engine);
kfree(sw_engine);
*engine = NULL;
}
static bool acquire_engine(
struct i2c_engine *engine,
struct ddc *ddc_handle)
{
return dal_i2caux_i2c_sw_engine_acquire_engine(engine, ddc_handle);
}
static const struct i2c_engine_funcs i2c_engine_funcs = {
.acquire_engine = acquire_engine,
.destroy = destroy,
.get_speed = dal_i2c_sw_engine_get_speed,
.set_speed = dal_i2c_sw_engine_set_speed,
.setup_engine = dal_i2c_engine_setup_i2c_engine,
.submit_channel_request = dal_i2c_sw_engine_submit_channel_request,
.process_channel_reply = dal_i2c_engine_process_channel_reply,
.get_channel_status = dal_i2c_sw_engine_get_channel_status,
};
static const struct engine_funcs engine_funcs = {
.release_engine = release_engine,
.get_engine_type = dal_i2c_sw_engine_get_engine_type,
.acquire = dal_i2c_engine_acquire,
.submit_request = dal_i2c_sw_engine_submit_request,
};
static void construct(
struct i2c_sw_engine_dce110 *engine_dce110,
const struct i2c_sw_engine_dce110_create_arg *arg_dce110)
{
struct i2c_sw_engine_create_arg arg_base;
arg_base.ctx = arg_dce110->ctx;
arg_base.default_speed = arg_dce110->default_speed;
dal_i2c_sw_engine_construct(&engine_dce110->base, &arg_base);
/*struct engine struct engine_funcs*/
engine_dce110->base.base.base.funcs = &engine_funcs;
/*struct i2c_engine struct i2c_engine_funcs*/
engine_dce110->base.base.funcs = &i2c_engine_funcs;
engine_dce110->base.default_speed = arg_dce110->default_speed;
engine_dce110->engine_id = arg_dce110->engine_id;
}
struct i2c_engine *dal_i2c_sw_engine_dce110_create(
const struct i2c_sw_engine_dce110_create_arg *arg)
{
struct i2c_sw_engine_dce110 *engine_dce110;
if (!arg) {
ASSERT_CRITICAL(false);
return NULL;
}
engine_dce110 = kzalloc(sizeof(struct i2c_sw_engine_dce110),
GFP_KERNEL);
if (!engine_dce110) {
ASSERT_CRITICAL(false);
return NULL;
}
construct(engine_dce110, arg);
return &engine_dce110->base.base;
}
drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.h deleted 100644 → 0
View file @ 1877ccf6
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_I2C_SW_ENGINE_DCE110_H__
#define __DAL_I2C_SW_ENGINE_DCE110_H__
struct i2c_sw_engine_dce110 {
struct i2c_sw_engine base;
uint32_t engine_id;
};
struct i2c_sw_engine_dce110_create_arg {
uint32_t engine_id;
uint32_t default_speed;
struct dc_context *ctx;
};
struct i2c_engine *dal_i2c_sw_engine_dce110_create(
const struct i2c_sw_engine_dce110_create_arg *arg);
#endif
drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c deleted 100644 → 0
View file @ 1877ccf6
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
/*
* Pre-requisites: headers required by header of this unit
*/
#include "include/i2caux_interface.h"
#include "../i2caux.h"
#include "../engine.h"
#include "../i2c_engine.h"
#include "../i2c_sw_engine.h"
#include "../i2c_hw_engine.h"
/*
* Header of this unit
*/
#include "i2caux_dce110.h"
#include "i2c_sw_engine_dce110.h"
#include "i2c_hw_engine_dce110.h"
#include "aux_engine_dce110.h"
#include "../../dc.h"
#include "dc_types.h"
/*
* Post-requisites: headers required by this unit
*/
/*
* This unit
*/
/*cast pointer to struct i2caux TO pointer to struct i2caux_dce110*/
#define FROM_I2C_AUX(ptr) \
container_of((ptr), struct i2caux_dce110, base)
static void destruct(
struct i2caux_dce110 *i2caux_dce110)
{
dal_i2caux_destruct(&i2caux_dce110->base);
}
static void destroy(
struct i2caux **i2c_engine)
{
struct i2caux_dce110 *i2caux_dce110 = FROM_I2C_AUX(*i2c_engine);
destruct(i2caux_dce110);
kfree(i2caux_dce110);
*i2c_engine = NULL;
}
static struct i2c_engine *acquire_i2c_hw_engine(
struct i2caux *i2caux,
struct ddc *ddc)
{
struct i2caux_dce110 *i2caux_dce110 = FROM_I2C_AUX(i2caux);
struct i2c_engine *engine = NULL;
/* generic hw engine is not used for EDID read
* It may be needed for external i2c device, like thermal chip,
* TODO will be implemented when needed.
* check dce80 bool non_generic for generic hw engine;
*/
if (!ddc)
return NULL;
if (ddc->hw_info.hw_supported) {
enum gpio_ddc_line line = dal_ddc_get_line(ddc);
if (line < GPIO_DDC_LINE_COUNT)
engine = i2caux->i2c_hw_engines[line];
}
if (!engine)
return NULL;
if (!i2caux_dce110->i2c_hw_buffer_in_use &&
engine->base.funcs->acquire(&engine->base, ddc)) {
i2caux_dce110->i2c_hw_buffer_in_use = true;
return engine;
}
return NULL;
}
static void release_engine(
struct i2caux *i2caux,
struct engine *engine)
{
struct i2caux_dce110 *i2caux_dce110 = FROM_I2C_AUX(i2caux);
if (engine->funcs->get_engine_type(engine) ==
I2CAUX_ENGINE_TYPE_I2C_DDC_HW)
i2caux_dce110->i2c_hw_buffer_in_use = false;
dal_i2caux_release_engine(i2caux, engine);
}
static const enum gpio_ddc_line hw_ddc_lines[] = {
GPIO_DDC_LINE_DDC1,
GPIO_DDC_LINE_DDC2,
GPIO_DDC_LINE_DDC3,
GPIO_DDC_LINE_DDC4,
GPIO_DDC_LINE_DDC5,
GPIO_DDC_LINE_DDC6,
};
static const enum gpio_ddc_line hw_aux_lines[] = {
GPIO_DDC_LINE_DDC1,
GPIO_DDC_LINE_DDC2,
GPIO_DDC_LINE_DDC3,
GPIO_DDC_LINE_DDC4,
GPIO_DDC_LINE_DDC5,
GPIO_DDC_LINE_DDC6,
};
/* function table */
static const struct i2caux_funcs i2caux_funcs = {
.destroy = destroy,
.acquire_i2c_hw_engine = acquire_i2c_hw_engine,
.release_engine = release_engine,
.acquire_i2c_sw_engine = dal_i2caux_acquire_i2c_sw_engine,
.acquire_aux_engine = dal_i2caux_acquire_aux_engine,
};
#include "dce/dce_11_0_d.h"
#include "dce/dce_11_0_sh_mask.h"
/* set register offset */
#define SR(reg_name)\
.reg_name = mm ## reg_name
/* set register offset with instance */
#define SRI(reg_name, block, id)\
.reg_name = mm ## block ## id ## _ ## reg_name
#define aux_regs(id)\
[id] = {\
AUX_COMMON_REG_LIST(id), \
.AUX_RESET_MASK = AUX_CONTROL__AUX_RESET_MASK \
}
#define hw_engine_regs(id)\
{\
I2C_HW_ENGINE_COMMON_REG_LIST(id) \
}
static const struct dce110_aux_registers dce110_aux_regs[] = {
aux_regs(0),
aux_regs(1),
aux_regs(2),
aux_regs(3),
aux_regs(4),
aux_regs(5)
};
static const struct dce110_i2c_hw_engine_registers i2c_hw_engine_regs[] = {
hw_engine_regs(1),
hw_engine_regs(2),
hw_engine_regs(3),
hw_engine_regs(4),
hw_engine_regs(5),
hw_engine_regs(6)
};
static const struct dce110_i2c_hw_engine_shift i2c_shift = {
I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
};
static const struct dce110_i2c_hw_engine_mask i2c_mask = {
I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
};
void dal_i2caux_dce110_construct(
struct i2caux_dce110 *i2caux_dce110,
struct dc_context *ctx,
unsigned int num_i2caux_inst,
const struct dce110_aux_registers aux_regs[],
const struct dce110_i2c_hw_engine_registers i2c_hw_engine_regs[],
const struct dce110_i2c_hw_engine_shift *i2c_shift,
const struct dce110_i2c_hw_engine_mask *i2c_mask)
{
uint32_t i = 0;
uint32_t reference_frequency = 0;
bool use_i2c_sw_engine = false;
struct i2caux *base = NULL;
/*TODO: For CZ bring up, if dal_i2caux_get_reference_clock
* does not return 48KHz, we need hard coded for 48Khz.
* Some BIOS setting incorrect cause this
* For production, we always get value from BIOS*/
reference_frequency =
dal_i2caux_get_reference_clock(ctx->dc_bios) >> 1;
base = &i2caux_dce110->base;
dal_i2caux_construct(base, ctx);
i2caux_dce110->base.funcs = &i2caux_funcs;
i2caux_dce110->i2c_hw_buffer_in_use = false;
/* Create I2C engines (DDC lines per connector)
* different I2C/AUX usage cases, DDC, Generic GPIO, AUX.
*/
do {
enum gpio_ddc_line line_id = hw_ddc_lines[i];
struct i2c_hw_engine_dce110_create_arg hw_arg_dce110;
if (use_i2c_sw_engine) {
struct i2c_sw_engine_dce110_create_arg sw_arg;
sw_arg.engine_id = i;
sw_arg.default_speed = base->default_i2c_sw_speed;
sw_arg.ctx = ctx;
base->i2c_sw_engines[line_id] =
dal_i2c_sw_engine_dce110_create(&sw_arg);
}
hw_arg_dce110.engine_id = i;
hw_arg_dce110.reference_frequency = reference_frequency;
hw_arg_dce110.default_speed = base->default_i2c_hw_speed;
hw_arg_dce110.ctx = ctx;
hw_arg_dce110.regs = &i2c_hw_engine_regs[i];
hw_arg_dce110.i2c_shift = i2c_shift;
hw_arg_dce110.i2c_mask = i2c_mask;
base->i2c_hw_engines[line_id] =
dal_i2c_hw_engine_dce110_create(&hw_arg_dce110);
if (base->i2c_hw_engines[line_id] != NULL) {
switch (ctx->dce_version) {
case DCN_VERSION_1_0:
base->i2c_hw_engines[line_id]->setup_limit =
I2C_SETUP_TIME_LIMIT_DCN;
base->i2c_hw_engines[line_id]->send_reset_length = 0;
break;
default:
base->i2c_hw_engines[line_id]->setup_limit =
I2C_SETUP_TIME_LIMIT_DCE;
base->i2c_hw_engines[line_id]->send_reset_length = 0;
break;
}
}
++i;
} while (i < num_i2caux_inst);
/* Create AUX engines for all lines which has assisted HW AUX
* 'i' (loop counter) used as DDC/AUX engine_id */
i = 0;
do {
enum gpio_ddc_line line_id = hw_aux_lines[i];
struct aux_engine_dce110_init_data aux_init_data;
aux_init_data.engine_id = i;
aux_init_data.timeout_period = base->aux_timeout_period;
aux_init_data.ctx = ctx;
aux_init_data.regs = &aux_regs[i];
base->aux_engines[line_id] =
dal_aux_engine_dce110_create(&aux_init_data);
++i;
} while (i < num_i2caux_inst);
/*TODO Generic I2C SW and HW*/
}
/*
* dal_i2caux_dce110_create
*
* @brief
* public interface to allocate memory for DCE11 I2CAUX
*
* @param
* struct adapter_service *as - [in]
* struct dc_context *ctx - [in]
*
* @return
* pointer to the base struct of DCE11 I2CAUX
*/
struct i2caux *dal_i2caux_dce110_create(
struct dc_context *ctx)
{
struct i2caux_dce110 *i2caux_dce110 =
kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL);
if (!i2caux_dce110) {
ASSERT_CRITICAL(false);
return NULL;
}
dal_i2caux_dce110_construct(i2caux_dce110,
ctx,
ARRAY_SIZE(dce110_aux_regs),
dce110_aux_regs,
i2c_hw_engine_regs,
&i2c_shift,
&i2c_mask);
return &i2caux_dce110->base;
}
drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.h deleted 100644 → 0
View file @ 1877ccf6
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_I2C_AUX_DCE110_H__
#define __DAL_I2C_AUX_DCE110_H__
#include "../i2caux.h"
struct i2caux_dce110 {
struct i2caux base;
/* indicate the I2C HW circular buffer is in use */
bool i2c_hw_buffer_in_use;
};
struct dce110_aux_registers;
struct dce110_i2c_hw_engine_registers;
struct dce110_i2c_hw_engine_shift;
struct dce110_i2c_hw_engine_mask;
struct i2caux *dal_i2caux_dce110_create(
struct dc_context *ctx);
void dal_i2caux_dce110_construct(
struct i2caux_dce110 *i2caux_dce110,
struct dc_context *ctx,
unsigned int num_i2caux_inst,
const struct dce110_aux_registers *aux_regs,
const struct dce110_i2c_hw_engine_registers *i2c_hw_engine_regs,
const struct dce110_i2c_hw_engine_shift *i2c_shift,
const struct dce110_i2c_hw_engine_mask *i2c_mask);
#endif /* __DAL_I2C_AUX_DCE110_H__ */
drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c deleted 100644 → 0
View file @ 1877ccf6
/*
* Copyright 2012-16 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "include/i2caux_interface.h"
#include "../i2caux.h"
#include "../engine.h"
#include "../i2c_engine.h"
#include "../i2c_sw_engine.h"
#include "../i2c_hw_engine.h"
#include "../dce110/i2c_hw_engine_dce110.h"
#include "../dce110/aux_engine_dce110.h"
#include "../dce110/i2caux_dce110.h"
#include "dce/dce_12_0_offset.h"
#include "dce/dce_12_0_sh_mask.h"
#include "soc15_hw_ip.h"
#include "vega10_ip_offset.h"
/* begin *********************
* macros to expend register list macro defined in HW object header file */
#define BASE_INNER(seg) \
DCE_BASE__INST0_SEG ## seg
/* compile time expand base address. */
#define BASE(seg) \
BASE_INNER(seg)
#define SR(reg_name)\
.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
mm ## reg_name
#define SRI(reg_name, block, id)\
.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
mm ## block ## id ## _ ## reg_name
/* macros to expend register list macro defined in HW object header file
* end *********************/
#define aux_regs(id)\
[id] = {\
AUX_COMMON_REG_LIST(id), \
.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK \
}
static const struct dce110_aux_registers dce120_aux_regs[] = {
aux_regs(0),
aux_regs(1),
aux_regs(2),
aux_regs(3),
aux_regs(4),
aux_regs(5),
};
#define hw_engine_regs(id)\
{\
I2C_HW_ENGINE_COMMON_REG_LIST(id) \
}
static const struct dce110_i2c_hw_engine_registers dce120_hw_engine_regs[] = {
hw_engine_regs(1),
hw_engine_regs(2),
hw_engine_regs(3),
hw_engine_regs(4),
hw_engine_regs(5),
hw_engine_regs(6)
};
static const struct dce110_i2c_hw_engine_shift i2c_shift = {
I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
};
static const struct dce110_i2c_hw_engine_mask i2c_mask = {
I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
};
struct i2caux *dal_i2caux_dce120_create(
struct dc_context *ctx)
{
struct i2caux_dce110 *i2caux_dce110 =
kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL);
if (!i2caux_dce110) {
ASSERT_CRITICAL(false);
return NULL;
}
dal_i2caux_dce110_construct(i2caux_dce110,
ctx,
ARRAY_SIZE(dce120_aux_regs),
dce120_aux_regs,
dce120_hw_engine_regs,
&i2c_shift,
&i2c_mask);
return &i2caux_dce110->base;
}
drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.h deleted 100644 → 0
View file @ 1877ccf6
/*
* Copyright 2012-16 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_I2C_AUX_DCE120_H__
#define __DAL_I2C_AUX_DCE120_H__
struct i2caux *dal_i2caux_dce120_create(
struct dc_context *ctx);
#endif /* __DAL_I2C_AUX_DCE120_H__ */
drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.h deleted 100644 → 0
View file @ 1877ccf6
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_I2C_HW_ENGINE_DCE80_H__
#define __DAL_I2C_HW_ENGINE_DCE80_H__
struct i2c_hw_engine_dce80 {
struct i2c_hw_engine base;
struct {
uint32_t DC_I2C_DDCX_SETUP;
uint32_t DC_I2C_DDCX_SPEED;
} addr;
uint32_t engine_id;
/* expressed in kilohertz */
uint32_t reference_frequency;
/* number of bytes currently used in HW buffer */
uint32_t buffer_used_bytes;
/* number of pending transactions (before GO) */
uint32_t transaction_count;
uint32_t engine_keep_power_up_count;
};
struct i2c_hw_engine_dce80_create_arg {
uint32_t engine_id;
uint32_t reference_frequency;
uint32_t default_speed;
struct dc_context *ctx;
};
struct i2c_engine *dal_i2c_hw_engine_dce80_create(
const struct i2c_hw_engine_dce80_create_arg *arg);
#endif
drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.h deleted 100644 → 0
View file @ 1877ccf6
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_I2C_SW_ENGINE_DCE80_H__
#define __DAL_I2C_SW_ENGINE_DCE80_H__
struct i2c_sw_engine_dce80 {
struct i2c_sw_engine base;
uint32_t engine_id;
};
struct i2c_sw_engine_dce80_create_arg {
uint32_t engine_id;
uint32_t default_speed;
struct dc_context *ctx;
};
struct i2c_engine *dal_i2c_sw_engine_dce80_create(
const struct i2c_sw_engine_dce80_create_arg *arg);
#endif
drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c deleted 100644 → 0
View file @ 1877ccf6
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
/*
* Pre-requisites: headers required by header of this unit
*/
#include "include/i2caux_interface.h"
#include "../i2caux.h"
/*
* Header of this unit
*/
#include "i2caux_dce80.h"
/*
* Post-requisites: headers required by this unit
*/
#include "../engine.h"
#include "../i2c_engine.h"
#include "../i2c_sw_engine.h"
#include "i2c_sw_engine_dce80.h"
#include "../i2c_hw_engine.h"
#include "i2c_hw_engine_dce80.h"
#include "../i2c_generic_hw_engine.h"
#include "../aux_engine.h"
#include "../dce110/aux_engine_dce110.h"
#include "../dce110/i2caux_dce110.h"
#include "dce/dce_8_0_d.h"
#include "dce/dce_8_0_sh_mask.h"
/* set register offset */
#define SR(reg_name)\
.reg_name = mm ## reg_name
/* set register offset with instance */
#define SRI(reg_name, block, id)\
.reg_name = mm ## block ## id ## _ ## reg_name
#define aux_regs(id)\
[id] = {\
AUX_COMMON_REG_LIST(id), \
.AUX_RESET_MASK = 0 \
}
static const struct dce110_aux_registers dce80_aux_regs[] = {
aux_regs(0),
aux_regs(1),
aux_regs(2),
aux_regs(3),
aux_regs(4),
aux_regs(5)
};
/*
* This unit
*/
#define FROM_I2C_AUX(ptr) \
container_of((ptr), struct i2caux_dce80, base)
static void destruct(
struct i2caux_dce80 *i2caux_dce80)
{
dal_i2caux_destruct(&i2caux_dce80->base);
}
static void destroy(
struct i2caux **i2c_engine)
{
struct i2caux_dce80 *i2caux_dce80 = FROM_I2C_AUX(*i2c_engine);
destruct(i2caux_dce80);
kfree(i2caux_dce80);
*i2c_engine = NULL;
}
static struct i2c_engine *acquire_i2c_hw_engine(
struct i2caux *i2caux,
struct ddc *ddc)
{
struct i2caux_dce80 *i2caux_dce80 = FROM_I2C_AUX(i2caux);
struct i2c_engine *engine = NULL;
bool non_generic;
if (!ddc)
return NULL;
if (ddc->hw_info.hw_supported) {
enum gpio_ddc_line line = dal_ddc_get_line(ddc);
if (line < GPIO_DDC_LINE_COUNT) {
non_generic = true;
engine = i2caux->i2c_hw_engines[line];
}
}
if (!engine) {
non_generic = false;
engine = i2caux->i2c_generic_hw_engine;
}
if (!engine)
return NULL;
if (non_generic) {
if (!i2caux_dce80->i2c_hw_buffer_in_use &&
engine->base.funcs->acquire(&engine->base, ddc)) {
i2caux_dce80->i2c_hw_buffer_in_use = true;
return engine;
}
} else {
if (engine->base.funcs->acquire(&engine->base, ddc))
return engine;
}
return NULL;
}
static void release_engine(
struct i2caux *i2caux,
struct engine *engine)
{
if (engine->funcs->get_engine_type(engine) ==
I2CAUX_ENGINE_TYPE_I2C_DDC_HW)
FROM_I2C_AUX(i2caux)->i2c_hw_buffer_in_use = false;
dal_i2caux_release_engine(i2caux, engine);
}
static const enum gpio_ddc_line hw_ddc_lines[] = {
GPIO_DDC_LINE_DDC1,
GPIO_DDC_LINE_DDC2,
GPIO_DDC_LINE_DDC3,
GPIO_DDC_LINE_DDC4,
GPIO_DDC_LINE_DDC5,
GPIO_DDC_LINE_DDC6,
GPIO_DDC_LINE_DDC_VGA
};
static const enum gpio_ddc_line hw_aux_lines[] = {
GPIO_DDC_LINE_DDC1,
GPIO_DDC_LINE_DDC2,
GPIO_DDC_LINE_DDC3,
GPIO_DDC_LINE_DDC4,
GPIO_DDC_LINE_DDC5,
GPIO_DDC_LINE_DDC6
};
static const struct i2caux_funcs i2caux_funcs = {
.destroy = destroy,
.acquire_i2c_hw_engine = acquire_i2c_hw_engine,
.release_engine = release_engine,
.acquire_i2c_sw_engine = dal_i2caux_acquire_i2c_sw_engine,
.acquire_aux_engine = dal_i2caux_acquire_aux_engine,
};
static void construct(
struct i2caux_dce80 *i2caux_dce80,
struct dc_context *ctx)
{
/* Entire family have I2C engine reference clock frequency
* changed from XTALIN (27) to XTALIN/2 (13.5) */
struct i2caux *base = &i2caux_dce80->base;
uint32_t reference_frequency =
dal_i2caux_get_reference_clock(ctx->dc_bios) >> 1;
/*bool use_i2c_sw_engine = dal_adapter_service_is_feature_supported(as,
FEATURE_RESTORE_USAGE_I2C_SW_ENGINE);*/
/* Use SWI2C for dce8 currently, sicne we have bug with hwi2c */
bool use_i2c_sw_engine = true;
uint32_t i;
dal_i2caux_construct(base, ctx);
i2caux_dce80->base.funcs = &i2caux_funcs;
i2caux_dce80->i2c_hw_buffer_in_use = false;
/* Create I2C HW engines (HW + SW pairs)
* for all lines which has assisted HW DDC
* 'i' (loop counter) used as DDC/AUX engine_id */
i = 0;
do {
enum gpio_ddc_line line_id = hw_ddc_lines[i];
struct i2c_hw_engine_dce80_create_arg hw_arg;
if (use_i2c_sw_engine) {
struct i2c_sw_engine_dce80_create_arg sw_arg;
sw_arg.engine_id = i;
sw_arg.default_speed = base->default_i2c_sw_speed;
sw_arg.ctx = ctx;
base->i2c_sw_engines[line_id] =
dal_i2c_sw_engine_dce80_create(&sw_arg);
}
hw_arg.engine_id = i;
hw_arg.reference_frequency = reference_frequency;
hw_arg.default_speed = base->default_i2c_hw_speed;
hw_arg.ctx = ctx;
base->i2c_hw_engines[line_id] =
dal_i2c_hw_engine_dce80_create(&hw_arg);
++i;
} while (i < ARRAY_SIZE(hw_ddc_lines));
/* Create AUX engines for all lines which has assisted HW AUX
* 'i' (loop counter) used as DDC/AUX engine_id */
i = 0;
do {
enum gpio_ddc_line line_id = hw_aux_lines[i];
struct aux_engine_dce110_init_data arg;
arg.engine_id = i;
arg.timeout_period = base->aux_timeout_period;
arg.ctx = ctx;
arg.regs = &dce80_aux_regs[i];
base->aux_engines[line_id] =
dal_aux_engine_dce110_create(&arg);
++i;
} while (i < ARRAY_SIZE(hw_aux_lines));
/* TODO Generic I2C SW and HW */
}
struct i2caux *dal_i2caux_dce80_create(
struct dc_context *ctx)
{
struct i2caux_dce80 *i2caux_dce80 =
kzalloc(sizeof(struct i2caux_dce80), GFP_KERNEL);
if (!i2caux_dce80) {
BREAK_TO_DEBUGGER();
return NULL;
}
construct(i2caux_dce80, ctx);
return &i2caux_dce80->base;
}
drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.h deleted 100644 → 0
View file @ 1877ccf6
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_I2C_AUX_DCE80_H__
#define __DAL_I2C_AUX_DCE80_H__
struct i2caux_dce80 {
struct i2caux base;
/* indicate the I2C HW circular buffer is in use */
bool i2c_hw_buffer_in_use;
};
struct i2caux *dal_i2caux_dce80_create(
struct dc_context *ctx);
#endif
drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c deleted 100644 → 0
View file @ 1877ccf6
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "include/i2caux_interface.h"
#include "../i2caux.h"
#include "../engine.h"
#include "../i2c_engine.h"
#include "../i2c_sw_engine.h"
#include "../i2c_hw_engine.h"
#include "../dce110/aux_engine_dce110.h"
#include "../dce110/i2c_hw_engine_dce110.h"
#include "../dce110/i2caux_dce110.h"
#include "dcn/dcn_1_0_offset.h"
#include "dcn/dcn_1_0_sh_mask.h"
#include "soc15_hw_ip.h"
#include "vega10_ip_offset.h"
/* begin *********************
* macros to expend register list macro defined in HW object header file */
#define BASE_INNER(seg) \
DCE_BASE__INST0_SEG ## seg
/* compile time expand base address. */
#define BASE(seg) \
BASE_INNER(seg)
#define SR(reg_name)\
.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
mm ## reg_name
#define SRI(reg_name, block, id)\
.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
mm ## block ## id ## _ ## reg_name
/* macros to expend register list macro defined in HW object header file
* end *********************/
#define aux_regs(id)\
[id] = {\
AUX_COMMON_REG_LIST(id), \
.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK \
}
#define hw_engine_regs(id)\
{\
I2C_HW_ENGINE_COMMON_REG_LIST(id) \
}
static const struct dce110_aux_registers dcn10_aux_regs[] = {
aux_regs(0),
aux_regs(1),
aux_regs(2),
aux_regs(3),
aux_regs(4),
aux_regs(5),
};
static const struct dce110_i2c_hw_engine_registers dcn10_hw_engine_regs[] = {
hw_engine_regs(1),
hw_engine_regs(2),
hw_engine_regs(3),
hw_engine_regs(4),
hw_engine_regs(5),
hw_engine_regs(6)
};
static const struct dce110_i2c_hw_engine_shift i2c_shift = {
I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
};
static const struct dce110_i2c_hw_engine_mask i2c_mask = {
I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
};
struct i2caux *dal_i2caux_dcn10_create(
struct dc_context *ctx)
{
struct i2caux_dce110 *i2caux_dce110 =
kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL);
if (!i2caux_dce110) {
ASSERT_CRITICAL(false);
return NULL;
}
dal_i2caux_dce110_construct(i2caux_dce110,
ctx,
ARRAY_SIZE(dcn10_aux_regs),
dcn10_aux_regs,
dcn10_hw_engine_regs,
&i2c_shift,
&i2c_mask);
return &i2caux_dce110->base;
}
drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.h deleted 100644 → 0
View file @ 1877ccf6
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_I2C_AUX_DCN10_H__
#define __DAL_I2C_AUX_DCN10_H__
struct i2caux *dal_i2caux_dcn10_create(
struct dc_context *ctx);
#endif /* __DAL_I2C_AUX_DCN10_H__ */
drivers/gpu/drm/amd/display/dc/i2caux/diagnostics/i2caux_diag.c deleted 100644 → 0
View file @ 1877ccf6
/*
* Copyright 2012-16 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
/*
* Pre-requisites: headers required by header of this unit
*/
#include "include/i2caux_interface.h"
#include "../i2caux.h"
#include "../engine.h"
#include "../i2c_engine.h"
#include "../i2c_sw_engine.h"
#include "../i2c_hw_engine.h"
/*
* Header of this unit
*/
#include "i2caux_diag.h"
/*
* Post-requisites: headers required by this unit
*/
/*
* This unit
*/
static void destruct(
struct i2caux *i2caux)
{
dal_i2caux_destruct(i2caux);
}
static void destroy(
struct i2caux **i2c_engine)
{
destruct(*i2c_engine);
kfree(*i2c_engine);
*i2c_engine = NULL;
}
/* function table */
static const struct i2caux_funcs i2caux_funcs = {
.destroy = destroy,
.acquire_i2c_hw_engine = NULL,
.release_engine = NULL,
.acquire_i2c_sw_engine = NULL,
.acquire_aux_engine = NULL,
};
static void construct(
struct i2caux *i2caux,
struct dc_context *ctx)
{
dal_i2caux_construct(i2caux, ctx);
i2caux->funcs = &i2caux_funcs;
}
struct i2caux *dal_i2caux_diag_fpga_create(
struct dc_context *ctx)
{
struct i2caux *i2caux = kzalloc(sizeof(struct i2caux),
GFP_KERNEL);
if (!i2caux) {
ASSERT_CRITICAL(false);
return NULL;
}
construct(i2caux, ctx);
return i2caux;
}
drivers/gpu/drm/amd/display/dc/i2caux/diagnostics/i2caux_diag.h deleted 100644 → 0
View file @ 1877ccf6
/*
* Copyright 2012-16 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_I2C_AUX_DIAG_FPGA_H__
#define __DAL_I2C_AUX_DIAG_FPGA_H__
struct i2caux *dal_i2caux_diag_fpga_create(
struct dc_context *ctx);
#endif /* __DAL_I2C_AUX_DIAG_FPGA_H__ */
drivers/gpu/drm/amd/display/dc/i2caux/engine.h deleted 100644 → 0
View file @ 1877ccf6
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_ENGINE_H__
#define __DAL_ENGINE_H__
#include "dc_ddc_types.h"
enum i2caux_transaction_operation {
I2CAUX_TRANSACTION_READ,
I2CAUX_TRANSACTION_WRITE
};
enum i2caux_transaction_address_space {
I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C = 1,
I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD
};
struct i2caux_transaction_payload {
enum i2caux_transaction_address_space address_space;
uint32_t address;
uint32_t length;
uint8_t *data;
};
enum i2caux_transaction_status {
I2CAUX_TRANSACTION_STATUS_UNKNOWN = (-1L),
I2CAUX_TRANSACTION_STATUS_SUCCEEDED,
I2CAUX_TRANSACTION_STATUS_FAILED_CHANNEL_BUSY,
I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT,
I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR,
I2CAUX_TRANSACTION_STATUS_FAILED_NACK,
I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE,
I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION,
I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION,
I2CAUX_TRANSACTION_STATUS_FAILED_BUFFER_OVERFLOW,
I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON
};
struct i2caux_transaction_request {
enum i2caux_transaction_operation operation;
struct i2caux_transaction_payload payload;
enum i2caux_transaction_status status;
};
enum i2caux_engine_type {
I2CAUX_ENGINE_TYPE_UNKNOWN = (-1L),
I2CAUX_ENGINE_TYPE_AUX,
I2CAUX_ENGINE_TYPE_I2C_DDC_HW,
I2CAUX_ENGINE_TYPE_I2C_GENERIC_HW,
I2CAUX_ENGINE_TYPE_I2C_SW
};
enum i2c_default_speed {
I2CAUX_DEFAULT_I2C_HW_SPEED = 50,
I2CAUX_DEFAULT_I2C_SW_SPEED = 50
};
struct engine;
struct engine_funcs {
enum i2caux_engine_type (*get_engine_type)(
const struct engine *engine);
bool (*acquire)(
struct engine *engine,
struct ddc *ddc);
bool (*submit_request)(
struct engine *engine,
struct i2caux_transaction_request *request,
bool middle_of_transaction);
void (*release_engine)(
struct engine *engine);
};
struct engine {
const struct engine_funcs *funcs;
uint32_t inst;
struct ddc *ddc;
struct dc_context *ctx;
};
void dal_i2caux_construct_engine(
struct engine *engine,
struct dc_context *ctx);
void dal_i2caux_destruct_engine(
struct engine *engine);
#endif
drivers/gpu/drm/amd/display/dc/i2caux/engine_base.c deleted 100644 → 0
View file @ 1877ccf6
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
/*
* Pre-requisites: headers required by header of this unit
*/
#include "include/i2caux_interface.h"
/*
* Header of this unit
*/
#include "engine.h"
void dal_i2caux_construct_engine(
struct engine *engine,
struct dc_context *ctx)
{
engine->ddc = NULL;
engine->ctx = ctx;
}
void dal_i2caux_destruct_engine(
struct engine *engine)
{
/* nothing to do */
}
drivers/gpu/drm/amd/display/dc/i2caux/i2c_engine.c deleted 100644 → 0
View file @ 1877ccf6
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
/*
* Pre-requisites: headers required by header of this unit
*/
#include "include/i2caux_interface.h"
#include "engine.h"
/*
* Header of this unit
*/
#include "i2c_engine.h"
/*
* Post-requisites: headers required by this unit
*/
/*
* This unit
*/
#define FROM_ENGINE(ptr) \
container_of((ptr), struct i2c_engine, base)
bool dal_i2c_engine_acquire(
struct engine *engine,
struct ddc *ddc_handle)
{
struct i2c_engine *i2c_engine = FROM_ENGINE(engine);
uint32_t counter = 0;
bool result;
do {
result = i2c_engine->funcs->acquire_engine(
i2c_engine, ddc_handle);
if (result)
break;
/* i2c_engine is busy by VBios, lets wait and retry */
udelay(10);
++counter;
} while (counter < 2);
if (result) {
if (!i2c_engine->funcs->setup_engine(i2c_engine)) {
engine->funcs->release_engine(engine);
result = false;
}
}
return result;
}
bool dal_i2c_engine_setup_i2c_engine(
struct i2c_engine *engine)
{
/* Derivative classes do not have to override this */
return true;
}
void dal_i2c_engine_submit_channel_request(
struct i2c_engine *engine,
struct i2c_request_transaction_data *request)
{
}
void dal_i2c_engine_process_channel_reply(
struct i2c_engine *engine,
struct i2c_reply_transaction_data *reply)
{
}
void dal_i2c_engine_construct(
struct i2c_engine *engine,
struct dc_context *ctx)
{
dal_i2caux_construct_engine(&engine->base, ctx);
engine->timeout_delay = 0;
}
void dal_i2c_engine_destruct(
struct i2c_engine *engine)
{
dal_i2caux_destruct_engine(&engine->base);
}
drivers/gpu/drm/amd/display/dc/i2caux/i2c_engine.h deleted 100644 → 0
View file @ 1877ccf6
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_I2C_ENGINE_H__
#define __DAL_I2C_ENGINE_H__
enum i2c_channel_operation_result {
I2C_CHANNEL_OPERATION_SUCCEEDED,
I2C_CHANNEL_OPERATION_FAILED,
I2C_CHANNEL_OPERATION_NOT_GRANTED,
I2C_CHANNEL_OPERATION_IS_BUSY,
I2C_CHANNEL_OPERATION_NO_HANDLE_PROVIDED,
I2C_CHANNEL_OPERATION_CHANNEL_IN_USE,
I2C_CHANNEL_OPERATION_CHANNEL_CLIENT_MAX_ALLOWED,
I2C_CHANNEL_OPERATION_ENGINE_BUSY,
I2C_CHANNEL_OPERATION_TIMEOUT,
I2C_CHANNEL_OPERATION_NO_RESPONSE,
I2C_CHANNEL_OPERATION_HW_REQUEST_I2C_BUS,
I2C_CHANNEL_OPERATION_WRONG_PARAMETER,
I2C_CHANNEL_OPERATION_OUT_NB_OF_RETRIES,
I2C_CHANNEL_OPERATION_NOT_STARTED
};
struct i2c_request_transaction_data {
enum i2caux_transaction_action action;
enum i2c_channel_operation_result status;
uint8_t address;
uint32_t length;
uint8_t *data;
};
struct i2c_reply_transaction_data {
uint32_t length;
uint8_t *data;
};
struct i2c_engine;
struct i2c_engine_funcs {
void (*destroy)(
struct i2c_engine **ptr);
uint32_t (*get_speed)(
const struct i2c_engine *engine);
void (*set_speed)(
struct i2c_engine *engine,
uint32_t speed);
bool (*acquire_engine)(
struct i2c_engine *engine,
struct ddc *ddc);
bool (*setup_engine)(
struct i2c_engine *engine);
void (*submit_channel_request)(
struct i2c_engine *engine,
struct i2c_request_transaction_data *request);
void (*process_channel_reply)(
struct i2c_engine *engine,
struct i2c_reply_transaction_data *reply);
enum i2c_channel_operation_result (*get_channel_status)(
struct i2c_engine *engine,
uint8_t *returned_bytes);
};
struct i2c_engine {
struct engine base;
const struct i2c_engine_funcs *funcs;
uint32_t timeout_delay;
uint32_t setup_limit;
uint32_t send_reset_length;
};
void dal_i2c_engine_construct(
struct i2c_engine *engine,
struct dc_context *ctx);
void dal_i2c_engine_destruct(
struct i2c_engine *engine);
bool dal_i2c_engine_setup_i2c_engine(
struct i2c_engine *engine);
void dal_i2c_engine_submit_channel_request(
struct i2c_engine *engine,
struct i2c_request_transaction_data *request);
void dal_i2c_engine_process_channel_reply(
struct i2c_engine *engine,
struct i2c_reply_transaction_data *reply);
bool dal_i2c_engine_acquire(
struct engine *ptr,
struct ddc *ddc_handle);
#endif
drivers/gpu/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.c deleted 100644 → 0
View file @ 1877ccf6
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
/*
* Pre-requisites: headers required by header of this unit
*/
#include "include/i2caux_interface.h"
#include "engine.h"
#include "i2c_engine.h"
#include "i2c_hw_engine.h"
/*
* Header of this unit
*/
#include "i2c_generic_hw_engine.h"
/*
* Post-requisites: headers required by this unit
*/
/*
* This unit
*/
/*
* @brief
* Cast 'struct i2c_hw_engine *'
* to 'struct i2c_generic_hw_engine *'
*/
#define FROM_I2C_HW_ENGINE(ptr) \
container_of((ptr), struct i2c_generic_hw_engine, base)
/*
* @brief
* Cast 'struct i2c_engine *'
* to 'struct i2c_generic_hw_engine *'
*/
#define FROM_I2C_ENGINE(ptr) \
FROM_I2C_HW_ENGINE(container_of((ptr), struct i2c_hw_engine, base))
/*
* @brief
* Cast 'struct engine *'
* to 'struct i2c_generic_hw_engine *'
*/
#define FROM_ENGINE(ptr) \
FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
enum i2caux_engine_type dal_i2c_generic_hw_engine_get_engine_type(
const struct engine *engine)
{
return I2CAUX_ENGINE_TYPE_I2C_GENERIC_HW;
}
/*
* @brief
* Single transaction handling.
* Since transaction may be bigger than HW buffer size,
* it divides transaction to sub-transactions
* and uses batch transaction feature of the engine.
*/
bool dal_i2c_generic_hw_engine_submit_request(
struct engine *engine,
struct i2caux_transaction_request *i2caux_request,
bool middle_of_transaction)
{
struct i2c_generic_hw_engine *hw_engine = FROM_ENGINE(engine);
struct i2c_hw_engine *base = &hw_engine->base;
uint32_t max_payload_size =
base->funcs->get_hw_buffer_available_size(base);
bool initial_stop_bit = !middle_of_transaction;
struct i2c_generic_transaction_attributes attributes;
enum i2c_channel_operation_result operation_result =
I2C_CHANNEL_OPERATION_FAILED;
bool result = false;
/* setup transaction initial properties */
uint8_t address = i2caux_request->payload.address;
uint8_t *current_payload = i2caux_request->payload.data;
uint32_t remaining_payload_size = i2caux_request->payload.length;
bool first_iteration = true;
if (i2caux_request->operation == I2CAUX_TRANSACTION_READ)
attributes.action = I2CAUX_TRANSACTION_ACTION_I2C_READ;
else if (i2caux_request->operation == I2CAUX_TRANSACTION_WRITE)
attributes.action = I2CAUX_TRANSACTION_ACTION_I2C_WRITE;
else {
i2caux_request->status =
I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION;
return false;
}
/* Do batch transaction.
* Divide read/write data into payloads which fit HW buffer size.
* 1. Single transaction:
* start_bit = 1, stop_bit depends on session state, ack_on_read = 0;
* 2. Start of batch transaction:
* start_bit = 1, stop_bit = 0, ack_on_read = 1;
* 3. Middle of batch transaction:
* start_bit = 0, stop_bit = 0, ack_on_read = 1;
* 4. End of batch transaction:
* start_bit = 0, stop_bit depends on session state, ack_on_read = 0.
* Session stop bit is set if 'middle_of_transaction' = 0. */
while (remaining_payload_size) {
uint32_t current_transaction_size;
uint32_t current_payload_size;
bool last_iteration;
bool stop_bit;
/* Calculate current transaction size and payload size.
* Transaction size = total number of bytes in transaction,
* including slave's address;
* Payload size = number of data bytes in transaction. */
if (first_iteration) {
/* In the first sub-transaction we send slave's address
* thus we need to reserve one byte for it */
current_transaction_size =
(remaining_payload_size > max_payload_size - 1) ?
max_payload_size :
remaining_payload_size + 1;
current_payload_size = current_transaction_size - 1;
} else {
/* Second and further sub-transactions will have
* entire buffer reserved for data */
current_transaction_size =
(remaining_payload_size > max_payload_size) ?
max_payload_size :
remaining_payload_size;
current_payload_size = current_transaction_size;
}
last_iteration =
(remaining_payload_size == current_payload_size);
stop_bit = last_iteration ? initial_stop_bit : false;
/* write slave device address */
if (first_iteration)
hw_engine->funcs->write_address(hw_engine, address);
/* write current portion of data, if requested */
if (i2caux_request->operation == I2CAUX_TRANSACTION_WRITE)
hw_engine->funcs->write_data(
hw_engine,
current_payload,
current_payload_size);
/* execute transaction */
attributes.start_bit = first_iteration;
attributes.stop_bit = stop_bit;
attributes.last_read = last_iteration;
attributes.transaction_size = current_transaction_size;
hw_engine->funcs->execute_transaction(hw_engine, &attributes);
/* wait until transaction is processed; if it fails - quit */
operation_result = base->funcs->wait_on_operation_result(
base,
base->funcs->get_transaction_timeout(
base, current_transaction_size),
I2C_CHANNEL_OPERATION_ENGINE_BUSY);
if (operation_result != I2C_CHANNEL_OPERATION_SUCCEEDED)
break;
/* read current portion of data, if requested */
/* the read offset should be 1 for first sub-transaction,
* and 0 for any next one */
if (i2caux_request->operation == I2CAUX_TRANSACTION_READ)
hw_engine->funcs->read_data(hw_engine, current_payload,
current_payload_size, first_iteration ? 1 : 0);
/* update loop variables */
first_iteration = false;
current_payload += current_payload_size;
remaining_payload_size -= current_payload_size;
}
/* update transaction status */
switch (operation_result) {
case I2C_CHANNEL_OPERATION_SUCCEEDED:
i2caux_request->status =
I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
result = true;
break;
case I2C_CHANNEL_OPERATION_NO_RESPONSE:
i2caux_request->status =
I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
break;
case I2C_CHANNEL_OPERATION_TIMEOUT:
i2caux_request->status =
I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
break;
case I2C_CHANNEL_OPERATION_FAILED:
i2caux_request->status =
I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE;
break;
default:
i2caux_request->status =
I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION;
}
return result;
}
/*
* @brief
* Returns number of microseconds to wait until timeout to be considered
*/
uint32_t dal_i2c_generic_hw_engine_get_transaction_timeout(
const struct i2c_hw_engine *engine,
uint32_t length)
{
const struct i2c_engine *base = &engine->base;
uint32_t speed = base->funcs->get_speed(base);
if (!speed)
return 0;
/* total timeout = period_timeout * (start + data bits count + stop) */
return ((1000 * TRANSACTION_TIMEOUT_IN_I2C_CLOCKS) / speed) *
(1 + (length << 3) + 1);
}
void dal_i2c_generic_hw_engine_construct(
struct i2c_generic_hw_engine *engine,
struct dc_context *ctx)
{
dal_i2c_hw_engine_construct(&engine->base, ctx);
}
void dal_i2c_generic_hw_engine_destruct(
struct i2c_generic_hw_engine *engine)
{
dal_i2c_hw_engine_destruct(&engine->base);
}
drivers/gpu/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.h deleted 100644 → 0
View file @ 1877ccf6
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_I2C_GENERIC_HW_ENGINE_H__
#define __DAL_I2C_GENERIC_HW_ENGINE_H__
struct i2c_generic_transaction_attributes {
enum i2caux_transaction_action action;
uint32_t transaction_size;
bool start_bit;
bool stop_bit;
bool last_read;
};
struct i2c_generic_hw_engine;
struct i2c_generic_hw_engine_funcs {
void (*write_address)(
struct i2c_generic_hw_engine *engine,
uint8_t address);
void (*write_data)(
struct i2c_generic_hw_engine *engine,
const uint8_t *buffer,
uint32_t length);
void (*read_data)(
struct i2c_generic_hw_engine *engine,
uint8_t *buffer,
uint32_t length,
uint32_t offset);
void (*execute_transaction)(
struct i2c_generic_hw_engine *engine,
struct i2c_generic_transaction_attributes *attributes);
};
struct i2c_generic_hw_engine {
struct i2c_hw_engine base;
const struct i2c_generic_hw_engine_funcs *funcs;
};
void dal_i2c_generic_hw_engine_construct(
struct i2c_generic_hw_engine *engine,
struct dc_context *ctx);
void dal_i2c_generic_hw_engine_destruct(
struct i2c_generic_hw_engine *engine);
enum i2caux_engine_type dal_i2c_generic_hw_engine_get_engine_type(
const struct engine *engine);
bool dal_i2c_generic_hw_engine_submit_request(
struct engine *ptr,
struct i2caux_transaction_request *i2caux_request,
bool middle_of_transaction);
uint32_t dal_i2c_generic_hw_engine_get_transaction_timeout(
const struct i2c_hw_engine *engine,
uint32_t length);
#endif
drivers/gpu/drm/amd/display/dc/i2caux/i2c_hw_engine.c deleted 100644 → 0
View file @ 1877ccf6
This diff is collapsed.
drivers/gpu/drm/amd/display/dc/i2caux/i2c_hw_engine.h deleted 100644 → 0
View file @ 1877ccf6
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_I2C_HW_ENGINE_H__
#define __DAL_I2C_HW_ENGINE_H__
enum {
TRANSACTION_TIMEOUT_IN_I2C_CLOCKS = 32
};
struct i2c_hw_engine;
struct i2c_hw_engine_funcs {
uint32_t (*get_hw_buffer_available_size)(
const struct i2c_hw_engine *engine);
enum i2c_channel_operation_result (*wait_on_operation_result)(
struct i2c_hw_engine *engine,
uint32_t timeout,
enum i2c_channel_operation_result expected_result);
uint32_t (*get_transaction_timeout)(
const struct i2c_hw_engine *engine,
uint32_t length);
};
struct i2c_hw_engine {
struct i2c_engine base;
const struct i2c_hw_engine_funcs *funcs;
/* Values below are in kilohertz */
uint32_t original_speed;
uint32_t default_speed;
};
void dal_i2c_hw_engine_construct(
struct i2c_hw_engine *engine,
struct dc_context *ctx);
void dal_i2c_hw_engine_destruct(
struct i2c_hw_engine *engine);
enum i2c_channel_operation_result dal_i2c_hw_engine_wait_on_operation_result(
struct i2c_hw_engine *engine,
uint32_t timeout,
enum i2c_channel_operation_result expected_result);
bool dal_i2c_hw_engine_acquire_engine(
struct i2c_engine *engine,
struct ddc *ddc);
bool dal_i2c_hw_engine_submit_request(
struct engine *ptr,
struct i2caux_transaction_request *i2caux_request,
bool middle_of_transaction);
enum i2caux_engine_type dal_i2c_hw_engine_get_engine_type(
const struct engine *engine);
#endif
drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c deleted 100644 → 0
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drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.h deleted 100644 → 0
View file @ 1877ccf6
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_I2C_SW_ENGINE_H__
#define __DAL_I2C_SW_ENGINE_H__
enum {
I2C_SW_RETRIES = 10,
I2C_SW_SCL_READ_RETRIES = 128,
/* following value is in microseconds */
I2C_SW_TIMEOUT_DELAY = 3000
};
struct i2c_sw_engine;
struct i2c_sw_engine {
struct i2c_engine base;
uint32_t clock_delay;
/* Values below are in KHz */
uint32_t speed;
uint32_t default_speed;
};
struct i2c_sw_engine_create_arg {
uint32_t default_speed;
struct dc_context *ctx;
};
void dal_i2c_sw_engine_construct(
struct i2c_sw_engine *engine,
const struct i2c_sw_engine_create_arg *arg);
bool dal_i2caux_i2c_sw_engine_acquire_engine(
struct i2c_engine *engine,
struct ddc *ddc_handle);
void dal_i2c_sw_engine_destruct(
struct i2c_sw_engine *engine);
struct i2c_engine *dal_i2c_sw_engine_create(
const struct i2c_sw_engine_create_arg *arg);
enum i2caux_engine_type dal_i2c_sw_engine_get_engine_type(
const struct engine *engine);
bool dal_i2c_sw_engine_submit_request(
struct engine *ptr,
struct i2caux_transaction_request *i2caux_request,
bool middle_of_transaction);
uint32_t dal_i2c_sw_engine_get_speed(
const struct i2c_engine *engine);
void dal_i2c_sw_engine_set_speed(
struct i2c_engine *ptr,
uint32_t speed);
void dal_i2c_sw_engine_submit_channel_request(
struct i2c_engine *ptr,
struct i2c_request_transaction_data *req);
enum i2c_channel_operation_result dal_i2c_sw_engine_get_channel_status(
struct i2c_engine *engine,
uint8_t *returned_bytes);
#endif
drivers/gpu/drm/amd/display/dc/i2caux/i2caux.h deleted 100644 → 0
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drivers/gpu/drm/amd/display/include/i2caux_interface.h
View file @ 077d0b6b
...@@ -76,27 +76,4 @@ union aux_config { ...@@ -76,27 +76,4 @@ union aux_config {
uint32_t raw; uint32_t raw;
}; };
struct i2caux;
struct i2caux *dal_i2caux_create(
struct dc_context *ctx);
bool dal_i2caux_submit_i2c_command(
struct i2caux *i2caux,
struct ddc *ddc,
struct i2c_command *cmd);
bool dal_i2caux_submit_aux_command(
struct i2caux *i2caux,
struct ddc *ddc,
struct aux_command *cmd);
void dal_i2caux_configure_aux(
struct i2caux *i2caux,
struct ddc *ddc,
union aux_config cfg);
void dal_i2caux_destroy(
struct i2caux **ptr);
#endif #endif
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