Commit 098e51e5 authored by Pascal van Leeuwen's avatar Pascal van Leeuwen Committed by Herbert Xu

crypto: inside-secure - Fix Unable to fit even 1 command desc error w/ EIP97

Due to the additions of support for modes like AES-CCM and AES-GCM, which
require large command tokens, the size of the descriptor has grown such that
it now does not fit into the descriptor cache of a standard EIP97 anymore.
This means that the driver no longer works on the Marvell Armada 3700LP chip
(as used on e.g. Espressobin) that it has always supported.
Additionally, performance on EIP197's like Marvell A8K may also degrade
due to being able to fit less descriptors in the on-chip cache.
Putting these tokens into the descriptor was really a hack and not how the
design was supposed to be used - resource allocation did not account for it.

So what this patch does, is move the command token out of the descriptor.
To avoid having to allocate buffers on the fly for these command tokens,
they are stuffed in a "shadow ring", which is a circular buffer of fixed
size blocks that runs in lock-step with the descriptor ring. i.e. there is
one token block per descriptor. The descriptor ring itself is then pre-
populated with the pointers to these token blocks so these do not need to
be filled in when building the descriptors later.
Signed-off-by: default avatarPascal van Leeuwen <pvanleeuwen@rambus.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent a3063762
...@@ -501,8 +501,8 @@ static int safexcel_hw_setup_cdesc_rings(struct safexcel_crypto_priv *priv) ...@@ -501,8 +501,8 @@ static int safexcel_hw_setup_cdesc_rings(struct safexcel_crypto_priv *priv)
writel(upper_32_bits(priv->ring[i].cdr.base_dma), writel(upper_32_bits(priv->ring[i].cdr.base_dma),
EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_RING_BASE_ADDR_HI); EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_RING_BASE_ADDR_HI);
writel(EIP197_xDR_DESC_MODE_64BIT | (priv->config.cd_offset << 14) | writel(EIP197_xDR_DESC_MODE_64BIT | EIP197_CDR_DESC_MODE_ADCP |
priv->config.cd_size, (priv->config.cd_offset << 14) | priv->config.cd_size,
EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_DESC_SIZE); EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_DESC_SIZE);
writel(((cd_fetch_cnt * writel(((cd_fetch_cnt *
(cd_size_rnd << priv->hwconfig.hwdataw)) << 16) | (cd_size_rnd << priv->hwconfig.hwdataw)) << 16) |
...@@ -974,16 +974,18 @@ int safexcel_invalidate_cache(struct crypto_async_request *async, ...@@ -974,16 +974,18 @@ int safexcel_invalidate_cache(struct crypto_async_request *async,
{ {
struct safexcel_command_desc *cdesc; struct safexcel_command_desc *cdesc;
struct safexcel_result_desc *rdesc; struct safexcel_result_desc *rdesc;
struct safexcel_token *dmmy;
int ret = 0; int ret = 0;
/* Prepare command descriptor */ /* Prepare command descriptor */
cdesc = safexcel_add_cdesc(priv, ring, true, true, 0, 0, 0, ctxr_dma); cdesc = safexcel_add_cdesc(priv, ring, true, true, 0, 0, 0, ctxr_dma,
&dmmy);
if (IS_ERR(cdesc)) if (IS_ERR(cdesc))
return PTR_ERR(cdesc); return PTR_ERR(cdesc);
cdesc->control_data.type = EIP197_TYPE_EXTENDED; cdesc->control_data.type = EIP197_TYPE_EXTENDED;
cdesc->control_data.options = 0; cdesc->control_data.options = 0;
cdesc->control_data.refresh = 0; cdesc->control_data.context_lo &= ~EIP197_CONTEXT_SIZE_MASK;
cdesc->control_data.control0 = CONTEXT_CONTROL_INV_TR; cdesc->control_data.control0 = CONTEXT_CONTROL_INV_TR;
/* Prepare result descriptor */ /* Prepare result descriptor */
...@@ -1331,6 +1333,7 @@ static void safexcel_configure(struct safexcel_crypto_priv *priv) ...@@ -1331,6 +1333,7 @@ static void safexcel_configure(struct safexcel_crypto_priv *priv)
priv->config.cd_size = EIP197_CD64_FETCH_SIZE; priv->config.cd_size = EIP197_CD64_FETCH_SIZE;
priv->config.cd_offset = (priv->config.cd_size + mask) & ~mask; priv->config.cd_offset = (priv->config.cd_size + mask) & ~mask;
priv->config.cdsh_offset = (EIP197_MAX_TOKENS + mask) & ~mask;
/* res token is behind the descr, but ofs must be rounded to buswdth */ /* res token is behind the descr, but ofs must be rounded to buswdth */
priv->config.res_offset = (EIP197_RD64_FETCH_SIZE + mask) & ~mask; priv->config.res_offset = (EIP197_RD64_FETCH_SIZE + mask) & ~mask;
...@@ -1341,6 +1344,7 @@ static void safexcel_configure(struct safexcel_crypto_priv *priv) ...@@ -1341,6 +1344,7 @@ static void safexcel_configure(struct safexcel_crypto_priv *priv)
/* convert dwords to bytes */ /* convert dwords to bytes */
priv->config.cd_offset *= sizeof(u32); priv->config.cd_offset *= sizeof(u32);
priv->config.cdsh_offset *= sizeof(u32);
priv->config.rd_offset *= sizeof(u32); priv->config.rd_offset *= sizeof(u32);
priv->config.res_offset *= sizeof(u32); priv->config.res_offset *= sizeof(u32);
} }
......
...@@ -40,7 +40,8 @@ ...@@ -40,7 +40,8 @@
/* Static configuration */ /* Static configuration */
#define EIP197_DEFAULT_RING_SIZE 400 #define EIP197_DEFAULT_RING_SIZE 400
#define EIP197_MAX_TOKENS 19 #define EIP197_EMB_TOKENS 4 /* Pad CD to 16 dwords */
#define EIP197_MAX_TOKENS 16
#define EIP197_MAX_RINGS 4 #define EIP197_MAX_RINGS 4
#define EIP197_FETCH_DEPTH 2 #define EIP197_FETCH_DEPTH 2
#define EIP197_MAX_BATCH_SZ 64 #define EIP197_MAX_BATCH_SZ 64
...@@ -207,6 +208,7 @@ ...@@ -207,6 +208,7 @@
/* EIP197_HIA_xDR_DESC_SIZE */ /* EIP197_HIA_xDR_DESC_SIZE */
#define EIP197_xDR_DESC_MODE_64BIT BIT(31) #define EIP197_xDR_DESC_MODE_64BIT BIT(31)
#define EIP197_CDR_DESC_MODE_ADCP BIT(30)
/* EIP197_HIA_xDR_DMA_CFG */ /* EIP197_HIA_xDR_DMA_CFG */
#define EIP197_HIA_xDR_WR_RES_BUF BIT(22) #define EIP197_HIA_xDR_WR_RES_BUF BIT(22)
...@@ -277,9 +279,9 @@ ...@@ -277,9 +279,9 @@
#define EIP197_HIA_DxE_CFG_MIN_CTRL_SIZE(n) ((n) << 16) #define EIP197_HIA_DxE_CFG_MIN_CTRL_SIZE(n) ((n) << 16)
#define EIP197_HIA_DxE_CFG_CTRL_CACHE_CTRL(n) (((n) & 0x7) << 20) #define EIP197_HIA_DxE_CFG_CTRL_CACHE_CTRL(n) (((n) & 0x7) << 20)
#define EIP197_HIA_DxE_CFG_MAX_CTRL_SIZE(n) ((n) << 24) #define EIP197_HIA_DxE_CFG_MAX_CTRL_SIZE(n) ((n) << 24)
#define EIP197_HIA_DFE_CFG_DIS_DEBUG (BIT(31) | BIT(29)) #define EIP197_HIA_DFE_CFG_DIS_DEBUG GENMASK(31, 29)
#define EIP197_HIA_DSE_CFG_EN_SINGLE_WR BIT(29) #define EIP197_HIA_DSE_CFG_EN_SINGLE_WR BIT(29)
#define EIP197_HIA_DSE_CFG_DIS_DEBUG BIT(31) #define EIP197_HIA_DSE_CFG_DIS_DEBUG GENMASK(31, 30)
/* EIP197_HIA_DFE/DSE_THR_CTRL */ /* EIP197_HIA_DFE/DSE_THR_CTRL */
#define EIP197_DxE_THR_CTRL_EN BIT(30) #define EIP197_DxE_THR_CTRL_EN BIT(30)
...@@ -553,6 +555,8 @@ static inline void eip197_noop_token(struct safexcel_token *token) ...@@ -553,6 +555,8 @@ static inline void eip197_noop_token(struct safexcel_token *token)
{ {
token->opcode = EIP197_TOKEN_OPCODE_NOOP; token->opcode = EIP197_TOKEN_OPCODE_NOOP;
token->packet_length = BIT(2); token->packet_length = BIT(2);
token->stat = 0;
token->instructions = 0;
} }
/* Instructions */ /* Instructions */
...@@ -574,14 +578,13 @@ struct safexcel_control_data_desc { ...@@ -574,14 +578,13 @@ struct safexcel_control_data_desc {
u16 application_id; u16 application_id;
u16 rsvd; u16 rsvd;
u8 refresh:2; u32 context_lo;
u32 context_lo:30;
u32 context_hi; u32 context_hi;
u32 control0; u32 control0;
u32 control1; u32 control1;
u32 token[EIP197_MAX_TOKENS]; u32 token[EIP197_EMB_TOKENS];
} __packed; } __packed;
#define EIP197_OPTION_MAGIC_VALUE BIT(0) #define EIP197_OPTION_MAGIC_VALUE BIT(0)
...@@ -591,7 +594,10 @@ struct safexcel_control_data_desc { ...@@ -591,7 +594,10 @@ struct safexcel_control_data_desc {
#define EIP197_OPTION_2_TOKEN_IV_CMD GENMASK(11, 10) #define EIP197_OPTION_2_TOKEN_IV_CMD GENMASK(11, 10)
#define EIP197_OPTION_4_TOKEN_IV_CMD GENMASK(11, 9) #define EIP197_OPTION_4_TOKEN_IV_CMD GENMASK(11, 9)
#define EIP197_TYPE_BCLA 0x0
#define EIP197_TYPE_EXTENDED 0x3 #define EIP197_TYPE_EXTENDED 0x3
#define EIP197_CONTEXT_SMALL 0x2
#define EIP197_CONTEXT_SIZE_MASK 0x3
/* Basic Command Descriptor format */ /* Basic Command Descriptor format */
struct safexcel_command_desc { struct safexcel_command_desc {
...@@ -599,13 +605,16 @@ struct safexcel_command_desc { ...@@ -599,13 +605,16 @@ struct safexcel_command_desc {
u8 rsvd0:5; u8 rsvd0:5;
u8 last_seg:1; u8 last_seg:1;
u8 first_seg:1; u8 first_seg:1;
u16 additional_cdata_size:8; u8 additional_cdata_size:8;
u32 rsvd1; u32 rsvd1;
u32 data_lo; u32 data_lo;
u32 data_hi; u32 data_hi;
u32 atok_lo;
u32 atok_hi;
struct safexcel_control_data_desc control_data; struct safexcel_control_data_desc control_data;
} __packed; } __packed;
...@@ -629,15 +638,20 @@ enum eip197_fw { ...@@ -629,15 +638,20 @@ enum eip197_fw {
struct safexcel_desc_ring { struct safexcel_desc_ring {
void *base; void *base;
void *shbase;
void *base_end; void *base_end;
void *shbase_end;
dma_addr_t base_dma; dma_addr_t base_dma;
dma_addr_t shbase_dma;
/* write and read pointers */ /* write and read pointers */
void *write; void *write;
void *shwrite;
void *read; void *read;
/* descriptor element offset */ /* descriptor element offset */
unsigned offset; unsigned int offset;
unsigned int shoffset;
}; };
enum safexcel_alg_type { enum safexcel_alg_type {
...@@ -652,6 +666,7 @@ struct safexcel_config { ...@@ -652,6 +666,7 @@ struct safexcel_config {
u32 cd_size; u32 cd_size;
u32 cd_offset; u32 cd_offset;
u32 cdsh_offset;
u32 rd_size; u32 rd_size;
u32 rd_offset; u32 rd_offset;
...@@ -862,7 +877,8 @@ struct safexcel_command_desc *safexcel_add_cdesc(struct safexcel_crypto_priv *pr ...@@ -862,7 +877,8 @@ struct safexcel_command_desc *safexcel_add_cdesc(struct safexcel_crypto_priv *pr
bool first, bool last, bool first, bool last,
dma_addr_t data, u32 len, dma_addr_t data, u32 len,
u32 full_data_len, u32 full_data_len,
dma_addr_t context); dma_addr_t context,
struct safexcel_token **atoken);
struct safexcel_result_desc *safexcel_add_rdesc(struct safexcel_crypto_priv *priv, struct safexcel_result_desc *safexcel_add_rdesc(struct safexcel_crypto_priv *priv,
int ring_id, int ring_id,
bool first, bool last, bool first, bool last,
......
...@@ -87,12 +87,14 @@ static void safexcel_hash_token(struct safexcel_command_desc *cdesc, ...@@ -87,12 +87,14 @@ static void safexcel_hash_token(struct safexcel_command_desc *cdesc,
input_length &= 15; input_length &= 15;
if (unlikely(cbcmac && input_length)) { if (unlikely(cbcmac && input_length)) {
token[0].stat = 0;
token[1].opcode = EIP197_TOKEN_OPCODE_INSERT; token[1].opcode = EIP197_TOKEN_OPCODE_INSERT;
token[1].packet_length = 16 - input_length; token[1].packet_length = 16 - input_length;
token[1].stat = EIP197_TOKEN_STAT_LAST_HASH; token[1].stat = EIP197_TOKEN_STAT_LAST_HASH;
token[1].instructions = EIP197_TOKEN_INS_TYPE_HASH; token[1].instructions = EIP197_TOKEN_INS_TYPE_HASH;
} else { } else {
token[0].stat = EIP197_TOKEN_STAT_LAST_HASH; token[0].stat = EIP197_TOKEN_STAT_LAST_HASH;
eip197_noop_token(&token[1]);
} }
token[2].opcode = EIP197_TOKEN_OPCODE_INSERT; token[2].opcode = EIP197_TOKEN_OPCODE_INSERT;
...@@ -101,6 +103,8 @@ static void safexcel_hash_token(struct safexcel_command_desc *cdesc, ...@@ -101,6 +103,8 @@ static void safexcel_hash_token(struct safexcel_command_desc *cdesc,
token[2].packet_length = result_length; token[2].packet_length = result_length;
token[2].instructions = EIP197_TOKEN_INS_TYPE_OUTPUT | token[2].instructions = EIP197_TOKEN_INS_TYPE_OUTPUT |
EIP197_TOKEN_INS_INSERT_HASH_DIGEST; EIP197_TOKEN_INS_INSERT_HASH_DIGEST;
eip197_noop_token(&token[3]);
} }
static void safexcel_context_control(struct safexcel_ahash_ctx *ctx, static void safexcel_context_control(struct safexcel_ahash_ctx *ctx,
...@@ -111,6 +115,7 @@ static void safexcel_context_control(struct safexcel_ahash_ctx *ctx, ...@@ -111,6 +115,7 @@ static void safexcel_context_control(struct safexcel_ahash_ctx *ctx,
u64 count = 0; u64 count = 0;
cdesc->control_data.control0 = ctx->alg; cdesc->control_data.control0 = ctx->alg;
cdesc->control_data.control1 = 0;
/* /*
* Copy the input digest if needed, and setup the context * Copy the input digest if needed, and setup the context
...@@ -314,6 +319,7 @@ static int safexcel_ahash_send_req(struct crypto_async_request *async, int ring, ...@@ -314,6 +319,7 @@ static int safexcel_ahash_send_req(struct crypto_async_request *async, int ring,
struct safexcel_command_desc *cdesc, *first_cdesc = NULL; struct safexcel_command_desc *cdesc, *first_cdesc = NULL;
struct safexcel_result_desc *rdesc; struct safexcel_result_desc *rdesc;
struct scatterlist *sg; struct scatterlist *sg;
struct safexcel_token *dmmy;
int i, extra = 0, n_cdesc = 0, ret = 0, cache_len, skip = 0; int i, extra = 0, n_cdesc = 0, ret = 0, cache_len, skip = 0;
u64 queued, len; u64 queued, len;
...@@ -397,7 +403,8 @@ static int safexcel_ahash_send_req(struct crypto_async_request *async, int ring, ...@@ -397,7 +403,8 @@ static int safexcel_ahash_send_req(struct crypto_async_request *async, int ring,
first_cdesc = safexcel_add_cdesc(priv, ring, 1, first_cdesc = safexcel_add_cdesc(priv, ring, 1,
(cache_len == len), (cache_len == len),
req->cache_dma, cache_len, req->cache_dma, cache_len,
len, ctx->base.ctxr_dma); len, ctx->base.ctxr_dma,
&dmmy);
if (IS_ERR(first_cdesc)) { if (IS_ERR(first_cdesc)) {
ret = PTR_ERR(first_cdesc); ret = PTR_ERR(first_cdesc);
goto unmap_cache; goto unmap_cache;
...@@ -436,7 +443,7 @@ static int safexcel_ahash_send_req(struct crypto_async_request *async, int ring, ...@@ -436,7 +443,7 @@ static int safexcel_ahash_send_req(struct crypto_async_request *async, int ring,
cdesc = safexcel_add_cdesc(priv, ring, !n_cdesc, cdesc = safexcel_add_cdesc(priv, ring, !n_cdesc,
!(queued - sglen), !(queued - sglen),
sg_dma_address(sg) + skip, sglen, sg_dma_address(sg) + skip, sglen,
len, ctx->base.ctxr_dma); len, ctx->base.ctxr_dma, &dmmy);
if (IS_ERR(cdesc)) { if (IS_ERR(cdesc)) {
ret = PTR_ERR(cdesc); ret = PTR_ERR(cdesc);
goto unmap_sg; goto unmap_sg;
......
...@@ -14,6 +14,11 @@ int safexcel_init_ring_descriptors(struct safexcel_crypto_priv *priv, ...@@ -14,6 +14,11 @@ int safexcel_init_ring_descriptors(struct safexcel_crypto_priv *priv,
struct safexcel_desc_ring *cdr, struct safexcel_desc_ring *cdr,
struct safexcel_desc_ring *rdr) struct safexcel_desc_ring *rdr)
{ {
int i;
struct safexcel_command_desc *cdesc;
dma_addr_t atok;
/* Actual command descriptor ring */
cdr->offset = priv->config.cd_offset; cdr->offset = priv->config.cd_offset;
cdr->base = dmam_alloc_coherent(priv->dev, cdr->base = dmam_alloc_coherent(priv->dev,
cdr->offset * EIP197_DEFAULT_RING_SIZE, cdr->offset * EIP197_DEFAULT_RING_SIZE,
...@@ -24,7 +29,34 @@ int safexcel_init_ring_descriptors(struct safexcel_crypto_priv *priv, ...@@ -24,7 +29,34 @@ int safexcel_init_ring_descriptors(struct safexcel_crypto_priv *priv,
cdr->base_end = cdr->base + cdr->offset * (EIP197_DEFAULT_RING_SIZE - 1); cdr->base_end = cdr->base + cdr->offset * (EIP197_DEFAULT_RING_SIZE - 1);
cdr->read = cdr->base; cdr->read = cdr->base;
/* Command descriptor shadow ring for storing additional token data */
cdr->shoffset = priv->config.cdsh_offset;
cdr->shbase = dmam_alloc_coherent(priv->dev,
cdr->shoffset *
EIP197_DEFAULT_RING_SIZE,
&cdr->shbase_dma, GFP_KERNEL);
if (!cdr->shbase)
return -ENOMEM;
cdr->shwrite = cdr->shbase;
cdr->shbase_end = cdr->shbase + cdr->shoffset *
(EIP197_DEFAULT_RING_SIZE - 1);
/*
* Populate command descriptors with physical pointers to shadow descs.
* Note that we only need to do this once if we don't overwrite them.
*/
cdesc = cdr->base;
atok = cdr->shbase_dma;
for (i = 0; i < EIP197_DEFAULT_RING_SIZE; i++) {
cdesc->atok_lo = lower_32_bits(atok);
cdesc->atok_hi = upper_32_bits(atok);
cdesc = (void *)cdesc + cdr->offset;
atok += cdr->shoffset;
}
rdr->offset = priv->config.rd_offset; rdr->offset = priv->config.rd_offset;
/* Use shoffset for result token offset here */
rdr->shoffset = priv->config.res_offset;
rdr->base = dmam_alloc_coherent(priv->dev, rdr->base = dmam_alloc_coherent(priv->dev,
rdr->offset * EIP197_DEFAULT_RING_SIZE, rdr->offset * EIP197_DEFAULT_RING_SIZE,
&rdr->base_dma, GFP_KERNEL); &rdr->base_dma, GFP_KERNEL);
...@@ -42,11 +74,40 @@ inline int safexcel_select_ring(struct safexcel_crypto_priv *priv) ...@@ -42,11 +74,40 @@ inline int safexcel_select_ring(struct safexcel_crypto_priv *priv)
return (atomic_inc_return(&priv->ring_used) % priv->config.rings); return (atomic_inc_return(&priv->ring_used) % priv->config.rings);
} }
static void *safexcel_ring_next_wptr(struct safexcel_crypto_priv *priv, static void *safexcel_ring_next_cwptr(struct safexcel_crypto_priv *priv,
struct safexcel_desc_ring *ring) struct safexcel_desc_ring *ring,
bool first,
struct safexcel_token **atoken)
{ {
void *ptr = ring->write; void *ptr = ring->write;
if (first)
*atoken = ring->shwrite;
if ((ring->write == ring->read - ring->offset) ||
(ring->read == ring->base && ring->write == ring->base_end))
return ERR_PTR(-ENOMEM);
if (ring->write == ring->base_end) {
ring->write = ring->base;
ring->shwrite = ring->shbase;
} else {
ring->write += ring->offset;
ring->shwrite += ring->shoffset;
}
return ptr;
}
static void *safexcel_ring_next_rwptr(struct safexcel_crypto_priv *priv,
struct safexcel_desc_ring *ring,
struct result_data_desc **rtoken)
{
void *ptr = ring->write;
/* Result token at relative offset shoffset */
*rtoken = ring->write + ring->shoffset;
if ((ring->write == ring->read - ring->offset) || if ((ring->write == ring->read - ring->offset) ||
(ring->read == ring->base && ring->write == ring->base_end)) (ring->read == ring->base && ring->write == ring->base_end))
return ERR_PTR(-ENOMEM); return ERR_PTR(-ENOMEM);
...@@ -106,10 +167,13 @@ void safexcel_ring_rollback_wptr(struct safexcel_crypto_priv *priv, ...@@ -106,10 +167,13 @@ void safexcel_ring_rollback_wptr(struct safexcel_crypto_priv *priv,
if (ring->write == ring->read) if (ring->write == ring->read)
return; return;
if (ring->write == ring->base) if (ring->write == ring->base) {
ring->write = ring->base_end; ring->write = ring->base_end;
else ring->shwrite = ring->shbase_end;
} else {
ring->write -= ring->offset; ring->write -= ring->offset;
ring->shwrite -= ring->shoffset;
}
} }
struct safexcel_command_desc *safexcel_add_cdesc(struct safexcel_crypto_priv *priv, struct safexcel_command_desc *safexcel_add_cdesc(struct safexcel_crypto_priv *priv,
...@@ -117,26 +181,26 @@ struct safexcel_command_desc *safexcel_add_cdesc(struct safexcel_crypto_priv *pr ...@@ -117,26 +181,26 @@ struct safexcel_command_desc *safexcel_add_cdesc(struct safexcel_crypto_priv *pr
bool first, bool last, bool first, bool last,
dma_addr_t data, u32 data_len, dma_addr_t data, u32 data_len,
u32 full_data_len, u32 full_data_len,
dma_addr_t context) { dma_addr_t context,
struct safexcel_token **atoken)
{
struct safexcel_command_desc *cdesc; struct safexcel_command_desc *cdesc;
int i;
cdesc = safexcel_ring_next_wptr(priv, &priv->ring[ring_id].cdr); cdesc = safexcel_ring_next_cwptr(priv, &priv->ring[ring_id].cdr,
first, atoken);
if (IS_ERR(cdesc)) if (IS_ERR(cdesc))
return cdesc; return cdesc;
memset(cdesc, 0, sizeof(struct safexcel_command_desc));
cdesc->first_seg = first;
cdesc->last_seg = last;
cdesc->particle_size = data_len; cdesc->particle_size = data_len;
cdesc->rsvd0 = 0;
cdesc->last_seg = last;
cdesc->first_seg = first;
cdesc->additional_cdata_size = 0;
cdesc->rsvd1 = 0;
cdesc->data_lo = lower_32_bits(data); cdesc->data_lo = lower_32_bits(data);
cdesc->data_hi = upper_32_bits(data); cdesc->data_hi = upper_32_bits(data);
if (first && context) { if (first) {
struct safexcel_token *token =
(struct safexcel_token *)cdesc->control_data.token;
/* /*
* Note that the length here MUST be >0 or else the EIP(1)97 * Note that the length here MUST be >0 or else the EIP(1)97
* may hang. Newer EIP197 firmware actually incorporates this * may hang. Newer EIP197 firmware actually incorporates this
...@@ -146,20 +210,12 @@ struct safexcel_command_desc *safexcel_add_cdesc(struct safexcel_crypto_priv *pr ...@@ -146,20 +210,12 @@ struct safexcel_command_desc *safexcel_add_cdesc(struct safexcel_crypto_priv *pr
cdesc->control_data.packet_length = full_data_len ?: 1; cdesc->control_data.packet_length = full_data_len ?: 1;
cdesc->control_data.options = EIP197_OPTION_MAGIC_VALUE | cdesc->control_data.options = EIP197_OPTION_MAGIC_VALUE |
EIP197_OPTION_64BIT_CTX | EIP197_OPTION_64BIT_CTX |
EIP197_OPTION_CTX_CTRL_IN_CMD; EIP197_OPTION_CTX_CTRL_IN_CMD |
cdesc->control_data.context_lo = EIP197_OPTION_RC_AUTO;
(lower_32_bits(context) & GENMASK(31, 2)) >> 2; cdesc->control_data.type = EIP197_TYPE_BCLA;
cdesc->control_data.context_lo = lower_32_bits(context) |
EIP197_CONTEXT_SMALL;
cdesc->control_data.context_hi = upper_32_bits(context); cdesc->control_data.context_hi = upper_32_bits(context);
if (priv->version == EIP197B_MRVL ||
priv->version == EIP197D_MRVL)
cdesc->control_data.options |= EIP197_OPTION_RC_AUTO;
/* TODO: large xform HMAC with SHA-384/512 uses refresh = 3 */
cdesc->control_data.refresh = 2;
for (i = 0; i < EIP197_MAX_TOKENS; i++)
eip197_noop_token(&token[i]);
} }
return cdesc; return cdesc;
...@@ -171,19 +227,27 @@ struct safexcel_result_desc *safexcel_add_rdesc(struct safexcel_crypto_priv *pri ...@@ -171,19 +227,27 @@ struct safexcel_result_desc *safexcel_add_rdesc(struct safexcel_crypto_priv *pri
dma_addr_t data, u32 len) dma_addr_t data, u32 len)
{ {
struct safexcel_result_desc *rdesc; struct safexcel_result_desc *rdesc;
struct result_data_desc *rtoken;
rdesc = safexcel_ring_next_wptr(priv, &priv->ring[ring_id].rdr); rdesc = safexcel_ring_next_rwptr(priv, &priv->ring[ring_id].rdr,
&rtoken);
if (IS_ERR(rdesc)) if (IS_ERR(rdesc))
return rdesc; return rdesc;
memset(rdesc, 0, sizeof(struct safexcel_result_desc)); rdesc->particle_size = len;
rdesc->rsvd0 = 0;
rdesc->first_seg = first; rdesc->descriptor_overflow = 0;
rdesc->buffer_overflow = 0;
rdesc->last_seg = last; rdesc->last_seg = last;
rdesc->first_seg = first;
rdesc->result_size = EIP197_RD64_RESULT_SIZE; rdesc->result_size = EIP197_RD64_RESULT_SIZE;
rdesc->particle_size = len; rdesc->rsvd1 = 0;
rdesc->data_lo = lower_32_bits(data); rdesc->data_lo = lower_32_bits(data);
rdesc->data_hi = upper_32_bits(data); rdesc->data_hi = upper_32_bits(data);
/* Clear length & error code in result token */
rtoken->packet_length = 0;
rtoken->error_code = 0;
return rdesc; return rdesc;
} }
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