Commit 0995b9a8 authored by Laurent Pinchart's avatar Laurent Pinchart Committed by Simon Horman

ARM: dts: r8a7740: Rename the serial port clock to fck

The clock is really the device functional clock, not the interface
clock. Rename it.
Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent d4be2f1b
...@@ -214,7 +214,7 @@ scifa0: serial@e6c40000 { ...@@ -214,7 +214,7 @@ scifa0: serial@e6c40000 {
reg = <0xe6c40000 0x100>; reg = <0xe6c40000 0x100>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>; clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
...@@ -224,7 +224,7 @@ scifa1: serial@e6c50000 { ...@@ -224,7 +224,7 @@ scifa1: serial@e6c50000 {
reg = <0xe6c50000 0x100>; reg = <0xe6c50000 0x100>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>; clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
...@@ -234,7 +234,7 @@ scifa2: serial@e6c60000 { ...@@ -234,7 +234,7 @@ scifa2: serial@e6c60000 {
reg = <0xe6c60000 0x100>; reg = <0xe6c60000 0x100>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>; clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
...@@ -244,7 +244,7 @@ scifa3: serial@e6c70000 { ...@@ -244,7 +244,7 @@ scifa3: serial@e6c70000 {
reg = <0xe6c70000 0x100>; reg = <0xe6c70000 0x100>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>; clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
...@@ -254,7 +254,7 @@ scifa4: serial@e6c80000 { ...@@ -254,7 +254,7 @@ scifa4: serial@e6c80000 {
reg = <0xe6c80000 0x100>; reg = <0xe6c80000 0x100>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>; clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
...@@ -264,7 +264,7 @@ scifa5: serial@e6cb0000 { ...@@ -264,7 +264,7 @@ scifa5: serial@e6cb0000 {
reg = <0xe6cb0000 0x100>; reg = <0xe6cb0000 0x100>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>; clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
...@@ -274,7 +274,7 @@ scifa6: serial@e6cc0000 { ...@@ -274,7 +274,7 @@ scifa6: serial@e6cc0000 {
reg = <0xe6cc0000 0x100>; reg = <0xe6cc0000 0x100>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>; clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
...@@ -284,7 +284,7 @@ scifa7: serial@e6cd0000 { ...@@ -284,7 +284,7 @@ scifa7: serial@e6cd0000 {
reg = <0xe6cd0000 0x100>; reg = <0xe6cd0000 0x100>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>; clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
...@@ -294,7 +294,7 @@ scifb: serial@e6c30000 { ...@@ -294,7 +294,7 @@ scifb: serial@e6c30000 {
reg = <0xe6c30000 0x100>; reg = <0xe6c30000 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFB>; clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
......
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