Commit 09c4e56b authored by Kamil Krawczyk's avatar Kamil Krawczyk Committed by Jeff Kirsher

i40e/i40evf: add ASQ write back timeout variable to AQ structure

Add new variable defining ASQ command write back timeout to allow for
dynamic modification of this timeout. Initialize it on AQ initialize
routine with default value, vary it on device ID.

Change-ID: I5c9908f9d7c5455634353b694a986d6f146d1b9d
Signed-off-by: default avatarKamil Krawczyk <kamil.krawczyk@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent fc86a970
...@@ -571,6 +571,9 @@ i40e_status i40e_init_adminq(struct i40e_hw *hw) ...@@ -571,6 +571,9 @@ i40e_status i40e_init_adminq(struct i40e_hw *hw)
/* Set up register offsets */ /* Set up register offsets */
i40e_adminq_init_regs(hw); i40e_adminq_init_regs(hw);
/* setup ASQ command write back timeout */
hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT;
/* allocate the ASQ */ /* allocate the ASQ */
ret_code = i40e_init_asq(hw); ret_code = i40e_init_asq(hw);
if (ret_code) if (ret_code)
...@@ -860,7 +863,7 @@ i40e_status i40e_asq_send_command(struct i40e_hw *hw, ...@@ -860,7 +863,7 @@ i40e_status i40e_asq_send_command(struct i40e_hw *hw,
/* ugh! delay while spin_lock */ /* ugh! delay while spin_lock */
udelay(delay_len); udelay(delay_len);
total_delay += delay_len; total_delay += delay_len;
} while (total_delay < I40E_ASQ_CMD_TIMEOUT); } while (total_delay < hw->aq.asq_cmd_timeout);
} }
/* if ready, copy the desc back to temp */ /* if ready, copy the desc back to temp */
......
...@@ -84,6 +84,7 @@ struct i40e_arq_event_info { ...@@ -84,6 +84,7 @@ struct i40e_arq_event_info {
struct i40e_adminq_info { struct i40e_adminq_info {
struct i40e_adminq_ring arq; /* receive queue */ struct i40e_adminq_ring arq; /* receive queue */
struct i40e_adminq_ring asq; /* send queue */ struct i40e_adminq_ring asq; /* send queue */
u32 asq_cmd_timeout; /* send queue cmd write back timeout*/
u16 num_arq_entries; /* receive queue depth */ u16 num_arq_entries; /* receive queue depth */
u16 num_asq_entries; /* send queue depth */ u16 num_asq_entries; /* send queue depth */
u16 arq_buf_size; /* receive queue buffer size */ u16 arq_buf_size; /* receive queue buffer size */
......
...@@ -567,6 +567,9 @@ i40e_status i40evf_init_adminq(struct i40e_hw *hw) ...@@ -567,6 +567,9 @@ i40e_status i40evf_init_adminq(struct i40e_hw *hw)
/* Set up register offsets */ /* Set up register offsets */
i40e_adminq_init_regs(hw); i40e_adminq_init_regs(hw);
/* setup ASQ command write back timeout */
hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT;
/* allocate the ASQ */ /* allocate the ASQ */
ret_code = i40e_init_asq(hw); ret_code = i40e_init_asq(hw);
if (ret_code) if (ret_code)
...@@ -814,7 +817,7 @@ i40e_status i40evf_asq_send_command(struct i40e_hw *hw, ...@@ -814,7 +817,7 @@ i40e_status i40evf_asq_send_command(struct i40e_hw *hw,
/* ugh! delay while spin_lock */ /* ugh! delay while spin_lock */
udelay(delay_len); udelay(delay_len);
total_delay += delay_len; total_delay += delay_len;
} while (total_delay < I40E_ASQ_CMD_TIMEOUT); } while (total_delay < hw->aq.asq_cmd_timeout);
} }
/* if ready, copy the desc back to temp */ /* if ready, copy the desc back to temp */
......
...@@ -84,6 +84,7 @@ struct i40e_arq_event_info { ...@@ -84,6 +84,7 @@ struct i40e_arq_event_info {
struct i40e_adminq_info { struct i40e_adminq_info {
struct i40e_adminq_ring arq; /* receive queue */ struct i40e_adminq_ring arq; /* receive queue */
struct i40e_adminq_ring asq; /* send queue */ struct i40e_adminq_ring asq; /* send queue */
u32 asq_cmd_timeout; /* send queue cmd write back timeout*/
u16 num_arq_entries; /* receive queue depth */ u16 num_arq_entries; /* receive queue depth */
u16 num_asq_entries; /* send queue depth */ u16 num_asq_entries; /* send queue depth */
u16 arq_buf_size; /* receive queue buffer size */ u16 arq_buf_size; /* receive queue buffer size */
......
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