Commit 0a650c1d authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher

drm/amd/powerplay: add Arcturus baco reset support

Enable baco reset support on Arcturus.
Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b4f8285a
...@@ -559,6 +559,7 @@ soc15_asic_reset_method(struct amdgpu_device *adev) ...@@ -559,6 +559,7 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
return AMD_RESET_METHOD_MODE2; return AMD_RESET_METHOD_MODE2;
case CHIP_VEGA10: case CHIP_VEGA10:
case CHIP_VEGA12: case CHIP_VEGA12:
case CHIP_ARCTURUS:
soc15_asic_get_baco_capability(adev, &baco_reset); soc15_asic_get_baco_capability(adev, &baco_reset);
break; break;
case CHIP_VEGA20: case CHIP_VEGA20:
......
...@@ -495,6 +495,7 @@ static int arcturus_store_powerplay_table(struct smu_context *smu) ...@@ -495,6 +495,7 @@ static int arcturus_store_powerplay_table(struct smu_context *smu)
{ {
struct smu_11_0_powerplay_table *powerplay_table = NULL; struct smu_11_0_powerplay_table *powerplay_table = NULL;
struct smu_table_context *table_context = &smu->smu_table; struct smu_table_context *table_context = &smu->smu_table;
struct smu_baco_context *smu_baco = &smu->smu_baco;
int ret = 0; int ret = 0;
if (!table_context->power_play_table) if (!table_context->power_play_table)
...@@ -507,6 +508,12 @@ static int arcturus_store_powerplay_table(struct smu_context *smu) ...@@ -507,6 +508,12 @@ static int arcturus_store_powerplay_table(struct smu_context *smu)
table_context->thermal_controller_type = powerplay_table->thermal_controller_type; table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
mutex_lock(&smu_baco->mutex);
if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
smu_baco->platform_support = true;
mutex_unlock(&smu_baco->mutex);
return ret; return ret;
} }
......
...@@ -1642,7 +1642,9 @@ bool smu_v11_0_baco_is_support(struct smu_context *smu) ...@@ -1642,7 +1642,9 @@ bool smu_v11_0_baco_is_support(struct smu_context *smu)
if (!baco_support) if (!baco_support)
return false; return false;
if (!smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) /* Arcturus does not support this bit mask */
if (smu_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
!smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
return false; return false;
val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
...@@ -1714,11 +1716,15 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state) ...@@ -1714,11 +1716,15 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
int smu_v11_0_baco_reset(struct smu_context *smu) int smu_v11_0_baco_reset(struct smu_context *smu)
{ {
struct amdgpu_device *adev = smu->adev;
int ret = 0; int ret = 0;
/* Arcturus does not need this audio workaround */
if (adev->asic_type != CHIP_ARCTURUS) {
ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO); ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
if (ret) if (ret)
return ret; return ret;
}
ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER); ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
if (ret) if (ret)
......
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