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Commit 0b19c1e5 authored by Jeff Garzik's avatar Jeff Garzik
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[netdrvr] Add S2IO 10gige network driver. 

Contributed by Leonid Grossman @ S2IO
parent 196c4ebd
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Documentation/networking/s2io.txt 0 → 100644
View file @ 0b19c1e5
S2IO Technologies XFrame 10 Gig adapter.
-------------------------------------------
I. Module loadable parameters.
When loaded as a module, the driver provides a host of Module loadable
parameters, so the device can be tuned as per the users needs.
A list of the Module params is given below.
(i) ring_num: This can be used to program the number of
receive rings used in the driver.
(ii) ring_len: This defines the number of descriptors each ring
can have. There can be a maximum of 8 rings.
(iii) frame_len: This is an array of size 8. Using this we can
set the maximum size of the received frame that can
be steered into the corrsponding receive ring.
(iv) fifo_num: This defines the number of Tx FIFOs thats used in
the driver.
(v) fifo_len: Each element defines the number of
Tx descriptors that can be associated with each
corresponding FIFO. There are a maximum of 8 FIFOs.
(vi) tx_prio: This is a bool, if module is loaded with a non-zero
value for tx_prio multi FIFO scheme is activated.
(vii) rx_prio: This is a bool, if module is loaded with a non-zero
value for tx_prio multi RING scheme is activated.
(viii) latency_timer: The value given against this param will be
loaded into the latency timer register in PCI Config
space, else the register is left with its reset value.
II. Performance tuning.
By changing a few sysctl parameters.
Copy the following lines into a file and run the following command,
"sysctl -p <file_name>"
### IPV4 specific settings
net.ipv4.tcp_timestamps = 0 # turns TCP timestamp support off, default 1, reduces CPU use
net.ipv4.tcp_sack = 0 # turn SACK support off, default on
# on systems with a VERY fast bus -> memory interface this is the big gainer
net.ipv4.tcp_rmem = 10000000 10000000 10000000 # sets min/default/max TCP read buffer, default 4096 87380 174760
net.ipv4.tcp_wmem = 10000000 10000000 10000000 # sets min/pressure/max TCP write buffer, default 4096 16384 131072
net.ipv4.tcp_mem = 10000000 10000000 10000000 # sets min/pressure/max TCP buffer space, default 31744 32256 32768
### CORE settings (mostly for socket and UDP effect)
net.core.rmem_max = 524287 # maximum receive socket buffer size, default 131071
net.core.wmem_max = 524287 # maximum send socket buffer size, default 131071
net.core.rmem_default = 524287 # default receive socket buffer size, default 65535
net.core.wmem_default = 524287 # default send socket buffer size, default 65535
net.core.optmem_max = 524287 # maximum amount of option memory buffers, default 10240
net.core.netdev_max_backlog = 300000 # number of unprocessed input packets before kernel starts dropping them, default 300
---End of performance tuning file---
drivers/net/Kconfig
View file @ 0b19c1e5
......@@ -2101,6 +2101,18 @@ config IXGB_NAPI
bool "Use Rx Polling (NAPI) (EXPERIMENTAL)"
depends on IXGB && EXPERIMENTAL
config S2IO
tristate "S2IO 10Gbe XFrame NIC"
depends on PCI
---help---
This driver supports the 10Gbe XFrame NIC of S2IO.
For help regarding driver compilation, installation and
tuning please look into ~/drivers/net/s2io/README.txt.
config S2IO_NAPI
bool "Use Rx Polling (NAPI) (EXPERIMENTAL)"
depends on S2IO && EXPERIMENTAL
endmenu
......
drivers/net/Makefile
View file @ 0b19c1e5
......@@ -175,6 +175,7 @@ obj-$(CONFIG_DL2K) += dl2k.o
obj-$(CONFIG_R8169) += r8169.o
obj-$(CONFIG_AMD8111_ETH) += amd8111e.o
obj-$(CONFIG_IBMVETH) += ibmveth.o
obj-$(CONFIG_S2IO) += s2io.o
obj-$(CONFIG_ARM) += arm/
obj-$(CONFIG_NET_FC) += fc/
......
drivers/net/s2io-regs.h 0 → 100644
View file @ 0b19c1e5
/************************************************************************
* regs.h: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC
* Copyright 2002 Raghavendra Koushik (raghavendra.koushik@s2io.com)
* This software may be used and distributed according to the terms of
* the GNU General Public License (GPL), incorporated herein by reference.
* Drivers based on or derived from this code fall under the GPL and must
* retain the authorship, copyright and license notice. This file is not
* a complete program and may only be used when the entire operating
* system is licensed under the GPL.
* See the file COPYING in this distribution for more information.
************************************************************************/
#ifndef _REGS_H
#define _REGS_H
#define TBD 0
typedef struct _XENA_dev_config {
/* Convention: mHAL_XXX is mask, vHAL_XXX is value */
/* General Control-Status Registers */
u64 general_int_status;
#define GEN_INTR_TXPIC BIT(0)
#define GEN_INTR_TXDMA BIT(1)
#define GEN_INTR_TXMAC BIT(2)
#define GEN_INTR_TXXGXS BIT(3)
#define GEN_INTR_TXTRAFFIC BIT(8)
#define GEN_INTR_RXPIC BIT(32)
#define GEN_INTR_RXDMA BIT(33)
#define GEN_INTR_RXMAC BIT(34)
#define GEN_INTR_MC BIT(35)
#define GEN_INTR_RXXGXS BIT(36)
#define GEN_INTR_RXTRAFFIC BIT(40)
#define GEN_ERROR_INTR GEN_INTR_TXPIC | GEN_INTR_RXPIC | \
GEN_INTR_TXDMA | GEN_INTR_RXDMA | \
GEN_INTR_TXMAC | GEN_INTR_RXMAC | \
GEN_INTR_TXXGXS| GEN_INTR_RXXGXS| \
GEN_INTR_MC
u64 general_int_mask;
u8 unused0[0x100 - 0x10];
u64 sw_reset;
/* XGXS must be removed from reset only once. */
#define SW_RESET_XENA vBIT(0xA5,0,8)
#define SW_RESET_FLASH vBIT(0xA5,8,8)
#define SW_RESET_EOI vBIT(0xA5,16,8)
#define SW_RESET_ALL (SW_RESET_XENA | \
SW_RESET_FLASH | \
SW_RESET_EOI)
/* The SW_RESET register must read this value after a successful reset. */
#define SW_RESET_RAW_VAL 0xA5000000
u64 adapter_status;
#define ADAPTER_STATUS_TDMA_READY BIT(0)
#define ADAPTER_STATUS_RDMA_READY BIT(1)
#define ADAPTER_STATUS_PFC_READY BIT(2)
#define ADAPTER_STATUS_TMAC_BUF_EMPTY BIT(3)
#define ADAPTER_STATUS_PIC_QUIESCENT BIT(5)
#define ADAPTER_STATUS_RMAC_REMOTE_FAULT BIT(6)
#define ADAPTER_STATUS_RMAC_LOCAL_FAULT BIT(7)
#define ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8)
#define ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8)
#define ADAPTER_STATUS_MC_DRAM_READY BIT(24)
#define ADAPTER_STATUS_MC_QUEUES_READY BIT(25)
#define ADAPTER_STATUS_M_PLL_LOCK BIT(30)
#define ADAPTER_STATUS_P_PLL_LOCK BIT(31)
u64 adapter_control;
#define ADAPTER_CNTL_EN BIT(7)
#define ADAPTER_EOI_TX_ON BIT(15)
#define ADAPTER_LED_ON BIT(23)
#define ADAPTER_UDPI(val) vBIT(val,36,4)
#define ADAPTER_WAIT_INT BIT(48)
#define ADAPTER_ECC_EN BIT(55)
u64 serr_source;
#define SERR_SOURCE_PIC BIT(0)
#define SERR_SOURCE_TXDMA BIT(1)
#define SERR_SOURCE_RXDMA BIT(2)
#define SERR_SOURCE_MAC BIT(3)
#define SERR_SOURCE_MC BIT(4)
#define SERR_SOURCE_XGXS BIT(5)
#define SERR_SOURCE_ANY (SERR_SOURCE_PIC | \
SERR_SOURCE_TXDMA | \
SERR_SOURCE_RXDMA | \
SERR_SOURCE_MAC | \
SERR_SOURCE_MC | \
SERR_SOURCE_XGXS)
u8 unused_0[0x800 - 0x120];
/* PCI-X Controller registers */
u64 pic_int_status;
u64 pic_int_mask;
#define PIC_INT_TX BIT(0)
#define PIC_INT_FLSH BIT(1)
#define PIC_INT_MDIO BIT(2)
#define PIC_INT_IIC BIT(3)
#define PIC_INT_GPIO BIT(4)
#define PIC_INT_RX BIT(32)
u64 txpic_int_reg;
u64 txpic_int_mask;
#define PCIX_INT_REG_ECC_SG_ERR BIT(0)
#define PCIX_INT_REG_ECC_DB_ERR BIT(1)
#define PCIX_INT_REG_FLASHR_R_FSM_ERR BIT(8)
#define PCIX_INT_REG_FLASHR_W_FSM_ERR BIT(9)
#define PCIX_INT_REG_INI_TX_FSM_SERR BIT(10)
#define PCIX_INT_REG_INI_TXO_FSM_ERR BIT(11)
#define PCIX_INT_REG_TRT_FSM_SERR BIT(13)
#define PCIX_INT_REG_SRT_FSM_SERR BIT(14)
#define PCIX_INT_REG_PIFR_FSM_SERR BIT(15)
#define PCIX_INT_REG_WRC_TX_SEND_FSM_SERR BIT(21)
#define PCIX_INT_REG_RRC_TX_REQ_FSM_SERR BIT(23)
#define PCIX_INT_REG_INI_RX_FSM_SERR BIT(48)
#define PCIX_INT_REG_RA_RX_FSM_SERR BIT(50)
/*
#define PCIX_INT_REG_WRC_RX_SEND_FSM_SERR BIT(52)
#define PCIX_INT_REG_RRC_RX_REQ_FSM_SERR BIT(54)
#define PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR BIT(58)
*/
u64 txpic_alarms;
u64 rxpic_int_reg;
u64 rxpic_int_mask;
u64 rxpic_alarms;
u64 flsh_int_reg;
u64 flsh_int_mask;
#define PIC_FLSH_INT_REG_CYCLE_FSM_ERR BIT(63)
#define PIC_FLSH_INT_REG_ERR BIT(62)
u64 flash_alarms;
u64 mdio_int_reg;
u64 mdio_int_mask;
#define MDIO_INT_REG_MDIO_BUS_ERR BIT(0)
#define MDIO_INT_REG_DTX_BUS_ERR BIT(8)
#define MDIO_INT_REG_LASI BIT(39)
u64 mdio_alarms;
u64 iic_int_reg;
u64 iic_int_mask;
#define IIC_INT_REG_BUS_FSM_ERR BIT(4)
#define IIC_INT_REG_BIT_FSM_ERR BIT(5)
#define IIC_INT_REG_CYCLE_FSM_ERR BIT(6)
#define IIC_INT_REG_REQ_FSM_ERR BIT(7)
#define IIC_INT_REG_ACK_ERR BIT(8)
u64 iic_alarms;
u8 unused4[0x08];
u64 gpio_int_reg;
u64 gpio_int_mask;
u64 gpio_alarms;
u8 unused5[0x38];
u64 tx_traffic_int;
#define TX_TRAFFIC_INT_n(n) BIT(n)
u64 tx_traffic_mask;
u64 rx_traffic_int;
#define RX_TRAFFIC_INT_n(n) BIT(n)
u64 rx_traffic_mask;
/* PIC Control registers */
u64 pic_control;
#define PIC_CNTL_RX_ALARM_MAP_1 BIT(0)
#define PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,4)
u64 swapper_ctrl;
#define SWAPPER_CTRL_PIF_R_FE BIT(0)
#define SWAPPER_CTRL_PIF_R_SE BIT(1)
#define SWAPPER_CTRL_PIF_W_FE BIT(8)
#define SWAPPER_CTRL_PIF_W_SE BIT(9)
#define SWAPPER_CTRL_TXP_FE BIT(16)
#define SWAPPER_CTRL_TXP_SE BIT(17)
#define SWAPPER_CTRL_TXD_R_FE BIT(18)
#define SWAPPER_CTRL_TXD_R_SE BIT(19)
#define SWAPPER_CTRL_TXD_W_FE BIT(20)
#define SWAPPER_CTRL_TXD_W_SE BIT(21)
#define SWAPPER_CTRL_TXF_R_FE BIT(22)
#define SWAPPER_CTRL_TXF_R_SE BIT(23)
#define SWAPPER_CTRL_RXD_R_FE BIT(32)
#define SWAPPER_CTRL_RXD_R_SE BIT(33)
#define SWAPPER_CTRL_RXD_W_FE BIT(34)
#define SWAPPER_CTRL_RXD_W_SE BIT(35)
#define SWAPPER_CTRL_RXF_W_FE BIT(36)
#define SWAPPER_CTRL_RXF_W_SE BIT(37)
#define SWAPPER_CTRL_XMSI_FE BIT(40)
#define SWAPPER_CTRL_XMSI_SE BIT(41)
#define SWAPPER_CTRL_STATS_FE BIT(48)
#define SWAPPER_CTRL_STATS_SE BIT(49)
u64 pif_rd_swapper_fb;
#define IF_RD_SWAPPER_FB 0x0123456789ABCDEF
u64 scheduled_int_ctrl;
#define SCHED_INT_CTRL_TIMER_EN BIT(0)
#define SCHED_INT_CTRL_ONE_SHOT BIT(1)
#define SCHED_INT_CTRL_INT2MSI TBD
#define SCHED_INT_PERIOD TBD
u64 txreqtimeout;
#define TXREQTO_VAL(val) vBIT(val,0,32)
#define TXREQTO_EN BIT(63)
u64 statsreqtimeout;
#define STATREQTO_VAL(n) TBD
#define STATREQTO_EN BIT(63)
u64 read_retry_delay;
u64 read_retry_acceleration;
u64 write_retry_delay;
u64 write_retry_acceleration;
u64 xmsi_control;
u64 xmsi_access;
u64 xmsi_address;
u64 xmsi_data;
u64 rx_mat;
u8 unused6[0x8];
u64 tx_mat0_7;
u64 tx_mat8_15;
u64 tx_mat16_23;
u64 tx_mat24_31;
u64 tx_mat32_39;
u64 tx_mat40_47;
u64 tx_mat48_55;
u64 tx_mat56_63;
u8 unused_1[0x10];
/* Automated statistics collection */
u64 stat_cfg;
#define STAT_CFG_STAT_EN BIT(0)
#define STAT_CFG_ONE_SHOT_EN BIT(1)
#define STAT_CFG_STAT_NS_EN BIT(8)
#define STAT_CFG_STAT_RO BIT(9)
#define STAT_TRSF_PER(n) TBD
#define PER_SEC 0x208d5
#define SET_UPDT_PERIOD(n) vBIT((PER_SEC*n),32,32)
u64 stat_addr;
/* General Configuration */
u64 mdio_control;
u64 dtx_control;
u64 i2c_control;
#define I2C_CONTROL_DEV_ID(id) vBIT(id,1,3)
#define I2C_CONTROL_ADDR(addr) vBIT(addr,5,11)
#define I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2)
#define I2C_CONTROL_READ BIT(24)
#define I2C_CONTROL_NACK BIT(25)
#define I2C_CONTROL_CNTL_START vBIT(0xE,28,4)
#define I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4))
#define I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF)
#define I2C_CONTROL_SET_DATA(val) vBIT(val,32,32)
u64 gpio_control;
#define GPIO_CTRL_GPIO_0 BIT(8)
u8 unused7[0x600];
/* TxDMA registers */
u64 txdma_int_status;
u64 txdma_int_mask;
#define TXDMA_PFC_INT BIT(0)
#define TXDMA_TDA_INT BIT(1)
#define TXDMA_PCC_INT BIT(2)
#define TXDMA_TTI_INT BIT(3)
#define TXDMA_LSO_INT BIT(4)
#define TXDMA_TPA_INT BIT(5)
#define TXDMA_SM_INT BIT(6)
u64 pfc_err_reg;
u64 pfc_err_mask;
u64 pfc_err_alarm;
u64 tda_err_reg;
u64 tda_err_mask;
u64 tda_err_alarm;
u64 pcc_err_reg;
u64 pcc_err_mask;
u64 pcc_err_alarm;
u64 tti_err_reg;
u64 tti_err_mask;
u64 tti_err_alarm;
u64 lso_err_reg;
u64 lso_err_mask;
u64 lso_err_alarm;
u64 tpa_err_reg;
u64 tpa_err_mask;
u64 tpa_err_alarm;
u64 sm_err_reg;
u64 sm_err_mask;
u64 sm_err_alarm;
u8 unused8[0x100 - 0xB8];
/* TxDMA arbiter */
u64 tx_dma_wrap_stat;
/* Tx FIFO controller */
#define X_MAX_FIFOS 8
#define X_FIFO_MAX_LEN 0x1FFF /*8191 */
u64 tx_fifo_partition_0;
#define TX_FIFO_PARTITION_EN BIT(0)
#define TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3)
#define TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13)
#define TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3)
#define TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 )
u64 tx_fifo_partition_1;
#define TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3)
#define TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13)
#define TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3)
#define TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13)
u64 tx_fifo_partition_2;
#define TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3)
#define TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13)
#define TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3)
#define TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13)
u64 tx_fifo_partition_3;
#define TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3)
#define TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13)
#define TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3)
#define TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13)
#define TX_FIFO_PARTITION_PRI_0 0 /* highest */
#define TX_FIFO_PARTITION_PRI_1 1
#define TX_FIFO_PARTITION_PRI_2 2
#define TX_FIFO_PARTITION_PRI_3 3
#define TX_FIFO_PARTITION_PRI_4 4
#define TX_FIFO_PARTITION_PRI_5 5
#define TX_FIFO_PARTITION_PRI_6 6
#define TX_FIFO_PARTITION_PRI_7 7 /* lowest */
u64 tx_w_round_robin_0;
u64 tx_w_round_robin_1;
u64 tx_w_round_robin_2;
u64 tx_w_round_robin_3;
u64 tx_w_round_robin_4;
u64 tti_command_mem;
#define TTI_CMD_MEM_WE BIT(7)
#define TTI_CMD_MEM_STROBE_NEW_CMD BIT(15)
#define TTI_CMD_MEM_STROBE_BEING_EXECUTED BIT(15)
#define TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6)
u64 tti_data1_mem;
#define TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26)
#define TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2)
#define TTI_DATA1_MEM_TX_TIMER_AC_EN BIT(38)
#define TTI_DATA1_MEM_TX_TIMER_CI_EN BIT(39)
#define TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7)
#define TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7)
#define TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7)
u64 tti_data2_mem;
#define TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0,16)
#define TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16,16)
#define TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32,16)
#define TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48,16)
/* Tx Protocol assist */
u64 tx_pa_cfg;
#define TX_PA_CFG_IGNORE_FRM_ERR BIT(1)
#define TX_PA_CFG_IGNORE_SNAP_OUI BIT(2)
#define TX_PA_CFG_IGNORE_LLC_CTRL BIT(3)
#define TX_PA_CFG_IGNORE_L2_ERR BIT(6)
/* Recent add, used only debug purposes. */
u64 pcc_enable;
u8 unused9[0x700 - 0x178];
u64 txdma_debug_ctrl;
u8 unused10[0x1800 - 0x1708];
/* RxDMA Registers */
u64 rxdma_int_status;
u64 rxdma_int_mask;
#define RXDMA_INT_RC_INT_M BIT(0)
#define RXDMA_INT_RPA_INT_M BIT(1)
#define RXDMA_INT_RDA_INT_M BIT(2)
#define RXDMA_INT_RTI_INT_M BIT(3)
u64 rda_err_reg;
u64 rda_err_mask;
u64 rda_err_alarm;
u64 rc_err_reg;
u64 rc_err_mask;
u64 rc_err_alarm;
u64 prc_pcix_err_reg;
u64 prc_pcix_err_mask;
u64 prc_pcix_err_alarm;
u64 rpa_err_reg;
u64 rpa_err_mask;
u64 rpa_err_alarm;
u64 rti_err_reg;
u64 rti_err_mask;
u64 rti_err_alarm;
u8 unused11[0x100 - 0x88];
/* DMA arbiter */
u64 rx_queue_priority;
#define RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3)
#define RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3)
#define RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3)
#define RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3)
#define RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3)
#define RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3)
#define RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3)
#define RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3)
#define RX_QUEUE_PRI_0 0 /* highest */
#define RX_QUEUE_PRI_1 1
#define RX_QUEUE_PRI_2 2
#define RX_QUEUE_PRI_3 3
#define RX_QUEUE_PRI_4 4
#define RX_QUEUE_PRI_5 5
#define RX_QUEUE_PRI_6 6
#define RX_QUEUE_PRI_7 7 /* lowest */
u64 rx_w_round_robin_0;
u64 rx_w_round_robin_1;
u64 rx_w_round_robin_2;
u64 rx_w_round_robin_3;
u64 rx_w_round_robin_4;
/* Per-ring controller regs */
#define RX_MAX_RINGS 8
#if 0
#define RX_MAX_RINGS_SZ 0xFFFF /* 65536 */
#define RX_MIN_RINGS_SZ 0x3F /* 63 */
#endif
u64 prc_rxd0_n[RX_MAX_RINGS];
u64 prc_ctrl_n[RX_MAX_RINGS];
#define PRC_CTRL_RC_ENABLED BIT(7)
#define PRC_CTRL_RING_MODE (BIT(14)|BIT(15))
#define PRC_CTRL_RING_MODE_1 vBIT(0,14,2)
#define PRC_CTRL_RING_MODE_3 vBIT(1,14,2)
#define PRC_CTRL_RING_MODE_5 vBIT(2,14,2)
#define PRC_CTRL_RING_MODE_x vBIT(3,14,2)
#define PRC_CTRL_NO_SNOOP (BIT(22)|BIT(23))
#define PRC_CTRL_NO_SNOOP_DESC BIT(22)
#define PRC_CTRL_NO_SNOOP_BUFF BIT(23)
#define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24)
u64 prc_alarm_action;
#define PRC_ALARM_ACTION_RR_R0_STOP BIT(3)
#define PRC_ALARM_ACTION_RW_R0_STOP BIT(7)
#define PRC_ALARM_ACTION_RR_R1_STOP BIT(11)
#define PRC_ALARM_ACTION_RW_R1_STOP BIT(15)
#define PRC_ALARM_ACTION_RR_R2_STOP BIT(19)
#define PRC_ALARM_ACTION_RW_R2_STOP BIT(23)
#define PRC_ALARM_ACTION_RR_R3_STOP BIT(27)
#define PRC_ALARM_ACTION_RW_R3_STOP BIT(31)
#define PRC_ALARM_ACTION_RR_R4_STOP BIT(35)
#define PRC_ALARM_ACTION_RW_R4_STOP BIT(39)
#define PRC_ALARM_ACTION_RR_R5_STOP BIT(43)
#define PRC_ALARM_ACTION_RW_R5_STOP BIT(47)
#define PRC_ALARM_ACTION_RR_R6_STOP BIT(51)
#define PRC_ALARM_ACTION_RW_R6_STOP BIT(55)
#define PRC_ALARM_ACTION_RR_R7_STOP BIT(59)
#define PRC_ALARM_ACTION_RW_R7_STOP BIT(63)
/* Receive traffic interrupts */
u64 rti_command_mem;
#define RTI_CMD_MEM_WE BIT(7)
#define RTI_CMD_MEM_STROBE BIT(15)
#define RTI_CMD_MEM_STROBE_NEW_CMD BIT(15)
#define RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED BIT(15)
#define RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3)
u64 rti_data1_mem;
#define RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29)
#define RTI_DATA1_MEM_RX_TIMER_AC_EN BIT(38)
#define RTI_DATA1_MEM_RX_TIMER_CI_EN BIT(39)
#define RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7)
#define RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7)
#define RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7)
u64 rti_data2_mem;
#define RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0,16)
#define RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16,16)
#define RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32,16)
#define RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16)
u64 rx_pa_cfg;
#define RX_PA_CFG_IGNORE_FRM_ERR BIT(1)
#define RX_PA_CFG_IGNORE_SNAP_OUI BIT(2)
#define RX_PA_CFG_IGNORE_LLC_CTRL BIT(3)
u8 unused12[0x700 - 0x1D8];
u64 rxdma_debug_ctrl;
u8 unused13[0x2000 - 0x1f08];
/* Media Access Controller Register */
u64 mac_int_status;
u64 mac_int_mask;
#define MAC_INT_STATUS_TMAC_INT BIT(0)
#define MAC_INT_STATUS_RMAC_INT BIT(1)
u64 mac_tmac_err_reg;
#define TMAC_ERR_REG_TMAC_ECC_DB_ERR BIT(15)
#define TMAC_ERR_REG_TMAC_TX_BUF_OVRN BIT(23)
#define TMAC_ERR_REG_TMAC_TX_CRI_ERR BIT(31)
u64 mac_tmac_err_mask;
u64 mac_tmac_err_alarm;
u64 mac_rmac_err_reg;
#define RMAC_ERR_REG_RX_BUFF_OVRN BIT(0)
#define RMAC_ERR_REG_RTS_ECC_DB_ERR BIT(14)
#define RMAC_ERR_REG_ECC_DB_ERR BIT(15)
#define RMAC_LINK_STATE_CHANGE_INT BIT(31)
u64 mac_rmac_err_mask;
u64 mac_rmac_err_alarm;
u8 unused14[0x100 - 0x40];
u64 mac_cfg;
#define MAC_CFG_TMAC_ENABLE BIT(0)
#define MAC_CFG_RMAC_ENABLE BIT(1)
#define MAC_CFG_LAN_NOT_WAN BIT(2)
#define MAC_CFG_TMAC_LOOPBACK BIT(3)
#define MAC_CFG_TMAC_APPEND_PAD BIT(4)
#define MAC_CFG_RMAC_STRIP_FCS BIT(5)
#define MAC_CFG_RMAC_STRIP_PAD BIT(6)
#define MAC_CFG_RMAC_PROM_ENABLE BIT(7)
#define MAC_RMAC_DISCARD_PFRM BIT(8)
#define MAC_RMAC_BCAST_ENABLE BIT(9)
#define MAC_RMAC_ALL_ADDR_ENABLE BIT(10)
#define MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8)
u64 tmac_avg_ipg;
#define TMAC_AVG_IPG(val) vBIT(val,0,8)
u64 rmac_max_pyld_len;
#define RMAC_MAX_PYLD_LEN(val) vBIT(val,2,14)
#define RMAC_MAX_PYLD_LEN_DEF vBIT(1500,2,14)
#define RMAC_MAX_PYLD_LEN_JUMBO_DEF vBIT(9600,2,14)
u64 rmac_err_cfg;
#define RMAC_ERR_FCS BIT(0)
#define RMAC_ERR_FCS_ACCEPT BIT(1)
#define RMAC_ERR_TOO_LONG BIT(1)
#define RMAC_ERR_TOO_LONG_ACCEPT BIT(1)
#define RMAC_ERR_RUNT BIT(2)
#define RMAC_ERR_RUNT_ACCEPT BIT(2)
#define RMAC_ERR_LEN_MISMATCH BIT(3)
#define RMAC_ERR_LEN_MISMATCH_ACCEPT BIT(3)
u64 rmac_cfg_key;
#define RMAC_CFG_KEY(val) vBIT(val,0,16)
#define MAX_MAC_ADDRESSES 16
#define MAX_MC_ADDRESSES 32 /* Multicast addresses */
#define MAC_MAC_ADDR_START_OFFSET 0
#define MAC_MC_ADDR_START_OFFSET 16
#define MAC_MC_ALL_MC_ADDR_OFFSET 63 /* enables all multicast pkts */
u64 rmac_addr_cmd_mem;
#define RMAC_ADDR_CMD_MEM_WE BIT(7)
#define RMAC_ADDR_CMD_MEM_RD 0
#define RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD BIT(15)
#define RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING BIT(15)
#define RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6)
u64 rmac_addr_data0_mem;
#define RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48)
#define RMAC_ADDR_DATA0_MEM_USER BIT(48)
u64 rmac_addr_data1_mem;
#define RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48)
u8 unused15[0x8];
/*
u64 rmac_addr_cfg;
#define RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n)
#define RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n)
#define RMAC_ADDR_BCAST_EN vBIT(0)_48
#define RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49
*/
u64 tmac_ipg_cfg;
u64 rmac_pause_cfg;
#define RMAC_PAUSE_GEN BIT(0)
#define RMAC_PAUSE_GEN_ENABLE BIT(0)
#define RMAC_PAUSE_RX BIT(1)
#define RMAC_PAUSE_RX_ENABLE BIT(1)
#define RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16)
#define RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16)
u64 rmac_red_cfg;
u64 rmac_red_rate_q0q3;
u64 rmac_red_rate_q4q7;
u64 mac_link_util;
#define MAC_TX_LINK_UTIL vBIT(0xFE,1,7)
#define MAC_TX_LINK_UTIL_DISABLE vBIT(0xF, 8,4)
#define MAC_TX_LINK_UTIL_VAL( n ) vBIT(n,8,4)
#define MAC_RX_LINK_UTIL vBIT(0xFE,33,7)
#define MAC_RX_LINK_UTIL_DISABLE vBIT(0xF,40,4)
#define MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40,4)
#define MAC_LINK_UTIL_DISABLE MAC_TX_LINK_UTIL_DISABLE | \
MAC_RX_LINK_UTIL_DISABLE
u64 rmac_invalid_ipg;
/* rx traffic steering */
#define MAC_RTS_FRM_LEN_SET(len) vBIT(len,2,14)
u64 rts_frm_len_n[8];
u64 rts_qos_steering;
#define MAX_DIX_MAP 4
u64 rts_dix_map_n[MAX_DIX_MAP];
#define RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16)
#define RTS_DIX_MAP_SCW(val) BIT(val,21)
u64 rts_q_alternates;
u64 rts_default_q;
u64 rts_ctrl;
#define RTS_CTRL_IGNORE_SNAP_OUI BIT(2)
#define RTS_CTRL_IGNORE_LLC_CTRL BIT(3)
u64 rts_pn_cam_ctrl;
#define RTS_PN_CAM_CTRL_WE BIT(7)
#define RTS_PN_CAM_CTRL_STROBE_NEW_CMD BIT(15)
#define RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED BIT(15)
#define RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8)
u64 rts_pn_cam_data;
#define RTS_PN_CAM_DATA_TCP_SELECT BIT(7)
#define RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16)
#define RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8)
u64 rts_ds_mem_ctrl;
#define RTS_DS_MEM_CTRL_WE BIT(7)
#define RTS_DS_MEM_CTRL_STROBE_NEW_CMD BIT(15)
#define RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED BIT(15)
#define RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6)
u64 rts_ds_mem_data;
#define RTS_DS_MEM_DATA(n) vBIT(n,0,8)
u8 unused16[0x700 - 0x220];
u64 mac_debug_ctrl;
#define MAC_DBG_ACTIVITY_VALUE 0x411040400000000ULL
u8 unused17[0x2800 - 0x2708];
/* memory controller registers */
u64 mc_int_status;
#define MC_INT_STATUS_MC_INT BIT(0)
u64 mc_int_mask;
#define MC_INT_MASK_MC_INT BIT(0)
u64 mc_err_reg;
#define MC_ERR_REG_ECC_DB_ERR_L BIT(14)
#define MC_ERR_REG_ECC_DB_ERR_U BIT(15)
#define MC_ERR_REG_MIRI_CRI_ERR_0 BIT(22)
#define MC_ERR_REG_MIRI_CRI_ERR_1 BIT(23)
#define MC_ERR_REG_SM_ERR BIT(31)
u64 mc_err_mask;
u64 mc_err_alarm;
u8 unused18[0x100 - 0x28];
/* MC configuration */
u64 rx_queue_cfg;
#define RX_QUEUE_CFG_Q0_SZ(n) vBIT(n,0,8)
#define RX_QUEUE_CFG_Q1_SZ(n) vBIT(n,8,8)
#define RX_QUEUE_CFG_Q2_SZ(n) vBIT(n,16,8)
#define RX_QUEUE_CFG_Q3_SZ(n) vBIT(n,24,8)
#define RX_QUEUE_CFG_Q4_SZ(n) vBIT(n,32,8)
#define RX_QUEUE_CFG_Q5_SZ(n) vBIT(n,40,8)
#define RX_QUEUE_CFG_Q6_SZ(n) vBIT(n,48,8)
#define RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8)
u64 mc_rldram_mrs;
#define MC_RLDRAM_QUEUE_SIZE_ENABLE BIT(39)
#define MC_RLDRAM_MRS_ENABLE BIT(47)
u64 mc_rldram_interleave;
u64 mc_pause_thresh_q0q3;
u64 mc_pause_thresh_q4q7;
u64 mc_red_thresh_q[8];
u8 unused19[0x200 - 0x168];
u64 mc_rldram_ref_per;
u8 unused20[0x220 - 0x208];
u64 mc_rldram_test_ctrl;
#define MC_RLDRAM_TEST_MODE BIT(47)
#define MC_RLDRAM_TEST_WRITE BIT(7)
#define MC_RLDRAM_TEST_GO BIT(15)
#define MC_RLDRAM_TEST_DONE BIT(23)
#define MC_RLDRAM_TEST_PASS BIT(31)
u8 unused21[0x240 - 0x228];
u64 mc_rldram_test_add;
u8 unused22[0x260 - 0x248];
u64 mc_rldram_test_d0;
u8 unused23[0x280 - 0x268];
u64 mc_rldram_test_d1;
u8 unused24[0x300 - 0x288];
u64 mc_rldram_test_d2;
u8 unused25[0x700 - 0x308];
u64 mc_debug_ctrl;
u8 unused26[0x3000 - 0x2f08];
/* XGXG */
/* XGXS control registers */
u64 xgxs_int_status;
#define XGXS_INT_STATUS_TXGXS BIT(0)
#define XGXS_INT_STATUS_RXGXS BIT(1)
u64 xgxs_int_mask;
#define XGXS_INT_MASK_TXGXS BIT(0)
#define XGXS_INT_MASK_RXGXS BIT(1)
u64 xgxs_txgxs_err_reg;
#define TXGXS_ECC_DB_ERR BIT(15)
u64 xgxs_txgxs_err_mask;
u64 xgxs_txgxs_err_alarm;
u64 xgxs_rxgxs_err_reg;
u64 xgxs_rxgxs_err_mask;
u64 xgxs_rxgxs_err_alarm;
u8 unused27[0x100 - 0x40];
u64 xgxs_cfg;
u64 xgxs_status;
u64 xgxs_cfg_key;
u64 xgxs_efifo_cfg; /* CHANGED */
u64 rxgxs_ber_0; /* CHANGED */
u64 rxgxs_ber_1; /* CHANGED */
} XENA_dev_config_t;
#define XENA_REG_SPACE sizeof(XENA_dev_config_t)
#define XENA_EEPROM_SPACE (0x01 << 11)
#endif /* _REGS_H */
drivers/net/s2io.c 0 → 100644
View file @ 0b19c1e5
This source diff could not be displayed because it is too large. You can view the blob instead.
drivers/net/s2io.h 0 → 100644
View file @ 0b19c1e5
/************************************************************************
* s2io.h: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC
* Copyright 2002 Raghavendra Koushik (raghavendra.koushik@s2io.com)
* This software may be used and distributed according to the terms of
* the GNU General Public License (GPL), incorporated herein by reference.
* Drivers based on or derived from this code fall under the GPL and must
* retain the authorship, copyright and license notice. This file is not
* a complete program and may only be used when the entire operating
* system is licensed under the GPL.
* See the file COPYING in this distribution for more information.
************************************************************************/
#ifndef _S2IO_H
#define _S2IO_H
#define TBD 0
#define BIT(loc) (1ULL << (loc))
#define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
#ifndef BOOL
#define BOOL int
#endif
#ifndef TRUE
#define TRUE 1
#define FALSE 0
#endif
#undef SUCCESS
#define SUCCESS 0
#define FAILURE -1
/* Maximum outstanding splits to be configured into xena. */
typedef enum xena_max_outstanding_splits {
XENA_ONE_SPLIT_TRANSACTION = 0,
XENA_TWO_SPLIT_TRANSACTION = 1,
XENA_THREE_SPLIT_TRANSACTION = 2,
XENA_FOUR_SPLIT_TRANSACTION = 3,
XENA_EIGHT_SPLIT_TRANSACTION = 4,
XENA_TWELVE_SPLIT_TRANSACTION = 5,
XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
} xena_max_outstanding_splits;
#define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
/* OS concerned variables and constants */
#define WATCH_DOG_TIMEOUT 5*HZ
#define EFILL 0x1234
#define ALIGN_SIZE 127
#define PCIX_COMMAND_REGISTER 0x62
/*
* Debug related variables.
*/
#define DEBUG_ON TRUE
/* different debug levels. */
#define ERR_DBG 0
#define INIT_DBG 1
#define INFO_DBG 2
#define TX_DBG 3
#define INTR_DBG 4
/* Global variable that defines the present debug level of the driver. */
int debug_level = ERR_DBG; /* Default level. */
/* DEBUG message print. */
#define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args)
/* Protocol assist features of the NIC */
#define L3_CKSUM_OK 0xFFFF
#define L4_CKSUM_OK 0xFFFF
#define S2IO_JUMBO_SIZE 9600
/* The statistics block of Xena */
typedef struct stat_block {
#ifdef __BIG_ENDIAN
/* Tx MAC statistics counters. */
u32 tmac_frms;
u32 tmac_data_octets;
u64 tmac_drop_frms;
u32 tmac_mcst_frms;
u32 tmac_bcst_frms;
u64 tmac_pause_ctrl_frms;
u32 tmac_ttl_octets;
u32 tmac_ucst_frms;
u32 tmac_nucst_frms;
u32 tmac_any_err_frms;
u64 tmac_ttl_less_fb_octets;
u64 tmac_vld_ip_octets;
u32 tmac_vld_ip;
u32 tmac_drop_ip;
u32 tmac_icmp;
u32 tmac_rst_tcp;
u64 tmac_tcp;
u32 tmac_udp;
u32 reserved_0;
/* Rx MAC Statistics counters. */
u32 rmac_vld_frms;
u32 rmac_data_octets;
u64 rmac_fcs_err_frms;
u64 rmac_drop_frms;
u32 rmac_vld_mcst_frms;
u32 rmac_vld_bcst_frms;
u32 rmac_in_rng_len_err_frms;
u32 rmac_out_rng_len_err_frms;
u64 rmac_long_frms;
u64 rmac_pause_ctrl_frms;
u64 rmac_unsup_ctrl_frms;
u32 rmac_ttl_octets;
u32 rmac_accepted_ucst_frms;
u32 rmac_accepted_nucst_frms;
u32 rmac_discarded_frms;
u32 rmac_drop_events;
u32 reserved_1;
u64 rmac_ttl_less_fb_octets;
u64 rmac_ttl_frms;
u64 reserved_2;
u32 reserved_3;
u32 rmac_usized_frms;
u32 rmac_osized_frms;
u32 rmac_frag_frms;
u32 rmac_jabber_frms;
u32 reserved_4;
u64 rmac_ttl_64_frms;
u64 rmac_ttl_65_127_frms;
u64 reserved_5;
u64 rmac_ttl_128_255_frms;
u64 rmac_ttl_256_511_frms;
u64 reserved_6;
u64 rmac_ttl_512_1023_frms;
u64 rmac_ttl_1024_1518_frms;
u32 reserved_7;
u32 rmac_ip;
u64 rmac_ip_octets;
u32 rmac_hdr_err_ip;
u32 rmac_drop_ip;
u32 rmac_icmp;
u32 reserved_8;
u64 rmac_tcp;
u32 rmac_udp;
u32 rmac_err_drp_udp;
u64 rmac_xgmii_err_sym;
u64 rmac_frms_q0;
u64 rmac_frms_q1;
u64 rmac_frms_q2;
u64 rmac_frms_q3;
u64 rmac_frms_q4;
u64 rmac_frms_q5;
u64 rmac_frms_q6;
u64 rmac_frms_q7;
u16 rmac_full_q0;
u16 rmac_full_q1;
u16 rmac_full_q2;
u16 rmac_full_q3;
u16 rmac_full_q4;
u16 rmac_full_q5;
u16 rmac_full_q6;
u16 rmac_full_q7;
u32 rmac_pause_cnt;
u32 reserved_9;
u64 rmac_xgmii_data_err_cnt;
u64 rmac_xgmii_ctrl_err_cnt;
u32 rmac_accepted_ip;
u32 rmac_err_tcp;
/* PCI/PCI-X Read transaction statistics. */
u32 rd_req_cnt;
u32 new_rd_req_cnt;
u32 new_rd_req_rtry_cnt;
u32 rd_rtry_cnt;
u32 wr_rtry_rd_ack_cnt;
/* PCI/PCI-X write transaction statistics. */
u32 wr_req_cnt;
u32 new_wr_req_cnt;
u32 new_wr_req_rtry_cnt;
u32 wr_rtry_cnt;
u32 wr_disc_cnt;
u32 rd_rtry_wr_ack_cnt;
/* DMA Transaction statistics. */
u32 txp_wr_cnt;
u32 txd_rd_cnt;
u32 txd_wr_cnt;
u32 rxd_rd_cnt;
u32 rxd_wr_cnt;
u32 txf_rd_cnt;
u32 rxf_wr_cnt;
#else
/* Tx MAC statistics counters. */
u32 tmac_data_octets;
u32 tmac_frms;
u64 tmac_drop_frms;
u32 tmac_bcst_frms;
u32 tmac_mcst_frms;
u64 tmac_pause_ctrl_frms;
u32 tmac_ucst_frms;
u32 tmac_ttl_octets;
u32 tmac_any_err_frms;
u32 tmac_nucst_frms;
u64 tmac_ttl_less_fb_octets;
u64 tmac_vld_ip_octets;
u32 tmac_drop_ip;
u32 tmac_vld_ip;
u32 tmac_rst_tcp;
u32 tmac_icmp;
u64 tmac_tcp;
u32 reserved_0;
u32 tmac_udp;
/* Rx MAC Statistics counters. */
u32 rmac_data_octets;
u32 rmac_vld_frms;
u64 rmac_fcs_err_frms;
u64 rmac_drop_frms;
u32 rmac_vld_bcst_frms;
u32 rmac_vld_mcst_frms;
u32 rmac_out_rng_len_err_frms;
u32 rmac_in_rng_len_err_frms;
u64 rmac_long_frms;
u64 rmac_pause_ctrl_frms;
u64 rmac_unsup_ctrl_frms;
u32 rmac_accepted_ucst_frms;
u32 rmac_ttl_octets;
u32 rmac_discarded_frms;
u32 rmac_accepted_nucst_frms;
u32 reserved_1;
u32 rmac_drop_events;
u64 rmac_ttl_less_fb_octets;
u64 rmac_ttl_frms;
u64 reserved_2;
u32 rmac_usized_frms;
u32 reserved_3;
u32 rmac_frag_frms;
u32 rmac_osized_frms;
u32 reserved_4;
u32 rmac_jabber_frms;
u64 rmac_ttl_64_frms;
u64 rmac_ttl_65_127_frms;
u64 reserved_5;
u64 rmac_ttl_128_255_frms;
u64 rmac_ttl_256_511_frms;
u64 reserved_6;
u64 rmac_ttl_512_1023_frms;
u64 rmac_ttl_1024_1518_frms;
u32 rmac_ip;
u32 reserved_7;
u64 rmac_ip_octets;
u32 rmac_drop_ip;
u32 rmac_hdr_err_ip;
u32 reserved_8;
u32 rmac_icmp;
u64 rmac_tcp;
u32 rmac_err_drp_udp;
u32 rmac_udp;
u64 rmac_xgmii_err_sym;
u64 rmac_frms_q0;
u64 rmac_frms_q1;
u64 rmac_frms_q2;
u64 rmac_frms_q3;
u64 rmac_frms_q4;
u64 rmac_frms_q5;
u64 rmac_frms_q6;
u64 rmac_frms_q7;
u16 rmac_full_q3;
u16 rmac_full_q2;
u16 rmac_full_q1;
u16 rmac_full_q0;
u16 rmac_full_q7;
u16 rmac_full_q6;
u16 rmac_full_q5;
u16 rmac_full_q4;
u32 reserved_9;
u32 rmac_pause_cnt;
u64 rmac_xgmii_data_err_cnt;
u64 rmac_xgmii_ctrl_err_cnt;
u32 rmac_err_tcp;
u32 rmac_accepted_ip;
/* PCI/PCI-X Read transaction statistics. */
u32 new_rd_req_cnt;
u32 rd_req_cnt;
u32 rd_rtry_cnt;
u32 new_rd_req_rtry_cnt;
/* PCI/PCI-X Write/Read transaction statistics. */
u32 wr_req_cnt;
u32 wr_rtry_rd_ack_cnt;
u32 new_wr_req_rtry_cnt;
u32 new_wr_req_cnt;
u32 wr_disc_cnt;
u32 wr_rtry_cnt;
/* PCI/PCI-X Write / DMA Transaction statistics. */
u32 txp_wr_cnt;
u32 rd_rtry_wr_ack_cnt;
u32 txd_wr_cnt;
u32 txd_rd_cnt;
u32 rxd_wr_cnt;
u32 rxd_rd_cnt;
u32 rxf_wr_cnt;
u32 txf_rd_cnt;
#endif
} StatInfo_t;
/* Structures representing different init time configuration
* parameters of the NIC.
*/
/* Maintains Per FIFO related information. */
typedef struct tx_fifo_config {
#define MAX_AVAILABLE_TXDS 8192
u32 FifoLen; /* specifies len of FIFO upto 8192, ie no of TxDLs */
/* Priority definition */
#define TX_FIFO_PRI_0 0 /*Highest */
#define TX_FIFO_PRI_1 1
#define TX_FIFO_PRI_2 2
#define TX_FIFO_PRI_3 3
#define TX_FIFO_PRI_4 4
#define TX_FIFO_PRI_5 5
#define TX_FIFO_PRI_6 6
#define TX_FIFO_PRI_7 7 /*lowest */
u8 FifoPriority; /* specifies pointer level for FIFO */
/* user should not set twos fifos with same pri */
u8 fNoSnoop;
#define NO_SNOOP_TXD 0x01
#define NO_SNOOP_TXD_BUFFER 0x02
} tx_fifo_config_t;
/* Maintains per Ring related information */
typedef struct rx_ring_config {
u32 NumRxd; /*No of RxDs per Rx Ring */
#define RX_RING_PRI_0 0 /* highest */
#define RX_RING_PRI_1 1
#define RX_RING_PRI_2 2
#define RX_RING_PRI_3 3
#define RX_RING_PRI_4 4
#define RX_RING_PRI_5 5
#define RX_RING_PRI_6 6
#define RX_RING_PRI_7 7 /* lowest */
u8 RingPriority; /*Specifies service priority of ring */
/* OSM should not set any two rings with same priority */
u8 RingOrg; /*Organization of ring */
#define RING_ORG_BUFF1 0x01
#define RX_RING_ORG_BUFF3 0x03
#define RX_RING_ORG_BUFF5 0x05
/* In case of 3 buffer recv. mode, size of three buffers is expected as.. */
#define BUFF_SZ_1 22 /* ethernet header */
#define BUFF_SZ_2 (64+64) /* max. IP+TCP header size */
#define BUFF_SZ_3 (1500-20-20) /* TCP payload */
#define BUFF_SZ_3_JUMBO (9600-20-20) /* Jumbo TCP payload */
u32 RxdThresh; /*No of used Rxds NIC can store before transfer to host */
#define DEFAULT_RXD_THRESHOLD 0x1 /* TODO */
u8 fNoSnoop;
#define NO_SNOOP_RXD 0x01
#define NO_SNOOP_RXD_BUFFER 0x02
u32 RxD_BackOff_Interval;
#define RXD_BACKOFF_INTERVAL_DEF 0x0
#define RXD_BACKOFF_INTERVAL_MIN 0x0
#define RXD_BACKOFF_INTERVAL_MAX 0x0
} rx_ring_config_t;
/* This structure provides contains values of the tunable parameters
* of the H/W
*/
struct config_param {
/* Tx Side */
u32 TxFIFONum; /*Number of Tx FIFOs */
#define MAX_TX_FIFOS 8
tx_fifo_config_t TxCfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
u32 MaxTxDs; /*Max no. of Tx buffer descriptor per TxDL */
BOOL TxVLANEnable; /*TRUE: Insert VLAN ID, FALSE: Don't insert */
#define TX_REQ_TIMEOUT_DEFAULT 0x0
#define TX_REQ_TIMEOUT_MIN 0x0
#define TX_REQ_TIMEOUT_MAX 0x0
u32 TxReqTimeOut;
BOOL TxFlow; /*Tx flow control enable */
BOOL RxFlow;
BOOL OverrideTxServiceState; /* TRUE: Overide, FALSE: Do not override
Use the new priority information
of service state. It is not recommended
to change but OSM can opt to do so */
#define MAX_SERVICE_STATES 36
u8 TxServiceState[MAX_SERVICE_STATES];
/* Array element represent 'priority'
* and array index represents
* 'Service state' e.g.
* TxServiceState[3]=7; it means
* Service state 3 is associated
* with priority 7 of a Tx FIFO */
u64 TxIntrType; /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
/* Rx Side */
u32 RxRingNum; /*Number of receive rings */
#define MAX_RX_RINGS 8
#define MAX_RX_BLOCKS_PER_RING 150
rx_ring_config_t RxCfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
BOOL RxVLANEnable; /*TRUE: Strip off VLAN tag from the frame,
FALSE: Don't strip off VLAN tag */
#define HEADER_ETHERNET_II_802_3_SIZE 14
#define HEADER_802_2_SIZE 3
#define HEADER_SNAP_SIZE 5
#define HEADER_VLAN_SIZE 4
#define HEADER_ALIGN_LAYER_3 2
#define MIN_MTU 46
#define MAX_PYLD 1500
#define MAX_MTU (MAX_PYLD+18)
#define MAX_MTU_VLAN (MAX_PYLD+22)
#define MAX_PYLD_JUMBO 9600
#define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
#define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
u32 MTU; /*Maximum Payload */
BOOL JumboEnable; /*Enable Jumbo frames recv/send */
BOOL OverrideRxServiceState; /* TRUE: Overide, FALSE: Do not override
Use the new priority information
of service state. It is not recommended
to change but OSM can opt to do so */
#define MAX_SERVICE_STATES 36
u8 RxServiceState[MAX_SERVICE_STATES];
/* Array element represent 'priority'
* and array index represents
* 'Service state'e.g.
* RxServiceState[3]=7; it means
* Service state 3 is associated
* with priority 7 of a Rx FIFO */
BOOL StatAutoRefresh; /* When true, StatRefreshTime have valid value */
u32 StatRefreshTime; /*Time for refreshing statistics */
#define STAT_TRSF_PER_1_SECOND 0x208D5
};
/* Structure representing MAC Addrs */
typedef struct mac_addr {
u8 mac_addr[ETH_ALEN];
} macaddr_t;
/* Structure that represent every FIFO element in the BAR1
* Address location.
*/
typedef struct _TxFIFO_element {
u64 TxDL_Pointer;
u64 List_Control;
#define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8)
#define TX_FIFO_FIRST_LIST BIT(14)
#define TX_FIFO_LAST_LIST BIT(15)
#define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2)
#define TX_FIFO_SPECIAL_FUNC BIT(23)
#define TX_FIFO_DS_NO_SNOOP BIT(31)
#define TX_FIFO_BUFF_NO_SNOOP BIT(30)
} TxFIFO_element_t;
/* Tx descriptor structure */
typedef struct _TxD {
u64 Control_1;
/* bit mask */
#define TXD_LIST_OWN_XENA BIT(7)
#define TXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
#define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE))
#define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12)
#define TXD_GATHER_CODE (BIT(22) | BIT(23))
#define TXD_GATHER_CODE_FIRST BIT(22)
#define TXD_GATHER_CODE_LAST BIT(23)
#define TXD_TCP_LSO_EN BIT(30)
#define TXD_UDP_COF_EN BIT(31)
#define TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
#define TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
u64 Control_2;
#define TXD_TX_CKO_CONTROL (BIT(5)|BIT(6)|BIT(7))
#define TXD_TX_CKO_IPV4_EN BIT(5)
#define TXD_TX_CKO_TCP_EN BIT(6)
#define TXD_TX_CKO_UDP_EN BIT(7)
#define TXD_VLAN_ENABLE BIT(15)
#define TXD_VLAN_TAG(val) vBIT(val,16,16)
#define TXD_INT_NUMBER(val) vBIT(val,34,6)
#define TXD_INT_TYPE_PER_LIST BIT(47)
#define TXD_INT_TYPE_UTILZ BIT(46)
#define TXD_SET_MARKER vBIT(0x6,0,4)
u64 Buffer_Pointer;
u64 Host_Control; /* reserved for host */
} TxD_t;
/* Rx descriptor structure */
typedef struct _RxD_t {
u64 Host_Control; /* reserved for host */
u64 Control_1;
#define RXD_OWN_XENA BIT(7)
#define RXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
#define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
#define RXD_FRAME_PROTO_IPV4 BIT(27)
#define RXD_FRAME_PROTO_IPV6 BIT(28)
#define RXD_FRAME_PROTO_TCP BIT(30)
#define RXD_FRAME_PROTO_UDP BIT(31)
#define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
#define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF)
#define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
u64 Control_2;
#define MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16)
#define SET_BUFFER0_SIZE(val) vBIT(val,0,16)
#define MASK_VLAN_TAG vBIT(0xFFFF,48,16)
#define SET_VLAN_TAG(val) vBIT(val,48,16)
#define SET_NUM_TAG(val) vBIT(val,16,32)
#define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0xFFFF,0,16)))
/*
#define TXD_GET_BUFFER1_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER1_SIZE) >> (63-31))
#define TXD_GET_BUFFER2_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER2_SIZE) >> (63-47))
*/
u64 Buffer0_ptr;
} RxD_t;
/* Structure that represents the Rx descriptor block which contains
* 128 Rx descriptors.
*/
typedef struct _RxD_block {
#define MAX_RXDS_PER_BLOCK 127
RxD_t rxd[MAX_RXDS_PER_BLOCK];
u64 reserved_0;
#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last Rxd in this blk */
u64 reserved_2_pNext_RxD_block; /*@ Logical ptr to next */
u64 pNext_RxD_Blk_physical; /* Buff0_ptr.
In a 32 bit arch the upper 32 bits
should be 0 */
} RxD_block_t;
/* Structure which stores all the MAC control parameters */
/* This structure stores the offset of the RxD in the ring
* from which the Rx Interrupt processor can start picking
* up the RxDs for processing.
*/
typedef struct _rx_curr_get_info_t {
u32 block_index;
u32 offset;
u32 ring_len;
} rx_curr_get_info_t;
typedef rx_curr_get_info_t rx_curr_put_info_t;
/* This structure stores the offset of the TxDl in the FIFO
* from which the Tx Interrupt processor can start picking
* up the TxDLs for send complete interrupt processing.
*/
typedef struct {
u32 offset;
u32 fifo_len;
} tx_curr_get_info_t;
typedef tx_curr_get_info_t tx_curr_put_info_t;
/* Infomation related to the Tx and Rx FIFOs and Rings of Xena
* is maintained in this structure.
*/
typedef struct mac_info {
/* rx side stuff */
u32 rxd_ring_mem_sz;
RxD_t *RxRing[MAX_RX_RINGS]; /* Logical Rx ring pointers */
dma_addr_t RxRing_Phy[MAX_RX_RINGS];
/* Put pointer info which indictes which RxD has to be replenished
* with a new buffer.
*/
rx_curr_put_info_t rx_curr_put_info[MAX_RX_RINGS];
/* Get pointer info which indictes which is the last RxD that was
* processed by the driver.
*/
rx_curr_get_info_t rx_curr_get_info[MAX_RX_RINGS];
u16 rmac_pause_time;
/* this will be used in receive function, this decides which ring would
be processed first. eg: ring with priority value 0 (highest) should
be processed first.
first 3 LSB bits represent ring number which should be processed
first, similarly next 3 bits represent next ring to be processed.
eg: value of _rx_ring_pri_map = 0x0000 003A means
ring #2 would be processed first and #7 would be processed next
*/
u32 _rx_ring_pri_map;
/* tx side stuff */
void *txd_list_mem; /* orignal pointer to allocated mem */
dma_addr_t txd_list_mem_phy;
u32 txd_list_mem_sz;
/* logical pointer of start of each Tx FIFO */
TxFIFO_element_t *tx_FIFO_start[MAX_TX_FIFOS];
/* logical pointer of start of TxDL which corresponds to each Tx FIFO */
TxD_t *txdl_start[MAX_TX_FIFOS];
/* Same as txdl_start but phy addr */
dma_addr_t txdl_start_phy[MAX_TX_FIFOS];
/* Current offset within tx_FIFO_start, where driver would write new Tx frame*/
tx_curr_put_info_t tx_curr_put_info[MAX_TX_FIFOS];
tx_curr_get_info_t tx_curr_get_info[MAX_TX_FIFOS];
u16 txdl_len; /* length of a TxDL, same for all */
void *stats_mem; /* orignal pointer to allocated mem */
dma_addr_t stats_mem_phy; /* Physical address of the stat block */
u32 stats_mem_sz;
StatInfo_t *StatsInfo; /* Logical address of the stat block */
} mac_info_t;
/* structure representing the user defined MAC addresses */
typedef struct {
char addr[ETH_ALEN];
int usage_cnt;
} usr_addr_t;
/* Structure that holds the Phy and virt addresses of the Blocks */
typedef struct rx_block_info {
RxD_t *block_virt_addr;
dma_addr_t block_dma_addr;
} rx_block_info_t;
/* Structure representing one instance of the NIC */
typedef struct s2io_nic {
#define MAX_MAC_SUPPORTED 16
#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
macaddr_t defMacAddr[MAX_MAC_SUPPORTED];
macaddr_t preMacAddr[MAX_MAC_SUPPORTED];
struct net_device_stats stats;
caddr_t bar0;
caddr_t bar1;
struct config_param config;
mac_info_t mac_control;
int high_dma_flag;
int device_close_flag;
int device_enabled_once;
char name[32];
struct tasklet_struct task;
atomic_t tasklet_status;
struct timer_list timer;
struct net_device *dev;
struct pci_dev *pdev;
u16 vendor_id;
u16 device_id;
u16 ccmd;
u32 cbar0_1;
u32 cbar0_2;
u32 cbar1_1;
u32 cbar1_2;
u32 cirq;
u8 cache_line;
u32 rom_expansion;
u16 pcix_cmd;
u32 config_space[256 / sizeof(u32)];
u32 irq;
atomic_t rx_bufs_left[MAX_RX_RINGS];
spinlock_t isr_lock;
spinlock_t tx_lock;
#define PROMISC 1
#define ALL_MULTI 2
#define MAX_ADDRS_SUPPORTED 64
u16 usr_addr_count;
u16 mc_addr_count;
usr_addr_t usr_addrs[MAX_ADDRS_SUPPORTED];
u16 m_cast_flg;
u16 all_multi_pos;
u16 promisc_flg;
u16 tx_pkt_count;
u16 rx_pkt_count;
u16 tx_err_count;
u16 rx_err_count;
#if DEBUG_ON
u64 rxpkt_bytes;
u64 txpkt_bytes;
int int_cnt;
int rxint_cnt;
int txint_cnt;
u64 rxpkt_cnt;
#endif
/* Place holders for the virtual and physical addresses of
* all the Rx Blocks
*/
struct rx_block_info
rx_blocks[MAX_RX_RINGS][MAX_RX_BLOCKS_PER_RING];
int block_count[MAX_RX_RINGS];
int pkt_cnt[MAX_RX_RINGS];
/* Id timer, used to blink NIC to physically identify NIC. */
struct timer_list id_timer;
/* Restart timer, used to restart NIC if the device is stuck and
* a schedule task that will set the correct Link state once the
* NIC's PHY has stabilized after a state change.
*/
#ifdef INIT_TQUEUE
struct tq_struct rst_timer_task;
struct tq_struct set_link_task;
#else
struct work_struct rst_timer_task;
struct work_struct set_link_task;
#endif
/* Flag that can be used to turn on or turn off the Rx checksum
* offload feature.
*/
int rx_csum;
/* after blink, the adapter must be restored with original
* values.
*/
u64 adapt_ctrl_org;
/* Last known link state. */
u16 last_link_state;
#define LINK_DOWN 1
#define LINK_UP 2
} nic_t;
#define RESET_ERROR 1;
#define CMD_ERROR 2;
/* Default Tunable parameters of the NIC. */
#define DEFAULT_FIFO_LEN 4096
#define SMALL_RXD_CNT 40 * (MAX_RXDS_PER_BLOCK+1)
#define LARGE_RXD_CNT 100 * (MAX_RXDS_PER_BLOCK+1)
/* OS related system calls */
#ifndef readq
static inline u64 readq(void *addr)
{
u64 ret = 0;
ret = readl(addr + 4);
(u64) ret <<= 32;
(u64) ret |= readl(addr);
return ret;
}
#endif
#ifndef writeq
static inline void writeq(u64 val, void *addr)
{
writel((u32) (val), addr);
writel((u32) (val >> 32), (addr + 4));
}
#endif
/* Interrupt related values of Xena */
#define ENABLE_INTRS 1
#define DISABLE_INTRS 2
/* Highest level interrupt blocks */
#define TX_PIC_INTR (0x0001<<0)
#define TX_DMA_INTR (0x0001<<1)
#define TX_MAC_INTR (0x0001<<2)
#define TX_XGXS_INTR (0x0001<<3)
#define TX_TRAFFIC_INTR (0x0001<<4)
#define RX_PIC_INTR (0x0001<<5)
#define RX_DMA_INTR (0x0001<<6)
#define RX_MAC_INTR (0x0001<<7)
#define RX_XGXS_INTR (0x0001<<8)
#define RX_TRAFFIC_INTR (0x0001<<9)
#define MC_INTR (0x0001<<10)
#define ENA_ALL_INTRS ( TX_PIC_INTR | \
TX_DMA_INTR | \
TX_MAC_INTR | \
TX_XGXS_INTR | \
TX_TRAFFIC_INTR | \
RX_PIC_INTR | \
RX_DMA_INTR | \
RX_MAC_INTR | \
RX_XGXS_INTR | \
RX_TRAFFIC_INTR | \
MC_INTR )
/* Interrupt masks for the general interrupt mask register */
#define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL
#define TXPIC_INT_M BIT(0)
#define TXDMA_INT_M BIT(1)
#define TXMAC_INT_M BIT(2)
#define TXXGXS_INT_M BIT(3)
#define TXTRAFFIC_INT_M BIT(8)
#define PIC_RX_INT_M BIT(32)
#define RXDMA_INT_M BIT(33)
#define RXMAC_INT_M BIT(34)
#define MC_INT_M BIT(35)
#define RXXGXS_INT_M BIT(36)
#define RXTRAFFIC_INT_M BIT(40)
/* PIC level Interrupts TODO*/
/* DMA level Inressupts */
#define TXDMA_PFC_INT_M BIT(0)
/* PFC block interrupts */
#define PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO full */
/*
* Prototype declaration.
*/
static int __devinit s2io_init_nic(struct pci_dev *pdev,
const struct pci_device_id *pre);
static void __exit s2io_rem_nic(struct pci_dev *pdev);
static int initSharedMem(struct s2io_nic *sp);
static void freeSharedMem(struct s2io_nic *sp);
static int initNic(struct s2io_nic *nic);
#ifndef CONFIG_S2IO_NAPI
static void rxIntrHandler(struct s2io_nic *sp);
#endif
static void txIntrHandler(struct s2io_nic *sp);
static void alarmIntrHandler(struct s2io_nic *sp);
static int s2io_starter(void);
void s2io_closer(void);
static void s2io_tx_watchdog(struct net_device *dev);
static void s2io_tasklet(unsigned long dev_addr);
static void s2io_set_multicast(struct net_device *dev);
static int rxOsmHandler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no);
void s2io_link(nic_t * sp, int link);
void s2io_reset(nic_t * sp);
#ifdef CONFIG_S2IO_NAPI
static int s2io_poll(struct net_device *dev, int *budget);
#endif
static void s2io_init_pci(nic_t * sp);
int s2io_set_mac_addr(struct net_device *dev, u8 * addr);
static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs);
static int verify_xena_quiescence(u64 val64, int flag);
static struct ethtool_ops netdev_ethtool_ops;
#endif /* _S2IO_H */
include/linux/pci_ids.h
View file @ 0b19c1e5
......@@ -1871,6 +1871,10 @@
#define PCI_DEVICE_ID_ALTIMA_AC9100 0x03ea
#define PCI_DEVICE_ID_ALTIMA_AC1003 0x03eb
#define PCI_VENDOR_ID_S2IO 0x17d5
#define PCI_DEVICE_ID_S2IO_WIN 0x5731
#define PCI_DEVICE_ID_S2IO_UNI 0x5831
#define PCI_VENDOR_ID_SYMPHONY 0x1c1c
#define PCI_DEVICE_ID_SYMPHONY_101 0x0001
......
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