ASoC: Fix FLL reference clock division setup in WM8993

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

ASoC: Fix FLL reference clock division setup in WM8993
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
0c11f655 · Mark Brown · 8aa2df53 · 0c11f655
Commit 0c11f655 authored Jul 17, 2009 by Mark Brown
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sound/soc/codecs/wm8993.c sound/soc/codecs/wm8993.c +2 -0

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--- a/sound/soc/codecs/wm8993.c
+++ b/sound/soc/codecs/wm8993.c
@@ -345,8 +345,10 @@ static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,

 	/* Fref must be <=13.5MHz */
 	div = 1;
+	fll_div->fll_clk_ref_div = 0;
 	while ((Fref / div) > 13500000) {
 		div *= 2;
+		fll_div->fll_clk_ref_div++;

 		if (div > 8) {
 			pr_err("Can't scale %dMHz input down to <=13.5MHz\n",