Commit 0da63bbb authored by Christian König's avatar Christian König Committed by Alex Deucher

drm/amdgpu: add PASID mapping for GMC v7

This way we can see the PASID in VM faults.
Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarChunming Zhou <david1.zhou@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9096d6e5
...@@ -24,7 +24,7 @@ ...@@ -24,7 +24,7 @@
#ifndef __CIK_H__ #ifndef __CIK_H__
#define __CIK_H__ #define __CIK_H__
#define CIK_FLUSH_GPU_TLB_NUM_WREG 2 #define CIK_FLUSH_GPU_TLB_NUM_WREG 3
void cik_srbm_select(struct amdgpu_device *adev, void cik_srbm_select(struct amdgpu_device *adev,
u32 me, u32 pipe, u32 queue, u32 vmid); u32 me, u32 pipe, u32 queue, u32 vmid);
......
...@@ -447,6 +447,8 @@ static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, ...@@ -447,6 +447,8 @@ static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8; reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
/* bits 0-15 are the VM contexts0-15 */ /* bits 0-15 are the VM contexts0-15 */
amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
......
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