Commit 130bce3a authored by Rander Wang's avatar Rander Wang Committed by Takashi Iwai

ALSA: hdac: clear link output stream mapping

Fix potential DMA hang upon starting playback on devices in HDA mode
on Intel platforms (Gemini Lake/Whiskey Lake/Comet Lake/Ice Lake). It
doesn't affect platforms before Gemini Lake or any Intel device in
non-HDA mode.

The reset value for the LOSDIV register is all output streams valid.
Clear this register to invalidate non-existent streams when the bus
is powered up.
Signed-off-by: default avatarRander Wang <rander.wang@linux.intel.com>
Signed-off-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20190930142945.7805-1-pierre-louis.bossart@linux.intel.comSigned-off-by: default avatarTakashi Iwai <tiwai@suse.de>
parent 1099f484
...@@ -264,6 +264,9 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; ...@@ -264,6 +264,9 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
#define AZX_REG_ML_LOUTPAY 0x20 #define AZX_REG_ML_LOUTPAY 0x20
#define AZX_REG_ML_LINPAY 0x30 #define AZX_REG_ML_LINPAY 0x30
/* bit0 is reserved, with BIT(1) mapping to stream1 */
#define ML_LOSIDV_STREAM_MASK 0xFFFE
#define ML_LCTL_SCF_MASK 0xF #define ML_LCTL_SCF_MASK 0xF
#define AZX_MLCTL_SPA (0x1 << 16) #define AZX_MLCTL_SPA (0x1 << 16)
#define AZX_MLCTL_CPA (0x1 << 23) #define AZX_MLCTL_CPA (0x1 << 23)
......
...@@ -270,6 +270,11 @@ int snd_hdac_ext_bus_link_get(struct hdac_bus *bus, ...@@ -270,6 +270,11 @@ int snd_hdac_ext_bus_link_get(struct hdac_bus *bus,
ret = snd_hdac_ext_bus_link_power_up(link); ret = snd_hdac_ext_bus_link_power_up(link);
/*
* clear the register to invalidate all the output streams
*/
snd_hdac_updatew(link->ml_addr, AZX_REG_ML_LOSIDV,
ML_LOSIDV_STREAM_MASK, 0);
/* /*
* wait for 521usec for codec to report status * wait for 521usec for codec to report status
* HDA spec section 4.3 - Codec Discovery * HDA spec section 4.3 - Codec Discovery
......
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