Commit 143b11c0 authored by David S. Miller's avatar David S. Miller
parents af01d537 18c8adeb
...@@ -144,6 +144,7 @@ struct ath_desc { ...@@ -144,6 +144,7 @@ struct ath_desc {
#define ATH9K_TXDESC_EXT_AND_CTL 0x0080 #define ATH9K_TXDESC_EXT_AND_CTL 0x0080
#define ATH9K_TXDESC_VMF 0x0100 #define ATH9K_TXDESC_VMF 0x0100
#define ATH9K_TXDESC_FRAG_IS_ON 0x0200 #define ATH9K_TXDESC_FRAG_IS_ON 0x0200
#define ATH9K_TXDESC_CAB 0x0400
#define ATH9K_RXDESC_INTREQ 0x0020 #define ATH9K_RXDESC_INTREQ 0x0020
...@@ -564,8 +565,6 @@ enum ath9k_cipher { ...@@ -564,8 +565,6 @@ enum ath9k_cipher {
#define CTL_5GHT40 8 #define CTL_5GHT40 8
#define AR_EEPROM_MAC(i) (0x1d+(i)) #define AR_EEPROM_MAC(i) (0x1d+(i))
#define EEP_SCALE 100
#define EEP_DELTA 10
#define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
#define AR_EEPROM_RFSILENT_GPIO_SEL_S 2 #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
...@@ -606,9 +605,6 @@ struct ath9k_country_entry { ...@@ -606,9 +605,6 @@ struct ath9k_country_entry {
#define REG_CLR_BIT(_a, _r, _f) \ #define REG_CLR_BIT(_a, _r, _f) \
REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f) REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
#define ATH9K_COMP_BUF_MAX_SIZE 9216
#define ATH9K_COMP_BUF_ALIGN_SIZE 512
#define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 #define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
#define INIT_AIFS 2 #define INIT_AIFS 2
...@@ -632,12 +628,6 @@ struct ath9k_country_entry { ...@@ -632,12 +628,6 @@ struct ath9k_country_entry {
(IEEE80211_WEP_IVLEN + \ (IEEE80211_WEP_IVLEN + \
IEEE80211_WEP_KIDLEN + \ IEEE80211_WEP_KIDLEN + \
IEEE80211_WEP_CRCLEN)) IEEE80211_WEP_CRCLEN))
#define IEEE80211_MAX_LEN (2300 + FCS_LEN + \
(IEEE80211_WEP_IVLEN + \
IEEE80211_WEP_KIDLEN + \
IEEE80211_WEP_CRCLEN))
#define MAX_REG_ADD_COUNT 129
#define MAX_RATE_POWER 63 #define MAX_RATE_POWER 63
enum ath9k_power_mode { enum ath9k_power_mode {
...@@ -707,13 +697,6 @@ enum phytype { ...@@ -707,13 +697,6 @@ enum phytype {
}; };
#define PHY_CCK PHY_DS #define PHY_CCK PHY_DS
enum start_adhoc_option {
START_ADHOC_NO_11A,
START_ADHOC_PER_11D,
START_ADHOC_IN_11A,
START_ADHOC_IN_11B,
};
enum ath9k_tp_scale { enum ath9k_tp_scale {
ATH9K_TP_SCALE_MAX = 0, ATH9K_TP_SCALE_MAX = 0,
ATH9K_TP_SCALE_50, ATH9K_TP_SCALE_50,
...@@ -769,14 +752,11 @@ struct ath9k_node_stats { ...@@ -769,14 +752,11 @@ struct ath9k_node_stats {
#define ATH9K_RSSI_EP_MULTIPLIER (1<<7) #define ATH9K_RSSI_EP_MULTIPLIER (1<<7)
enum ath9k_gpio_output_mux_type { #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
ATH9K_GPIO_OUTPUT_MUX_AS_OUTPUT, #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
ATH9K_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED, #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
ATH9K_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED, #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
ATH9K_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED, #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
ATH9K_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED,
ATH9K_GPIO_OUTPUT_MUX_NUM_ENTRIES
};
enum { enum {
ATH9K_RESET_POWER_ON, ATH9K_RESET_POWER_ON,
...@@ -790,19 +770,20 @@ struct ath_hal { ...@@ -790,19 +770,20 @@ struct ath_hal {
u32 ah_magic; u32 ah_magic;
u16 ah_devid; u16 ah_devid;
u16 ah_subvendorid; u16 ah_subvendorid;
struct ath_softc *ah_sc;
void __iomem *ah_sh;
u16 ah_countryCode;
u32 ah_macVersion; u32 ah_macVersion;
u16 ah_macRev; u16 ah_macRev;
u16 ah_phyRev; u16 ah_phyRev;
u16 ah_analog5GhzRev; u16 ah_analog5GhzRev;
u16 ah_analog2GhzRev; u16 ah_analog2GhzRev;
u8 ah_decompMask[ATH9K_DECOMP_MASK_SIZE];
u32 ah_flags; void __iomem *ah_sh;
struct ath_softc *ah_sc;
enum ath9k_opmode ah_opmode; enum ath9k_opmode ah_opmode;
struct ath9k_ops_config ah_config; struct ath9k_ops_config ah_config;
struct ath9k_hw_capabilities ah_caps; struct ath9k_hw_capabilities ah_caps;
u16 ah_countryCode;
u32 ah_flags;
int16_t ah_powerLimit; int16_t ah_powerLimit;
u16 ah_maxPowerLevel; u16 ah_maxPowerLevel;
u32 ah_tpScale; u32 ah_tpScale;
...@@ -812,15 +793,16 @@ struct ath_hal { ...@@ -812,15 +793,16 @@ struct ath_hal {
u16 ah_currentRD5G; u16 ah_currentRD5G;
u16 ah_currentRD2G; u16 ah_currentRD2G;
char ah_iso[4]; char ah_iso[4];
enum start_adhoc_option ah_adHocMode;
bool ah_commonMode;
struct ath9k_channel ah_channels[150]; struct ath9k_channel ah_channels[150];
u32 ah_nchan;
struct ath9k_channel *ah_curchan; struct ath9k_channel *ah_curchan;
u32 ah_nchan;
u16 ah_rfsilent; u16 ah_rfsilent;
bool ah_rfkillEnabled; bool ah_rfkillEnabled;
bool ah_isPciExpress; bool ah_isPciExpress;
u16 ah_txTrigLevel; u16 ah_txTrigLevel;
#ifndef ATH_NF_PER_CHAN #ifndef ATH_NF_PER_CHAN
struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
#endif #endif
...@@ -853,7 +835,7 @@ bool ath9k_regd_init_channels(struct ath_hal *ah, ...@@ -853,7 +835,7 @@ bool ath9k_regd_init_channels(struct ath_hal *ah,
u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags); u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags);
enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah,
enum ath9k_int ints); enum ath9k_int ints);
bool ath9k_hw_reset(struct ath_hal *ah, enum ath9k_opmode opmode, bool ath9k_hw_reset(struct ath_hal *ah,
struct ath9k_channel *chan, struct ath9k_channel *chan,
enum ath9k_ht_macmode macmode, enum ath9k_ht_macmode macmode,
u8 txchainmask, u8 rxchainmask, u8 txchainmask, u8 rxchainmask,
...@@ -1018,4 +1000,7 @@ void ath9k_hw_get_channel_centers(struct ath_hal *ah, ...@@ -1018,4 +1000,7 @@ void ath9k_hw_get_channel_centers(struct ath_hal *ah,
bool ath9k_get_channel_edges(struct ath_hal *ah, bool ath9k_get_channel_edges(struct ath_hal *ah,
u16 flags, u16 *low, u16 flags, u16 *low,
u16 *high); u16 *high);
void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
u32 ah_signal_type);
void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 value);
#endif #endif
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...@@ -314,9 +314,6 @@ struct ar5416_desc { ...@@ -314,9 +314,6 @@ struct ar5416_desc {
#define RXSTATUS_RATE(ah, ads) (AR_SREV_5416_V20_OR_LATER(ah) ? \ #define RXSTATUS_RATE(ah, ads) (AR_SREV_5416_V20_OR_LATER(ah) ? \
MS(ads->ds_rxstatus0, AR_RxRate) : \ MS(ads->ds_rxstatus0, AR_RxRate) : \
(ads->ds_rxstatus3 >> 2) & 0xFF) (ads->ds_rxstatus3 >> 2) & 0xFF)
#define RXSTATUS_DUPLICATE(ah, ads) (AR_SREV_5416_V20_OR_LATER(ah) ? \
MS(ads->ds_rxstatus3, AR_Parallel40) : \
(ads->ds_rxstatus3 >> 10) & 0x1)
#define set11nTries(_series, _index) \ #define set11nTries(_series, _index) \
(SM((_series)[_index].Tries, AR_XmitDataTries##_index)) (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
...@@ -346,9 +343,6 @@ struct ar5416_desc { ...@@ -346,9 +343,6 @@ struct ar5416_desc {
#define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1) #define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1)
#define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD #define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD
#define NUM_CORNER_FIX_BITS_2133 7
#define CCK_OFDM_GAIN_DELTA 15
struct ar5416AniState { struct ar5416AniState {
struct ath9k_channel c; struct ath9k_channel c;
u8 noiseImmunityLevel; u8 noiseImmunityLevel;
...@@ -377,9 +371,6 @@ struct ar5416AniState { ...@@ -377,9 +371,6 @@ struct ar5416AniState {
}; };
#define HAL_PROCESS_ANI 0x00000001 #define HAL_PROCESS_ANI 0x00000001
#define HAL_RADAR_EN 0x80000000
#define HAL_AR_EN 0x40000000
#define DO_ANI(ah) \ #define DO_ANI(ah) \
((AH5416(ah)->ah_procPhyErr & HAL_PROCESS_ANI)) ((AH5416(ah)->ah_procPhyErr & HAL_PROCESS_ANI))
...@@ -425,7 +416,6 @@ struct ar5416Stats { ...@@ -425,7 +416,6 @@ struct ar5416Stats {
#define AR5416_EEP_MINOR_VER_7 0x7 #define AR5416_EEP_MINOR_VER_7 0x7
#define AR5416_EEP_MINOR_VER_9 0x9 #define AR5416_EEP_MINOR_VER_9 0x9
#define AR5416_EEP_START_LOC 256
#define AR5416_NUM_5G_CAL_PIERS 8 #define AR5416_NUM_5G_CAL_PIERS 8
#define AR5416_NUM_2G_CAL_PIERS 4 #define AR5416_NUM_2G_CAL_PIERS 4
#define AR5416_NUM_5G_20_TARGET_POWERS 8 #define AR5416_NUM_5G_20_TARGET_POWERS 8
...@@ -441,25 +431,10 @@ struct ar5416Stats { ...@@ -441,25 +431,10 @@ struct ar5416Stats {
#define AR5416_EEPROM_MODAL_SPURS 5 #define AR5416_EEPROM_MODAL_SPURS 5
#define AR5416_MAX_RATE_POWER 63 #define AR5416_MAX_RATE_POWER 63
#define AR5416_NUM_PDADC_VALUES 128 #define AR5416_NUM_PDADC_VALUES 128
#define AR5416_NUM_RATES 16
#define AR5416_BCHAN_UNUSED 0xFF #define AR5416_BCHAN_UNUSED 0xFF
#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
#define AR5416_EEPMISC_BIG_ENDIAN 0x01
#define AR5416_MAX_CHAINS 3 #define AR5416_MAX_CHAINS 3
#define AR5416_ANT_16S 25
#define AR5416_NUM_ANT_CHAIN_FIELDS 7
#define AR5416_NUM_ANT_COMMON_FIELDS 4
#define AR5416_SIZE_ANT_CHAIN_FIELD 3
#define AR5416_SIZE_ANT_COMMON_FIELD 4
#define AR5416_ANT_CHAIN_MASK 0x7
#define AR5416_ANT_COMMON_MASK 0xf
#define AR5416_CHAIN_0_IDX 0
#define AR5416_CHAIN_1_IDX 1
#define AR5416_CHAIN_2_IDX 2
#define AR5416_PWR_TABLE_OFFSET -5 #define AR5416_PWR_TABLE_OFFSET -5
#define AR5416_LEGACY_CHAINMASK 1
enum eeprom_param { enum eeprom_param {
EEP_NFTHRESH_5, EEP_NFTHRESH_5,
...@@ -696,25 +671,29 @@ struct hal_cal_list { ...@@ -696,25 +671,29 @@ struct hal_cal_list {
struct ath_hal_5416 { struct ath_hal_5416 {
struct ath_hal ah; struct ath_hal ah;
struct ar5416_eeprom ah_eeprom; struct ar5416_eeprom ah_eeprom;
struct ar5416Stats ah_stats;
struct ath9k_tx_queue_info ah_txq[ATH9K_NUM_TX_QUEUES];
void __iomem *ah_cal_mem;
u8 ah_macaddr[ETH_ALEN]; u8 ah_macaddr[ETH_ALEN];
u8 ah_bssid[ETH_ALEN]; u8 ah_bssid[ETH_ALEN];
u8 ah_bssidmask[ETH_ALEN]; u8 ah_bssidmask[ETH_ALEN];
u16 ah_assocId; u16 ah_assocId;
int16_t ah_curchanRadIndex; int16_t ah_curchanRadIndex;
u32 ah_maskReg; u32 ah_maskReg;
struct ar5416Stats ah_stats;
u32 ah_txDescMask;
u32 ah_txOkInterruptMask; u32 ah_txOkInterruptMask;
u32 ah_txErrInterruptMask; u32 ah_txErrInterruptMask;
u32 ah_txDescInterruptMask; u32 ah_txDescInterruptMask;
u32 ah_txEolInterruptMask; u32 ah_txEolInterruptMask;
u32 ah_txUrnInterruptMask; u32 ah_txUrnInterruptMask;
struct ath9k_tx_queue_info ah_txq[ATH9K_NUM_TX_QUEUES];
enum ath9k_power_mode ah_powerMode;
bool ah_chipFullSleep; bool ah_chipFullSleep;
u32 ah_atimWindow; u32 ah_atimWindow;
enum ath9k_ant_setting ah_diversityControl;
u16 ah_antennaSwitchSwap; u16 ah_antennaSwitchSwap;
enum ath9k_power_mode ah_powerMode;
enum ath9k_ant_setting ah_diversityControl;
/* Calibration */
enum hal_cal_types ah_suppCals; enum hal_cal_types ah_suppCals;
struct hal_cal_list ah_iqCalData; struct hal_cal_list ah_iqCalData;
struct hal_cal_list ah_adcGainCalData; struct hal_cal_list ah_adcGainCalData;
...@@ -751,16 +730,16 @@ struct ath_hal_5416 { ...@@ -751,16 +730,16 @@ struct ath_hal_5416 {
int32_t sign[AR5416_MAX_CHAINS]; int32_t sign[AR5416_MAX_CHAINS];
} ah_Meas3; } ah_Meas3;
u16 ah_CalSamples; u16 ah_CalSamples;
u32 ah_tx6PowerInHalfDbm;
u32 ah_staId1Defaults; u32 ah_staId1Defaults;
u32 ah_miscMode; u32 ah_miscMode;
bool ah_tpcEnabled;
u32 ah_beaconInterval;
enum { enum {
AUTO_32KHZ, AUTO_32KHZ,
USE_32KHZ, USE_32KHZ,
DONT_USE_32KHZ, DONT_USE_32KHZ,
} ah_enable32kHzClock; } ah_enable32kHzClock;
/* RF */
u32 *ah_analogBank0Data; u32 *ah_analogBank0Data;
u32 *ah_analogBank1Data; u32 *ah_analogBank1Data;
u32 *ah_analogBank2Data; u32 *ah_analogBank2Data;
...@@ -770,8 +749,9 @@ struct ath_hal_5416 { ...@@ -770,8 +749,9 @@ struct ath_hal_5416 {
u32 *ah_analogBank7Data; u32 *ah_analogBank7Data;
u32 *ah_addac5416_21; u32 *ah_addac5416_21;
u32 *ah_bank6Temp; u32 *ah_bank6Temp;
u32 ah_ofdmTxPower;
int16_t ah_txPowerIndexOffset; int16_t ah_txPowerIndexOffset;
u32 ah_beaconInterval;
u32 ah_slottime; u32 ah_slottime;
u32 ah_acktimeout; u32 ah_acktimeout;
u32 ah_ctstimeout; u32 ah_ctstimeout;
...@@ -780,7 +760,8 @@ struct ath_hal_5416 { ...@@ -780,7 +760,8 @@ struct ath_hal_5416 {
u32 ah_gpioSelect; u32 ah_gpioSelect;
u32 ah_polarity; u32 ah_polarity;
u32 ah_gpioBit; u32 ah_gpioBit;
bool ah_eepEnabled;
/* ANI */
u32 ah_procPhyErr; u32 ah_procPhyErr;
bool ah_hasHwPhyCounters; bool ah_hasHwPhyCounters;
u32 ah_aniPeriod; u32 ah_aniPeriod;
...@@ -790,18 +771,14 @@ struct ath_hal_5416 { ...@@ -790,18 +771,14 @@ struct ath_hal_5416 {
int ah_coarseHigh[5]; int ah_coarseHigh[5];
int ah_coarseLow[5]; int ah_coarseLow[5];
int ah_firpwr[5]; int ah_firpwr[5];
u16 ah_ratesArray[16]; enum ath9k_ani_cmd ah_ani_function;
u32 ah_intrTxqs; u32 ah_intrTxqs;
bool ah_intrMitigation; bool ah_intrMitigation;
u32 ah_cycleCount;
u32 ah_ctlBusy;
u32 ah_extBusy;
enum ath9k_ht_extprotspacing ah_extprotspacing; enum ath9k_ht_extprotspacing ah_extprotspacing;
u8 ah_txchainmask; u8 ah_txchainmask;
u8 ah_rxchainmask; u8 ah_rxchainmask;
int ah_hwp;
void __iomem *ah_cal_mem;
enum ath9k_ani_cmd ah_ani_function;
struct ar5416IniArray ah_iniModes; struct ar5416IniArray ah_iniModes;
struct ar5416IniArray ah_iniCommon; struct ar5416IniArray ah_iniCommon;
struct ar5416IniArray ah_iniBank0; struct ar5416IniArray ah_iniBank0;
...@@ -820,10 +797,6 @@ struct ath_hal_5416 { ...@@ -820,10 +797,6 @@ struct ath_hal_5416 {
#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
#define IS_5416_EMU(ah) \
((ah->ah_devid == AR5416_DEVID_EMU) || \
(ah->ah_devid == AR5416_DEVID_EMU_PCIE))
#define ar5416RfDetach(ah) do { \ #define ar5416RfDetach(ah) do { \
if (AH5416(ah)->ah_rfHal.rfDetach != NULL) \ if (AH5416(ah)->ah_rfHal.rfDetach != NULL) \
AH5416(ah)->ah_rfHal.rfDetach(ah); \ AH5416(ah)->ah_rfHal.rfDetach(ah); \
...@@ -852,10 +825,6 @@ struct ath_hal_5416 { ...@@ -852,10 +825,6 @@ struct ath_hal_5416 {
#define COEF_SCALE_S 24 #define COEF_SCALE_S 24
#define HT40_CHANNEL_CENTER_SHIFT 10 #define HT40_CHANNEL_CENTER_SHIFT 10
#define ar5416CheckOpMode(_opmode) \
((_opmode == ATH9K_M_STA) || (_opmode == ATH9K_M_IBSS) || \
(_opmode == ATH9K_M_HOSTAP) || (_opmode == ATH9K_M_MONITOR))
#define AR5416_EEPROM_MAGIC_OFFSET 0x0 #define AR5416_EEPROM_MAGIC_OFFSET 0x0
#define AR5416_EEPROM_S 2 #define AR5416_EEPROM_S 2
...@@ -871,11 +840,6 @@ struct ath_hal_5416 { ...@@ -871,11 +840,6 @@ struct ath_hal_5416 {
(((_txchainmask >> 2) & 1) + \ (((_txchainmask >> 2) & 1) + \
((_txchainmask >> 1) & 1) + (_txchainmask & 1)) ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
#define IS_EEP_MINOR_V3(_ahp) \
(ath9k_hw_get_eeprom((_ahp), EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_3)
#define FIXED_CCA_THRESHOLD 15
#ifdef __BIG_ENDIAN #ifdef __BIG_ENDIAN
#define AR5416_EEPROM_MAGIC 0x5aa5 #define AR5416_EEPROM_MAGIC 0x5aa5
#else #else
...@@ -910,8 +874,6 @@ struct ath_hal_5416 { ...@@ -910,8 +874,6 @@ struct ath_hal_5416 {
#define AR_GPIOD_MASK 0x00001FFF #define AR_GPIOD_MASK 0x00001FFF
#define AR_GPIO_BIT(_gpio) (1 << (_gpio)) #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
#define MAX_ANALOG_START 319
#define HAL_EP_RND(x, mul) \ #define HAL_EP_RND(x, mul) \
((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
#define BEACON_RSSI(ahp) \ #define BEACON_RSSI(ahp) \
...@@ -923,8 +885,6 @@ struct ath_hal_5416 { ...@@ -923,8 +885,6 @@ struct ath_hal_5416 {
#define AH_TIMEOUT 100000 #define AH_TIMEOUT 100000
#define AH_TIME_QUANTUM 10 #define AH_TIME_QUANTUM 10
#define IS(_c, _f) (((_c)->channelFlags & _f) || 0)
#define AR_KEYTABLE_SIZE 128 #define AR_KEYTABLE_SIZE 128
#define POWER_UP_TIME 200000 #define POWER_UP_TIME 200000
......
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...@@ -847,9 +847,9 @@ void ath_rate_newstate(struct ath_softc *sc, struct ath_vap *avp) ...@@ -847,9 +847,9 @@ void ath_rate_newstate(struct ath_softc *sc, struct ath_vap *avp)
/* For half and quarter rate channles use different /* For half and quarter rate channles use different
* rate tables * rate tables
*/ */
if (sc->sc_curchan.channelFlags & CHANNEL_HALF) if (sc->sc_ah->ah_curchan->channelFlags & CHANNEL_HALF)
ar5416_sethalf_ratetable(asc); ar5416_sethalf_ratetable(asc);
else if (sc->sc_curchan.channelFlags & CHANNEL_QUARTER) else if (sc->sc_ah->ah_curchan->channelFlags & CHANNEL_QUARTER)
ar5416_setquarter_ratetable(asc); ar5416_setquarter_ratetable(asc);
else /* full rate */ else /* full rate */
ar5416_setfull_ratetable(asc); ar5416_setfull_ratetable(asc);
...@@ -1141,7 +1141,7 @@ static void ath_rc_ratefind(struct ath_softc *sc, ...@@ -1141,7 +1141,7 @@ static void ath_rc_ratefind(struct ath_softc *sc,
/* /*
* Return the Tx rate series. * Return the Tx rate series.
*/ */
void ath_rate_findrate(struct ath_softc *sc, static void ath_rate_findrate(struct ath_softc *sc,
struct ath_rate_node *ath_rc_priv, struct ath_rate_node *ath_rc_priv,
int num_tries, int num_tries,
int num_rates, int num_rates,
...@@ -1152,7 +1152,8 @@ void ath_rate_findrate(struct ath_softc *sc, ...@@ -1152,7 +1152,8 @@ void ath_rate_findrate(struct ath_softc *sc,
{ {
struct ath_vap *avp = ath_rc_priv->avp; struct ath_vap *avp = ath_rc_priv->avp;
DPRINTF(sc, ATH_DBG_RATE, "%s", __func__); DPRINTF(sc, ATH_DBG_RATE, "%s\n", __func__);
if (!num_rates || !num_tries) if (!num_rates || !num_tries)
return; return;
...@@ -1174,8 +1175,7 @@ void ath_rate_findrate(struct ath_softc *sc, ...@@ -1174,8 +1175,7 @@ void ath_rate_findrate(struct ath_softc *sc,
unsigned int mcs; unsigned int mcs;
u8 series_rix = 0; u8 series_rix = 0;
series[idx].tries = series[idx].tries = IEEE80211_RATE_IDX_ENTRY(
IEEE80211_RATE_IDX_ENTRY(
avp->av_config.av_fixed_retryset, idx); avp->av_config.av_fixed_retryset, idx);
mcs = IEEE80211_RATE_IDX_ENTRY( mcs = IEEE80211_RATE_IDX_ENTRY(
...@@ -1295,8 +1295,7 @@ static void ath_rc_update_ht(struct ath_softc *sc, ...@@ -1295,8 +1295,7 @@ static void ath_rc_update_ht(struct ath_softc *sc,
if (retries >= count) if (retries >= count)
retries = count - 1; retries = count - 1;
if (info_priv->n_bad_frames) { if (info_priv->n_bad_frames) {
/* new_PER = 7/8*old_PER + 1/8*(currentPER) */ /* new_PER = 7/8*old_PER + 1/8*(currentPER)
/*
* Assuming that n_frames is not 0. The current PER * Assuming that n_frames is not 0. The current PER
* from the retries is 100 * retries / (retries+1), * from the retries is 100 * retries / (retries+1),
* since the first retries attempts failed, and the * since the first retries attempts failed, and the
...@@ -1637,7 +1636,6 @@ static void ath_rc_update(struct ath_softc *sc, ...@@ -1637,7 +1636,6 @@ static void ath_rc_update(struct ath_softc *sc,
xretries, long_retry); xretries, long_retry);
} }
/* /*
* Process a tx descriptor for a completed transmit (success or failure). * Process a tx descriptor for a completed transmit (success or failure).
*/ */
...@@ -1651,8 +1649,8 @@ static void ath_rate_tx_complete(struct ath_softc *sc, ...@@ -1651,8 +1649,8 @@ static void ath_rate_tx_complete(struct ath_softc *sc,
struct ath_vap *avp; struct ath_vap *avp;
avp = rc_priv->avp; avp = rc_priv->avp;
if ((avp->av_config.av_fixed_rateset != IEEE80211_FIXED_RATE_NONE) if ((avp->av_config.av_fixed_rateset != IEEE80211_FIXED_RATE_NONE) ||
|| info_priv->tx.ts_status & ATH9K_TXERR_FILT) (info_priv->tx.ts_status & ATH9K_TXERR_FILT))
return; return;
if (info_priv->tx.ts_rssi > 0) { if (info_priv->tx.ts_rssi > 0) {
...@@ -1682,7 +1680,6 @@ static void ath_rate_tx_complete(struct ath_softc *sc, ...@@ -1682,7 +1680,6 @@ static void ath_rate_tx_complete(struct ath_softc *sc,
info_priv->tx.ts_longretry); info_priv->tx.ts_longretry);
} }
/* /*
* Update the SIB's rate control information * Update the SIB's rate control information
* *
...@@ -1701,8 +1698,8 @@ static void ath_rc_sib_update(struct ath_softc *sc, ...@@ -1701,8 +1698,8 @@ static void ath_rc_sib_update(struct ath_softc *sc,
struct ath_rate_softc *asc = (struct ath_rate_softc *)sc->sc_rc; struct ath_rate_softc *asc = (struct ath_rate_softc *)sc->sc_rc;
struct ath_rateset *rateset = negotiated_rates; struct ath_rateset *rateset = negotiated_rates;
u8 *ht_mcs = (u8 *)negotiated_htrates; u8 *ht_mcs = (u8 *)negotiated_htrates;
struct ath_tx_ratectrl *rate_ctrl = (struct ath_tx_ratectrl *) struct ath_tx_ratectrl *rate_ctrl =
(ath_rc_priv); (struct ath_tx_ratectrl *)ath_rc_priv;
u8 i, j, k, hi = 0, hthi = 0; u8 i, j, k, hi = 0, hthi = 0;
rate_table = (struct ath_rate_table *) rate_table = (struct ath_rate_table *)
...@@ -1824,7 +1821,8 @@ static void ath_setup_rates(struct ieee80211_local *local, struct sta_info *sta) ...@@ -1824,7 +1821,8 @@ static void ath_setup_rates(struct ieee80211_local *local, struct sta_info *sta)
struct ath_rate_node *rc_priv = sta->rate_ctrl_priv; struct ath_rate_node *rc_priv = sta->rate_ctrl_priv;
int i, j = 0; int i, j = 0;
DPRINTF(sc, ATH_DBG_RATE, "%s", __func__); DPRINTF(sc, ATH_DBG_RATE, "%s\n", __func__);
sband = local->hw.wiphy->bands[local->hw.conf.channel->band]; sband = local->hw.wiphy->bands[local->hw.conf.channel->band];
for (i = 0; i < sband->n_bitrates; i++) { for (i = 0; i < sband->n_bitrates; i++) {
if (sta->supp_rates[local->hw.conf.channel->band] & BIT(i)) { if (sta->supp_rates[local->hw.conf.channel->band] & BIT(i)) {
...@@ -1903,7 +1901,7 @@ static void ath_tx_aggr_resp(struct ath_softc *sc, ...@@ -1903,7 +1901,7 @@ static void ath_tx_aggr_resp(struct ath_softc *sc,
int state; int state;
DECLARE_MAC_BUF(mac); DECLARE_MAC_BUF(mac);
if (!sc->sc_txaggr) if (!(sc->sc_flags & SC_OP_TXAGGR))
return; return;
txtid = ATH_AN_2_TID(an, tidno); txtid = ATH_AN_2_TID(an, tidno);
...@@ -1944,7 +1942,7 @@ static void ath_get_rate(void *priv, struct net_device *dev, ...@@ -1944,7 +1942,7 @@ static void ath_get_rate(void *priv, struct net_device *dev,
struct ath_rate_node *ath_rc_priv; struct ath_rate_node *ath_rc_priv;
struct ath_node *an; struct ath_node *an;
struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
int is_probe, chk, ret; int is_probe = FALSE, chk, ret;
s8 lowest_idx; s8 lowest_idx;
__le16 fc = hdr->frame_control; __le16 fc = hdr->frame_control;
u8 *qc, tid; u8 *qc, tid;
...@@ -2035,6 +2033,7 @@ static void ath_rate_init(void *priv, void *priv_sta, ...@@ -2035,6 +2033,7 @@ static void ath_rate_init(void *priv, void *priv_sta,
struct ieee80211_hw *hw = local_to_hw(local); struct ieee80211_hw *hw = local_to_hw(local);
struct ieee80211_conf *conf = &local->hw.conf; struct ieee80211_conf *conf = &local->hw.conf;
struct ath_softc *sc = hw->priv; struct ath_softc *sc = hw->priv;
struct ath_rate_node *ath_rc_priv = priv_sta;
int i, j = 0; int i, j = 0;
DPRINTF(sc, ATH_DBG_RATE, "%s\n", __func__); DPRINTF(sc, ATH_DBG_RATE, "%s\n", __func__);
...@@ -2046,12 +2045,11 @@ static void ath_rate_init(void *priv, void *priv_sta, ...@@ -2046,12 +2045,11 @@ static void ath_rate_init(void *priv, void *priv_sta,
if (conf->flags & IEEE80211_CONF_SUPPORT_HT_MODE) { if (conf->flags & IEEE80211_CONF_SUPPORT_HT_MODE) {
for (i = 0; i < MCS_SET_SIZE; i++) { for (i = 0; i < MCS_SET_SIZE; i++) {
if (conf->ht_conf.supp_mcs_set[i/8] & (1<<(i%8))) if (conf->ht_conf.supp_mcs_set[i/8] & (1<<(i%8)))
((struct ath_rate_node *) ath_rc_priv->neg_ht_rates.rs_rates[j++] = i;
priv_sta)->neg_ht_rates.rs_rates[j++] = i;
if (j == ATH_RATE_MAX) if (j == ATH_RATE_MAX)
break; break;
} }
((struct ath_rate_node *)priv_sta)->neg_ht_rates.rs_nrates = j; ath_rc_priv->neg_ht_rates.rs_nrates = j;
} }
ath_rc_node_update(hw, priv_sta); ath_rc_node_update(hw, priv_sta);
} }
...@@ -2066,7 +2064,7 @@ static void *ath_rate_alloc(struct ieee80211_local *local) ...@@ -2066,7 +2064,7 @@ static void *ath_rate_alloc(struct ieee80211_local *local)
struct ieee80211_hw *hw = local_to_hw(local); struct ieee80211_hw *hw = local_to_hw(local);
struct ath_softc *sc = hw->priv; struct ath_softc *sc = hw->priv;
DPRINTF(sc, ATH_DBG_RATE, "%s", __func__); DPRINTF(sc, ATH_DBG_RATE, "%s\n", __func__);
return local->hw.priv; return local->hw.priv;
} }
...@@ -2081,14 +2079,17 @@ static void *ath_rate_alloc_sta(void *priv, gfp_t gfp) ...@@ -2081,14 +2079,17 @@ static void *ath_rate_alloc_sta(void *priv, gfp_t gfp)
struct ath_vap *avp = sc->sc_vaps[0]; struct ath_vap *avp = sc->sc_vaps[0];
struct ath_rate_node *rate_priv; struct ath_rate_node *rate_priv;
DPRINTF(sc, ATH_DBG_RATE, "%s", __func__); DPRINTF(sc, ATH_DBG_RATE, "%s\n", __func__);
rate_priv = ath_rate_node_alloc(avp, sc->sc_rc, gfp); rate_priv = ath_rate_node_alloc(avp, sc->sc_rc, gfp);
if (!rate_priv) { if (!rate_priv) {
DPRINTF(sc, ATH_DBG_FATAL, "%s:Unable to allocate" DPRINTF(sc, ATH_DBG_FATAL,
"private rate control structure", __func__); "%s: Unable to allocate private rc structure\n",
__func__);
return NULL; return NULL;
} }
ath_rc_sib_init(rate_priv); ath_rc_sib_init(rate_priv);
return rate_priv; return rate_priv;
} }
......
...@@ -71,9 +71,6 @@ enum ieee80211_fixed_rate_mode { ...@@ -71,9 +71,6 @@ enum ieee80211_fixed_rate_mode {
*/ */
#define IEEE80211_RATE_IDX_ENTRY(val, idx) (((val&(0xff<<(idx*8)))>>(idx*8))) #define IEEE80211_RATE_IDX_ENTRY(val, idx) (((val&(0xff<<(idx*8)))>>(idx*8)))
#define SHORT_PRE 1
#define LONG_PRE 0
#define WLAN_PHY_HT_20_SS WLAN_RC_PHY_HT_20_SS #define WLAN_PHY_HT_20_SS WLAN_RC_PHY_HT_20_SS
#define WLAN_PHY_HT_20_DS WLAN_RC_PHY_HT_20_DS #define WLAN_PHY_HT_20_DS WLAN_RC_PHY_HT_20_DS
#define WLAN_PHY_HT_20_DS_HGI WLAN_RC_PHY_HT_20_DS_HGI #define WLAN_PHY_HT_20_DS_HGI WLAN_RC_PHY_HT_20_DS_HGI
...@@ -135,50 +132,53 @@ enum { ...@@ -135,50 +132,53 @@ enum {
#define WLAN_RC_SGI_FLAG (0x04) #define WLAN_RC_SGI_FLAG (0x04)
#define WLAN_RC_HT_FLAG (0x08) #define WLAN_RC_HT_FLAG (0x08)
/* Index into the rate table */
#define INIT_RATE_MAX_20 23
#define INIT_RATE_MAX_40 40
#define RATE_TABLE_SIZE 64 #define RATE_TABLE_SIZE 64
/* XXX: Convert to kdoc */ /**
* struct ath_rate_table - Rate Control table
* @valid: valid for use in rate control
* @valid_single_stream: valid for use in rate control for
* single stream operation
* @phy: CCK/OFDM
* @ratekbps: rate in Kbits per second
* @user_ratekbps: user rate in Kbits per second
* @ratecode: rate that goes into HW descriptors
* @short_preamble: Mask for enabling short preamble in ratecode for CCK
* @dot11rate: value that goes into supported
* rates info element of MLME
* @ctrl_rate: Index of next lower basic rate, used for duration computation
* @max_4ms_framelen: maximum frame length(bytes) for tx duration
* @probe_interval: interval for rate control to probe for other rates
* @rssi_reduce_interval: interval for rate control to reduce rssi
* @initial_ratemax: initial ratemax value used in ath_rc_sib_update()
*/
struct ath_rate_table { struct ath_rate_table {
int rate_cnt; int rate_cnt;
struct { struct {
int valid; /* Valid for use in rate control */ int valid;
int valid_single_stream;/* Valid for use in rate control int valid_single_stream;
for single stream operation */ u8 phy;
u8 phy; /* CCK/OFDM/TURBO/XR */ u32 ratekbps;
u32 ratekbps; /* Rate in Kbits per second */ u32 user_ratekbps;
u32 user_ratekbps; /* User rate in KBits per second */ u8 ratecode;
u8 ratecode; /* rate that goes into u8 short_preamble;
hw descriptors */ u8 dot11rate;
u8 short_preamble; /* Mask for enabling short preamble u8 ctrl_rate;
in rate code for CCK */ int8_t rssi_ack_validmin;
u8 dot11rate; /* Value that goes into supported int8_t rssi_ack_deltamin;
rates info element of MLME */ u8 base_index;
u8 ctrl_rate; /* Index of next lower basic rate, u8 cw40index;
used for duration computation */ u8 sgi_index;
int8_t rssi_ack_validmin; /* Rate control related */ u8 ht_index;
int8_t rssi_ack_deltamin; /* Rate control related */ u32 max_4ms_framelen;
u8 base_index; /* base rate index */
u8 cw40index; /* 40cap rate index */
u8 sgi_index; /* shortgi rate index */
u8 ht_index; /* shortgi rate index */
u32 max_4ms_framelen; /* Maximum frame length(bytes)
for 4ms tx duration */
} info[RATE_TABLE_SIZE]; } info[RATE_TABLE_SIZE];
u32 probe_interval; /* interval for ratectrl to u32 probe_interval;
probe for other rates */ u32 rssi_reduce_interval;
u32 rssi_reduce_interval; /* interval for ratectrl u8 initial_ratemax;
to reduce RSSI */
u8 initial_ratemax; /* the initial ratemax value used
in ath_rc_sib_update() */
}; };
#define ATH_RC_PROBE_ALLOWED 0x00000001 #define ATH_RC_PROBE_ALLOWED 0x00000001
#define ATH_RC_MINRATE_LASTRATE 0x00000002 #define ATH_RC_MINRATE_LASTRATE 0x00000002
#define ATH_RC_SHORT_PREAMBLE 0x00000004
struct ath_rc_series { struct ath_rc_series {
u8 rix; u8 rix;
...@@ -205,38 +205,52 @@ struct ath_tx_ratectrl_state { ...@@ -205,38 +205,52 @@ struct ath_tx_ratectrl_state {
u8 per; /* recent estimate of packet error rate (%) */ u8 per; /* recent estimate of packet error rate (%) */
}; };
/**
* struct ath_tx_ratectrl - TX Rate control Information
* @state: RC state
* @rssi_last: last ACK rssi
* @rssi_last_lookup: last ACK rssi used for lookup
* @rssi_last_prev: previous last ACK rssi
* @rssi_last_prev2: 2nd previous last ACK rssi
* @rssi_sum_cnt: count of rssi_sum for averaging
* @rssi_sum_rate: rate that we are averaging
* @rssi_sum: running sum of rssi for averaging
* @probe_rate: rate we are probing at
* @rssi_time: msec timestamp for last ack rssi
* @rssi_down_time: msec timestamp for last down step
* @probe_time: msec timestamp for last probe
* @hw_maxretry_pktcnt: num of packets since we got HW max retry error
* @max_valid_rate: maximum number of valid rate
* @per_down_time: msec timestamp for last PER down step
* @valid_phy_ratecnt: valid rate count
* @rate_max_phy: phy index for the max rate
* @probe_interval: interval for ratectrl to probe for other rates
*/
struct ath_tx_ratectrl { struct ath_tx_ratectrl {
struct ath_tx_ratectrl_state state[MAX_TX_RATE_TBL]; /* state */ struct ath_tx_ratectrl_state state[MAX_TX_RATE_TBL];
int8_t rssi_last; /* last ack rssi */ int8_t rssi_last;
int8_t rssi_last_lookup; /* last ack rssi used for lookup */ int8_t rssi_last_lookup;
int8_t rssi_last_prev; /* previous last ack rssi */ int8_t rssi_last_prev;
int8_t rssi_last_prev2; /* 2nd previous last ack rssi */ int8_t rssi_last_prev2;
int32_t rssi_sum_cnt; /* count of rssi_sum for averaging */ int32_t rssi_sum_cnt;
int32_t rssi_sum_rate; /* rate that we are averaging */ int32_t rssi_sum_rate;
int32_t rssi_sum; /* running sum of rssi for averaging */ int32_t rssi_sum;
u32 valid_txrate_mask; /* mask of valid rates */ u8 rate_table_size;
u8 rate_table_size; /* rate table size */ u8 probe_rate;
u8 rate_max; /* max rate that has recently worked */ u32 rssi_time;
u8 probe_rate; /* rate we are probing at */ u32 rssi_down_time;
u32 rssi_time; /* msec timestamp for last ack rssi */ u32 probe_time;
u32 rssi_down_time; /* msec timestamp for last down step */ u8 hw_maxretry_pktcnt;
u32 probe_time; /* msec timestamp for last probe */ u8 max_valid_rate;
u8 hw_maxretry_pktcnt; /* num packets since we got u8 valid_rate_index[MAX_TX_RATE_TBL];
HW max retry error */ u32 per_down_time;
u8 max_valid_rate; /* maximum number of valid rate */
u8 valid_rate_index[MAX_TX_RATE_TBL]; /* valid rate index */
u32 per_down_time; /* msec timstamp for last
PER down step */
/* 11n state */ /* 11n state */
u8 valid_phy_ratecnt[WLAN_RC_PHY_MAX]; /* valid rate count */ u8 valid_phy_ratecnt[WLAN_RC_PHY_MAX];
u8 valid_phy_rateidx[WLAN_RC_PHY_MAX][MAX_TX_RATE_TBL]; u8 valid_phy_rateidx[WLAN_RC_PHY_MAX][MAX_TX_RATE_TBL];
u8 rc_phy_mode; u8 rc_phy_mode;
u8 rate_max_phy; /* Phy index for the max rate */ u8 rate_max_phy;
u32 rate_max_lastused; /* msec timstamp of when we u32 probe_interval;
last used rateMaxPhy */
u32 probe_interval; /* interval for ratectrl to probe
for other rates */
}; };
struct ath_rateset { struct ath_rateset {
...@@ -248,29 +262,32 @@ struct ath_rateset { ...@@ -248,29 +262,32 @@ struct ath_rateset {
struct ath_rate_softc { struct ath_rate_softc {
/* phy tables that contain rate control data */ /* phy tables that contain rate control data */
const void *hw_rate_table[ATH9K_MODE_MAX]; const void *hw_rate_table[ATH9K_MODE_MAX];
int fixedrix; /* -1 or index of fixed rate */
/* -1 or index of fixed rate */
int fixedrix;
}; };
/* per-node state */ /* per-node state */
struct ath_rate_node { struct ath_rate_node {
struct ath_tx_ratectrl tx_ratectrl; /* rate control state proper */ struct ath_tx_ratectrl tx_ratectrl;
u32 prev_data_rix; /* rate idx of last data frame */
/* rate idx of last data frame */
u32 prev_data_rix;
/* ht capabilities */
u8 ht_cap;
/* map of rate ix -> negotiated rate set ix */ /* When TRUE, only single stream Tx possible */
u8 rixmap[MAX_TX_RATE_TBL]; u8 single_stream;
/* map of ht rate ix -> negotiated rate set ix */ /* Negotiated rates */
u8 ht_rixmap[MAX_TX_RATE_TBL]; struct ath_rateset neg_rates;
u8 ht_cap; /* ht capabilities */ /* Negotiated HT rates */
u8 ant_tx; /* current transmit antenna */ struct ath_rateset neg_ht_rates;
u8 single_stream; /* When TRUE, only single struct ath_rate_softc *asc;
stream Tx possible */ struct ath_vap *avp;
struct ath_rateset neg_rates; /* Negotiated rates */
struct ath_rateset neg_ht_rates; /* Negotiated HT rates */
struct ath_rate_softc *asc; /* back pointer to atheros softc */
struct ath_vap *avp; /* back pointer to vap */
}; };
/* Driver data of ieee80211_tx_info */ /* Driver data of ieee80211_tx_info */
...@@ -296,13 +313,6 @@ void ath_rate_detach(struct ath_rate_softc *asc); ...@@ -296,13 +313,6 @@ void ath_rate_detach(struct ath_rate_softc *asc);
void ath_rc_node_update(struct ieee80211_hw *hw, struct ath_rate_node *rc_priv); void ath_rc_node_update(struct ieee80211_hw *hw, struct ath_rate_node *rc_priv);
void ath_rate_newstate(struct ath_softc *sc, struct ath_vap *avp); void ath_rate_newstate(struct ath_softc *sc, struct ath_vap *avp);
/*
* Return the tx rate series.
*/
void ath_rate_findrate(struct ath_softc *sc, struct ath_rate_node *ath_rc_priv,
int num_tries, int num_rates,
unsigned int rcflag, struct ath_rc_series[],
int *is_probe, int isretry);
/* /*
* Return rate index for given Dot11 Rate. * Return rate index for given Dot11 Rate.
*/ */
......
...@@ -184,7 +184,7 @@ static int ath_ampdu_input(struct ath_softc *sc, ...@@ -184,7 +184,7 @@ static int ath_ampdu_input(struct ath_softc *sc,
tid = qc[0] & 0xf; tid = qc[0] & 0xf;
} }
if (sc->sc_opmode == ATH9K_M_STA) { if (sc->sc_ah->ah_opmode == ATH9K_M_STA) {
/* Drop the frame not belonging to me. */ /* Drop the frame not belonging to me. */
if (memcmp(hdr->addr1, sc->sc_myaddr, ETH_ALEN)) { if (memcmp(hdr->addr1, sc->sc_myaddr, ETH_ALEN)) {
dev_kfree_skb(skb); dev_kfree_skb(skb);
...@@ -448,17 +448,16 @@ static int ath_rx_indicate(struct ath_softc *sc, ...@@ -448,17 +448,16 @@ static int ath_rx_indicate(struct ath_softc *sc,
int type; int type;
/* indicate frame to the stack, which will free the old skb. */ /* indicate frame to the stack, which will free the old skb. */
type = ath__rx_indicate(sc, skb, status, keyix); type = _ath_rx_indicate(sc, skb, status, keyix);
/* allocate a new skb and queue it to for H/W processing */ /* allocate a new skb and queue it to for H/W processing */
nskb = ath_rxbuf_alloc(sc, sc->sc_rxbufsize); nskb = ath_rxbuf_alloc(sc, sc->sc_rxbufsize);
if (nskb != NULL) { if (nskb != NULL) {
bf->bf_mpdu = nskb; bf->bf_mpdu = nskb;
bf->bf_buf_addr = ath_skb_map_single(sc, bf->bf_buf_addr = pci_map_single(sc->pdev, nskb->data,
nskb, skb_end_pointer(nskb) - nskb->head,
PCI_DMA_FROMDEVICE, PCI_DMA_FROMDEVICE);
/* XXX: Remove get_dma_mem_context() */ bf->bf_dmacontext = bf->bf_buf_addr;
get_dma_mem_context(bf, bf_dmacontext));
ATH_RX_CONTEXT(nskb)->ctx_rxbuf = bf; ATH_RX_CONTEXT(nskb)->ctx_rxbuf = bf;
/* queue the new wbuf to H/W */ /* queue the new wbuf to H/W */
...@@ -504,7 +503,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs) ...@@ -504,7 +503,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
do { do {
spin_lock_init(&sc->sc_rxflushlock); spin_lock_init(&sc->sc_rxflushlock);
sc->sc_rxflush = 0; sc->sc_flags &= ~SC_OP_RXFLUSH;
spin_lock_init(&sc->sc_rxbuflock); spin_lock_init(&sc->sc_rxbuflock);
/* /*
...@@ -541,9 +540,10 @@ int ath_rx_init(struct ath_softc *sc, int nbufs) ...@@ -541,9 +540,10 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
} }
bf->bf_mpdu = skb; bf->bf_mpdu = skb;
bf->bf_buf_addr = bf->bf_buf_addr = pci_map_single(sc->pdev, skb->data,
ath_skb_map_single(sc, skb, PCI_DMA_FROMDEVICE, skb_end_pointer(skb) - skb->head,
get_dma_mem_context(bf, bf_dmacontext)); PCI_DMA_FROMDEVICE);
bf->bf_dmacontext = bf->bf_buf_addr;
ATH_RX_CONTEXT(skb)->ctx_rxbuf = bf; ATH_RX_CONTEXT(skb)->ctx_rxbuf = bf;
} }
sc->sc_rxlink = NULL; sc->sc_rxlink = NULL;
...@@ -597,6 +597,7 @@ void ath_rx_cleanup(struct ath_softc *sc) ...@@ -597,6 +597,7 @@ void ath_rx_cleanup(struct ath_softc *sc)
u32 ath_calcrxfilter(struct ath_softc *sc) u32 ath_calcrxfilter(struct ath_softc *sc)
{ {
#define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR) #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR)
u32 rfilt; u32 rfilt;
rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE) rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE)
...@@ -604,25 +605,29 @@ u32 ath_calcrxfilter(struct ath_softc *sc) ...@@ -604,25 +605,29 @@ u32 ath_calcrxfilter(struct ath_softc *sc)
| ATH9K_RX_FILTER_MCAST; | ATH9K_RX_FILTER_MCAST;
/* If not a STA, enable processing of Probe Requests */ /* If not a STA, enable processing of Probe Requests */
if (sc->sc_opmode != ATH9K_M_STA) if (sc->sc_ah->ah_opmode != ATH9K_M_STA)
rfilt |= ATH9K_RX_FILTER_PROBEREQ; rfilt |= ATH9K_RX_FILTER_PROBEREQ;
/* Can't set HOSTAP into promiscous mode */ /* Can't set HOSTAP into promiscous mode */
if (sc->sc_opmode == ATH9K_M_MONITOR) { if (((sc->sc_ah->ah_opmode != ATH9K_M_HOSTAP) &&
(sc->rx_filter & FIF_PROMISC_IN_BSS)) ||
(sc->sc_ah->ah_opmode == ATH9K_M_MONITOR)) {
rfilt |= ATH9K_RX_FILTER_PROM; rfilt |= ATH9K_RX_FILTER_PROM;
/* ??? To prevent from sending ACK */ /* ??? To prevent from sending ACK */
rfilt &= ~ATH9K_RX_FILTER_UCAST; rfilt &= ~ATH9K_RX_FILTER_UCAST;
} }
if (sc->sc_opmode == ATH9K_M_STA || sc->sc_opmode == ATH9K_M_IBSS || if (((sc->sc_ah->ah_opmode == ATH9K_M_STA) &&
sc->sc_scanning) (sc->rx_filter & FIF_BCN_PRBRESP_PROMISC)) ||
(sc->sc_ah->ah_opmode == ATH9K_M_IBSS))
rfilt |= ATH9K_RX_FILTER_BEACON; rfilt |= ATH9K_RX_FILTER_BEACON;
/* If in HOSTAP mode, want to enable reception of PSPOLL frames /* If in HOSTAP mode, want to enable reception of PSPOLL frames
& beacon frames */ & beacon frames */
if (sc->sc_opmode == ATH9K_M_HOSTAP) if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP)
rfilt |= (ATH9K_RX_FILTER_BEACON | ATH9K_RX_FILTER_PSPOLL); rfilt |= (ATH9K_RX_FILTER_BEACON | ATH9K_RX_FILTER_PSPOLL);
return rfilt; return rfilt;
#undef RX_FILTER_PRESERVE #undef RX_FILTER_PRESERVE
} }
...@@ -702,11 +707,11 @@ void ath_flushrecv(struct ath_softc *sc) ...@@ -702,11 +707,11 @@ void ath_flushrecv(struct ath_softc *sc)
* progress (see references to sc_rxflush) * progress (see references to sc_rxflush)
*/ */
spin_lock_bh(&sc->sc_rxflushlock); spin_lock_bh(&sc->sc_rxflushlock);
sc->sc_rxflush = 1; sc->sc_flags |= SC_OP_RXFLUSH;
ath_rx_tasklet(sc, 1); ath_rx_tasklet(sc, 1);
sc->sc_rxflush = 0; sc->sc_flags &= ~SC_OP_RXFLUSH;
spin_unlock_bh(&sc->sc_rxflushlock); spin_unlock_bh(&sc->sc_rxflushlock);
} }
...@@ -719,7 +724,7 @@ int ath_rx_input(struct ath_softc *sc, ...@@ -719,7 +724,7 @@ int ath_rx_input(struct ath_softc *sc,
struct ath_recv_status *rx_status, struct ath_recv_status *rx_status,
enum ATH_RX_TYPE *status) enum ATH_RX_TYPE *status)
{ {
if (is_ampdu && sc->sc_rxaggr) { if (is_ampdu && (sc->sc_flags & SC_OP_RXAGGR)) {
*status = ATH_RX_CONSUMED; *status = ATH_RX_CONSUMED;
return ath_ampdu_input(sc, an, skb, rx_status); return ath_ampdu_input(sc, an, skb, rx_status);
} else { } else {
...@@ -750,7 +755,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush) ...@@ -750,7 +755,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
do { do {
/* If handling rx interrupt and flush is in progress => exit */ /* If handling rx interrupt and flush is in progress => exit */
if (sc->sc_rxflush && (flush == 0)) if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
break; break;
spin_lock_bh(&sc->sc_rxbuflock); spin_lock_bh(&sc->sc_rxbuflock);
...@@ -900,7 +905,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush) ...@@ -900,7 +905,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
* Enable this if you want to see * Enable this if you want to see
* error frames in Monitor mode. * error frames in Monitor mode.
*/ */
if (sc->sc_opmode != ATH9K_M_MONITOR) if (sc->sc_ah->ah_opmode != ATH9K_M_MONITOR)
goto rx_next; goto rx_next;
#endif #endif
/* fall thru for monitor mode handling... */ /* fall thru for monitor mode handling... */
...@@ -945,7 +950,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush) ...@@ -945,7 +950,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
* decryption and MIC failures. For monitor mode, * decryption and MIC failures. For monitor mode,
* we also ignore the CRC error. * we also ignore the CRC error.
*/ */
if (sc->sc_opmode == ATH9K_M_MONITOR) { if (sc->sc_ah->ah_opmode == ATH9K_M_MONITOR) {
if (ds->ds_rxstat.rs_status & if (ds->ds_rxstat.rs_status &
~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
ATH9K_RXERR_CRC)) ATH9K_RXERR_CRC))
...@@ -1089,7 +1094,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush) ...@@ -1089,7 +1094,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
"%s: Reset rx chain mask. " "%s: Reset rx chain mask. "
"Do internal reset\n", __func__); "Do internal reset\n", __func__);
ASSERT(flush == 0); ASSERT(flush == 0);
ath_internal_reset(sc); ath_reset(sc, false);
} }
return 0; return 0;
...@@ -1127,7 +1132,7 @@ int ath_rx_aggr_start(struct ath_softc *sc, ...@@ -1127,7 +1132,7 @@ int ath_rx_aggr_start(struct ath_softc *sc,
rxtid = &an->an_aggr.rx.tid[tid]; rxtid = &an->an_aggr.rx.tid[tid];
spin_lock_bh(&rxtid->tidlock); spin_lock_bh(&rxtid->tidlock);
if (sc->sc_rxaggr) { if (sc->sc_flags & SC_OP_RXAGGR) {
/* Allow aggregation reception /* Allow aggregation reception
* Adjust rx BA window size. Peer might indicate a * Adjust rx BA window size. Peer might indicate a
* zero buffer size for a _dont_care_ condition. * zero buffer size for a _dont_care_ condition.
...@@ -1227,7 +1232,7 @@ void ath_rx_aggr_teardown(struct ath_softc *sc, ...@@ -1227,7 +1232,7 @@ void ath_rx_aggr_teardown(struct ath_softc *sc,
void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an) void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an)
{ {
if (sc->sc_rxaggr) { if (sc->sc_flags & SC_OP_RXAGGR) {
struct ath_arx_tid *rxtid; struct ath_arx_tid *rxtid;
int tidno; int tidno;
...@@ -1259,7 +1264,7 @@ void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an) ...@@ -1259,7 +1264,7 @@ void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an)
void ath_rx_node_cleanup(struct ath_softc *sc, struct ath_node *an) void ath_rx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
{ {
if (sc->sc_rxaggr) { if (sc->sc_flags & SC_OP_RXAGGR) {
struct ath_arx_tid *rxtid; struct ath_arx_tid *rxtid;
int tidno, i; int tidno, i;
...@@ -1292,27 +1297,3 @@ void ath_rx_node_free(struct ath_softc *sc, struct ath_node *an) ...@@ -1292,27 +1297,3 @@ void ath_rx_node_free(struct ath_softc *sc, struct ath_node *an)
{ {
ath_rx_node_cleanup(sc, an); ath_rx_node_cleanup(sc, an);
} }
dma_addr_t ath_skb_map_single(struct ath_softc *sc,
struct sk_buff *skb,
int direction,
dma_addr_t *pa)
{
/*
* NB: do NOT use skb->len, which is 0 on initialization.
* Use skb's entire data area instead.
*/
*pa = pci_map_single(sc->pdev, skb->data,
skb_end_pointer(skb) - skb->head, direction);
return *pa;
}
void ath_skb_unmap_single(struct ath_softc *sc,
struct sk_buff *skb,
int direction,
dma_addr_t *pa)
{
/* Unmap skb's entire data area */
pci_unmap_single(sc->pdev, *pa,
skb_end_pointer(skb) - skb->head, direction);
}
...@@ -899,12 +899,6 @@ enum { ...@@ -899,12 +899,6 @@ enum {
#define AR_GPIO_OUTPUT_MUX2 0x4064 #define AR_GPIO_OUTPUT_MUX2 0x4064
#define AR_GPIO_OUTPUT_MUX3 0x4068 #define AR_GPIO_OUTPUT_MUX3 0x4068
#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
#define AR_INPUT_STATE 0x406c #define AR_INPUT_STATE 0x406c
#define AR_EEPROM_STATUS_DATA 0x407c #define AR_EEPROM_STATUS_DATA 0x407c
......
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b43-y += main.o b43-y += main.o
b43-y += tables.o b43-y += tables.o
b43-$(CONFIG_B43_NPHY) += tables_nphy.o b43-$(CONFIG_B43_NPHY) += tables_nphy.o
b43-y += phy.o b43-y += phy_common.o
b43-y += phy_g.o
b43-y += phy_a.o
b43-$(CONFIG_B43_NPHY) += nphy.o b43-$(CONFIG_B43_NPHY) += nphy.o
b43-y += sysfs.o b43-y += sysfs.o
b43-y += xmit.o b43-y += xmit.o
......
...@@ -12,7 +12,7 @@ ...@@ -12,7 +12,7 @@
#include "leds.h" #include "leds.h"
#include "rfkill.h" #include "rfkill.h"
#include "lo.h" #include "lo.h"
#include "phy.h" #include "phy_common.h"
/* The unique identifier of the firmware that's officially supported by /* The unique identifier of the firmware that's officially supported by
...@@ -173,6 +173,11 @@ enum { ...@@ -173,6 +173,11 @@ enum {
#define B43_SHM_SH_CHAN 0x00A0 /* Current channel (low 8bit only) */ #define B43_SHM_SH_CHAN 0x00A0 /* Current channel (low 8bit only) */
#define B43_SHM_SH_CHAN_5GHZ 0x0100 /* Bit set, if 5Ghz channel */ #define B43_SHM_SH_CHAN_5GHZ 0x0100 /* Bit set, if 5Ghz channel */
#define B43_SHM_SH_BCMCFIFOID 0x0108 /* Last posted cookie to the bcast/mcast FIFO */ #define B43_SHM_SH_BCMCFIFOID 0x0108 /* Last posted cookie to the bcast/mcast FIFO */
/* TSSI information */
#define B43_SHM_SH_TSSI_CCK 0x0058 /* TSSI for last 4 CCK frames (32bit) */
#define B43_SHM_SH_TSSI_OFDM_A 0x0068 /* TSSI for last 4 OFDM frames (32bit) */
#define B43_SHM_SH_TSSI_OFDM_G 0x0070 /* TSSI for last 4 OFDM frames (32bit) */
#define B43_TSSI_MAX 0x7F /* Max value for one TSSI value */
/* SHM_SHARED TX FIFO variables */ /* SHM_SHARED TX FIFO variables */
#define B43_SHM_SH_SIZE01 0x0098 /* TX FIFO size for FIFO 0 (low) and 1 (high) */ #define B43_SHM_SH_SIZE01 0x0098 /* TX FIFO size for FIFO 0 (low) and 1 (high) */
#define B43_SHM_SH_SIZE23 0x009A /* TX FIFO size for FIFO 2 and 3 */ #define B43_SHM_SH_SIZE23 0x009A /* TX FIFO size for FIFO 2 and 3 */
...@@ -508,122 +513,6 @@ struct b43_iv { ...@@ -508,122 +513,6 @@ struct b43_iv {
} __attribute__((__packed__)); } __attribute__((__packed__));
struct b43_phy {
/* Band support flags. */
bool supports_2ghz;
bool supports_5ghz;
/* GMODE bit enabled? */
bool gmode;
/* Analog Type */
u8 analog;
/* B43_PHYTYPE_ */
u8 type;
/* PHY revision number. */
u8 rev;
/* Radio versioning */
u16 radio_manuf; /* Radio manufacturer */
u16 radio_ver; /* Radio version */
u8 radio_rev; /* Radio revision */
bool dyn_tssi_tbl; /* tssi2dbm is kmalloc()ed. */
/* ACI (adjacent channel interference) flags. */
bool aci_enable;
bool aci_wlan_automatic;
bool aci_hw_rssi;
/* Radio switched on/off */
bool radio_on;
struct {
/* Values saved when turning the radio off.
* They are needed when turning it on again. */
bool valid;
u16 rfover;
u16 rfoverval;
} radio_off_context;
u16 minlowsig[2];
u16 minlowsigpos[2];
/* TSSI to dBm table in use */
const s8 *tssi2dbm;
/* Target idle TSSI */
int tgt_idle_tssi;
/* Current idle TSSI */
int cur_idle_tssi;
/* LocalOscillator control values. */
struct b43_txpower_lo_control *lo_control;
/* Values from b43_calc_loopback_gain() */
s16 max_lb_gain; /* Maximum Loopback gain in hdB */
s16 trsw_rx_gain; /* TRSW RX gain in hdB */
s16 lna_lod_gain; /* LNA lod */
s16 lna_gain; /* LNA */
s16 pga_gain; /* PGA */
/* Desired TX power level (in dBm).
* This is set by the user and adjusted in b43_phy_xmitpower(). */
u8 power_level;
/* A-PHY TX Power control value. */
u16 txpwr_offset;
/* Current TX power level attenuation control values */
struct b43_bbatt bbatt;
struct b43_rfatt rfatt;
u8 tx_control; /* B43_TXCTL_XXX */
/* Hardware Power Control enabled? */
bool hardware_power_control;
/* Current Interference Mitigation mode */
int interfmode;
/* Stack of saved values from the Interference Mitigation code.
* Each value in the stack is layed out as follows:
* bit 0-11: offset
* bit 12-15: register ID
* bit 16-32: value
* register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
*/
#define B43_INTERFSTACK_SIZE 26
u32 interfstack[B43_INTERFSTACK_SIZE]; //FIXME: use a data structure
/* Saved values from the NRSSI Slope calculation */
s16 nrssi[2];
s32 nrssislope;
/* In memory nrssi lookup table. */
s8 nrssi_lt[64];
/* current channel */
u8 channel;
u16 lofcal;
u16 initval; //FIXME rename?
/* PHY TX errors counter. */
atomic_t txerr_cnt;
/* The device does address auto increment for the OFDM tables.
* We cache the previously used address here and omit the address
* write on the next table access, if possible. */
u16 ofdmtab_addr; /* The address currently set in hardware. */
enum { /* The last data flow direction. */
B43_OFDMTAB_DIRECTION_UNKNOWN = 0,
B43_OFDMTAB_DIRECTION_READ,
B43_OFDMTAB_DIRECTION_WRITE,
} ofdmtab_addr_direction;
#if B43_DEBUG
/* Manual TX-power control enabled? */
bool manual_txpower_control;
/* PHY registers locked by b43_phy_lock()? */
bool phy_locked;
#endif /* B43_DEBUG */
};
/* Data structures for DMA transmission, per 80211 core. */ /* Data structures for DMA transmission, per 80211 core. */
struct b43_dma { struct b43_dma {
struct b43_dmaring *tx_ring_AC_BK; /* Background */ struct b43_dmaring *tx_ring_AC_BK; /* Background */
...@@ -764,6 +653,11 @@ struct b43_wl { ...@@ -764,6 +653,11 @@ struct b43_wl {
struct b43_qos_params qos_params[4]; struct b43_qos_params qos_params[4];
/* Workqueue for updating QOS parameters in hardware. */ /* Workqueue for updating QOS parameters in hardware. */
struct work_struct qos_update_work; struct work_struct qos_update_work;
/* Work for adjustment of the transmission power.
* This is scheduled when we determine that the actual TX output
* power doesn't match what we want. */
struct work_struct txpower_adjust_work;
}; };
/* In-memory representation of a cached microcode file. */ /* In-memory representation of a cached microcode file. */
...@@ -908,6 +802,15 @@ static inline int b43_is_mode(struct b43_wl *wl, int type) ...@@ -908,6 +802,15 @@ static inline int b43_is_mode(struct b43_wl *wl, int type)
return (wl->operating && wl->if_type == type); return (wl->operating && wl->if_type == type);
} }
/**
* b43_current_band - Returns the currently used band.
* Returns one of IEEE80211_BAND_2GHZ and IEEE80211_BAND_5GHZ.
*/
static inline enum ieee80211_band b43_current_band(struct b43_wl *wl)
{
return wl->hw->conf.channel->band;
}
static inline u16 b43_read16(struct b43_wldev *dev, u16 offset) static inline u16 b43_read16(struct b43_wldev *dev, u16 offset)
{ {
return ssb_read16(dev->dev, offset); return ssb_read16(dev->dev, offset);
......
...@@ -443,76 +443,6 @@ static ssize_t txstat_read_file(struct b43_wldev *dev, ...@@ -443,76 +443,6 @@ static ssize_t txstat_read_file(struct b43_wldev *dev,
return count; return count;
} }
static ssize_t txpower_g_read_file(struct b43_wldev *dev,
char *buf, size_t bufsize)
{
ssize_t count = 0;
if (dev->phy.type != B43_PHYTYPE_G) {
fappend("Device is not a G-PHY\n");
goto out;
}
fappend("Control: %s\n", dev->phy.manual_txpower_control ?
"MANUAL" : "AUTOMATIC");
fappend("Baseband attenuation: %u\n", dev->phy.bbatt.att);
fappend("Radio attenuation: %u\n", dev->phy.rfatt.att);
fappend("TX Mixer Gain: %s\n",
(dev->phy.tx_control & B43_TXCTL_TXMIX) ? "ON" : "OFF");
fappend("PA Gain 2dB: %s\n",
(dev->phy.tx_control & B43_TXCTL_PA2DB) ? "ON" : "OFF");
fappend("PA Gain 3dB: %s\n",
(dev->phy.tx_control & B43_TXCTL_PA3DB) ? "ON" : "OFF");
fappend("\n\n");
fappend("You can write to this file:\n");
fappend("Writing \"auto\" enables automatic txpower control.\n");
fappend
("Writing the attenuation values as \"bbatt rfatt txmix pa2db pa3db\" "
"enables manual txpower control.\n");
fappend("Example: 5 4 0 0 1\n");
fappend("Enables manual control with Baseband attenuation 5, "
"Radio attenuation 4, No TX Mixer Gain, "
"No PA Gain 2dB, With PA Gain 3dB.\n");
out:
return count;
}
static int txpower_g_write_file(struct b43_wldev *dev,
const char *buf, size_t count)
{
if (dev->phy.type != B43_PHYTYPE_G)
return -ENODEV;
if ((count >= 4) && (memcmp(buf, "auto", 4) == 0)) {
/* Automatic control */
dev->phy.manual_txpower_control = 0;
b43_phy_xmitpower(dev);
} else {
int bbatt = 0, rfatt = 0, txmix = 0, pa2db = 0, pa3db = 0;
/* Manual control */
if (sscanf(buf, "%d %d %d %d %d", &bbatt, &rfatt,
&txmix, &pa2db, &pa3db) != 5)
return -EINVAL;
b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
dev->phy.manual_txpower_control = 1;
dev->phy.bbatt.att = bbatt;
dev->phy.rfatt.att = rfatt;
dev->phy.tx_control = 0;
if (txmix)
dev->phy.tx_control |= B43_TXCTL_TXMIX;
if (pa2db)
dev->phy.tx_control |= B43_TXCTL_PA2DB;
if (pa3db)
dev->phy.tx_control |= B43_TXCTL_PA3DB;
b43_phy_lock(dev);
b43_radio_lock(dev);
b43_set_txpower_g(dev, &dev->phy.bbatt,
&dev->phy.rfatt, dev->phy.tx_control);
b43_radio_unlock(dev);
b43_phy_unlock(dev);
}
return 0;
}
/* wl->irq_lock is locked */ /* wl->irq_lock is locked */
static int restart_write_file(struct b43_wldev *dev, static int restart_write_file(struct b43_wldev *dev,
const char *buf, size_t count) const char *buf, size_t count)
...@@ -560,7 +490,7 @@ static ssize_t loctls_read_file(struct b43_wldev *dev, ...@@ -560,7 +490,7 @@ static ssize_t loctls_read_file(struct b43_wldev *dev,
err = -ENODEV; err = -ENODEV;
goto out; goto out;
} }
lo = phy->lo_control; lo = phy->g->lo_control;
fappend("-- Local Oscillator calibration data --\n\n"); fappend("-- Local Oscillator calibration data --\n\n");
fappend("HW-power-control enabled: %d\n", fappend("HW-power-control enabled: %d\n",
dev->phy.hardware_power_control); dev->phy.hardware_power_control);
...@@ -578,8 +508,8 @@ static ssize_t loctls_read_file(struct b43_wldev *dev, ...@@ -578,8 +508,8 @@ static ssize_t loctls_read_file(struct b43_wldev *dev,
list_for_each_entry(cal, &lo->calib_list, list) { list_for_each_entry(cal, &lo->calib_list, list) {
bool active; bool active;
active = (b43_compare_bbatt(&cal->bbatt, &phy->bbatt) && active = (b43_compare_bbatt(&cal->bbatt, &phy->g->bbatt) &&
b43_compare_rfatt(&cal->rfatt, &phy->rfatt)); b43_compare_rfatt(&cal->rfatt, &phy->g->rfatt));
fappend("BB(%d), RF(%d,%d) -> I=%d, Q=%d " fappend("BB(%d), RF(%d,%d) -> I=%d, Q=%d "
"(expires in %lu sec)%s\n", "(expires in %lu sec)%s\n",
cal->bbatt.att, cal->bbatt.att,
...@@ -763,7 +693,6 @@ B43_DEBUGFS_FOPS(mmio32read, mmio32read__read_file, mmio32read__write_file, 1); ...@@ -763,7 +693,6 @@ B43_DEBUGFS_FOPS(mmio32read, mmio32read__read_file, mmio32read__write_file, 1);
B43_DEBUGFS_FOPS(mmio32write, NULL, mmio32write__write_file, 1); B43_DEBUGFS_FOPS(mmio32write, NULL, mmio32write__write_file, 1);
B43_DEBUGFS_FOPS(tsf, tsf_read_file, tsf_write_file, 1); B43_DEBUGFS_FOPS(tsf, tsf_read_file, tsf_write_file, 1);
B43_DEBUGFS_FOPS(txstat, txstat_read_file, NULL, 0); B43_DEBUGFS_FOPS(txstat, txstat_read_file, NULL, 0);
B43_DEBUGFS_FOPS(txpower_g, txpower_g_read_file, txpower_g_write_file, 0);
B43_DEBUGFS_FOPS(restart, NULL, restart_write_file, 1); B43_DEBUGFS_FOPS(restart, NULL, restart_write_file, 1);
B43_DEBUGFS_FOPS(loctls, loctls_read_file, NULL, 0); B43_DEBUGFS_FOPS(loctls, loctls_read_file, NULL, 0);
...@@ -877,7 +806,6 @@ void b43_debugfs_add_device(struct b43_wldev *dev) ...@@ -877,7 +806,6 @@ void b43_debugfs_add_device(struct b43_wldev *dev)
ADD_FILE(mmio32write, 0200); ADD_FILE(mmio32write, 0200);
ADD_FILE(tsf, 0600); ADD_FILE(tsf, 0600);
ADD_FILE(txstat, 0400); ADD_FILE(txstat, 0400);
ADD_FILE(txpower_g, 0600);
ADD_FILE(restart, 0200); ADD_FILE(restart, 0200);
ADD_FILE(loctls, 0400); ADD_FILE(loctls, 0400);
...@@ -907,7 +835,6 @@ void b43_debugfs_remove_device(struct b43_wldev *dev) ...@@ -907,7 +835,6 @@ void b43_debugfs_remove_device(struct b43_wldev *dev)
debugfs_remove(e->file_mmio32write.dentry); debugfs_remove(e->file_mmio32write.dentry);
debugfs_remove(e->file_tsf.dentry); debugfs_remove(e->file_tsf.dentry);
debugfs_remove(e->file_txstat.dentry); debugfs_remove(e->file_txstat.dentry);
debugfs_remove(e->file_txpower_g.dentry);
debugfs_remove(e->file_restart.dentry); debugfs_remove(e->file_restart.dentry);
debugfs_remove(e->file_loctls.dentry); debugfs_remove(e->file_loctls.dentry);
......
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#ifndef B43_LO_H_ #ifndef B43_LO_H_
#define B43_LO_H_ #define B43_LO_H_
#include "phy.h" /* G-PHY Local Oscillator */
#include "phy_g.h"
struct b43_wldev; struct b43_wldev;
......
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...@@ -24,7 +24,7 @@ ...@@ -24,7 +24,7 @@
#include "b43.h" #include "b43.h"
#include "tables_nphy.h" #include "tables_nphy.h"
#include "phy.h" #include "phy_common.h"
#include "nphy.h" #include "nphy.h"
......
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