Commit 165bcfcf authored by Linus Torvalds's avatar Linus Torvalds

Merge http://xfs.org:8090/xfs-linux-2.6

into ppc970.osdl.org:/home/torvalds/v2.6/linux
parents 4c9ff8d0 abfd7fc4
...@@ -32,6 +32,7 @@ ...@@ -32,6 +32,7 @@
#include <linux/config.h> #include <linux/config.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h> #include <linux/errno.h>
#include <linux/signal.h> #include <linux/signal.h>
#include <linux/sched.h> #include <linux/sched.h>
...@@ -190,10 +191,6 @@ ...@@ -190,10 +191,6 @@
#define FALSE 0 #define FALSE 0
#endif #endif
#define DEBUG 0
/* /*
* Things needed by tty driver * Things needed by tty driver
*/ */
...@@ -763,9 +760,7 @@ static void siccuart_change_speed(struct SICC_info *info, struct termios *old_te ...@@ -763,9 +760,7 @@ static void siccuart_change_speed(struct SICC_info *info, struct termios *old_te
cflag = info->tty->termios->c_cflag; cflag = info->tty->termios->c_cflag;
#ifdef DEBUG pr_debug("siccuart_set_cflag(0x%x) called\n", cflag);
printk("siccuart_set_cflag(0x%x) called\n", cflag);
#endif
/* byte size and parity */ /* byte size and parity */
switch (cflag & CSIZE) { switch (cflag & CSIZE) {
case CS7: lcr_h = _LCR_PE_DISABLE | _LCR_DB_7_BITS | _LCR_SB_1_BIT; bits = 9; break; case CS7: lcr_h = _LCR_PE_DISABLE | _LCR_DB_7_BITS | _LCR_SB_1_BIT; bits = 9; break;
...@@ -1027,9 +1022,7 @@ static void siccuart_flush_buffer(struct tty_struct *tty) ...@@ -1027,9 +1022,7 @@ static void siccuart_flush_buffer(struct tty_struct *tty)
struct SICC_info *info = tty->driver_data; struct SICC_info *info = tty->driver_data;
unsigned long flags; unsigned long flags;
#ifdef DEBUG pr_debug("siccuart_flush_buffer(%d) called\n", tty->index);
printk("siccuart_flush_buffer(%d) called\n", tty->index);
#endif
save_flags(flags); cli(); save_flags(flags); cli();
info->xmit.head = info->xmit.tail = 0; info->xmit.head = info->xmit.tail = 0;
restore_flags(flags); restore_flags(flags);
...@@ -1433,9 +1426,7 @@ static void siccuart_close(struct tty_struct *tty, struct file *filp) ...@@ -1433,9 +1426,7 @@ static void siccuart_close(struct tty_struct *tty, struct file *filp)
state = info->state; state = info->state;
#ifdef DEBUG //pr_debug("siccuart_close() called\n");
//printk("siccuart_close() called\n");
#endif
save_flags(flags); cli(); save_flags(flags); cli();
...@@ -1544,11 +1535,9 @@ static void siccuart_wait_until_sent(struct tty_struct *tty, int timeout) ...@@ -1544,11 +1535,9 @@ static void siccuart_wait_until_sent(struct tty_struct *tty, int timeout)
timeout = 2 * info->timeout; timeout = 2 * info->timeout;
expire = jiffies + timeout; expire = jiffies + timeout;
#ifdef DEBUG pr_debug("siccuart_wait_until_sent(%d), jiff=%lu, expire=%lu char_time=%lu...\n",
printk("siccuart_wait_until_sent(%d), jiff=%lu, expire=%lu char_time=%lu...\n",
tty->index, jiffies, tty->index, jiffies,
expire, char_time); expire, char_time);
#endif
while ((readb(info->port->uart_base + BL_SICC_LSR) & _LSR_TX_ALL) != _LSR_TX_ALL) { while ((readb(info->port->uart_base + BL_SICC_LSR) & _LSR_TX_ALL) != _LSR_TX_ALL) {
set_current_state(TASK_INTERRUPTIBLE); set_current_state(TASK_INTERRUPTIBLE);
schedule_timeout(char_time); schedule_timeout(char_time);
...@@ -1831,9 +1820,8 @@ static int siccuart_console_read(struct console *co, const char *s, u_int count) ...@@ -1831,9 +1820,8 @@ static int siccuart_console_read(struct console *co, const char *s, u_int count)
unsigned int status; unsigned int status;
char *w; char *w;
int c; int c;
#ifdef DEBUG
printk("siccuart_console_read() called\n"); pr_debug("siccuart_console_read() called\n");
#endif
c = 0; c = 0;
w = s; w = s;
......
...@@ -609,7 +609,7 @@ config PPC_OF ...@@ -609,7 +609,7 @@ config PPC_OF
config PPC_GEN550 config PPC_GEN550
bool bool
depends on SANDPOINT || MCPN765 || SPRUCE || PPLUS || PCORE depends on SANDPOINT || MCPN765 || SPRUCE || PPLUS || PCORE || PRPMC750 || K2
default y default y
config FORCE config FORCE
......
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...@@ -33,7 +33,7 @@ ...@@ -33,7 +33,7 @@
#include <asm/pgtable.h> #include <asm/pgtable.h>
#include <asm/cacheflush.h> #include <asm/cacheflush.h>
#define DEBUG_SIG 0 #undef DEBUG_SIG
#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
......
...@@ -33,7 +33,7 @@ obj-$(CONFIG_EST8260) += est8260_setup.o ...@@ -33,7 +33,7 @@ obj-$(CONFIG_EST8260) += est8260_setup.o
obj-$(CONFIG_TQM8260) += tqm8260_setup.o obj-$(CONFIG_TQM8260) += tqm8260_setup.o
obj-$(CONFIG_EV64260) += ev64260_setup.o obj-$(CONFIG_EV64260) += ev64260_setup.o
obj-$(CONFIG_GEMINI) += gemini_pci.o gemini_setup.o gemini_prom.o obj-$(CONFIG_GEMINI) += gemini_pci.o gemini_setup.o gemini_prom.o
obj-$(CONFIG_K2) += k2_setup.o k2_pci.o obj-$(CONFIG_K2) += k2.o
obj-$(CONFIG_LOPEC) += lopec_setup.o lopec_pci.o obj-$(CONFIG_LOPEC) += lopec_setup.o lopec_pci.o
obj-$(CONFIG_MCPN765) += mcpn765.o obj-$(CONFIG_MCPN765) += mcpn765.o
obj-$(CONFIG_MENF1) += menf1_setup.o menf1_pci.o obj-$(CONFIG_MENF1) += menf1_setup.o menf1_pci.o
...@@ -42,7 +42,7 @@ obj-$(CONFIG_PAL4) += pal4_setup.o pal4_pci.o ...@@ -42,7 +42,7 @@ obj-$(CONFIG_PAL4) += pal4_setup.o pal4_pci.o
obj-$(CONFIG_PCORE) += pcore.o obj-$(CONFIG_PCORE) += pcore.o
obj-$(CONFIG_POWERPMC250) += powerpmc250.o obj-$(CONFIG_POWERPMC250) += powerpmc250.o
obj-$(CONFIG_PPLUS) += pplus.o obj-$(CONFIG_PPLUS) += pplus.o
obj-$(CONFIG_PRPMC750) += prpmc750_setup.o prpmc750_pci.o obj-$(CONFIG_PRPMC750) += prpmc750.o
obj-$(CONFIG_PRPMC800) += prpmc800_setup.o prpmc800_pci.o obj-$(CONFIG_PRPMC800) += prpmc800_setup.o prpmc800_pci.o
obj-$(CONFIG_SANDPOINT) += sandpoint.o obj-$(CONFIG_SANDPOINT) += sandpoint.o
obj-$(CONFIG_SPRUCE) += spruce.o obj-$(CONFIG_SPRUCE) += spruce.o
......
...@@ -407,6 +407,9 @@ void __init chrp_init_IRQ(void) ...@@ -407,6 +407,9 @@ void __init chrp_init_IRQ(void)
OpenPIC_NumInitSenses = NR_IRQS - NUM_8259_INTERRUPTS; OpenPIC_NumInitSenses = NR_IRQS - NUM_8259_INTERRUPTS;
openpic_init(NUM_8259_INTERRUPTS); openpic_init(NUM_8259_INTERRUPTS);
/* We have a cascade on OpenPIC IRQ 0, Linux IRQ 16 */
openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
i8259_irq);
for (i = 0; i < NUM_8259_INTERRUPTS; i++) for (i = 0; i < NUM_8259_INTERRUPTS; i++)
irq_desc[i].handler = &i8259_pic; irq_desc[i].handler = &i8259_pic;
......
/*
* arch/ppc/platforms/k2_setup.c
*
* Board setup routines for SBS K2
*
* Author: Matt Porter <mporter@mvista.com>
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/config.h>
#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/reboot.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/types.h>
#include <linux/major.h>
#include <linux/initrd.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/ide.h>
#include <linux/irq.h>
#include <linux/seq_file.h>
#include <linux/root_dev.h>
#include <asm/system.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/dma.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/time.h>
#include <asm/i8259.h>
#include <asm/todc.h>
#include <asm/bootinfo.h>
#include "k2.h"
extern void k2_setup_hoses(void);
extern unsigned long loops_per_jiffy;
static unsigned int cpu_7xx[16] = {
0, 15, 14, 0, 0, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0
};
static unsigned int cpu_6xx[16] = {
0, 0, 14, 0, 0, 13, 5, 9, 6, 11, 8, 10, 0, 12, 7, 0
};
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
/* IDE functions */
static void __init
k2_ide_init_hwif_ports (hw_regs_t *hw, unsigned long data_port,
unsigned long ctrl_port, int *irq)
{
unsigned long reg = data_port;
int i = 8;
for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
hw->io_ports[i] = reg;
reg += 1;
}
if (ctrl_port)
hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
else
hw->io_ports[IDE_CONTROL_OFFSET] =
hw->io_ports[IDE_DATA_OFFSET] + 0x206;
if (irq != NULL)
*irq = 0;
}
#endif
static int
k2_get_bus_speed(void)
{
int bus_speed;
unsigned char board_id;
board_id = *(unsigned char *)K2_BOARD_ID_REG;
switch( K2_BUS_SPD(board_id) ) {
case 0:
default:
bus_speed = 100000000;
break;
case 1:
bus_speed = 83333333;
break;
case 2:
bus_speed = 75000000;
break;
case 3:
bus_speed = 66666666;
break;
}
return bus_speed;
}
static int
k2_get_cpu_speed(void)
{
unsigned long hid1;
int cpu_speed;
hid1 = mfspr(HID1) >> 28;
if ((mfspr(PVR) >> 16) == 8)
hid1 = cpu_7xx[hid1];
else
hid1 = cpu_6xx[hid1];
cpu_speed = k2_get_bus_speed()*hid1/2;
return cpu_speed;
}
static void __init
k2_calibrate_decr(void)
{
int freq, divisor = 4;
/* determine processor bus speed */
freq = k2_get_bus_speed();
tb_ticks_per_jiffy = freq / HZ / divisor;
tb_to_us = mulhwu_scale_factor(freq/divisor, 1000000);
}
static int
k2_show_cpuinfo(struct seq_file *m)
{
unsigned char k2_geo_bits, k2_system_slot;
seq_printf(m, "vendor\t\t: SBS\n");
seq_printf(m, "machine\t\t: K2\n");
seq_printf(m, "cpu speed\t: %dMhz\n", k2_get_cpu_speed()/1000000);
seq_printf(m, "bus speed\t: %dMhz\n", k2_get_bus_speed()/1000000);
seq_printf(m, "memory type\t: SDRAM\n");
k2_geo_bits = readb(K2_MSIZ_GEO_REG) & K2_GEO_ADR_MASK;
k2_system_slot = !(readb(K2_MISC_REG) & K2_SYS_SLOT_MASK);
seq_printf(m, "backplane\t: %s slot board",
k2_system_slot ? "System" : "Non system");
seq_printf(m, "with geographical address %x\n", k2_geo_bits);
return 0;
}
extern char cmd_line[];
TODC_ALLOC();
static void __init
k2_setup_arch(void)
{
unsigned int cpu;
/* Setup TODC access */
TODC_INIT(TODC_TYPE_MK48T37, 0, 0,
ioremap(K2_RTC_BASE_ADDRESS, K2_RTC_SIZE),
8);
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
/* Setup PCI host bridges */
k2_setup_hoses();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_HDC1;
#endif
#ifdef CONFIG_DUMMY_CONSOLE
conswitchp = &dummy_con;
#endif
/* Identify the system */
printk("System Identification: SBS K2 - PowerPC 750 @ %d Mhz\n", k2_get_cpu_speed()/1000000);
printk("SBS K2 port (C) 2001 MontaVista Software, Inc. (source@mvista.com)\n");
/* Identify the CPU manufacturer */
cpu = PVR_REV(mfspr(PVR));
printk("CPU manufacturer: %s [rev=%04x]\n", (cpu & (1<<15)) ? "IBM" :
"Motorola", cpu);
}
static void
k2_restart(char *cmd)
{
local_irq_disable();
/* SRR0 has system reset vector, SRR1 has default MSR value */
/* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
__asm__ __volatile__
("lis 3,0xfff0\n\t"
"ori 3,3,0x0100\n\t"
"mtspr 26,3\n\t"
"li 3,0\n\t"
"mtspr 27,3\n\t"
"rfi\n\t");
for(;;);
}
static void
k2_power_off(void)
{
for(;;);
}
static void
k2_halt(void)
{
k2_restart(NULL);
}
/*
* Set BAT 3 to map PCI32 I/O space.
*/
static __inline__ void
k2_set_bat(void)
{
unsigned long bat3u, bat3l;
static int mapping_set = 0;
if (!mapping_set)
{
__asm__ __volatile__
("lis %0,0x8000\n\t"
"ori %1,%0,0x002a\n\t"
"ori %0,%0,0x1ffe\n\t"
"mtspr 0x21e,%0\n\t"
"mtspr 0x21f,%1\n\t"
"isync\n\t"
"sync\n\t"
: "=r" (bat3u), "=r" (bat3l));
mapping_set = 1;
}
return;
}
static unsigned long __init
k2_find_end_of_memory(void)
{
unsigned long total;
unsigned char msize = 7; /* Default to 128MB */
k2_set_bat();
msize = K2_MEM_SIZE(readb(K2_MSIZ_GEO_REG));
switch (msize)
{
case 2:
/*
* This will break without a lowered
* KERNELBASE or CONFIG_HIGHMEM on.
* It seems non 1GB builds exist yet,
* though.
*/
total = K2_MEM_SIZE_1GB;
break;
case 3:
case 4:
total = K2_MEM_SIZE_512MB;
break;
case 5:
case 6:
total = K2_MEM_SIZE_256MB;
break;
case 7:
total = K2_MEM_SIZE_128MB;
break;
default:
printk("K2: Invalid memory size detected, defaulting to 128MB\n");
total = K2_MEM_SIZE_128MB;
break;
}
return total;
}
static void __init
k2_map_io(void)
{
io_block_mapping(K2_PCI32_IO_BASE,
K2_PCI32_IO_BASE,
0x00200000,
_PAGE_IO);
io_block_mapping(0xff000000,
0xff000000,
0x01000000,
_PAGE_IO);
}
static void __init
k2_init_irq(void)
{
int i;
for ( i = 0 ; i < 16 ; i++ )
irq_desc[i].handler = &i8259_pic;
i8259_init(NULL);
}
void __init platform_init(unsigned long r3, unsigned long r4,
unsigned long r5, unsigned long r6, unsigned long r7)
{
parse_bootinfo((struct bi_record *) (r3 + KERNELBASE));
isa_io_base = K2_ISA_IO_BASE;
isa_mem_base = K2_ISA_MEM_BASE;
pci_dram_offset = K2_PCI32_SYS_MEM_BASE;
ppc_md.setup_arch = k2_setup_arch;
ppc_md.show_cpuinfo = k2_show_cpuinfo;
ppc_md.init_IRQ = k2_init_irq;
ppc_md.get_irq = i8259_irq;
ppc_md.find_end_of_memory = k2_find_end_of_memory;
ppc_md.setup_io_mappings = k2_map_io;
ppc_md.restart = k2_restart;
ppc_md.power_off = k2_power_off;
ppc_md.halt = k2_halt;
ppc_md.time_init = todc_time_init;
ppc_md.set_rtc_time = todc_set_rtc_time;
ppc_md.get_rtc_time = todc_get_rtc_time;
ppc_md.calibrate_decr = k2_calibrate_decr;
ppc_md.nvram_read_val = todc_direct_read_val;
ppc_md.nvram_write_val = todc_direct_write_val;
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
ppc_ide_md.ide_init_hwif = k2_ide_init_hwif_ports;
#endif
}
...@@ -208,6 +208,9 @@ lopec_init_IRQ(void) ...@@ -208,6 +208,9 @@ lopec_init_IRQ(void)
openpic_set_sources(19, 1, OpenPIC_Addr + 0x110C0); openpic_set_sources(19, 1, OpenPIC_Addr + 0x110C0);
openpic_init(NUM_8259_INTERRUPTS); openpic_init(NUM_8259_INTERRUPTS);
/* We have a cascade on OpenPIC IRQ 0, Linux IRQ 16 */
openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
&i8259_irq);
/* Map i8259 interrupts */ /* Map i8259 interrupts */
for(i = 0; i < NUM_8259_INTERRUPTS; i++) for(i = 0; i < NUM_8259_INTERRUPTS; i++)
......
...@@ -30,9 +30,6 @@ ...@@ -30,9 +30,6 @@
#include <linux/console.h> #include <linux/console.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/irq.h> #include <linux/irq.h>
#if 0
#include <linux/ide.h>
#endif
#include <linux/seq_file.h> #include <linux/seq_file.h>
#include <linux/root_dev.h> #include <linux/root_dev.h>
#include <linux/serial.h> #include <linux/serial.h>
...@@ -385,6 +382,8 @@ mcpn765_init_IRQ(void) ...@@ -385,6 +382,8 @@ mcpn765_init_IRQ(void)
ppc_md.progress("init_irq: enter", 0); ppc_md.progress("init_irq: enter", 0);
openpic_init(NUM_8259_INTERRUPTS); openpic_init(NUM_8259_INTERRUPTS);
openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
i8259_irq);
for(i=0; i < NUM_8259_INTERRUPTS; i++) for(i=0; i < NUM_8259_INTERRUPTS; i++)
irq_desc[i].handler = &i8259_pic; irq_desc[i].handler = &i8259_pic;
......
...@@ -138,6 +138,7 @@ mvme5100_init_IRQ(void) ...@@ -138,6 +138,7 @@ mvme5100_init_IRQ(void)
#ifdef CONFIG_MVME5100_IPMC761_PRESENT #ifdef CONFIG_MVME5100_IPMC761_PRESENT
openpic_init(1, NUM_8259_INTERRUPTS, NULL, -1); openpic_init(1, NUM_8259_INTERRUPTS, NULL, -1);
openpic_hookup_cascade(NUM_8259_INTERRUPTS,"82c59 cascade",&i8259_irq);
for(i=0; i < NUM_8259_INTERRUPTS; i++) for(i=0; i < NUM_8259_INTERRUPTS; i++)
irq_desc[i].handler = &i8259_pic; irq_desc[i].handler = &i8259_pic;
......
...@@ -672,6 +672,8 @@ static void __init pplus_init_IRQ(void) ...@@ -672,6 +672,8 @@ static void __init pplus_init_IRQ(void)
openpic_set_sources(0, 16, OpenPIC_Addr + 0x10000); openpic_set_sources(0, 16, OpenPIC_Addr + 0x10000);
openpic_init(NUM_8259_INTERRUPTS); openpic_init(NUM_8259_INTERRUPTS);
openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
i8259_irq);
ppc_md.get_irq = openpic_get_irq; ppc_md.get_irq = openpic_get_irq;
} }
......
...@@ -134,6 +134,7 @@ EXPORT_SYMBOL(ppc_cs4232_dma2); ...@@ -134,6 +134,7 @@ EXPORT_SYMBOL(ppc_cs4232_dma2);
#define PREP_IBM_CAROLINA_IDE_0 0xf0 #define PREP_IBM_CAROLINA_IDE_0 0xf0
#define PREP_IBM_CAROLINA_IDE_1 0xf1 #define PREP_IBM_CAROLINA_IDE_1 0xf1
#define PREP_IBM_CAROLINA_IDE_2 0xf2 #define PREP_IBM_CAROLINA_IDE_2 0xf2
#define PREP_IBM_CAROLINA_IDE_3 0xf3
/* 7248-43P */ /* 7248-43P */
#define PREP_IBM_CAROLINA_SCSI_0 0xf4 #define PREP_IBM_CAROLINA_SCSI_0 0xf4
#define PREP_IBM_CAROLINA_SCSI_1 0xf5 #define PREP_IBM_CAROLINA_SCSI_1 0xf5
...@@ -855,8 +856,12 @@ prep_init_IRQ(void) ...@@ -855,8 +856,12 @@ prep_init_IRQ(void)
int i; int i;
unsigned int pci_viddid, pci_did; unsigned int pci_viddid, pci_did;
if (OpenPIC_Addr != NULL) if (OpenPIC_Addr != NULL) {
openpic_init(NUM_8259_INTERRUPTS); openpic_init(NUM_8259_INTERRUPTS);
/* We have a cascade on OpenPIC IRQ 0, Linux IRQ 16 */
openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
i8259_irq);
}
for ( i = 0 ; i < NUM_8259_INTERRUPTS ; i++ ) for ( i = 0 ; i < NUM_8259_INTERRUPTS ; i++ )
irq_desc[i].handler = &i8259_pic; irq_desc[i].handler = &i8259_pic;
/* If we have a Raven PCI bridge or a Hawk PCI bridge / Memory /* If we have a Raven PCI bridge or a Hawk PCI bridge / Memory
......
...@@ -19,27 +19,47 @@ ...@@ -19,27 +19,47 @@
#include <linux/serial_reg.h> #include <linux/serial_reg.h>
#define PRPMC750_PCI_CONFIG_ADDR 0x80000cf8 /*
#define PRPMC750_PCI_CONFIG_DATA 0x80000cfc * Due to limiations imposed by legacy hardware (primaryily IDE controllers),
* the PrPMC750 carrier board operates using a PReP address map.
*
* From Processor (physical) -> PCI:
* PCI Mem Space: 0xc0000000 - 0xfe000000 -> 0x00000000 - 0x3e000000 (768 MB)
* PCI I/O Space: 0x80000000 - 0x90000000 -> 0x00000000 - 0x10000000 (256 MB)
* Note: Must skip 0xfe000000-0xfe400000 for CONFIG_HIGHMEM/PKMAP area
*
* From PCI -> Processor (physical):
* System Memory: 0x80000000 -> 0x00000000
*/
#define PRPMC750_PCI_PHY_MEM_BASE 0xc0000000 #define PRPMC750_ISA_IO_BASE PREP_ISA_IO_BASE
#define PRPMC750_PCI_MEM_BASE 0xf0000000 #define PRPMC750_ISA_MEM_BASE PREP_ISA_MEM_BASE
#define PRPMC750_PCI_IO_BASE 0x80000000
#define PRPMC750_ISA_IO_BASE PRPMC750_PCI_IO_BASE /* PCI Memory space mapping info */
#define PRPMC750_ISA_MEM_BASE PRPMC750_PCI_MEM_BASE #define PRPMC750_PCI_MEM_SIZE 0x30000000U
#define PRPMC750_PCI_MEM_OFFSET PRPMC750_PCI_PHY_MEM_BASE #define PRPMC750_PROC_PCI_MEM_START PRPMC750_ISA_MEM_BASE
#define PRPMC750_PROC_PCI_MEM_END (PRPMC750_PROC_PCI_MEM_START + \
PRPMC750_PCI_MEM_SIZE - 1)
#define PRPMC750_PCI_MEM_START 0x00000000U
#define PRPMC750_PCI_MEM_END (PRPMC750_PCI_MEM_START + \
PRPMC750_PCI_MEM_SIZE - 1)
#define PRPMC750_SYS_MEM_BASE 0x80000000 /* PCI I/O space mapping info */
#define PRPMC750_PCI_IO_SIZE 0x10000000U
#define PRPMC750_PROC_PCI_IO_START PRPMC750_ISA_IO_BASE
#define PRPMC750_PROC_PCI_IO_END (PRPMC750_PROC_PCI_IO_START + \
PRPMC750_PCI_IO_SIZE - 1)
#define PRPMC750_PCI_IO_START 0x00000000U
#define PRPMC750_PCI_IO_END (PRPMC750_PCI_IO_START + \
PRPMC750_PCI_IO_SIZE - 1)
#define PRPMC750_PCI_LOWER_MEM 0x00000000 /* System memory mapping info */
#define PRPMC750_PCI_UPPER_MEM_AUTO 0x3bf7ffff #define PRPMC750_PCI_DRAM_OFFSET PREP_PCI_DRAM_OFFSET
#define PRPMC750_PCI_UPPER_MEM 0x3bffffff #define PRPMC750_PCI_PHY_MEM_OFFSET (PRPMC750_ISA_MEM_BASE-PRPMC750_PCI_MEM_START)
#define PRPMC750_PCI_LOWER_IO 0x00000000
#define PRPMC750_PCI_UPPER_IO 0x0ff7ffff
#define PRPMC750_HAWK_MPIC_BASE 0xfbf80000 /* Register address definitions */
#define PRPMC750_HAWK_SMC_BASE 0xfef80000 #define PRPMC750_HAWK_SMC_BASE 0xfef80000U
#define PRPMC750_HAWK_PPC_REG_BASE 0xfeff0000U
#define PRPMC750_BASE_BAUD 1843200 #define PRPMC750_BASE_BAUD 1843200
#define PRPMC750_SERIAL_0 0xfef88000 #define PRPMC750_SERIAL_0 0xfef88000
...@@ -61,5 +81,5 @@ ...@@ -61,5 +81,5 @@
#define PRPMC750_TBEN_REG 0xfef880c0 #define PRPMC750_TBEN_REG 0xfef880c0
#define PRPMC750_TBEN_MASK 0x01 #define PRPMC750_TBEN_MASK 0x01
#endif /* __ASM_PRPMC750_H__ */ #endif /* __ASM_PRPMC750_H__ */
#endif /* __KERNEL__ */ #endif /* __KERNEL__ */
/*
* arch/ppc/platforms/prpmc750_pci.c
*
* PCI support for Motorola PrPMC750
*
* Author: Matt Porter <mporter@mvista.com>
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <asm/byteorder.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <platforms/prpmc750.h>
/*
* Motorola PrPMC750/PrPMC800 in PrPMCBASE or PrPMC-Carrier
* Combined irq tables. Only Base has IDSEL 14, only Carrier has 21 and 22.
*/
static inline int
prpmc_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
{
static char pci_irq_table[][4] =
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
{12, 0, 0, 0}, /* IDSEL 14 - Ethernet, base */
{0, 0, 0, 0}, /* IDSEL 15 - unused */
{10, 11, 12, 9}, /* IDSEL 16 - PMC A1, PMC1 */
{10, 11, 12, 9}, /* IDSEL 17 - PrPMC-A-B, PMC2-B */
{11, 12, 9, 10}, /* IDSEL 18 - PMC A1-B, PMC1-B */
{0, 0, 0, 0}, /* IDSEL 19 - unused */
{9, 10, 11, 12}, /* IDSEL 20 - P2P Bridge */
{11, 12, 9, 10}, /* IDSEL 21 - PMC A2, carrier */
{12, 9, 10, 11}, /* IDSEL 22 - PMC A2-B, carrier */
};
const long min_idsel = 14, max_idsel = 22, irqs_per_slot = 4;
return PCI_IRQ_TABLE_LOOKUP;
};
static void __init
prpmc750_pcibios_fixup(void)
{
struct pci_dev *dev;
unsigned short wtmp;
/*
* Kludge to clean up after PPC6BUG which doesn't
* configure the CL5446 VGA card. Also the
* resource subsystem doesn't fixup the
* PCI mem resources on the CL5446.
*/
if ((dev = pci_find_device(PCI_VENDOR_ID_CIRRUS,
PCI_DEVICE_ID_CIRRUS_5446, 0)))
{
dev->resource[0].start += PRPMC750_PCI_PHY_MEM_BASE;
dev->resource[0].end += PRPMC750_PCI_PHY_MEM_BASE;
pci_read_config_word(dev,
PCI_COMMAND,
&wtmp);
pci_write_config_word(dev,
PCI_COMMAND,
wtmp|3);
/* Enable Color mode in MISC reg */
outb(0x03, 0x3c2);
/* Select DRAM config reg */
outb(0x0f, 0x3c4);
/* Set proper DRAM config */
outb(0xdf, 0x3c5);
}
}
void __init
prpmc750_find_bridges(void)
{
struct pci_controller* hose;
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
hose->pci_mem_offset = PRPMC750_PCI_PHY_MEM_BASE;
pci_init_resource(&hose->io_resource,
PRPMC750_PCI_LOWER_IO,
PRPMC750_PCI_UPPER_IO,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
PRPMC750_PCI_LOWER_MEM + PRPMC750_PCI_PHY_MEM_BASE,
PRPMC750_PCI_UPPER_MEM + PRPMC750_PCI_PHY_MEM_BASE,
IORESOURCE_MEM,
"PCI host bridge");
hose->io_space.start = PRPMC750_PCI_LOWER_IO;
hose->io_space.end = PRPMC750_PCI_UPPER_IO;
hose->mem_space.start = PRPMC750_PCI_LOWER_MEM;
hose->mem_space.end = PRPMC750_PCI_UPPER_MEM_AUTO;
hose->io_base_virt = (void *)PRPMC750_ISA_IO_BASE;
setup_indirect_pci(hose,
PRPMC750_PCI_CONFIG_ADDR,
PRPMC750_PCI_CONFIG_DATA);
/*
* Disable MPIC response to PCI I/O space (BAR 0).
* Make MPIC respond to PCI Mem space at specified address.
* (BAR 1).
*/
early_write_config_dword(hose,
0,
PCI_DEVFN(0,0),
PCI_BASE_ADDRESS_0,
0x00000000 | 0x1);
early_write_config_dword(hose,
0,
PCI_DEVFN(0,0),
PCI_BASE_ADDRESS_1,
(PRPMC750_HAWK_MPIC_BASE -
PRPMC750_PCI_MEM_OFFSET) | 0x0);
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pcibios_fixup = prpmc750_pcibios_fixup;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = prpmc_map_irq;
}
...@@ -444,6 +444,8 @@ sandpoint_init_IRQ(void) ...@@ -444,6 +444,8 @@ sandpoint_init_IRQ(void)
openpic_set_sources(0, 16, OpenPIC_Addr + 0x10200); openpic_set_sources(0, 16, OpenPIC_Addr + 0x10200);
openpic_init(NUM_8259_INTERRUPTS); openpic_init(NUM_8259_INTERRUPTS);
openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
i8259_irq);
/* /*
* openpic_init() has set up irq_desc[16-31] to be openpic * openpic_init() has set up irq_desc[16-31] to be openpic
......
...@@ -39,7 +39,7 @@ obj-$(CONFIG_ADIR) += i8259.o indirect_pci.o pci_auto.o \ ...@@ -39,7 +39,7 @@ obj-$(CONFIG_ADIR) += i8259.o indirect_pci.o pci_auto.o \
obj-$(CONFIG_EBONY) += indirect_pci.o pci_auto.o todc_time.o obj-$(CONFIG_EBONY) += indirect_pci.o pci_auto.o todc_time.o
obj-$(CONFIG_EV64260) += gt64260_common.o gt64260_pic.o \ obj-$(CONFIG_EV64260) += gt64260_common.o gt64260_pic.o \
indirect_pci.o todc_time.o pci_auto.o indirect_pci.o todc_time.o pci_auto.o
obj-$(CONFIG_GEMINI) += open_pic.o i8259.o indirect_pci.o obj-$(CONFIG_GEMINI) += open_pic.o indirect_pci.o
obj-$(CONFIG_K2) += i8259.o indirect_pci.o todc_time.o \ obj-$(CONFIG_K2) += i8259.o indirect_pci.o todc_time.o \
pci_auto.o pci_auto.o
obj-$(CONFIG_LOPEC) += pci_auto.o open_pic.o i8259.o todc_time.o obj-$(CONFIG_LOPEC) += pci_auto.o open_pic.o i8259.o todc_time.o
......
...@@ -26,8 +26,10 @@ ...@@ -26,8 +26,10 @@
#define ERRC 0xff001050 #define ERRC 0xff001050
#define SESR 0xff001060 #define SESR 0xff001060
#define SEAR 0xff001070 #define SEAR 0xff001070
#define SIOC1 0xff001090
#define PGCHP 0xff001100 #define PGCHP 0xff001100
#define GPDIR 0xff001130 #define GPDIR 0xff001130
#define GPOUT 0xff001150
#define ATAS 0xff001160 #define ATAS 0xff001160
#define AVDG 0xff001170 #define AVDG 0xff001170
#define MCCR 0xff001200 #define MCCR 0xff001200
......
...@@ -48,6 +48,8 @@ static u_int NumProcessors; ...@@ -48,6 +48,8 @@ static u_int NumProcessors;
static u_int NumSources; static u_int NumSources;
static int open_pic_irq_offset; static int open_pic_irq_offset;
static volatile OpenPIC_Source *ISR[NR_IRQS]; static volatile OpenPIC_Source *ISR[NR_IRQS];
static int openpic_cascade_irq = -1;
static int (*openpic_cascade_fn)(struct pt_regs *);
/* Global Operations */ /* Global Operations */
static void openpic_disable_8259_pass_through(void); static void openpic_disable_8259_pass_through(void);
...@@ -416,13 +418,6 @@ void __init openpic_init(int offset) ...@@ -416,13 +418,6 @@ void __init openpic_init(int offset)
/* Initialize the spurious interrupt */ /* Initialize the spurious interrupt */
if (ppc_md.progress) ppc_md.progress("openpic: spurious",0x3bd); if (ppc_md.progress) ppc_md.progress("openpic: spurious",0x3bd);
openpic_set_spurious(OPENPIC_VEC_SPURIOUS+offset); openpic_set_spurious(OPENPIC_VEC_SPURIOUS+offset);
/* Initialize the cascade */
if (offset) {
if (request_irq(offset, no_action, SA_INTERRUPT,
"82c59 cascade", NULL))
printk("Unable to get OpenPIC IRQ 0 for cascade\n");
}
openpic_disable_8259_pass_through(); openpic_disable_8259_pass_through();
#ifdef CONFIG_EPIC_SERIAL_MODE #ifdef CONFIG_EPIC_SERIAL_MODE
openpic_eicr_set_clk(7); /* Slowest value until we know better */ openpic_eicr_set_clk(7); /* Slowest value until we know better */
...@@ -682,6 +677,19 @@ openpic_init_nmi_irq(u_int irq) ...@@ -682,6 +677,19 @@ openpic_init_nmi_irq(u_int irq)
* *
*/ */
/*
* Hookup a cascade to the OpenPIC.
*/
void __init
openpic_hookup_cascade(u_int irq, char *name,
int (*cascade_fn)(struct pt_regs *))
{
openpic_cascade_irq = irq;
openpic_cascade_fn = cascade_fn;
if (request_irq(irq, no_action, SA_INTERRUPT, name, NULL))
printk("Unable to get OpenPIC IRQ %d for cascade\n",
irq - open_pic_irq_offset);
}
/* /*
* Enable/disable an external interrupt source * Enable/disable an external interrupt source
...@@ -841,14 +849,19 @@ openpic_get_irq(struct pt_regs *regs) ...@@ -841,14 +849,19 @@ openpic_get_irq(struct pt_regs *regs)
int irq = openpic_irq(); int irq = openpic_irq();
/* /*
* This needs to be cleaned up. We don't necessarily have * Check for the cascade interrupt and call the cascaded
* an i8259 cascaded or even a cascade. * interrupt controller function (usually i8259_irq) if so.
* This should move to irq.c eventually. -- paulus
*/ */
if (open_pic_irq_offset && irq == open_pic_irq_offset) { if (irq == openpic_cascade_irq && openpic_cascade_fn != NULL) {
/* Get the IRQ from the cascade. */ int cirq = openpic_cascade_fn(regs);
irq = i8259_irq(regs);
openpic_eoi(); /* Allow for the cascade being shared with other devices */
} else if (irq == OPENPIC_VEC_SPURIOUS + open_pic_irq_offset) if (cirq != -1) {
irq = cirq;
openpic_eoi();
}
} else if (irq == OPENPIC_VEC_SPURIOUS + open_pic_irq_offset)
irq = -1; irq = -1;
return irq; return irq;
} }
......
...@@ -184,6 +184,8 @@ static int __init parse_numa_properties(void) ...@@ -184,6 +184,8 @@ static int __init parse_numa_properties(void)
if (numa_domain >= MAX_NUMNODES) if (numa_domain >= MAX_NUMNODES)
BUG(); BUG();
node_set_online(numa_domain);
if (max_domain < numa_domain) if (max_domain < numa_domain)
max_domain = numa_domain; max_domain = numa_domain;
......
...@@ -1325,7 +1325,6 @@ int vfs_quota_off(struct super_block *sb, int type) ...@@ -1325,7 +1325,6 @@ int vfs_quota_off(struct super_block *sb, int type)
dqopt->ops[cnt] = NULL; dqopt->ops[cnt] = NULL;
} }
up(&dqopt->dqonoff_sem); up(&dqopt->dqonoff_sem);
out:
return 0; return 0;
} }
......
...@@ -74,6 +74,8 @@ typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG]; ...@@ -74,6 +74,8 @@ typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
#ifdef __KERNEL__ #ifdef __KERNEL__
struct task_struct;
/* /*
* This is used to ensure we don't load something for the wrong architecture. * This is used to ensure we don't load something for the wrong architecture.
*/ */
......
...@@ -41,6 +41,8 @@ extern void* OpenPIC_Addr; ...@@ -41,6 +41,8 @@ extern void* OpenPIC_Addr;
extern void openpic_set_sources(int first_irq, int num_irqs, void *isr); extern void openpic_set_sources(int first_irq, int num_irqs, void *isr);
extern void openpic_init(int linux_irq_offset); extern void openpic_init(int linux_irq_offset);
extern void openpic_init_nmi_irq(u_int irq); extern void openpic_init_nmi_irq(u_int irq);
extern void openpic_hookup_cascade(u_int irq, char *name,
int (*cascade_fn)(struct pt_regs *));
extern u_int openpic_irq(void); extern u_int openpic_irq(void);
extern void openpic_eoi(void); extern void openpic_eoi(void);
extern void openpic_request_IPIs(void); extern void openpic_request_IPIs(void);
......
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