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Commit 167f53d0 authored by Stephen Hemminger's avatar Stephen Hemminger Committed by David S. Miller
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sky2: use pci_config access functions 

Use the PCI layer config access functions. The driver was using the
memory mapped window in device, to workaround issues accessing the
advanced error reporting registers.
Signed-off-by: default avatarStephen Hemminger <shemminger@linux-foundation.org>
Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 555382cb
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Showing with 51 additions and 63 deletions
drivers/net/sky2.c
View file @ 167f53d0
......@@ -223,21 +223,22 @@ static void sky2_power_on(struct sky2_hw *hw)
sky2_write8(hw, B2_Y2_CLK_GATE, 0);
if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
struct pci_dev *pdev = hw->pdev;
u32 reg;
sky2_pci_write32(hw, PCI_DEV_REG3, 0);
pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
reg = sky2_pci_read32(hw, PCI_DEV_REG4);
pci_read_config_dword(pdev, PCI_DEV_REG4, &reg);
/* set all bits to 0 except bits 15..12 and 8 */
reg &= P_ASPM_CONTROL_MSK;
sky2_pci_write32(hw, PCI_DEV_REG4, reg);
pci_write_config_dword(pdev, PCI_DEV_REG4, reg);
reg = sky2_pci_read32(hw, PCI_DEV_REG5);
pci_read_config_dword(pdev, PCI_DEV_REG5, &reg);
/* set all bits to 0 except bits 28 & 27 */
reg &= P_CTL_TIM_VMAIN_AV_MSK;
sky2_pci_write32(hw, PCI_DEV_REG5, reg);
pci_write_config_dword(pdev, PCI_DEV_REG5, reg);
sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
pci_write_config_dword(pdev, PCI_CFG_REG_1, 0);
/* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
reg = sky2_read32(hw, B2_GP_IO);
......@@ -603,6 +604,7 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
{
struct pci_dev *pdev = hw->pdev;
u32 reg1;
static const u32 phy_power[]
= { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
......@@ -611,15 +613,16 @@ static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
onoff = !onoff;
reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
pci_read_config_dword(pdev, PCI_DEV_REG1, &reg1);
if (onoff)
/* Turn off phy power saving */
reg1 &= ~phy_power[port];
else
reg1 |= phy_power[port];
sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
sky2_pci_read32(hw, PCI_DEV_REG1);
pci_write_config_dword(pdev, PCI_DEV_REG1, reg1);
pci_read_config_dword(pdev, PCI_DEV_REG1, &reg1);
udelay(100);
}
......@@ -687,9 +690,9 @@ static void sky2_wol_init(struct sky2_port *sky2)
sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
/* Turn on legacy PCI-Express PME mode */
reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
reg1 |= PCI_Y2_PME_LEGACY;
sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
/* block receiver */
sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
......@@ -1306,9 +1309,9 @@ static int sky2_up(struct net_device *dev)
struct sky2_port *osky2 = netdev_priv(otherdev);
u16 cmd;
cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
pci_read_config_word(hw->pdev, cap + PCI_X_CMD, &cmd);
cmd &= ~PCI_X_CMD_MAX_SPLIT;
sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
pci_write_config_word(hw->pdev, cap + PCI_X_CMD, cmd);
sky2->rx_csum = 0;
osky2->rx_csum = 0;
......@@ -2434,12 +2437,12 @@ static void sky2_hw_intr(struct sky2_hw *hw)
if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
u16 pci_err;
pci_err = sky2_pci_read16(hw, PCI_STATUS);
pci_read_config_word(pdev, PCI_STATUS, &pci_err);
if (net_ratelimit())
dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
pci_err);
sky2_pci_write16(hw, PCI_STATUS,
pci_write_config_word(pdev, PCI_STATUS,
pci_err | PCI_STATUS_ERROR_BITS);
}
......@@ -2694,10 +2697,13 @@ static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
static int __devinit sky2_init(struct sky2_hw *hw)
{
int rc;
u8 t8;
/* Enable all clocks */
sky2_pci_write32(hw, PCI_DEV_REG3, 0);
/* Enable all clocks and check for bad PCI access */
rc = pci_write_config_dword(hw->pdev, PCI_DEV_REG3, 0);
if (rc)
return rc;
sky2_write8(hw, B0_CTST, CS_RST_CLR);
......@@ -2791,10 +2797,9 @@ static void sky2_reset(struct sky2_hw *hw)
sky2_write8(hw, B0_CTST, CS_RST_CLR);
/* clear PCI errors, if any */
status = sky2_pci_read16(hw, PCI_STATUS);
sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
pci_read_config_word(pdev, PCI_STATUS, &status);
status |= PCI_STATUS_ERROR_BITS;
pci_write_config_word(pdev, PCI_STATUS, status);
sky2_write8(hw, B0_CTST, CS_MRST_CLR);
......@@ -3606,26 +3611,31 @@ static int sky2_get_eeprom_len(struct net_device *dev)
struct sky2_port *sky2 = netdev_priv(dev);
u16 reg2;
reg2 = sky2_pci_read32(sky2->hw, PCI_DEV_REG2);
pci_read_config_word(sky2->hw->pdev, PCI_DEV_REG2, &reg2);
return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
}
static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
static u32 sky2_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
{
sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
u32 val;
pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
while (!(sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F))
cpu_relax();
return sky2_pci_read32(hw, cap + PCI_VPD_DATA);
do {
pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
} while (!(offset & PCI_VPD_ADDR_F));
pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
return val;
}
static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
static void sky2_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
{
sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
pci_write_config_word(pdev, cap + PCI_VPD_DATA, val);
pci_write_config_dword(pdev, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
do {
cpu_relax();
} while (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F);
pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
} while (offset & PCI_VPD_ADDR_F);
}
static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
......@@ -3642,7 +3652,7 @@ static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom
eeprom->magic = SKY2_EEPROM_MAGIC;
while (length > 0) {
u32 val = sky2_vpd_read(sky2->hw, cap, offset);
u32 val = sky2_vpd_read(sky2->hw->pdev, cap, offset);
int n = min_t(int, length, sizeof(val));
memcpy(data, &val, n);
......@@ -3672,10 +3682,10 @@ static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom
int n = min_t(int, length, sizeof(val));
if (n < sizeof(val))
val = sky2_vpd_read(sky2->hw, cap, offset);
val = sky2_vpd_read(sky2->hw->pdev, cap, offset);
memcpy(&val, data, n);
sky2_vpd_write(sky2->hw, cap, offset, val);
sky2_vpd_write(sky2->hw->pdev, cap, offset, val);
length -= n;
data += n;
......@@ -4116,15 +4126,14 @@ static int __devinit sky2_probe(struct pci_dev *pdev,
*/
{
u32 reg;
reg = sky2_pci_read32(hw, PCI_DEV_REG2);
pci_read_config_dword(pdev,PCI_DEV_REG2, &reg);
reg &= ~PCI_REV_DESC;
sky2_pci_write32(hw, PCI_DEV_REG2, reg);
pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
}
#endif
/* ring for status responses */
hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
&hw->st_dma);
hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
if (!hw->st_le)
goto err_out_iounmap;
......@@ -4201,7 +4210,7 @@ static int __devinit sky2_probe(struct pci_dev *pdev,
free_netdev(dev);
err_out_free_pci:
sky2_write8(hw, B0_CTST, CS_RST_SET);
pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
err_out_iounmap:
iounmap(hw->regs);
err_out_free_hw:
......@@ -4312,7 +4321,7 @@ static int sky2_resume(struct pci_dev *pdev)
if (hw->chip_id == CHIP_ID_YUKON_EX ||
hw->chip_id == CHIP_ID_YUKON_EC_U ||
hw->chip_id == CHIP_ID_YUKON_FE_P)
sky2_pci_write32(hw, PCI_DEV_REG3, 0);
pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
sky2_reset(hw);
......
drivers/net/sky2.h
View file @ 167f53d0
......@@ -2129,25 +2129,4 @@ static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg,
gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
}
/* PCI config space access */
static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg)
{
return sky2_read32(hw, Y2_CFG_SPC + reg);
}
static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg)
{
return sky2_read16(hw, Y2_CFG_SPC + reg);
}
static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val)
{
sky2_write32(hw, Y2_CFG_SPC + reg, val);
}
static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val)
{
sky2_write16(hw, Y2_CFG_SPC + reg, val);
}
#endif
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