Commit 16f2411f authored by Felix Fietkau's avatar Felix Fietkau Committed by John W. Linville

ath9k_hw: remove ATH9K_CAP_MCAST_KEYSRCH

The driver always sets this to enabled, but this can be simplified with
a small change to ah->sta_id1_defaults instead.
This change also removes the now-obsolete ath9k_hw_setcapability function.
Signed-off-by: default avatarFelix Fietkau <nbd@openwrt.org>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent f32a4884
...@@ -569,11 +569,6 @@ static void ath9k_init_crypto(struct ath9k_htc_priv *priv) ...@@ -569,11 +569,6 @@ static void ath9k_init_crypto(struct ath9k_htc_priv *priv)
*/ */
for (i = 0; i < common->keymax; i++) for (i = 0; i < common->keymax; i++)
ath9k_hw_keyreset(priv->ah, (u16) i); ath9k_hw_keyreset(priv->ah, (u16) i);
/* turn on mcast key search if possible */
if (!ath9k_hw_getcapability(priv->ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
(void)ath9k_hw_setcapability(priv->ah, ATH9K_CAP_MCAST_KEYSRCH,
1, 1, NULL);
} }
static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv) static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv)
......
...@@ -425,7 +425,9 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah) ...@@ -425,7 +425,9 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
ah->ah_flags = AH_USE_EEPROM; ah->ah_flags = AH_USE_EEPROM;
ah->atim_window = 0; ah->atim_window = 0;
ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE; ah->sta_id1_defaults =
AR_STA_ID1_CRPT_MIC_ENABLE |
AR_STA_ID1_MCAST_KSRCH;
ah->beacon_interval = 100; ah->beacon_interval = 100;
ah->enable_32kHz_clock = DONT_USE_32KHZ; ah->enable_32kHz_clock = DONT_USE_32KHZ;
ah->slottime = (u32) -1; ah->slottime = (u32) -1;
...@@ -2259,20 +2261,6 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, ...@@ -2259,20 +2261,6 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
u32 capability, u32 *result) u32 capability, u32 *result)
{ {
switch (type) { switch (type) {
case ATH9K_CAP_MCAST_KEYSRCH:
switch (capability) {
case 0:
return true;
case 1:
if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
return false;
} else {
return (ah->sta_id1_defaults &
AR_STA_ID1_MCAST_KSRCH) ? true :
false;
}
}
return false;
case ATH9K_CAP_DS: case ATH9K_CAP_DS:
return (AR_SREV_9280_20_OR_LATER(ah) && return (AR_SREV_9280_20_OR_LATER(ah) &&
(ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1)) (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
...@@ -2283,21 +2271,6 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, ...@@ -2283,21 +2271,6 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
} }
EXPORT_SYMBOL(ath9k_hw_getcapability); EXPORT_SYMBOL(ath9k_hw_getcapability);
bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
u32 capability, u32 setting, int *status)
{
switch (type) {
case ATH9K_CAP_MCAST_KEYSRCH:
if (setting)
ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
else
ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
return true;
default:
return false;
}
}
EXPORT_SYMBOL(ath9k_hw_setcapability);
/****************************/ /****************************/
/* GPIO / RFKILL / Antennae */ /* GPIO / RFKILL / Antennae */
......
...@@ -207,7 +207,6 @@ enum ath9k_hw_caps { ...@@ -207,7 +207,6 @@ enum ath9k_hw_caps {
}; };
enum ath9k_capability_type { enum ath9k_capability_type {
ATH9K_CAP_MCAST_KEYSRCH,
ATH9K_CAP_DS ATH9K_CAP_DS
}; };
...@@ -855,8 +854,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, ...@@ -855,8 +854,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
int ath9k_hw_fill_cap_info(struct ath_hw *ah); int ath9k_hw_fill_cap_info(struct ath_hw *ah);
bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
u32 capability, u32 *result); u32 capability, u32 *result);
bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
u32 capability, u32 setting, int *status);
u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan); u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
/* Key Cache Management */ /* Key Cache Management */
......
...@@ -387,12 +387,6 @@ static void ath9k_init_crypto(struct ath_softc *sc) ...@@ -387,12 +387,6 @@ static void ath9k_init_crypto(struct ath_softc *sc)
*/ */
if (!(sc->sc_ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA)) if (!(sc->sc_ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA))
common->splitmic = 1; common->splitmic = 1;
/* turn on mcast key search if possible */
if (!ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
(void)ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_MCAST_KEYSRCH,
1, 1, NULL);
} }
static int ath9k_init_btcoex(struct ath_softc *sc) static int ath9k_init_btcoex(struct ath_softc *sc)
......
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