Blackfin arch: update blackfin header files to latest one in VDSP.

a) add new processor BF52x/BF54x header files
b) update blackfin BF533/BF537/BF561 header files to latest one in VDSP.
c) scrub watchdog/rtc masks from headers as we dont need/want them (too generic and the drivers dont use them)
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com>
Signed-off-by: Roy Huang <roy.huang@analog.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

include/asm-blackfin/mach-bf527/cdefBF522.h

+/*
+ * File:         include/asm-blackfin/mach-bf527/cdefbf522.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:  system mmr register map
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _CDEF_BF522_H
+#define _CDEF_BF522_H
+
+/* include all Core registers and bit definitions */
+#include "defBF522.h"
+
+/* include core specific register pointer definitions */
+#include <asm/mach-common/cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
+
+/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
+#include "cdefBF52x_base.h"
+
+#endif /* _CDEF_BF522_H */

include/asm-blackfin/mach-bf527/defBF522.h

+/*
+ * File:         include/asm-blackfin/mach-bf527/defBF522.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _DEF_BF522_H
+#define _DEF_BF522_H
+
+/* Include all Core registers and bit definitions */
+#include <asm/mach-common/def_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
+
+/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
+#include "defBF52x_base.h"
+
+#endif /* _DEF_BF522_H */

include/asm-blackfin/mach-bf533/cdefBF532.h

@@ -51,10 +51,6 @@
 #define bfin_read_PLL_LOCKCNT()              bfin_read16(PLL_LOCKCNT)
 #define bfin_write_PLL_LOCKCNT(val)          bfin_write16(PLL_LOCKCNT,val)
 #define bfin_read_CHIPID()                   bfin_read32(CHIPID)
-#define bfin_read_SWRST()                    bfin_read16(SWRST)
-#define bfin_write_SWRST(val)                bfin_write16(SWRST,val)
-#define bfin_read_SYSCR()                    bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)                bfin_write16(SYSCR,val)
 #define bfin_read_PLL_DIV()                  bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)              bfin_write16(PLL_DIV,val)
 #define bfin_read_VR_CTL()                   bfin_read16(VR_CTL)
@@ -78,6 +74,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 }
 
 /* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
+#define bfin_read_SWRST()                    bfin_read16(SWRST)
+#define bfin_write_SWRST(val)                bfin_write16(SWRST,val)
+#define bfin_read_SYSCR()                    bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)                bfin_write16(SYSCR,val)
 #define bfin_read_SIC_IAR0()                 bfin_read32(SIC_IAR0)
 #define bfin_write_SIC_IAR0(val)             bfin_write32(SIC_IAR0,val)
 #define bfin_read_SIC_IAR1()                 bfin_read32(SIC_IAR1)
@@ -117,6 +117,18 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 #define bfin_read_RTC_PREN()                 bfin_read16(RTC_PREN)
 #define bfin_write_RTC_PREN(val)             bfin_write16(RTC_PREN,val)
 
+/* DMA Traffic controls */
+#define bfin_read_DMA_TCPER()                bfin_read16(DMA_TCPER)
+#define bfin_write_DMA_TCPER(val)            bfin_write16(DMA_TCPER,val)
+#define bfin_read_DMA_TCCNT()                bfin_read16(DMA_TCCNT)
+#define bfin_write_DMA_TCCNT(val)            bfin_write16(DMA_TCCNT,val)
+
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define bfin_read_DMA_TC_PER()               bfin_read16(DMA_TC_PER)
+#define bfin_write_DMA_TC_PER(val)           bfin_write16(DMA_TC_PER,val)
+#define bfin_read_DMA_TC_CNT()               bfin_read16(DMA_TC_CNT)
+#define bfin_write_DMA_TC_CNT(val)           bfin_write16(DMA_TC_CNT,val)
+
 /* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
 #define bfin_read_FIO_DIR()                  bfin_read16(FIO_DIR)
 #define bfin_write_FIO_DIR(val)              bfin_write16(FIO_DIR,val)
@@ -153,16 +165,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 #define bfin_read_FIO_MASKB_T()              bfin_read16(FIO_MASKB_T)
 #define bfin_write_FIO_MASKB_T(val)          bfin_write16(FIO_MASKB_T,val)
 
-/* DMA Traffic controls */
-#define bfin_read_DMA_TCPER()                bfin_read16(DMA_TCPER)
-#define bfin_write_DMA_TCPER(val)            bfin_write16(DMA_TCPER,val)
-#define bfin_read_DMA_TCCNT()                bfin_read16(DMA_TCCNT)
-#define bfin_write_DMA_TCCNT(val)            bfin_write16(DMA_TCCNT,val)
-#define bfin_read_DMA_TC_PER()               bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val)           bfin_write16(DMA_TC_PER,val)
-#define bfin_read_DMA_TC_CNT()               bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val)           bfin_write16(DMA_TC_CNT,val)
-
 /* DMA Controller */
 #define bfin_read_DMA0_CONFIG()              bfin_read16(DMA0_CONFIG)
 #define bfin_write_DMA0_CONFIG(val)          bfin_write16(DMA0_CONFIG,val)

include/asm-blackfin/mach-bf537/cdefBF534.h

@@ -399,6 +399,12 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 #define bfin_write_EBIU_SDSTAT(val)          bfin_write16(EBIU_SDSTAT,val)
 
 /* DMA Traffic Control Registers													*/
+#define bfin_read_DMA_TC_PER()                bfin_read16(DMA_TC_PER)
+#define bfin_write_DMA_TC_PER(val)            bfin_write16(DMA_TC_PER,val)
+#define bfin_read_DMA_TC_CNT()                bfin_read16(DMA_TC_CNT)
+#define bfin_write_DMA_TC_CNT(val)            bfin_write16(DMA_TC_CNT,val)
+
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
 #define bfin_read_DMA_TCPER()                bfin_read16(DMA_TCPER)
 #define bfin_write_DMA_TCPER(val)            bfin_write16(DMA_TCPER,val)
 #define bfin_read_DMA_TCCNT()                bfin_read16(DMA_TCCNT)
@@ -1075,8 +1081,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 #define bfin_write_CAN_UCRC(val)             bfin_write16(CAN_UCRC,val)
 #define bfin_read_CAN_UCCNF()                bfin_read16(CAN_UCCNF)
 #define bfin_write_CAN_UCCNF(val)            bfin_write16(CAN_UCCNF,val)
-#define bfin_read_CAN_SFCMVER2()             bfin_read16(CAN_SFCMVER2)
-#define bfin_write_CAN_SFCMVER2(val)         bfin_write16(CAN_SFCMVER2,val)
 
 /* Mailbox Acceptance Masks */
 #define bfin_read_CAN_AM00L()                bfin_read16(CAN_AM00L)

include/asm-blackfin/mach-bf537/defBF534.h

@@ -216,6 +216,10 @@
 #define EBIU_SDSTAT			0xFFC00A1C	/* SDRAM Status Register                                                */
 
 /* DMA Traffic Control Registers													*/
+#define DMA_TC_PER			0xFFC00B0C	/* Traffic Control Periods Register			*/
+#define DMA_TC_CNT			0xFFC00B10	/* Traffic Control Current Counts Register	*/
+
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
 #define DMA_TCPER			0xFFC00B0C	/* Traffic Control Periods Register			*/
 #define DMA_TCCNT			0xFFC00B10	/* Traffic Control Current Counts Register	*/
 
@@ -563,7 +567,7 @@
 #define CAN_GIF				0xFFC02A9C	/* Global Interrupt Flag Register                               */
 #define CAN_CONTROL			0xFFC02AA0	/* Master Control Register                                              */
 #define CAN_INTR			0xFFC02AA4	/* Interrupt Pending Register                                   */
-#define CAN_SFCMVER			0xFFC02AA8	/* Version Code Register                                                */
+
 #define CAN_MBTD			0xFFC02AAC	/* Mailbox Temporary Disable Feature                    */
 #define CAN_EWR				0xFFC02AB0	/* Programmable Warning Level                                   */
 #define CAN_ESR				0xFFC02AB4	/* Error Status Register                                                */
@@ -1026,10 +1030,11 @@
 #define	VLEV_130		0x00F0	/*              VLEV = 1.30 V (-5% - +10% Accuracy)     */
 
 #define	WAKE			0x0100	/* Enable RTC/Reset Wakeup From Hibernate       */
-#define PHYWE			0x0200	/* Enable PHY Wakeup From Hibernate                     */
-#define	CANWE			0x0400	/* Enable CAN Wakeup From Hibernate                     */
-#define	PHYCLKOE		0x4000	/* PHY Clock Output Enable                                      */
-#define	CKELOW			0x8000	/* Enable Drive CKE Low During Reset            */
+#define	CANWE			0x0200	/* Enable CAN Wakeup From Hibernate			*/
+#define	PHYWE			0x0400	/* Enable PHY Wakeup From Hibernate			*/
+#define	CLKBUFOE		0x4000	/* CLKIN Buffer Output Enable */
+#define	PHYCLKOE		CLKBUFOE	/* Alternative legacy name for the above */
+#define	SCKELOW		0x8000	/* Enable Drive CKE Low During Reset		*/
 
 /* PLL_STAT Masks																	*/
 #define ACTIVE_PLLENABLED	0x0001	/* Processor In Active Mode With PLL Enabled    */
@@ -1050,7 +1055,7 @@
 #define RESET_SOFTWARE		0x8000	/* SW Reset Occurred Since Last Read Of SWRST   */
 
 /* SYSCR Masks																				*/
-#define BMODE				0x0006	/* Boot Mode - Latched During HW Reset From Mode Pins   */
+#define BMODE				0x0007	/* Boot Mode - Latched During HW Reset From Mode Pins   */
 #define	NOBOOT				0x0010	/* Execute From L1 or ASYNC Bank 0 When BMODE = 0               */
 
 /* *************  SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
@@ -1107,19 +1112,9 @@
 #define IWR_ENABLE(x)	(1 << ((x)&0x1F))	/* Wakeup Enable Peripheral #x          */
 #define IWR_DISABLE(x)	(0xFFFFFFFF ^ (1 << ((x)&0x1F)))	/* Wakeup Disable Peripheral #x         */
 
-/* ***************  WATCHDOG TIMER MASKS  *******************************************/
-/* WDOG_CTL Masks																	*/
-#define WDOG_RESET		0x0000	/* Generate Reset Event                                                 */
-#define WDOG_NMI		0x0002	/* Generate Non-Maskable Interrupt (NMI) Event  */
-#define WDOG_GPI		0x0004	/* Generate General Purpose (GP) Interrupt              */
-#define WDOG_NONE		0x0006	/* Disable Watchdog Timer Interrupts                    */
-#define TMR_EN			0x0FF0	/* Watchdog Counter Enable                                              */
-#define	TMR_DIS			0x0AD0	/* Watchdog Counter Disable                                             */
-#define TRO			0x8000	/* Watchdog Expired                                                     */
-
 /* ************** UART CONTROLLER MASKS *************************/
 /* UARTx_LCR Masks												*/
-#define WLS(x)		((((x)&0x3)-5) & 0x03)	/* Word Length Select   */
+#define WLS(x)		(((x)-5) & 0x03)	/* Word Length Select   */
 #define STB			0x04	/* Stop Bits                    */
 #define PEN			0x08	/* Parity Enable                */
 #define EPS			0x10	/* Even Parity Select   */
@@ -1128,8 +1123,8 @@
 #define DLAB		0x80	/* Divisor Latch Access */
 
 /* UARTx_MCR Mask										*/
-#define LOOP		0x10	/* Loopback Mode Enable         */
-
+#define LOOP_ENA		0x10	/* Loopback Mode Enable         */
+#define LOOP_ENA_P	0x04
 /* UARTx_LSR Masks										*/
 #define DR			0x01	/* Data Ready                           */
 #define OE			0x02	/* Overrun Error                        */
@@ -1229,10 +1224,10 @@
 #define TIMIL1			0x00000002	/* Timer 1 Interrupt                            */
 #define TIMIL2			0x00000004	/* Timer 2 Interrupt                            */
 #define TIMIL3			0x00000008	/* Timer 3 Interrupt                            */
-#define TOVL_ERR0		0x00000010	/* Timer 0 Counter Overflow                     */
-#define TOVL_ERR1		0x00000020	/* Timer 1 Counter Overflow                     */
-#define TOVL_ERR2		0x00000040	/* Timer 2 Counter Overflow                     */
-#define TOVL_ERR3		0x00000080	/* Timer 3 Counter Overflow                     */
+#define TOVF_ERR0		0x00000010	/* Timer 0 Counter Overflow			*/
+#define TOVF_ERR1		0x00000020	/* Timer 1 Counter Overflow			*/
+#define TOVF_ERR2		0x00000040	/* Timer 2 Counter Overflow			*/
+#define TOVF_ERR3		0x00000080	/* Timer 3 Counter Overflow			*/
 #define TRUN0			0x00001000	/* Timer 0 Slave Enable Status          */
 #define TRUN1			0x00002000	/* Timer 1 Slave Enable Status          */
 #define TRUN2			0x00004000	/* Timer 2 Slave Enable Status          */
@@ -1241,15 +1236,24 @@
 #define TIMIL5			0x00020000	/* Timer 5 Interrupt                            */
 #define TIMIL6			0x00040000	/* Timer 6 Interrupt                            */
 #define TIMIL7			0x00080000	/* Timer 7 Interrupt                            */
-#define TOVL_ERR4		0x00100000	/* Timer 4 Counter Overflow                     */
-#define TOVL_ERR5		0x00200000	/* Timer 5 Counter Overflow                     */
-#define TOVL_ERR6		0x00400000	/* Timer 6 Counter Overflow                     */
-#define TOVL_ERR7		0x00800000	/* Timer 7 Counter Overflow                     */
+#define TOVF_ERR4		0x00100000	/* Timer 4 Counter Overflow			*/
+#define TOVF_ERR5		0x00200000	/* Timer 5 Counter Overflow			*/
+#define TOVF_ERR6		0x00400000	/* Timer 6 Counter Overflow			*/
+#define TOVF_ERR7		0x00800000	/* Timer 7 Counter Overflow			*/
 #define TRUN4			0x10000000	/* Timer 4 Slave Enable Status          */
 #define TRUN5			0x20000000	/* Timer 5 Slave Enable Status          */
 #define TRUN6			0x40000000	/* Timer 6 Slave Enable Status          */
 #define TRUN7			0x80000000	/* Timer 7 Slave Enable Status          */
 
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define TOVL_ERR0 TOVF_ERR0
+#define TOVL_ERR1 TOVF_ERR1
+#define TOVL_ERR2 TOVF_ERR2
+#define TOVL_ERR3 TOVF_ERR3
+#define TOVL_ERR4 TOVF_ERR4
+#define TOVL_ERR5 TOVF_ERR5
+#define TOVL_ERR6 TOVF_ERR6
+#define TOVL_ERR7 TOVF_ERR7
 /* TIMERx_CONFIG Masks													*/
 #define PWM_OUT			0x0001	/* Pulse-Width Modulation Output Mode   */
 #define WDTH_CAP		0x0002	/* Width Capture Input Mode                             */
@@ -1647,6 +1651,8 @@
 #define EBSZ_32			0x0002	/* SDRAM External Bank Size = 32MB                                              */
 #define EBSZ_64			0x0004	/* SDRAM External Bank Size = 64MB                                              */
 #define EBSZ_128		0x0006	/* SDRAM External Bank Size = 128MB                                             */
+#define EBSZ_256		0x0008		/* SDRAM External Bank Size = 256MB 	*/
+#define EBSZ_512		0x000A		/* SDRAM External Bank Size = 512MB		*/
 #define EBCAW_8			0x0000	/* SDRAM External Bank Column Address Width = 8 Bits    */
 #define EBCAW_9			0x0010	/* SDRAM External Bank Column Address Width = 9 Bits    */
 #define EBCAW_10		0x0020	/* SDRAM External Bank Column Address Width = 10 Bits   */
@@ -1859,8 +1865,10 @@
 #define	TXECNT		0xFF00	/* Transmit Error Counter       */
 
 /* CAN_INTR Masks											*/
-#define	MBRIF		0x0001	/* Mailbox Receive Interrupt    */
-#define	MBTIF		0x0002	/* Mailbox Transmit Interrupt   */
+#define	MBRIRQ	0x0001	/* Mailbox Receive Interrupt	*/
+#define	MBRIF		MBRIRQ	/* legacy */
+#define	MBTIRQ	0x0002	/* Mailbox Transmit Interrupt	*/
+#define	MBTIF		MBTIRQ	/* legacy */
 #define	GIRQ		0x0004	/* Global Interrupt                             */
 #define	SMACK		0x0008	/* Sleep Mode Acknowledge               */
 #define	CANTX		0x0040	/* CAN TX Bus Value                             */
@@ -2445,8 +2453,8 @@
 #define	PJCE_SPI		0x0004	/*              Enable SPI_SSEL7                        */
 
 #define	PFDE			0x0008	/* Port F DMA Request Enable            */
-#define	PGDE_UART		0x0000	/*              Enable UART0 RX/TX                      */
-#define	PGDE_DMA		0x0008	/*              Enable DMAR1:0                          */
+#define	PFDE_UART		0x0000	/*              Enable UART0 RX/TX                      */
+#define	PFDE_DMA		0x0008	/*              Enable DMAR1:0                          */
 
 #define	PFTE			0x0010	/* Port F Timer Enable                          */
 #define	PFTE_UART		0x0000	/*              Enable UART1 RX/TX                      */
@@ -2498,4 +2506,20 @@
 #define	OI			0x4000	/* Overflow Interrupt Generated                         */
 #define	BDI			0x8000	/* Block Done Interrupt Generated                       */
 
+/* entry addresses of the user-callable Boot ROM functions */
+
+#define _BOOTROM_RESET 0xEF000000 
+#define _BOOTROM_FINAL_INIT 0xEF000002 
+#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
+#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 
+#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A 
+#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C 
+#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
+#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
+#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define	PGDE_UART   PFDE_UART
+#define	PGDE_DMA    PFDE_DMA
+#define	CKELOW		SCKELOW
 #endif				/* _DEF_BF534_H */

include/asm-blackfin/mach-bf537/defBF537.h

@@ -32,12 +32,12 @@
 #ifndef _DEF_BF537_H
 #define _DEF_BF537_H
 
-/*include all Core registers and bit definitions*/
-#include "defBF537.h"
-
-/*include core specific register pointer definitions*/
+/* Include all Core registers and bit definitions*/
 #include <asm/mach-common/cdef_LPBlackfin.h>
 
+/* Include all MMR and bit defines common to BF534 */
+#include "defBF534.h"
+
 /************************************************************************************
 ** Define EMAC Section Unique to BF536/BF537
 *************************************************************************************/

include/asm-blackfin/mach-bf561/defBF561.h

@@ -904,23 +904,6 @@
 #define IWR_ENABLE(x)	       (1 << (x))	/* Wakeup Enable Peripheral #x */
 #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x)))	/* Wakeup Disable Peripheral #x */
 
-/* *********  WATCHDOG TIMER MASKS  ********************8 */
-
-/* Watchdog Timer WDOG_CTL Register */
-#define ICTL(x) ((x<<1) & 0x0006)
-#define ENABLE_RESET     0x00000000	/* Set Watchdog Timer to generate reset */
-#define ENABLE_NMI       0x00000002	/* Set Watchdog Timer to generate non-maskable interrupt */
-#define ENABLE_GPI       0x00000004	/* Set Watchdog Timer to generate general-purpose interrupt */
-#define DISABLE_EVT      0x00000006	/* Disable Watchdog Timer interrupts */
-
-#define TMR_EN		0x0000
-#define TMR_DIS		0x0AD0
-#define TRO		0x8000
-
-#define ICTL_P0		0x01
-#define ICTL_P1		0x02
-#define TRO_P		0x0F
-
 /* ***************************** UART CONTROLLER MASKS ********************** */
 
 /* UART_LCR Register */
@@ -1214,18 +1197,18 @@
 #define TIMIL9		0x0002
 #define TIMIL10		0x0004
 #define TIMIL11		0x0008
-#define TOVL_ERR0	0x00000010
-#define TOVL_ERR1	0x00000020
-#define TOVL_ERR2	0x00000040
-#define TOVL_ERR3	0x00000080
-#define TOVL_ERR4	0x00100000
-#define TOVL_ERR5	0x00200000
-#define TOVL_ERR6	0x00400000
-#define TOVL_ERR7	0x00800000
-#define TOVL_ERR8	0x0010
-#define TOVL_ERR9	0x0020
-#define TOVL_ERR10	0x0040
-#define TOVL_ERR11	0x0080
+#define TOVF_ERR0	0x00000010
+#define TOVF_ERR1	0x00000020
+#define TOVF_ERR2	0x00000040
+#define TOVF_ERR3	0x00000080
+#define TOVF_ERR4	0x00100000
+#define TOVF_ERR5	0x00200000
+#define TOVF_ERR6	0x00400000
+#define TOVF_ERR7	0x00800000
+#define TOVF_ERR8	0x0010
+#define TOVF_ERR9	0x0020
+#define TOVF_ERR10	0x0040
+#define TOVF_ERR11	0x0080
 #define TRUN0		0x00001000
 #define TRUN1		0x00002000
 #define TRUN2		0x00004000
@@ -1251,18 +1234,18 @@
 #define TIMIL9_P	0x01
 #define TIMIL10_P	0x02
 #define TIMIL11_P	0x03
-#define TOVL_ERR0_P	0x04
-#define TOVL_ERR1_P	0x05
-#define TOVL_ERR2_P	0x06
-#define TOVL_ERR3_P	0x07
-#define TOVL_ERR4_P	0x14
-#define TOVL_ERR5_P	0x15
-#define TOVL_ERR6_P	0x16
-#define TOVL_ERR7_P	0x17
-#define TOVL_ERR8_P	0x04
-#define TOVL_ERR9_P	0x05
-#define TOVL_ERR10_P	0x06
-#define TOVL_ERR11_P	0x07
+#define TOVF_ERR0_P	0x04
+#define TOVF_ERR1_P	0x05
+#define TOVF_ERR2_P	0x06
+#define TOVF_ERR3_P	0x07
+#define TOVF_ERR4_P	0x14
+#define TOVF_ERR5_P	0x15
+#define TOVF_ERR6_P	0x16
+#define TOVF_ERR7_P	0x17
+#define TOVF_ERR8_P	0x04
+#define TOVF_ERR9_P	0x05
+#define TOVF_ERR10_P	0x06
+#define TOVF_ERR11_P	0x07
 #define TRUN0_P		0x0C
 #define TRUN1_P		0x0D
 #define TRUN2_P		0x0E
@@ -1276,6 +1259,32 @@
 #define TRUN10_P	0x0E
 #define TRUN11_P	0x0F
 
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define TOVL_ERR0 TOVF_ERR0
+#define TOVL_ERR1 TOVF_ERR1
+#define TOVL_ERR2 TOVF_ERR2
+#define TOVL_ERR3 TOVF_ERR3
+#define TOVL_ERR4 TOVF_ERR4
+#define TOVL_ERR5 TOVF_ERR5
+#define TOVL_ERR6 TOVF_ERR6
+#define TOVL_ERR7 TOVF_ERR7
+#define TOVL_ERR8 TOVF_ERR8
+#define TOVL_ERR9 TOVF_ERR9
+#define TOVL_ERR10 TOVF_ERR10
+#define TOVL_ERR11 TOVF_ERR11
+#define TOVL_ERR0_P TOVF_ERR0_P
+#define TOVL_ERR1_P TOVF_ERR1_P
+#define TOVL_ERR2_P TOVF_ERR2_P
+#define TOVL_ERR3_P TOVF_ERR3_P
+#define TOVL_ERR4_P TOVF_ERR4_P
+#define TOVL_ERR5_P TOVF_ERR5_P
+#define TOVL_ERR6_P TOVF_ERR6_P
+#define TOVL_ERR7_P TOVF_ERR7_P
+#define TOVL_ERR8_P TOVF_ERR8_P
+#define TOVL_ERR9_P TOVF_ERR9_P
+#define TOVL_ERR10_P TOVF_ERR10_P
+#define TOVL_ERR11_P TOVF_ERR11_P
+
 /* TIMERx_CONFIG Registers */
 #define PWM_OUT		0x0001
 #define WDTH_CAP	0x0002
@@ -1700,18 +1709,4 @@
 #define SDEASE		    0x00000010	/* SDRAM EAB sticky error status - W1C */
 #define BGSTAT			0x00000020	/* Bus granted */
 
-/*VR_CTL Masks*/
-#define WAKE                    0x100
-#define VLEV_6                  0x60
-#define VLEV_7                  0x70
-#define VLEV_8                  0x80
-#define VLEV_9                  0x90
-#define VLEV_10                 0xA0
-#define VLEV_11                 0xB0
-#define VLEV_12                 0xC0
-#define VLEV_13                 0xD0
-#define VLEV_14                 0xE0
-#define VLEV_15                 0xF0
-#define FREQ_3                  0x03
-
 #endif				/* _DEF_BF561_H */