Commit 1bdcc35f authored by Chiawen Huang's avatar Chiawen Huang Committed by Alex Deucher

drm/amd/display: reduce sr_xxx_time by 3 us when ppt disable

[Why]
when ppt disabled, the watermark doesn't get fine tune causing
underflow.

[How]
It is a temporary solution to reduce sr_xxx_time by 3 us when ppt
disable.
Signed-off-by: default avatarChiawen Huang <chiawen.huang@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ca751df2
...@@ -634,6 +634,42 @@ static struct wm_table lpddr4_wm_table = { ...@@ -634,6 +634,42 @@ static struct wm_table lpddr4_wm_table = {
} }
}; };
static struct wm_table lpddr4_wm_table_with_disabled_ppt = {
.entries = {
{
.wm_inst = WM_A,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
.sr_exit_time_us = 8.32,
.sr_enter_plus_exit_time_us = 9.38,
.valid = true,
},
{
.wm_inst = WM_B,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
.sr_exit_time_us = 9.82,
.sr_enter_plus_exit_time_us = 11.196,
.valid = true,
},
{
.wm_inst = WM_C,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
.sr_exit_time_us = 9.89,
.sr_enter_plus_exit_time_us = 11.24,
.valid = true,
},
{
.wm_inst = WM_D,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
.sr_exit_time_us = 9.748,
.sr_enter_plus_exit_time_us = 11.102,
.valid = true,
},
}
};
static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage) static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)
{ {
...@@ -738,6 +774,7 @@ void rn_clk_mgr_construct( ...@@ -738,6 +774,7 @@ void rn_clk_mgr_construct(
struct clk_log_info log_info = {0}; struct clk_log_info log_info = {0};
clk_mgr->smu_ver = rn_vbios_smu_get_smu_version(clk_mgr); clk_mgr->smu_ver = rn_vbios_smu_get_smu_version(clk_mgr);
clk_mgr->periodic_retraining_disabled = rn_vbios_smu_is_periodic_retraining_disabled(clk_mgr);
/* SMU Version 55.51.0 and up no longer have an issue /* SMU Version 55.51.0 and up no longer have an issue
* that needs to limit minimum dispclk */ * that needs to limit minimum dispclk */
...@@ -752,7 +789,11 @@ void rn_clk_mgr_construct( ...@@ -752,7 +789,11 @@ void rn_clk_mgr_construct(
clk_mgr->base.dentist_vco_freq_khz = 3600000; clk_mgr->base.dentist_vco_freq_khz = 3600000;
if (ctx->dc_bios->integrated_info->memory_type == LpDdr4MemType) { if (ctx->dc_bios->integrated_info->memory_type == LpDdr4MemType) {
rn_bw_params.wm_table = lpddr4_wm_table; if (clk_mgr->periodic_retraining_disabled) {
rn_bw_params.wm_table = lpddr4_wm_table_with_disabled_ppt;
} else {
rn_bw_params.wm_table = lpddr4_wm_table;
}
} else { } else {
rn_bw_params.wm_table = ddr4_wm_table; rn_bw_params.wm_table = ddr4_wm_table;
} }
......
...@@ -52,7 +52,8 @@ ...@@ -52,7 +52,8 @@
#define VBIOSSMC_MSG_GetFclkFrequency 0xB #define VBIOSSMC_MSG_GetFclkFrequency 0xB
#define VBIOSSMC_MSG_SetDisplayCount 0xC #define VBIOSSMC_MSG_SetDisplayCount 0xC
#define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0xD #define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0xD
#define VBIOSSMC_MSG_UpdatePmeRestore 0xE #define VBIOSSMC_MSG_UpdatePmeRestore 0xE
#define VBIOSSMC_MSG_IsPeriodicRetrainingDisabled 0xF
#define VBIOSSMC_Status_BUSY 0x0 #define VBIOSSMC_Status_BUSY 0x0
#define VBIOSSMC_Result_OK 0x1 #define VBIOSSMC_Result_OK 0x1
...@@ -100,7 +101,7 @@ int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned ...@@ -100,7 +101,7 @@ int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned
result = rn_smu_wait_for_response(clk_mgr, 10, 1000); result = rn_smu_wait_for_response(clk_mgr, 10, 1000);
ASSERT(result == VBIOSSMC_Result_OK); ASSERT(result == VBIOSSMC_Result_OK || result == VBIOSSMC_Result_UnknownCmd);
/* Actual dispclk set is returned in the parameter register */ /* Actual dispclk set is returned in the parameter register */
return REG_READ(MP1_SMN_C2PMSG_83); return REG_READ(MP1_SMN_C2PMSG_83);
...@@ -232,3 +233,11 @@ void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr) ...@@ -232,3 +233,11 @@ void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)
VBIOSSMC_MSG_UpdatePmeRestore, VBIOSSMC_MSG_UpdatePmeRestore,
0); 0);
} }
int rn_vbios_smu_is_periodic_retraining_disabled(struct clk_mgr_internal *clk_mgr)
{
return rn_vbios_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_IsPeriodicRetrainingDisabled,
0);
}
...@@ -36,5 +36,6 @@ int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_ ...@@ -36,5 +36,6 @@ int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_
void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, int display_count); void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, int display_count);
void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable); void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr); void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
int rn_vbios_smu_is_periodic_retraining_disabled(struct clk_mgr_internal *clk_mgr);
#endif /* DAL_DC_DCN10_RV1_CLK_MGR_VBIOS_SMU_H_ */ #endif /* DAL_DC_DCN10_RV1_CLK_MGR_VBIOS_SMU_H_ */
...@@ -270,6 +270,7 @@ struct clk_mgr_internal { ...@@ -270,6 +270,7 @@ struct clk_mgr_internal {
enum dm_pp_clocks_state max_clks_state; enum dm_pp_clocks_state max_clks_state;
enum dm_pp_clocks_state cur_min_clks_state; enum dm_pp_clocks_state cur_min_clks_state;
bool periodic_retraining_disabled;
unsigned int cur_phyclk_req_table[MAX_PIPES * 2]; unsigned int cur_phyclk_req_table[MAX_PIPES * 2];
#ifdef CONFIG_DRM_AMD_DC_DCN3_0 #ifdef CONFIG_DRM_AMD_DC_DCN3_0
......
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