Commit 1ce02996 authored by Mark A. Greer's avatar Mark A. Greer Committed by Kevin Hilman

arm: omap3: am35x: Don't mark missing features as present

The Chip Identification register on the am35x family of SoCs
has bits 12, 7:5, and 3:2 marked as reserved and are read as
zeroes.  Unfortunately, on other omap SoCs, a 0 bit means a
feature is "Full Use" so the OMAP3_CHECK_FEATURE() macro
called by omap3_check_features() will incorrectly interpret
those zeroes to mean that a feature is present even though it
isn't.  To fix that, the feature bits that are incorrectly
set (namely, OMAP3_HAS_IVA and OMAP3_HAS_ISP) need to be
cleared after all of the calls to OMAP3_CHECK_FEATURE() in
omap3_check_features() are made.
Signed-off-by: default avatarMark A. Greer <mgreer@animalcreek.com>
[khilman@ti.com: use soc_is_am35xx() instead of cpu_is_am35xx()]
Signed-off-by: default avatarKevin Hilman <khilman@ti.com>
parent 99b59df0
...@@ -246,6 +246,17 @@ void __init omap3xxx_check_features(void) ...@@ -246,6 +246,17 @@ void __init omap3xxx_check_features(void)
omap_features |= OMAP3_HAS_SDRC; omap_features |= OMAP3_HAS_SDRC;
/*
* am35x fixups:
* - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as
* reserved and therefore return 0 when read. Unfortunately,
* OMAP3_CHECK_FEATURE() will interpret some of those zeroes to
* mean that a feature is present even though it isn't so clear
* the incorrectly set feature bits.
*/
if (soc_is_am35xx())
omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP);
/* /*
* TODO: Get additional info (where applicable) * TODO: Get additional info (where applicable)
* e.g. Size of L2 cache. * e.g. Size of L2 cache.
......
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