Commit 1e7decdb authored by David Daney's avatar David Daney Committed by John Crispin

MIPS: Probe for and report hardware virtualization support.

The presence of the MIPS Virtualization Application-Specific Extension
is indicated by CP0_Config3[23].  Probe for this and report it in
/proc/cpuinfo.
Signed-off-by: default avatarDavid Daney <david.daney@cavium.com>
Patchwork: http://patchwork.linux-mips.org/patch/4904/Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
parent 27ea052a
...@@ -263,4 +263,8 @@ ...@@ -263,4 +263,8 @@
#define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI) #define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI)
#endif #endif
#ifndef cpu_has_vz
#define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ)
#endif
#endif /* __ASM_CPU_FEATURES_H */ #endif /* __ASM_CPU_FEATURES_H */
...@@ -336,6 +336,6 @@ enum cpu_type_enum { ...@@ -336,6 +336,6 @@ enum cpu_type_enum {
#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ #define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ #define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */
#define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */ #define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */
#define MIPS_ASE_VZ 0x00000080 /* Virtualization ASE */
#endif /* _ASM_CPU_H */ #endif /* _ASM_CPU_H */
...@@ -596,6 +596,7 @@ ...@@ -596,6 +596,7 @@
#define MIPS_CONF3_RXI (_ULCAST_(1) << 12) #define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
#define MIPS_CONF3_ISA (_ULCAST_(3) << 14) #define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
#define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
......
...@@ -442,6 +442,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) ...@@ -442,6 +442,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
c->options |= MIPS_CPU_ULRI; c->options |= MIPS_CPU_ULRI;
if (config3 & MIPS_CONF3_ISA) if (config3 & MIPS_CONF3_ISA)
c->options |= MIPS_CPU_MICROMIPS; c->options |= MIPS_CPU_MICROMIPS;
if (config3 & MIPS_CONF3_VZ)
c->ases |= MIPS_ASE_VZ;
return config3 & MIPS_CONF_M; return config3 & MIPS_CONF_M;
} }
......
...@@ -74,6 +74,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) ...@@ -74,6 +74,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
if (cpu_has_dsp2) seq_printf(m, "%s", " dsp2"); if (cpu_has_dsp2) seq_printf(m, "%s", " dsp2");
if (cpu_has_mipsmt) seq_printf(m, "%s", " mt"); if (cpu_has_mipsmt) seq_printf(m, "%s", " mt");
if (cpu_has_mmips) seq_printf(m, "%s", " micromips"); if (cpu_has_mmips) seq_printf(m, "%s", " micromips");
if (cpu_has_vz) seq_printf(m, "%s", " vz");
seq_printf(m, "\n"); seq_printf(m, "\n");
seq_printf(m, "shadow register sets\t: %d\n", seq_printf(m, "shadow register sets\t: %d\n",
......
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