Commit 1f150b3e authored by Marcin Slusarz's avatar Marcin Slusarz Committed by Ben Skeggs

drm/nv40: allocate ctxprog with kmalloc

Some archs defconfigs have CONFIG_FRAME_WARN set to 1024, which lead to this
warning:
drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c: warning: the frame size
of 1184 bytes is larger than 1024 bytes
Reported-by: default avatarGeert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: default avatarMarcin Slusarz <marcin.slusarz@gmail.com>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 4113014f
...@@ -669,21 +669,27 @@ nv40_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem) ...@@ -669,21 +669,27 @@ nv40_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem)
}); });
} }
void int
nv40_grctx_init(struct nouveau_device *device, u32 *size) nv40_grctx_init(struct nouveau_device *device, u32 *size)
{ {
u32 ctxprog[256], i; u32 *ctxprog = kmalloc(256 * 4, GFP_KERNEL), i;
struct nouveau_grctx ctx = { struct nouveau_grctx ctx = {
.device = device, .device = device,
.mode = NOUVEAU_GRCTX_PROG, .mode = NOUVEAU_GRCTX_PROG,
.data = ctxprog, .data = ctxprog,
.ctxprog_max = ARRAY_SIZE(ctxprog) .ctxprog_max = 256,
}; };
if (!ctxprog)
return -ENOMEM;
nv40_grctx_generate(&ctx); nv40_grctx_generate(&ctx);
nv_wr32(device, 0x400324, 0); nv_wr32(device, 0x400324, 0);
for (i = 0; i < ctx.ctxprog_len; i++) for (i = 0; i < ctx.ctxprog_len; i++)
nv_wr32(device, 0x400328, ctxprog[i]); nv_wr32(device, 0x400328, ctxprog[i]);
*size = ctx.ctxvals_pos * 4; *size = ctx.ctxvals_pos * 4;
kfree(ctxprog);
return 0;
} }
...@@ -346,7 +346,9 @@ nv40_graph_init(struct nouveau_object *object) ...@@ -346,7 +346,9 @@ nv40_graph_init(struct nouveau_object *object)
return ret; return ret;
/* generate and upload context program */ /* generate and upload context program */
nv40_grctx_init(nv_device(priv), &priv->size); ret = nv40_grctx_init(nv_device(priv), &priv->size);
if (ret)
return ret;
/* No context present currently */ /* No context present currently */
nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000); nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
......
...@@ -15,7 +15,7 @@ nv44_graph_class(void *priv) ...@@ -15,7 +15,7 @@ nv44_graph_class(void *priv)
return !(0x0baf & (1 << (device->chipset & 0x0f))); return !(0x0baf & (1 << (device->chipset & 0x0f)));
} }
void nv40_grctx_init(struct nouveau_device *, u32 *size); int nv40_grctx_init(struct nouveau_device *, u32 *size);
void nv40_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *); void nv40_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *);
#endif #endif
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