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Commit 1f6a717f authored by Benoit Cousson's avatar Benoit Cousson Committed by Tony Lindgren
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OMAP4: hwmod data: Move the smartreflex structures 

The merge of the SR series on top of the already modified
omap_hwmod_data_44xx.c moved the smartreflex structures at the wrong
position in the file.
- Re-order the structures properly.
Signed-off-by: default avatarBenoit Cousson <b-cousson@ti.com>
Cc: Thara Gopinath <thara@ti.com>
Tested-by: default avatarG, Manjunath Kondaiah <manjugk@ti.com>
Acked-by: default avatarKevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 4d218826
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Showing with 169 additions and 172 deletions
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
View file @ 1f6a717f
...@@ -556,9 +556,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { ...@@ -556,9 +556,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
* sl2if * sl2if
* slimbus1 * slimbus1
* slimbus2 * slimbus2
* smartreflex_core
* smartreflex_iva
* smartreflex_mpu
* spinlock * spinlock
* timer1 * timer1
* timer10 * timer10
...@@ -1392,6 +1389,170 @@ static struct omap_hwmod omap44xx_mpu_hwmod = { ...@@ -1392,6 +1389,170 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
}; };
/*
* 'smartreflex' class
* smartreflex module (monitor silicon performance and outputs a measure of
* performance error)
*/
/* The IP is not compliant to type1 / type2 scheme */
static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
.sidle_shift = 24,
.enwkup_shift = 26,
};
static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
.sysc_offs = 0x0038,
.sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type_smartreflex,
};
static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
.name = "smartreflex",
.sysc = &omap44xx_smartreflex_sysc,
.rev = 2,
};
/* smartreflex_core */
static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
{ .irq = 19 + OMAP44XX_IRQ_GIC_START },
};
static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
{
.pa_start = 0x4a0dd000,
.pa_end = 0x4a0dd03f,
.flags = ADDR_TYPE_RT
},
};
/* l4_cfg -> smartreflex_core */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_smartreflex_core_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_smartreflex_core_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* smartreflex_core slave ports */
static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
&omap44xx_l4_cfg__smartreflex_core,
};
static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
.name = "smartreflex_core",
.class = &omap44xx_smartreflex_hwmod_class,
.mpu_irqs = omap44xx_smartreflex_core_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
.main_clk = "smartreflex_core_fck",
.vdd_name = "core",
.prcm = {
.omap4 = {
.clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
},
},
.slaves = omap44xx_smartreflex_core_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* smartreflex_iva */
static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
{ .irq = 102 + OMAP44XX_IRQ_GIC_START },
};
static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
{
.pa_start = 0x4a0db000,
.pa_end = 0x4a0db03f,
.flags = ADDR_TYPE_RT
},
};
/* l4_cfg -> smartreflex_iva */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_smartreflex_iva_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_smartreflex_iva_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* smartreflex_iva slave ports */
static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
&omap44xx_l4_cfg__smartreflex_iva,
};
static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
.name = "smartreflex_iva",
.class = &omap44xx_smartreflex_hwmod_class,
.mpu_irqs = omap44xx_smartreflex_iva_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
.main_clk = "smartreflex_iva_fck",
.vdd_name = "iva",
.prcm = {
.omap4 = {
.clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
},
},
.slaves = omap44xx_smartreflex_iva_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* smartreflex_mpu */
static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
{ .irq = 18 + OMAP44XX_IRQ_GIC_START },
};
static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
{
.pa_start = 0x4a0d9000,
.pa_end = 0x4a0d903f,
.flags = ADDR_TYPE_RT
},
};
/* l4_cfg -> smartreflex_mpu */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_smartreflex_mpu_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_smartreflex_mpu_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* smartreflex_mpu slave ports */
static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
&omap44xx_l4_cfg__smartreflex_mpu,
};
static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
.name = "smartreflex_mpu",
.class = &omap44xx_smartreflex_hwmod_class,
.mpu_irqs = omap44xx_smartreflex_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
.main_clk = "smartreflex_mpu_fck",
.vdd_name = "mpu",
.prcm = {
.omap4 = {
.clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
},
},
.slaves = omap44xx_smartreflex_mpu_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* /*
* 'uart' class * 'uart' class
* universal asynchronous receiver/transmitter (uart) * universal asynchronous receiver/transmitter (uart)
...@@ -1842,170 +2003,6 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = { ...@@ -1842,170 +2003,6 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
}; };
/*
* 'smartreflex' class
* smartreflex module (monitor silicon performance and outputs a measure of
* performance error)
*/
/* The IP is not compliant to type1 / type2 scheme */
static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
.sidle_shift = 24,
.enwkup_shift = 26,
};
static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
.sysc_offs = 0x0038,
.sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type_smartreflex,
};
static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
.name = "smartreflex",
.sysc = &omap44xx_smartreflex_sysc,
.rev = 2,
};
/* smartreflex_core */
static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
{ .irq = 19 + OMAP44XX_IRQ_GIC_START },
};
static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
{
.pa_start = 0x4a0dd000,
.pa_end = 0x4a0dd03f,
.flags = ADDR_TYPE_RT
},
};
/* l4_cfg -> smartreflex_core */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_smartreflex_core_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_smartreflex_core_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* smartreflex_core slave ports */
static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
&omap44xx_l4_cfg__smartreflex_core,
};
static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
.name = "smartreflex_core",
.class = &omap44xx_smartreflex_hwmod_class,
.mpu_irqs = omap44xx_smartreflex_core_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
.main_clk = "smartreflex_core_fck",
.vdd_name = "core",
.prcm = {
.omap4 = {
.clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
},
},
.slaves = omap44xx_smartreflex_core_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* smartreflex_iva */
static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
{ .irq = 102 + OMAP44XX_IRQ_GIC_START },
};
static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
{
.pa_start = 0x4a0db000,
.pa_end = 0x4a0db03f,
.flags = ADDR_TYPE_RT
},
};
/* l4_cfg -> smartreflex_iva */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_smartreflex_iva_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_smartreflex_iva_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* smartreflex_iva slave ports */
static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
&omap44xx_l4_cfg__smartreflex_iva,
};
static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
.name = "smartreflex_iva",
.class = &omap44xx_smartreflex_hwmod_class,
.mpu_irqs = omap44xx_smartreflex_iva_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
.main_clk = "smartreflex_iva_fck",
.vdd_name = "iva",
.prcm = {
.omap4 = {
.clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
},
},
.slaves = omap44xx_smartreflex_iva_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* smartreflex_mpu */
static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
{ .irq = 18 + OMAP44XX_IRQ_GIC_START },
};
static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
{
.pa_start = 0x4a0d9000,
.pa_end = 0x4a0d903f,
.flags = ADDR_TYPE_RT
},
};
/* l4_cfg -> smartreflex_mpu */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_smartreflex_mpu_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_smartreflex_mpu_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* smartreflex_mpu slave ports */
static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
&omap44xx_l4_cfg__smartreflex_mpu,
};
static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
.name = "smartreflex_mpu",
.class = &omap44xx_smartreflex_hwmod_class,
.mpu_irqs = omap44xx_smartreflex_mpu_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
.main_clk = "smartreflex_mpu_fck",
.vdd_name = "mpu",
.prcm = {
.omap4 = {
.clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
},
},
.slaves = omap44xx_smartreflex_mpu_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static __initdata struct omap_hwmod *omap44xx_hwmods[] = { static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
/* dmm class */ /* dmm class */
&omap44xx_dmm_hwmod, &omap44xx_dmm_hwmod,
...@@ -2057,6 +2054,11 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { ...@@ -2057,6 +2054,11 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
/* mpu class */ /* mpu class */
&omap44xx_mpu_hwmod, &omap44xx_mpu_hwmod,
/* smartreflex class */
&omap44xx_smartreflex_core_hwmod,
&omap44xx_smartreflex_iva_hwmod,
&omap44xx_smartreflex_mpu_hwmod,
/* uart class */ /* uart class */
&omap44xx_uart1_hwmod, &omap44xx_uart1_hwmod,
&omap44xx_uart2_hwmod, &omap44xx_uart2_hwmod,
...@@ -2067,11 +2069,6 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { ...@@ -2067,11 +2069,6 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
&omap44xx_wd_timer2_hwmod, &omap44xx_wd_timer2_hwmod,
&omap44xx_wd_timer3_hwmod, &omap44xx_wd_timer3_hwmod,
/* smartreflex class */
&omap44xx_smartreflex_core_hwmod,
&omap44xx_smartreflex_iva_hwmod,
&omap44xx_smartreflex_mpu_hwmod,
NULL, NULL,
}; };
......
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