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Commit 20906ece authored by Scott Wood's avatar Scott Wood Committed by Kumar Gala
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[POWERPC] 8xx: mpc885ads cleanup 

It now uses the new CPM binding and the generic pin/clock functions, and
has assorted fixes and cleanup.
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 96fca1de
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Showing with 420 additions and 561 deletions
arch/powerpc/boot/dts/mpc885ads.dts
View file @ 20906ece
......@@ -2,6 +2,7 @@
* MPC885 ADS Device Tree Source
*
* Copyright 2006 MontaVista Software, Inc.
* Copyright 2007 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -12,7 +13,7 @@
/ {
model = "MPC885ADS";
compatible = "mpc8xx";
compatible = "fsl,mpc885ads";
#address-cells = <1>;
#size-cells = <1>;
......@@ -23,156 +24,188 @@ cpus {
PowerPC,885@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <20>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes
d-cache-size = <2000>; // L1, 8K
i-cache-size = <2000>; // L1, 8K
d-cache-line-size = <d#16>;
i-cache-line-size = <d#16>;
d-cache-size = <d#8192>;
i-cache-size = <d#8192>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
interrupts = <f 2>; // decrementer interrupt
interrupt-parent = <&Mpc8xx_pic>;
interrupt-parent = <&PIC>;
};
};
memory {
device_type = "memory";
reg = <00000000 800000>;
reg = <0 0>;
};
soc885@ff000000 {
localbus@ff000100 {
compatible = "fsl,mpc885-localbus", "fsl,pq1-localbus";
#address-cells = <2>;
#size-cells = <1>;
reg = <ff000100 40>;
ranges = <
0 0 fe000000 00800000
1 0 ff080000 00008000
5 0 ff0a0000 00008000
>;
flash@0,0 {
compatible = "jedec-flash";
reg = <0 0 800000>;
bank-width = <4>;
device-width = <1>;
};
board-control@1,0 {
reg = <1 0 20 5 300 4>;
compatible = "fsl,mpc885ads-bcsr";
};
};
soc@ff000000 {
compatible = "fsl,mpc885", "fsl,pq1-soc";
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <0 ff000000 00100000>;
reg = <ff000000 00000200>;
ranges = <0 ff000000 00004000>;
bus-frequency = <0>;
mdio@e80 {
device_type = "mdio";
compatible = "fs_enet";
reg = <e80 8>;
// Temporary -- will go away once kernel uses ranges for get_immrbase().
reg = <ff000000 4000>;
mdio@e00 {
compatible = "fsl,mpc885-fec-mdio", "fsl,pq1-fec-mdio";
reg = <e00 188>;
#address-cells = <1>;
#size-cells = <0>;
Phy0: ethernet-phy@0 {
PHY0: ethernet-phy@0 {
reg = <0>;
device_type = "ethernet-phy";
};
Phy1: ethernet-phy@1 {
PHY1: ethernet-phy@1 {
reg = <1>;
device_type = "ethernet-phy";
};
Phy2: ethernet-phy@2 {
PHY2: ethernet-phy@2 {
reg = <2>;
device_type = "ethernet-phy";
};
};
fec@e00 {
ethernet@e00 {
device_type = "network";
compatible = "fs_enet";
model = "FEC";
device-id = <1>;
compatible = "fsl,mpc885-fec-enet",
"fsl,pq1-fec-enet";
reg = <e00 188>;
mac-address = [ 00 00 0C 00 01 FD ];
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <3 1>;
interrupt-parent = <&Mpc8xx_pic>;
phy-handle = <&Phy1>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY0>;
linux,network-index = <0>;
};
fec@1e00 {
ethernet@1e00 {
device_type = "network";
compatible = "fs_enet";
model = "FEC";
device-id = <2>;
compatible = "fsl,mpc885-fec-enet",
"fsl,pq1-fec-enet";
reg = <1e00 188>;
mac-address = [ 00 00 0C 00 02 FD ];
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <7 1>;
interrupt-parent = <&Mpc8xx_pic>;
phy-handle = <&Phy2>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY1>;
linux,network-index = <1>;
};
Mpc8xx_pic: pic@ff000000 {
PIC: interrupt-controller@0 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0 24>;
device_type = "mpc8xx-pic";
compatible = "CPM";
compatible = "fsl,mpc885-pic", "fsl,pq1-pic";
};
pcmcia@0080 {
pcmcia@80 {
#address-cells = <3>;
#interrupt-cells = <1>;
#size-cells = <2>;
compatible = "fsl,pq-pcmcia";
device_type = "pcmcia";
reg = <80 80>;
interrupt-parent = <&Mpc8xx_pic>;
interrupt-parent = <&PIC>;
interrupts = <d 1>;
};
cpm@ff000000 {
cpm@9c0 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "cpm";
model = "CPM";
ranges = <0 0 4000>;
reg = <860 f0>;
compatible = "fsl,mpc885-cpm", "fsl,cpm1";
command-proc = <9c0>;
brg-frequency = <0>;
interrupts = <0 2>; // cpm error interrupt
interrupt-parent = <&Cpm_pic>;
interrupts = <0>; // cpm error interrupt
interrupt-parent = <&CPM_PIC>;
reg = <9c0 40 2000 1c00>;
ranges;
Cpm_pic: pic@930 {
brg@9f0 {
compatible = "fsl,mpc885-brg",
"fsl,cpm1-brg",
"fsl,cpm-brg";
reg = <9f0 10>;
};
CPM_PIC: interrupt-controller@930 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
#interrupt-cells = <1>;
interrupts = <5 2 0 2>;
interrupt-parent = <&Mpc8xx_pic>;
interrupt-parent = <&PIC>;
reg = <930 20>;
device_type = "cpm-pic";
compatible = "CPM";
compatible = "fsl,mpc885-cpm-pic",
"fsl,cpm1-pic";
};
smc@a80 {
serial@a80 {
device_type = "serial";
compatible = "cpm_uart";
model = "SMC";
device-id = <1>;
compatible = "fsl,mpc885-smc-uart",
"fsl,cpm1-smc-uart";
reg = <a80 10 3e80 40>;
clock-setup = <00ffffff 0>;
rx-clock = <1>;
tx-clock = <1>;
current-speed = <0>;
interrupts = <4 3>;
interrupt-parent = <&Cpm_pic>;
interrupts = <4>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <1>;
fsl,cpm-command = <0090>;
};
smc@a90 {
serial@a90 {
device_type = "serial";
compatible = "cpm_uart";
model = "SMC";
device-id = <2>;
reg = <a90 20 3f80 40>;
clock-setup = <ff00ffff 90000>;
rx-clock = <2>;
tx-clock = <2>;
current-speed = <0>;
interrupts = <3 3>;
interrupt-parent = <&Cpm_pic>;
compatible = "fsl,mpc885-smc-uart",
"fsl,cpm1-smc-uart";
reg = <a90 10 3f80 40>;
interrupts = <3>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <2>;
fsl,cpm-command = <00d0>;
};
scc@a40 {
ethernet@a40 {
device_type = "network";
compatible = "fs_enet";
model = "SCC";
device-id = <3>;
reg = <a40 18 3e00 80>;
mac-address = [ 00 00 0C 00 03 FD ];
interrupts = <1c 3>;
interrupt-parent = <&Cpm_pic>;
phy-handle = <&Phy2>;
compatible = "fsl,mpc885-scc-enet",
"fsl,cpm1-scc-enet";
reg = <a40 18 3e00 100>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <1c>;
interrupt-parent = <&CPM_PIC>;
phy-handle = <&PHY2>;
fsl,cpm-command = <0080>;
linux,network-index = <2>;
};
};
};
chosen {
linux,stdout-path = "/soc/cpm/serial@a80";
};
};
arch/powerpc/configs/mpc885_ads_defconfig
View file @ 20906ece
This diff is collapsed.
arch/powerpc/platforms/8xx/Kconfig
View file @ 20906ece
......@@ -26,6 +26,7 @@ config MPC86XADS
config MPC885ADS
bool "MPC885ADS"
select CPM1
select PPC_CPM_NEW_BINDING
help
Freescale Semiconductor MPC885 Application Development System (ADS).
Also known as DUET.
......
arch/powerpc/platforms/8xx/mpc885ads.h
View file @ 20906ece
......@@ -17,25 +17,10 @@
#include <sysdev/fsl_soc.h>
/* U-Boot maps BCSR to 0xff080000 */
#define BCSR_ADDR ((uint)0xff080000)
#define BCSR_SIZE ((uint)32)
#define BCSR0 ((uint)(BCSR_ADDR + 0x00))
#define BCSR1 ((uint)(BCSR_ADDR + 0x04))
#define BCSR2 ((uint)(BCSR_ADDR + 0x08))
#define BCSR3 ((uint)(BCSR_ADDR + 0x0c))
#define BCSR4 ((uint)(BCSR_ADDR + 0x10))
#define CFG_PHYDEV_ADDR ((uint)0xff0a0000)
#define BCSR5 ((uint)(CFG_PHYDEV_ADDR + 0x300))
#define MPC8xx_CPM_OFFSET (0x9c0)
#define CPM_MAP_ADDR (get_immrbase() + MPC8xx_CPM_OFFSET)
#define CPM_IRQ_OFFSET 16 // for compability with cpm_uart driver
#define PCMCIA_MEM_ADDR ((uint)0xff020000)
#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
/* Bits of interest in the BCSRs.
*/
#define BCSR1_ETHEN ((uint)0x20000000)
......@@ -64,28 +49,5 @@
#define BCSR5_MII1_EN 0x02
#define BCSR5_MII1_RST 0x01
/* Interrupt level assignments */
#define PHY_INTERRUPT SIU_IRQ7 /* PHY link change interrupt */
#define SIU_INT_FEC1 SIU_LEVEL1 /* FEC1 interrupt */
#define SIU_INT_FEC2 SIU_LEVEL3 /* FEC2 interrupt */
#define FEC_INTERRUPT SIU_INT_FEC1 /* FEC interrupt */
/* We don't use the 8259 */
#define NR_8259_INTS 0
/* CPM Ethernet through SCC3 */
#define PA_ENET_RXD ((ushort)0x0040)
#define PA_ENET_TXD ((ushort)0x0080)
#define PE_ENET_TCLK ((uint)0x00004000)
#define PE_ENET_RCLK ((uint)0x00008000)
#define PE_ENET_TENA ((uint)0x00000010)
#define PC_ENET_CLSN ((ushort)0x0400)
#define PC_ENET_RENA ((ushort)0x0800)
/* Control bits in the SICR to route TCLK (CLK5) and RCLK (CLK6) to
* SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero */
#define SICR_ENET_MASK ((uint)0x00ff0000)
#define SICR_ENET_CLKRT ((uint)0x002c0000)
#endif /* __ASM_MPC885ADS_H__ */
#endif /* __KERNEL__ */
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