Commit 20dbc43d authored by Kukjin Kim's avatar Kukjin Kim

ARM: S5PC100: 2nd Change to using s3c_gpio_cfgrange_nopull()

This patch changes code setting special-function and no pull-up
to use the s3c_gpio_cfgrange_nopull() wrapper.
NOTE: This is for missed things from the previous patch.
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 3e9b7261
...@@ -24,7 +24,7 @@ ...@@ -24,7 +24,7 @@
static void s5pc100_fb_setgpios(unsigned int base, unsigned int nr) static void s5pc100_fb_setgpios(unsigned int base, unsigned int nr)
{ {
s3c_gpio_cfgall_range(base, nr, S3C_GPIO_SFN(2), S3C_GPIO_PULL_NONE); s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(2));
} }
void s5pc100_fb_gpio_setup_24bpp(void) void s5pc100_fb_gpio_setup_24bpp(void)
......
...@@ -19,7 +19,7 @@ ...@@ -19,7 +19,7 @@
static void s5pc100_ide_cfg_gpios(unsigned int base, unsigned int nr) static void s5pc100_ide_cfg_gpios(unsigned int base, unsigned int nr)
{ {
s3c_gpio_cfgall_range(base, nr, S3C_GPIO_SFN(4), S3C_GPIO_PULL_NONE); s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(4));
for (; nr > 0; nr--, base++) for (; nr > 0; nr--, base++)
s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4); s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4);
...@@ -49,8 +49,7 @@ void s5pc100_ide_setup_gpio(void) ...@@ -49,8 +49,7 @@ void s5pc100_ide_setup_gpio(void)
s3c_gpio_cfgpin_range(S5PC100_GPK0(6), 2, S3C_GPIO_SFN(0)); s3c_gpio_cfgpin_range(S5PC100_GPK0(6), 2, S3C_GPIO_SFN(0));
/* CF_OE, CF_WE */ /* CF_OE, CF_WE */
s3c_gpio_cfgall_range(S5PC100_GPK1(6), 8, s3c_gpio_cfgrange_nopull(S5PC100_GPK1(6), 8, S3C_GPIO_SFN(2));
S3C_GPIO_SFN(2), S3C_GPIO_PULL_NONE);
/* CF_CD */ /* CF_CD */
s3c_gpio_cfgpin(S5PC100_GPK3(5), S3C_GPIO_SFN(2)); s3c_gpio_cfgpin(S5PC100_GPK3(5), S3C_GPIO_SFN(2));
......
...@@ -16,10 +16,8 @@ ...@@ -16,10 +16,8 @@
void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols) void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
{ {
/* Set all the necessary GPH3 pins to special-function 3: KP_ROW[x] */ /* Set all the necessary GPH3 pins to special-function 3: KP_ROW[x] */
s3c_gpio_cfgall_range(S5PC100_GPH3(0), rows, s3c_gpio_cfgrange_nopull(S5PC100_GPH3(0), rows, S3C_GPIO_SFN(3));
S3C_GPIO_SFN(3), S3C_GPIO_PULL_NONE);
/* Set all the necessary GPH2 pins to special-function 3: KP_COL[x] */ /* Set all the necessary GPH2 pins to special-function 3: KP_COL[x] */
s3c_gpio_cfgall_range(S5PC100_GPH2(0), cols, s3c_gpio_cfgrange_nopull(S5PC100_GPH2(0), cols, S3C_GPIO_SFN(3));
S3C_GPIO_SFN(3), S3C_GPIO_PULL_NONE);
} }
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment