Commit 220cad3c authored by Eric Anholt's avatar Eric Anholt Committed by Chris Wilson

drm/i915: Always set the DP transcoder config to 8BPC.

The pipe is always set to 8BPC, but here we were leaving whatever
previous bits were set by the BIOS in place.
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
Tested-by: default avatarKeith Packard <keithp@keithp.com>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: stable@kernel.org
parent 94c35de9
...@@ -3033,6 +3033,7 @@ ...@@ -3033,6 +3033,7 @@
#define TRANS_DP_10BPC (1<<9) #define TRANS_DP_10BPC (1<<9)
#define TRANS_DP_6BPC (2<<9) #define TRANS_DP_6BPC (2<<9)
#define TRANS_DP_12BPC (3<<9) #define TRANS_DP_12BPC (3<<9)
#define TRANS_DP_BPC_MASK (3<<9)
#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
#define TRANS_DP_VSYNC_ACTIVE_LOW 0 #define TRANS_DP_VSYNC_ACTIVE_LOW 0
#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
......
...@@ -2120,9 +2120,11 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) ...@@ -2120,9 +2120,11 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
reg = TRANS_DP_CTL(pipe); reg = TRANS_DP_CTL(pipe);
temp = I915_READ(reg); temp = I915_READ(reg);
temp &= ~(TRANS_DP_PORT_SEL_MASK | temp &= ~(TRANS_DP_PORT_SEL_MASK |
TRANS_DP_SYNC_MASK); TRANS_DP_SYNC_MASK |
TRANS_DP_BPC_MASK);
temp |= (TRANS_DP_OUTPUT_ENABLE | temp |= (TRANS_DP_OUTPUT_ENABLE |
TRANS_DP_ENH_FRAMING); TRANS_DP_ENH_FRAMING);
temp |= TRANS_DP_8BPC;
if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
......
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