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Commit 2395133b authored by Ralf Bächle's avatar Ralf Bächle Committed by Linus Torvalds
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[PATCH] SGI IP22 bits 

An update for the Indy aka IP22 support.  Consolidates the 32-bit and
64-bit copies of the support code into one directory, so in total this
patch deletes quite a bit of code.
parent f19e2d9e
Hide whitespace changes
Inline Side-by-side
Showing with 4672 additions and 5694 deletions
arch/mips/defconfig
View file @ 2395133b
......@@ -2,97 +2,132 @@
# Automatically generated make config: don't edit
#
CONFIG_MIPS=y
# CONFIG_SMP is not set
CONFIG_MIPS32=y
# CONFIG_MIPS64 is not set
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
#
# General setup
#
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_EMBEDDED is not set
CONFIG_FUTEX=y
CONFIG_EPOLL=y
#
# Loadable module support
#
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
CONFIG_OBSOLETE_MODPARM=y
CONFIG_MODVERSIONS=y
CONFIG_KMOD=y
#
# Machine selection
#
# CONFIG_ACER_PICA_61 is not set
# CONFIG_ALGOR_P4032 is not set
# CONFIG_BAGET_MIPS is not set
# CONFIG_CASIO_E55 is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_DECSTATION is not set
# CONFIG_DDB5074 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_LASAT is not set
# CONFIG_HP_LASERJET is not set
# CONFIG_IBM_WORKPAD is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MIPS_ATLAS is not set
# CONFIG_MIPS_MALTA is not set
# CONFIG_NINO is not set
# CONFIG_MIPS_MAGNUM_4000 is not set
# CONFIG_MIPS_MALTA is not set
# CONFIG_MIPS_SEAD is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_DDB5074 is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_NEC_OSPREY is not set
# CONFIG_NEC_EAGLE is not set
# CONFIG_OLIVETTI_M700 is not set
CONFIG_SGI_IP22=y
# CONFIG_SGI_IP32 is not set
# CONFIG_SOC_AU1X00 is not set
# CONFIG_SIBYTE_SB1xxx_SOC is not set
# CONFIG_SNI_RM200_PCI is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_PB1000 is not set
# CONFIG_TANBAC_TB0226 is not set
# CONFIG_TANBAC_TB0229 is not set
# CONFIG_TOSHIBA_JMR3927 is not set
# CONFIG_TOSHIBA_RBTX4927 is not set
# CONFIG_VICTOR_MPC30X is not set
# CONFIG_ZAO_CAPCELLA is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
# CONFIG_MCA is not set
# CONFIG_SBUS is not set
CONFIG_ARC=y
CONFIG_GENERIC_ISA_DMA=y
CONFIG_NONCOHERENT_IO=y
# CONFIG_CPU_LITTLE_ENDIAN is not set
CONFIG_IRQ_CPU=y
CONFIG_SWAP_IO_SPACE=y
CONFIG_BOOT_ELF32=y
CONFIG_L1_CACHE_SHIFT=5
CONFIG_ARC32=y
# CONFIG_FB is not set
CONFIG_ARC_CONSOLE=y
CONFIG_ARC_PROMLIB=y
CONFIG_BOARD_SCACHE=y
CONFIG_PC_KEYB=y
CONFIG_SGI=y
CONFIG_NEW_IRQ=y
CONFIG_OLD_TIME_C=y
# CONFIG_ISA is not set
# CONFIG_EISA is not set
# CONFIG_PCI is not set
# CONFIG_I8259 is not set
#
# Loadable module support
#
CONFIG_MODULES=y
# CONFIG_MODVERSIONS is not set
CONFIG_KMOD=y
#
# CPU selection
#
# CONFIG_CPU_MIPS32 is not set
# CONFIG_CPU_MIPS64 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_VR41XX is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_TX49XX is not set
CONFIG_CPU_R5000=y
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_SB1 is not set
# CONFIG_CPU_MIPS32 is not set
# CONFIG_CPU_MIPS64 is not set
# CONFIG_64BIT_PHYS_ADDR is not set
# CONFIG_CPU_ADVANCED is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_LLDSCD=y
# CONFIG_CPU_HAS_WB is not set
CONFIG_CPU_HAS_SYNC=y
# CONFIG_PREEMPT is not set
CONFIG_KALLSYMS=y
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
#
# General setup
# Bus options (PCI, PCMCIA, EISA, ISA, TC)
#
# CONFIG_ISA is not set
CONFIG_MMU=y
# CONFIG_HOTPLUG is not set
#
# Executable file formats
#
# CONFIG_CPU_LITTLE_ENDIAN is not set
CONFIG_KCORE_ELF=y
CONFIG_ELF_KERNEL=y
CONFIG_BINFMT_IRIX=y
CONFIG_FORWARD_KEYBOARD=y
# CONFIG_ARC_CONSOLE is not set
# CONFIG_BINFMT_AOUT is not set
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_NET=y
# CONFIG_HOTPLUG is not set
# CONFIG_PCMCIA is not set
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
CONFIG_BINFMT_IRIX=y
#
# Memory Technology Devices (MTD)
......@@ -104,42 +139,91 @@ CONFIG_SYSCTL=y
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
# CONFIG_PNP is not set
#
# Generic Driver Options
#
# CONFIG_FW_LOADER is not set
#
# Block devices
#
# CONFIG_BLK_DEV_FD is not set
# CONFIG_BLK_DEV_XD is not set
# CONFIG_PARIDE is not set
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_BLK_DEV_INITRD is not set
#
# ATA/ATAPI/MFM/RLL support
#
# CONFIG_IDE is not set
#
# SCSI device support
#
CONFIG_SCSI=y
#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_ST=y
# CONFIG_CHR_DEV_OSST is not set
CONFIG_BLK_DEV_SR=y
# CONFIG_BLK_DEV_SR_VENDOR is not set
# CONFIG_CHR_DEV_SG is not set
#
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
#
# CONFIG_SCSI_MULTI_LUN is not set
# CONFIG_SCSI_REPORT_LUNS is not set
CONFIG_SCSI_CONSTANTS=y
# CONFIG_SCSI_LOGGING is not set
#
# SCSI low-level drivers
#
CONFIG_SGIWD93_SCSI=y
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC7XXX_OLD is not set
# CONFIG_SCSI_DPT_I2O is not set
# CONFIG_SCSI_EATA_PIO is not set
# CONFIG_SCSI_DEBUG is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
# CONFIG_BLK_DEV_MD is not set
# CONFIG_MD_LINEAR is not set
# CONFIG_MD_RAID0 is not set
# CONFIG_MD_RAID1 is not set
# CONFIG_MD_RAID5 is not set
# CONFIG_BLK_DEV_LVM is not set
#
# Fusion MPT device support
#
# CONFIG_FUSION is not set
#
# I2O device support
#
#
# Networking support
#
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_MMAP=y
CONFIG_NETLINK=y
CONFIG_RTNETLINK=y
CONFIG_NETLINK_DEV=y
# CONFIG_NETFILTER is not set
# CONFIG_FILTER is not set
CONFIG_UNIX=y
CONFIG_NET_KEY=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
# CONFIG_IP_ADVANCED_ROUTER is not set
......@@ -153,20 +237,24 @@ CONFIG_IP_PNP_BOOTP=y
# CONFIG_ARPD is not set
# CONFIG_INET_ECN is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_IPV6 is not set
# CONFIG_KHTTPD is not set
# CONFIG_ATM is not set
# CONFIG_XFRM_USER is not set
#
#
# SCTP Configuration (EXPERIMENTAL)
#
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
CONFIG_IPV6_SCTP__=y
# CONFIG_IP_SCTP is not set
# CONFIG_ATM is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_LLC is not set
# CONFIG_DECNET is not set
# CONFIG_BRIDGE is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_LLC is not set
# CONFIG_NET_DIVERT is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
......@@ -179,87 +267,10 @@ CONFIG_IP_PNP_BOOTP=y
# CONFIG_NET_SCHED is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
# CONFIG_PHONE_IXJ is not set
# CONFIG_PHONE_IXJ_PCMCIA is not set
#
# SCSI support
#
CONFIG_SCSI=y
#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
CONFIG_SD_EXTRA_DEVS=40
CONFIG_CHR_DEV_ST=y
# CONFIG_CHR_DEV_OSST is not set
CONFIG_BLK_DEV_SR=y
# CONFIG_BLK_DEV_SR_VENDOR is not set
CONFIG_SR_EXTRA_DEVS=2
# CONFIG_CHR_DEV_SG is not set
#
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
#
# CONFIG_SCSI_DEBUG_QUEUES is not set
# CONFIG_SCSI_MULTI_LUN is not set
CONFIG_SCSI_CONSTANTS=y
# CONFIG_SCSI_LOGGING is not set
#
# SCSI low-level drivers
#
CONFIG_SGIWD93_SCSI=y
# CONFIG_SCSI_7000FASST is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AHA152X is not set
# CONFIG_SCSI_AHA1542 is not set
# CONFIG_SCSI_AHA1740 is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC7XXX_OLD is not set
# CONFIG_SCSI_DPT_I2O is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_IN2000 is not set
# CONFIG_SCSI_AM53C974 is not set
# CONFIG_SCSI_MEGARAID is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_DTC3280 is not set
# CONFIG_SCSI_EATA is not set
# CONFIG_SCSI_EATA_DMA is not set
# CONFIG_SCSI_EATA_PIO is not set
# CONFIG_SCSI_FUTURE_DOMAIN is not set
# CONFIG_SCSI_GDTH is not set
# CONFIG_SCSI_GENERIC_NCR5380 is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_NCR53C406A is not set
# CONFIG_SCSI_NCR_D700 is not set
# CONFIG_SCSI_NCR53C7xx is not set
# CONFIG_SCSI_PAS16 is not set
# CONFIG_SCSI_PCI2000 is not set
# CONFIG_SCSI_PCI2220I is not set
# CONFIG_SCSI_PSI240I is not set
# CONFIG_SCSI_QLOGIC_FAS is not set
# CONFIG_SCSI_SIM710 is not set
# CONFIG_SCSI_SYM53C416 is not set
# CONFIG_SCSI_T128 is not set
# CONFIG_SCSI_U14_34F is not set
# CONFIG_SCSI_DEBUG is not set
#
# Network device support
# Network testing
#
# CONFIG_NET_PKTGEN is not set
CONFIG_NETDEVICES=y
#
# ARCnet devices
#
# CONFIG_ARCNET is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
......@@ -270,33 +281,16 @@ CONFIG_NETDEVICES=y
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
# CONFIG_SUNLANCE is not set
# CONFIG_SUNBMAC is not set
# CONFIG_SUNQE is not set
# CONFIG_SUNLANCE is not set
# CONFIG_SUNGEM is not set
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_LANCE is not set
# CONFIG_NET_VENDOR_SMC is not set
# CONFIG_NET_VENDOR_RACAL is not set
# CONFIG_NET_ISA is not set
# CONFIG_NET_PCI is not set
# CONFIG_NET_POCKET is not set
# CONFIG_MII is not set
CONFIG_SGISEEQ=y
#
# Ethernet (1000 Mbit)
#
# CONFIG_ACENIC is not set
# CONFIG_DL2K is not set
# CONFIG_MYRI_SBUS is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_SK98LIN is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_PLIP is not set
#
# Ethernet (10000 Mbit)
#
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
......@@ -306,11 +300,8 @@ CONFIG_SGISEEQ=y
# CONFIG_NET_RADIO is not set
#
# Token Ring devices
# Token Ring devices (depends on LLC=y)
#
# CONFIG_TR is not set
# CONFIG_NET_FC is not set
# CONFIG_RCPCI is not set
# CONFIG_SHAPER is not set
#
......@@ -331,21 +322,69 @@ CONFIG_SGISEEQ=y
#
# ISDN subsystem
#
# CONFIG_ISDN is not set
# CONFIG_ISDN_BOOL is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
#
# Old CD-ROM drivers (not SCSI, not IDE)
# Input device support
#
# CONFIG_CD_NO_IDESCSI is not set
CONFIG_INPUT=y
#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input I/O drivers
#
# CONFIG_GAMEPORT is not set
CONFIG_SOUND_GAMEPORT=y
CONFIG_SERIO=y
CONFIG_SERIO_I8042=y
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_CT82C710 is not set
#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Character devices
#
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
# CONFIG_SERIAL is not set
# CONFIG_SERIAL_EXTENDED is not set
CONFIG_HW_CONSOLE=y
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_IP22_ZILOG=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_UNIX98_PTY_COUNT=256
......@@ -355,36 +394,58 @@ CONFIG_UNIX98_PTY_COUNT=256
# CONFIG_I2C is not set
#
# Mice
# I2C Hardware Sensors Mainboard support
#
# CONFIG_BUSMOUSE is not set
# CONFIG_MOUSE is not set
#
# Joysticks
# I2C Hardware Sensors Chip support
#
# CONFIG_INPUT_GAMEPORT is not set
# CONFIG_I2C_SENSOR is not set
#
# Input core support is needed for gameports
# Mice
#
# CONFIG_BUSMOUSE is not set
# CONFIG_QIC02_TAPE is not set
#
# Input core support is needed for joysticks
# IPMI
#
# CONFIG_QIC02_TAPE is not set
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_INTEL_RNG is not set
CONFIG_WATCHDOG=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
# CONFIG_SOFT_WATCHDOG is not set
# CONFIG_WDT is not set
# CONFIG_WDTPCI is not set
# CONFIG_PCWATCHDOG is not set
# CONFIG_ACQUIRE_WDT is not set
# CONFIG_ADVANTECH_WDT is not set
# CONFIG_EUROTECH_WDT is not set
# CONFIG_IB700_WDT is not set
# CONFIG_I810_TCO is not set
# CONFIG_MIXCOMWD is not set
# CONFIG_SCx200_WDT is not set
# CONFIG_60XX_WDT is not set
# CONFIG_W83877F_WDT is not set
# CONFIG_MACHZ_WDT is not set
CONFIG_INDYDOG=y
# CONFIG_SC520_WDT is not set
# CONFIG_AMD7XX_TCO is not set
# CONFIG_ALIM7101_WDT is not set
# CONFIG_SC1200_WDT is not set
# CONFIG_WAFER_WDT is not set
# CONFIG_CPU5_WDT is not set
# CONFIG_NVRAM is not set
# CONFIG_RTC is not set
# CONFIG_GEN_RTC is not set
CONFIG_SGI_DS1286=y
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
# CONFIG_SONYPI is not set
#
# Ftape, the floppy tape device driver
......@@ -392,6 +453,8 @@ CONFIG_UNIX98_PTY_COUNT=256
# CONFIG_FTAPE is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_HANGCHECK_TIMER is not set
#
# Multimedia devices
......@@ -399,89 +462,92 @@ CONFIG_UNIX98_PTY_COUNT=256
# CONFIG_VIDEO_DEV is not set
#
# SGI Character devices
# Digital Video Broadcasting Devices
#
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_SGI_NEWPORT_CONSOLE=y
CONFIG_FONT_8x16=y
# CONFIG_PSMOUSE is not set
CONFIG_UNIX98_PTYS=y
CONFIG_UNIX98_PTY_COUNT=256
# CONFIG_DVB is not set
#
# File systems
#
# CONFIG_EXT2_FS is not set
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_XATTR=y
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
CONFIG_JBD=y
# CONFIG_JBD_DEBUG is not set
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
CONFIG_FS_POSIX_ACL=y
# CONFIG_XFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_QUOTA is not set
CONFIG_AUTOFS_FS=y
CONFIG_AUTOFS4_FS=y
# CONFIG_REISERFS_FS is not set
# CONFIG_REISERFS_CHECK is not set
# CONFIG_REISERFS_PROC_INFO is not set
#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=y
# CONFIG_JOLIET is not set
# CONFIG_ZISOFS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_FAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_DEVFS_FS is not set
CONFIG_DEVPTS_FS=y
CONFIG_DEVPTS_FS_XATTR=y
CONFIG_DEVPTS_FS_SECURITY=y
# CONFIG_TMPFS is not set
CONFIG_RAMFS=y
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_ADFS_FS_RW is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_CMS_FS is not set
# CONFIG_EXT3_FS is not set
# CONFIG_JBD is not set
# CONFIG_JBD_DEBUG is not set
# CONFIG_FAT_FS is not set
# CONFIG_MSDOS_FS is not set
# CONFIG_UMSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS_FS is not set
# CONFIG_JFFS2_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_TMPFS is not set
# CONFIG_RAMFS is not set
CONFIG_ISO9660_FS=y
# CONFIG_JOLIET is not set
# CONFIG_MINIX_FS is not set
# CONFIG_FREEVXFS_FS is not set
# CONFIG_NTFS_FS is not set
# CONFIG_NTFS_DEBUG is not set
# CONFIG_NTFS_RW is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
CONFIG_PROC_FS=y
# CONFIG_DEVFS_FS is not set
# CONFIG_DEVFS_MOUNT is not set
# CONFIG_DEVFS_DEBUG is not set
CONFIG_DEVPTS_FS=y
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX4FS_RW is not set
# CONFIG_ROMFS_FS is not set
CONFIG_EXT2_FS=y
# CONFIG_SYSV_FS is not set
# CONFIG_UDF_FS is not set
# CONFIG_UDF_RW is not set
# CONFIG_UFS_FS is not set
# CONFIG_UFS_FS_WRITE is not set
#
# Network File Systems
#
# CONFIG_CODA_FS is not set
# CONFIG_INTERMEZZO_FS is not set
CONFIG_NFS_FS=y
# CONFIG_NFS_V3 is not set
CONFIG_ROOT_NFS=y
# CONFIG_NFS_V4 is not set
CONFIG_NFSD=y
# CONFIG_NFSD_V3 is not set
CONFIG_SUNRPC=y
# CONFIG_NFSD_TCP is not set
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
CONFIG_EXPORTFS=y
CONFIG_SUNRPC=y
# CONFIG_SUNRPC_GSS is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_NCPFS_PACKET_SIGNING is not set
# CONFIG_NCPFS_IOCTL_LOCKING is not set
# CONFIG_NCPFS_STRONG is not set
# CONFIG_NCPFS_NFS_NS is not set
# CONFIG_NCPFS_OS2_NS is not set
# CONFIG_NCPFS_SMALLDOS is not set
# CONFIG_NCPFS_NLS is not set
# CONFIG_NCPFS_EXTRAS is not set
# CONFIG_CODA_FS is not set
# CONFIG_INTERMEZZO_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
......@@ -498,147 +564,82 @@ CONFIG_MSDOS_PARTITION=y
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set
# CONFIG_NEC98_PARTITION is not set
CONFIG_SGI_PARTITION=y
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_SMB_NLS is not set
# CONFIG_NLS is not set
# CONFIG_EFI_PARTITION is not set
#
# Graphics support
#
#
# Console drivers
# Console display driver support
#
# CONFIG_VGA_CONSOLE is not set
# CONFIG_MDA_CONSOLE is not set
CONFIG_SGI_NEWPORT_CONSOLE=y
CONFIG_DUMMY_CONSOLE=y
CONFIG_FONT_8x16=y
#
# Frame-buffer support
# Logo configuration
#
# CONFIG_FB is not set
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_LOGO_LINUX_CLUT224 is not set
CONFIG_LOGO_SGI_CLUT224=y
#
# Sound
#
# CONFIG_SOUND is not set
#
# SGI devices
#
CONFIG_SGI_SERIAL=y
# CONFIG_SERIAL_CONSOLE is not set
CONFIG_SGI_DS1286=y
# CONFIG_SGI_NEWPORT_GFX is not set
#
# USB support
#
# CONFIG_USB is not set
#
# USB Controllers
#
# CONFIG_USB_UHCI is not set
# CONFIG_USB_UHCI_ALT is not set
# CONFIG_USB_OHCI is not set
#
# USB Device Class drivers
#
# CONFIG_USB_AUDIO is not set
# CONFIG_USB_BLUETOOTH is not set
# CONFIG_USB_STORAGE is not set
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set
# CONFIG_USB_STORAGE_DPCM is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set
#
# USB Human Interface Devices (HID)
#
#
# Input core support is needed for USB HID
#
#
# USB Imaging devices
#
# CONFIG_USB_DC2XX is not set
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_SCANNER is not set
# CONFIG_USB_MICROTEK is not set
# CONFIG_USB_HPUSBSCSI is not set
# CONFIG_USB_GADGET is not set
#
# USB Multimedia devices
# Bluetooth support
#
# CONFIG_BT is not set
#
# Video4Linux support is needed for USB Multimedia device support
#
# CONFIG_USB_DABUSB is not set
#
# USB Network adaptors
#
# CONFIG_USB_PLUSB is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_CATC is not set
# CONFIG_USB_CDCETHER is not set
# CONFIG_USB_USBNET is not set
#
# USB port drivers
#
# CONFIG_USB_USS720 is not set
#
# USB Serial Converter support
# Kernel hacking
#
# CONFIG_USB_SERIAL is not set
# CONFIG_USB_SERIAL_GENERIC is not set
# CONFIG_USB_SERIAL_BELKIN is not set
# CONFIG_USB_SERIAL_WHITEHEAT is not set
# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
# CONFIG_USB_SERIAL_EMPEG is not set
# CONFIG_USB_SERIAL_FTDI_SIO is not set
# CONFIG_USB_SERIAL_VISOR is not set
# CONFIG_USB_SERIAL_EDGEPORT is not set
# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
# CONFIG_USB_SERIAL_KEYSPAN is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
# CONFIG_USB_SERIAL_MCT_U232 is not set
# CONFIG_USB_SERIAL_PL2303 is not set
# CONFIG_USB_SERIAL_CYBERJACK is not set
# CONFIG_USB_SERIAL_OMNINET is not set
CONFIG_CROSSCOMPILE=y
# CONFIG_DEBUG_KERNEL is not set
#
# Miscellaneous USB drivers
# Security options
#
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_ID75 is not set
# CONFIG_SECURITY is not set
#
# Input core support
# Cryptographic options
#
# CONFIG_INPUT is not set
# CONFIG_INPUT_KEYBDEV is not set
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_EVDEV is not set
CONFIG_CRYPTO=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_BLOWFISH=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_SERPENT=y
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_DEFLATE=y
# CONFIG_CRYPTO_TEST is not set
#
# Kernel hacking
# Library routines
#
CONFIG_CROSSCOMPILE=y
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_MIPS_UNCACHED is not set
# CONFIG_CRC32 is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
arch/mips/defconfig-ip22
View file @ 2395133b
......@@ -2,97 +2,132 @@
# Automatically generated make config: don't edit
#
CONFIG_MIPS=y
# CONFIG_SMP is not set
CONFIG_MIPS32=y
# CONFIG_MIPS64 is not set
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
#
# General setup
#
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_EMBEDDED is not set
CONFIG_FUTEX=y
CONFIG_EPOLL=y
#
# Loadable module support
#
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
CONFIG_OBSOLETE_MODPARM=y
CONFIG_MODVERSIONS=y
CONFIG_KMOD=y
#
# Machine selection
#
# CONFIG_ACER_PICA_61 is not set
# CONFIG_ALGOR_P4032 is not set
# CONFIG_BAGET_MIPS is not set
# CONFIG_CASIO_E55 is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_DECSTATION is not set
# CONFIG_DDB5074 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_LASAT is not set
# CONFIG_HP_LASERJET is not set
# CONFIG_IBM_WORKPAD is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MIPS_ATLAS is not set
# CONFIG_MIPS_MALTA is not set
# CONFIG_NINO is not set
# CONFIG_MIPS_MAGNUM_4000 is not set
# CONFIG_MIPS_MALTA is not set
# CONFIG_MIPS_SEAD is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_DDB5074 is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_NEC_OSPREY is not set
# CONFIG_NEC_EAGLE is not set
# CONFIG_OLIVETTI_M700 is not set
CONFIG_SGI_IP22=y
# CONFIG_SGI_IP32 is not set
# CONFIG_SOC_AU1X00 is not set
# CONFIG_SIBYTE_SB1xxx_SOC is not set
# CONFIG_SNI_RM200_PCI is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_PB1000 is not set
# CONFIG_TANBAC_TB0226 is not set
# CONFIG_TANBAC_TB0229 is not set
# CONFIG_TOSHIBA_JMR3927 is not set
# CONFIG_TOSHIBA_RBTX4927 is not set
# CONFIG_VICTOR_MPC30X is not set
# CONFIG_ZAO_CAPCELLA is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
# CONFIG_MCA is not set
# CONFIG_SBUS is not set
CONFIG_ARC=y
CONFIG_GENERIC_ISA_DMA=y
CONFIG_NONCOHERENT_IO=y
# CONFIG_CPU_LITTLE_ENDIAN is not set
CONFIG_IRQ_CPU=y
CONFIG_SWAP_IO_SPACE=y
CONFIG_BOOT_ELF32=y
CONFIG_L1_CACHE_SHIFT=5
CONFIG_ARC32=y
# CONFIG_FB is not set
CONFIG_ARC_CONSOLE=y
CONFIG_ARC_PROMLIB=y
CONFIG_BOARD_SCACHE=y
CONFIG_PC_KEYB=y
CONFIG_SGI=y
CONFIG_NEW_IRQ=y
CONFIG_OLD_TIME_C=y
# CONFIG_ISA is not set
# CONFIG_EISA is not set
# CONFIG_PCI is not set
# CONFIG_I8259 is not set
#
# Loadable module support
#
CONFIG_MODULES=y
# CONFIG_MODVERSIONS is not set
CONFIG_KMOD=y
#
# CPU selection
#
# CONFIG_CPU_MIPS32 is not set
# CONFIG_CPU_MIPS64 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_VR41XX is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_TX49XX is not set
CONFIG_CPU_R5000=y
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_SB1 is not set
# CONFIG_CPU_MIPS32 is not set
# CONFIG_CPU_MIPS64 is not set
# CONFIG_64BIT_PHYS_ADDR is not set
# CONFIG_CPU_ADVANCED is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_LLDSCD=y
# CONFIG_CPU_HAS_WB is not set
CONFIG_CPU_HAS_SYNC=y
# CONFIG_PREEMPT is not set
CONFIG_KALLSYMS=y
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
#
# General setup
# Bus options (PCI, PCMCIA, EISA, ISA, TC)
#
# CONFIG_ISA is not set
CONFIG_MMU=y
# CONFIG_HOTPLUG is not set
#
# Executable file formats
#
# CONFIG_CPU_LITTLE_ENDIAN is not set
CONFIG_KCORE_ELF=y
CONFIG_ELF_KERNEL=y
CONFIG_BINFMT_IRIX=y
CONFIG_FORWARD_KEYBOARD=y
# CONFIG_ARC_CONSOLE is not set
# CONFIG_BINFMT_AOUT is not set
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_NET=y
# CONFIG_HOTPLUG is not set
# CONFIG_PCMCIA is not set
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
CONFIG_BINFMT_IRIX=y
#
# Memory Technology Devices (MTD)
......@@ -104,42 +139,91 @@ CONFIG_SYSCTL=y
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
# CONFIG_PNP is not set
#
# Generic Driver Options
#
# CONFIG_FW_LOADER is not set
#
# Block devices
#
# CONFIG_BLK_DEV_FD is not set
# CONFIG_BLK_DEV_XD is not set
# CONFIG_PARIDE is not set
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_BLK_DEV_INITRD is not set
#
# ATA/ATAPI/MFM/RLL support
#
# CONFIG_IDE is not set
#
# SCSI device support
#
CONFIG_SCSI=y
#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_ST=y
# CONFIG_CHR_DEV_OSST is not set
CONFIG_BLK_DEV_SR=y
# CONFIG_BLK_DEV_SR_VENDOR is not set
# CONFIG_CHR_DEV_SG is not set
#
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
#
# CONFIG_SCSI_MULTI_LUN is not set
# CONFIG_SCSI_REPORT_LUNS is not set
CONFIG_SCSI_CONSTANTS=y
# CONFIG_SCSI_LOGGING is not set
#
# SCSI low-level drivers
#
CONFIG_SGIWD93_SCSI=y
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC7XXX_OLD is not set
# CONFIG_SCSI_DPT_I2O is not set
# CONFIG_SCSI_EATA_PIO is not set
# CONFIG_SCSI_DEBUG is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
# CONFIG_BLK_DEV_MD is not set
# CONFIG_MD_LINEAR is not set
# CONFIG_MD_RAID0 is not set
# CONFIG_MD_RAID1 is not set
# CONFIG_MD_RAID5 is not set
# CONFIG_BLK_DEV_LVM is not set
#
# Fusion MPT device support
#
# CONFIG_FUSION is not set
#
# I2O device support
#
#
# Networking support
#
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_MMAP=y
CONFIG_NETLINK=y
CONFIG_RTNETLINK=y
CONFIG_NETLINK_DEV=y
# CONFIG_NETFILTER is not set
# CONFIG_FILTER is not set
CONFIG_UNIX=y
CONFIG_NET_KEY=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
# CONFIG_IP_ADVANCED_ROUTER is not set
......@@ -153,20 +237,24 @@ CONFIG_IP_PNP_BOOTP=y
# CONFIG_ARPD is not set
# CONFIG_INET_ECN is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_IPV6 is not set
# CONFIG_KHTTPD is not set
# CONFIG_ATM is not set
# CONFIG_XFRM_USER is not set
#
#
# SCTP Configuration (EXPERIMENTAL)
#
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
CONFIG_IPV6_SCTP__=y
# CONFIG_IP_SCTP is not set
# CONFIG_ATM is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_LLC is not set
# CONFIG_DECNET is not set
# CONFIG_BRIDGE is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_LLC is not set
# CONFIG_NET_DIVERT is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
......@@ -179,87 +267,10 @@ CONFIG_IP_PNP_BOOTP=y
# CONFIG_NET_SCHED is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
# CONFIG_PHONE_IXJ is not set
# CONFIG_PHONE_IXJ_PCMCIA is not set
#
# SCSI support
#
CONFIG_SCSI=y
#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
CONFIG_SD_EXTRA_DEVS=40
CONFIG_CHR_DEV_ST=y
# CONFIG_CHR_DEV_OSST is not set
CONFIG_BLK_DEV_SR=y
# CONFIG_BLK_DEV_SR_VENDOR is not set
CONFIG_SR_EXTRA_DEVS=2
# CONFIG_CHR_DEV_SG is not set
#
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
#
# CONFIG_SCSI_DEBUG_QUEUES is not set
# CONFIG_SCSI_MULTI_LUN is not set
CONFIG_SCSI_CONSTANTS=y
# CONFIG_SCSI_LOGGING is not set
#
# SCSI low-level drivers
#
CONFIG_SGIWD93_SCSI=y
# CONFIG_SCSI_7000FASST is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AHA152X is not set
# CONFIG_SCSI_AHA1542 is not set
# CONFIG_SCSI_AHA1740 is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC7XXX_OLD is not set
# CONFIG_SCSI_DPT_I2O is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_IN2000 is not set
# CONFIG_SCSI_AM53C974 is not set
# CONFIG_SCSI_MEGARAID is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_DTC3280 is not set
# CONFIG_SCSI_EATA is not set
# CONFIG_SCSI_EATA_DMA is not set
# CONFIG_SCSI_EATA_PIO is not set
# CONFIG_SCSI_FUTURE_DOMAIN is not set
# CONFIG_SCSI_GDTH is not set
# CONFIG_SCSI_GENERIC_NCR5380 is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_NCR53C406A is not set
# CONFIG_SCSI_NCR_D700 is not set
# CONFIG_SCSI_NCR53C7xx is not set
# CONFIG_SCSI_PAS16 is not set
# CONFIG_SCSI_PCI2000 is not set
# CONFIG_SCSI_PCI2220I is not set
# CONFIG_SCSI_PSI240I is not set
# CONFIG_SCSI_QLOGIC_FAS is not set
# CONFIG_SCSI_SIM710 is not set
# CONFIG_SCSI_SYM53C416 is not set
# CONFIG_SCSI_T128 is not set
# CONFIG_SCSI_U14_34F is not set
# CONFIG_SCSI_DEBUG is not set
#
# Network device support
# Network testing
#
# CONFIG_NET_PKTGEN is not set
CONFIG_NETDEVICES=y
#
# ARCnet devices
#
# CONFIG_ARCNET is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
......@@ -270,33 +281,16 @@ CONFIG_NETDEVICES=y
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
# CONFIG_SUNLANCE is not set
# CONFIG_SUNBMAC is not set
# CONFIG_SUNQE is not set
# CONFIG_SUNLANCE is not set
# CONFIG_SUNGEM is not set
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_LANCE is not set
# CONFIG_NET_VENDOR_SMC is not set
# CONFIG_NET_VENDOR_RACAL is not set
# CONFIG_NET_ISA is not set
# CONFIG_NET_PCI is not set
# CONFIG_NET_POCKET is not set
# CONFIG_MII is not set
CONFIG_SGISEEQ=y
#
# Ethernet (1000 Mbit)
#
# CONFIG_ACENIC is not set
# CONFIG_DL2K is not set
# CONFIG_MYRI_SBUS is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_SK98LIN is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_PLIP is not set
#
# Ethernet (10000 Mbit)
#
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
......@@ -306,11 +300,8 @@ CONFIG_SGISEEQ=y
# CONFIG_NET_RADIO is not set
#
# Token Ring devices
# Token Ring devices (depends on LLC=y)
#
# CONFIG_TR is not set
# CONFIG_NET_FC is not set
# CONFIG_RCPCI is not set
# CONFIG_SHAPER is not set
#
......@@ -331,21 +322,69 @@ CONFIG_SGISEEQ=y
#
# ISDN subsystem
#
# CONFIG_ISDN is not set
# CONFIG_ISDN_BOOL is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
#
# Old CD-ROM drivers (not SCSI, not IDE)
# Input device support
#
# CONFIG_CD_NO_IDESCSI is not set
CONFIG_INPUT=y
#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input I/O drivers
#
# CONFIG_GAMEPORT is not set
CONFIG_SOUND_GAMEPORT=y
CONFIG_SERIO=y
CONFIG_SERIO_I8042=y
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_CT82C710 is not set
#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Character devices
#
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
# CONFIG_SERIAL is not set
# CONFIG_SERIAL_EXTENDED is not set
CONFIG_HW_CONSOLE=y
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_IP22_ZILOG=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_UNIX98_PTY_COUNT=256
......@@ -355,36 +394,58 @@ CONFIG_UNIX98_PTY_COUNT=256
# CONFIG_I2C is not set
#
# Mice
# I2C Hardware Sensors Mainboard support
#
# CONFIG_BUSMOUSE is not set
# CONFIG_MOUSE is not set
#
# Joysticks
# I2C Hardware Sensors Chip support
#
# CONFIG_INPUT_GAMEPORT is not set
# CONFIG_I2C_SENSOR is not set
#
# Input core support is needed for gameports
# Mice
#
# CONFIG_BUSMOUSE is not set
# CONFIG_QIC02_TAPE is not set
#
# Input core support is needed for joysticks
# IPMI
#
# CONFIG_QIC02_TAPE is not set
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_INTEL_RNG is not set
CONFIG_WATCHDOG=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
# CONFIG_SOFT_WATCHDOG is not set
# CONFIG_WDT is not set
# CONFIG_WDTPCI is not set
# CONFIG_PCWATCHDOG is not set
# CONFIG_ACQUIRE_WDT is not set
# CONFIG_ADVANTECH_WDT is not set
# CONFIG_EUROTECH_WDT is not set
# CONFIG_IB700_WDT is not set
# CONFIG_I810_TCO is not set
# CONFIG_MIXCOMWD is not set
# CONFIG_SCx200_WDT is not set
# CONFIG_60XX_WDT is not set
# CONFIG_W83877F_WDT is not set
# CONFIG_MACHZ_WDT is not set
CONFIG_INDYDOG=y
# CONFIG_SC520_WDT is not set
# CONFIG_AMD7XX_TCO is not set
# CONFIG_ALIM7101_WDT is not set
# CONFIG_SC1200_WDT is not set
# CONFIG_WAFER_WDT is not set
# CONFIG_CPU5_WDT is not set
# CONFIG_NVRAM is not set
# CONFIG_RTC is not set
# CONFIG_GEN_RTC is not set
CONFIG_SGI_DS1286=y
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
# CONFIG_SONYPI is not set
#
# Ftape, the floppy tape device driver
......@@ -392,6 +453,8 @@ CONFIG_UNIX98_PTY_COUNT=256
# CONFIG_FTAPE is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_HANGCHECK_TIMER is not set
#
# Multimedia devices
......@@ -399,89 +462,92 @@ CONFIG_UNIX98_PTY_COUNT=256
# CONFIG_VIDEO_DEV is not set
#
# SGI Character devices
# Digital Video Broadcasting Devices
#
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_SGI_NEWPORT_CONSOLE=y
CONFIG_FONT_8x16=y
# CONFIG_PSMOUSE is not set
CONFIG_UNIX98_PTYS=y
CONFIG_UNIX98_PTY_COUNT=256
# CONFIG_DVB is not set
#
# File systems
#
# CONFIG_EXT2_FS is not set
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_XATTR=y
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
CONFIG_JBD=y
# CONFIG_JBD_DEBUG is not set
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
CONFIG_FS_POSIX_ACL=y
# CONFIG_XFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_QUOTA is not set
CONFIG_AUTOFS_FS=y
CONFIG_AUTOFS4_FS=y
# CONFIG_REISERFS_FS is not set
# CONFIG_REISERFS_CHECK is not set
# CONFIG_REISERFS_PROC_INFO is not set
#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=y
# CONFIG_JOLIET is not set
# CONFIG_ZISOFS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_FAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_DEVFS_FS is not set
CONFIG_DEVPTS_FS=y
CONFIG_DEVPTS_FS_XATTR=y
CONFIG_DEVPTS_FS_SECURITY=y
# CONFIG_TMPFS is not set
CONFIG_RAMFS=y
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_ADFS_FS_RW is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_CMS_FS is not set
# CONFIG_EXT3_FS is not set
# CONFIG_JBD is not set
# CONFIG_JBD_DEBUG is not set
# CONFIG_FAT_FS is not set
# CONFIG_MSDOS_FS is not set
# CONFIG_UMSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS_FS is not set
# CONFIG_JFFS2_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_TMPFS is not set
# CONFIG_RAMFS is not set
CONFIG_ISO9660_FS=y
# CONFIG_JOLIET is not set
# CONFIG_MINIX_FS is not set
# CONFIG_FREEVXFS_FS is not set
# CONFIG_NTFS_FS is not set
# CONFIG_NTFS_DEBUG is not set
# CONFIG_NTFS_RW is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
CONFIG_PROC_FS=y
# CONFIG_DEVFS_FS is not set
# CONFIG_DEVFS_MOUNT is not set
# CONFIG_DEVFS_DEBUG is not set
CONFIG_DEVPTS_FS=y
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX4FS_RW is not set
# CONFIG_ROMFS_FS is not set
CONFIG_EXT2_FS=y
# CONFIG_SYSV_FS is not set
# CONFIG_UDF_FS is not set
# CONFIG_UDF_RW is not set
# CONFIG_UFS_FS is not set
# CONFIG_UFS_FS_WRITE is not set
#
# Network File Systems
#
# CONFIG_CODA_FS is not set
# CONFIG_INTERMEZZO_FS is not set
CONFIG_NFS_FS=y
# CONFIG_NFS_V3 is not set
CONFIG_ROOT_NFS=y
# CONFIG_NFS_V4 is not set
CONFIG_NFSD=y
# CONFIG_NFSD_V3 is not set
CONFIG_SUNRPC=y
# CONFIG_NFSD_TCP is not set
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
CONFIG_EXPORTFS=y
CONFIG_SUNRPC=y
# CONFIG_SUNRPC_GSS is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_NCPFS_PACKET_SIGNING is not set
# CONFIG_NCPFS_IOCTL_LOCKING is not set
# CONFIG_NCPFS_STRONG is not set
# CONFIG_NCPFS_NFS_NS is not set
# CONFIG_NCPFS_OS2_NS is not set
# CONFIG_NCPFS_SMALLDOS is not set
# CONFIG_NCPFS_NLS is not set
# CONFIG_NCPFS_EXTRAS is not set
# CONFIG_CODA_FS is not set
# CONFIG_INTERMEZZO_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
......@@ -498,147 +564,82 @@ CONFIG_MSDOS_PARTITION=y
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set
# CONFIG_NEC98_PARTITION is not set
CONFIG_SGI_PARTITION=y
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_SMB_NLS is not set
# CONFIG_NLS is not set
# CONFIG_EFI_PARTITION is not set
#
# Graphics support
#
#
# Console drivers
# Console display driver support
#
# CONFIG_VGA_CONSOLE is not set
# CONFIG_MDA_CONSOLE is not set
CONFIG_SGI_NEWPORT_CONSOLE=y
CONFIG_DUMMY_CONSOLE=y
CONFIG_FONT_8x16=y
#
# Frame-buffer support
# Logo configuration
#
# CONFIG_FB is not set
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_LOGO_LINUX_CLUT224 is not set
CONFIG_LOGO_SGI_CLUT224=y
#
# Sound
#
# CONFIG_SOUND is not set
#
# SGI devices
#
CONFIG_SGI_SERIAL=y
# CONFIG_SERIAL_CONSOLE is not set
CONFIG_SGI_DS1286=y
# CONFIG_SGI_NEWPORT_GFX is not set
#
# USB support
#
# CONFIG_USB is not set
#
# USB Controllers
#
# CONFIG_USB_UHCI is not set
# CONFIG_USB_UHCI_ALT is not set
# CONFIG_USB_OHCI is not set
#
# USB Device Class drivers
#
# CONFIG_USB_AUDIO is not set
# CONFIG_USB_BLUETOOTH is not set
# CONFIG_USB_STORAGE is not set
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set
# CONFIG_USB_STORAGE_DPCM is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set
#
# USB Human Interface Devices (HID)
#
#
# Input core support is needed for USB HID
#
#
# USB Imaging devices
#
# CONFIG_USB_DC2XX is not set
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_SCANNER is not set
# CONFIG_USB_MICROTEK is not set
# CONFIG_USB_HPUSBSCSI is not set
# CONFIG_USB_GADGET is not set
#
# USB Multimedia devices
# Bluetooth support
#
# CONFIG_BT is not set
#
# Video4Linux support is needed for USB Multimedia device support
#
# CONFIG_USB_DABUSB is not set
#
# USB Network adaptors
#
# CONFIG_USB_PLUSB is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_CATC is not set
# CONFIG_USB_CDCETHER is not set
# CONFIG_USB_USBNET is not set
#
# USB port drivers
#
# CONFIG_USB_USS720 is not set
#
# USB Serial Converter support
# Kernel hacking
#
# CONFIG_USB_SERIAL is not set
# CONFIG_USB_SERIAL_GENERIC is not set
# CONFIG_USB_SERIAL_BELKIN is not set
# CONFIG_USB_SERIAL_WHITEHEAT is not set
# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
# CONFIG_USB_SERIAL_EMPEG is not set
# CONFIG_USB_SERIAL_FTDI_SIO is not set
# CONFIG_USB_SERIAL_VISOR is not set
# CONFIG_USB_SERIAL_EDGEPORT is not set
# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
# CONFIG_USB_SERIAL_KEYSPAN is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
# CONFIG_USB_SERIAL_MCT_U232 is not set
# CONFIG_USB_SERIAL_PL2303 is not set
# CONFIG_USB_SERIAL_CYBERJACK is not set
# CONFIG_USB_SERIAL_OMNINET is not set
CONFIG_CROSSCOMPILE=y
# CONFIG_DEBUG_KERNEL is not set
#
# Miscellaneous USB drivers
# Security options
#
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_ID75 is not set
# CONFIG_SECURITY is not set
#
# Input core support
# Cryptographic options
#
# CONFIG_INPUT is not set
# CONFIG_INPUT_KEYBDEV is not set
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_EVDEV is not set
CONFIG_CRYPTO=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_BLOWFISH=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_SERPENT=y
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_DEFLATE=y
# CONFIG_CRYPTO_TEST is not set
#
# Kernel hacking
# Library routines
#
CONFIG_CROSSCOMPILE=y
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_MIPS_UNCACHED is not set
# CONFIG_CRC32 is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
arch/mips/sgi/kernel/Makefile → arch/mips/sgi-ip22/Makefile
View file @ 2395133b
......@@ -3,7 +3,10 @@
# under Linux.
#
obj-y += indy_mc.o indy_sc.o indy_hpc.o indy_int.o indy_rtc.o system.o \
indyIRQ.o reset.o setup.o time.o
obj-y += ip22-mc.o ip22-hpc.o ip22-int.o ip22-irq.o ip22-berr.o \
ip22-time.o ip22-rtc.o ip22-nvram.o ip22-reset.o \
ip22-setup.o ip22-ksyms.o
obj-$(CONFIG_EISA) += ip22-eisa.o
EXTRA_AFLAGS := $(CFLAGS)
arch/mips/sgi-ip22/ip22-berr.c 0 → 100644
View file @ 2395133b
/*
* ip22-berr.c: Bus error handling.
*
* Copyright (C) 2002 Ladislav Michl
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <asm/addrspace.h>
#include <asm/system.h>
#include <asm/traps.h>
#include <asm/branch.h>
#include <asm/sgi/mc.h>
#include <asm/sgi/hpc3.h>
static unsigned int cpu_err_stat; /* Status reg for CPU */
static unsigned int gio_err_stat; /* Status reg for GIO */
static unsigned int cpu_err_addr; /* Error address reg for CPU */
static unsigned int gio_err_addr; /* Error address reg for GIO */
static void save_and_clear_buserr(void)
{
/* save memory controler's error status registers */
cpu_err_addr = sgimc->cerr;
cpu_err_stat = sgimc->cstat;
gio_err_addr = sgimc->gerr;
gio_err_stat = sgimc->gstat;
sgimc->cstat = sgimc->gstat = 0;
}
#define GIO_ERRMASK 0xff00
#define CPU_ERRMASK 0x3f00
static void print_buserr(void)
{
if (cpu_err_stat & CPU_ERRMASK)
printk(KERN_ALERT "CPU error 0x%x<%s%s%s%s%s%s> @ 0x%08x\n",
cpu_err_stat,
cpu_err_stat & SGIMC_CSTAT_RD ? "RD " : "",
cpu_err_stat & SGIMC_CSTAT_PAR ? "PAR " : "",
cpu_err_stat & SGIMC_CSTAT_ADDR ? "ADDR " : "",
cpu_err_stat & SGIMC_CSTAT_SYSAD_PAR ? "SYSAD " : "",
cpu_err_stat & SGIMC_CSTAT_SYSCMD_PAR ? "SYSCMD " : "",
cpu_err_stat & SGIMC_CSTAT_BAD_DATA ? "BAD_DATA " : "",
cpu_err_addr);
if (gio_err_stat & GIO_ERRMASK)
printk(KERN_ALERT "GIO error 0x%x:<%s%s%s%s%s%s%s%s> @ 0x08%x\n",
gio_err_stat,
gio_err_stat & SGIMC_GSTAT_RD ? "RD " : "",
gio_err_stat & SGIMC_GSTAT_WR ? "WR " : "",
gio_err_stat & SGIMC_GSTAT_TIME ? "TIME " : "",
gio_err_stat & SGIMC_GSTAT_PROM ? "PROM " : "",
gio_err_stat & SGIMC_GSTAT_ADDR ? "ADDR " : "",
gio_err_stat & SGIMC_GSTAT_BC ? "BC " : "",
gio_err_stat & SGIMC_GSTAT_PIO_RD ? "PIO_RD " : "",
gio_err_stat & SGIMC_GSTAT_PIO_WR ? "PIO_WR " : "",
gio_err_addr);
}
/*
* MC sends an interrupt whenever bus or parity errors occur. In addition,
* if the error happened during a CPU read, it also asserts the bus error
* pin on the R4K. Code in bus error handler save the MC bus error registers
* and then clear the interrupt when this happens.
*/
void ip22_be_interrupt(int irq, struct pt_regs *regs)
{
save_and_clear_buserr();
print_buserr();
panic("Bus error, epc == %08lx, ra == %08lx",
regs->cp0_epc, regs->regs[31]);
}
int ip22_be_handler(struct pt_regs *regs, int is_fixup)
{
save_and_clear_buserr();
if (is_fixup)
return MIPS_BE_FIXUP;
print_buserr();
return MIPS_BE_FATAL;
}
void __init ip22_be_init(void)
{
board_be_handler = ip22_be_handler;
}
arch/mips/sgi-ip22/ip22-eisa.c 0 → 100644
View file @ 2395133b
/*
* Basic EISA bus support for the SGI Indigo-2.
*
* (C) 2002 Pascal Dameme <netinet@freesurf.fr>
* and Marc Zyngier <mzyngier@freesurf.fr>
*
* This code is released under both the GPL version 2 and BSD
* licenses. Either license may be used.
*
* This code offers a very basic support for this EISA bus present in
* the SGI Indigo-2. It currently only supports PIO (forget about DMA
* for the time being). This is enough for a low-end ethernet card,
* but forget about your favorite SCSI card...
*
* TODO :
* - Fix bugs...
* - Add ISA support
* - Add DMA (yeah, right...).
* - Fix more bugs.
*/
#include <linux/config.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/kernel_stat.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/processor.h>
#include <asm/sgi/ioc.h>
#include <asm/sgi/mc.h>
#include <asm/sgi/ip22.h>
#define EISA_MAX_SLOTS 4
#define EISA_MAX_IRQ 16
#define EISA_TO_PHYS(x) (0x00080000 | (x))
#define EISA_TO_KSEG1(x) ((void *) KSEG1ADDR(EISA_TO_PHYS((x))))
#define EIU_MODE_REG 0x0009ffc0
#define EIU_STAT_REG 0x0009ffc4
#define EIU_PREMPT_REG 0x0009ffc8
#define EIU_QUIET_REG 0x0009ffcc
#define EIU_INTRPT_ACK 0x00090004
#define EISA_DMA1_STATUS 8
#define EISA_INT1_CTRL 0x20
#define EISA_INT1_MASK 0x21
#define EISA_INT2_CTRL 0xA0
#define EISA_INT2_MASK 0xA1
#define EISA_DMA2_STATUS 0xD0
#define EISA_DMA2_WRITE_SINGLE 0xD4
#define EISA_EXT_NMI_RESET_CTRL 0x461
#define EISA_INT1_EDGE_LEVEL 0x4D0
#define EISA_INT2_EDGE_LEVEL 0x4D1
#define EISA_VENDOR_ID_OFFSET 0xC80
#define EIU_WRITE_32(x,y) { *((u32 *) KSEG1ADDR(x)) = (u32) (y); mb(); }
#define EIU_READ_8(x) *((u8 *) KSEG1ADDR(x))
#define EISA_WRITE_8(x,y) { *((u8 *) EISA_TO_KSEG1(x)) = (u8) (y); mb(); }
#define EISA_READ_8(x) *((u8 *) EISA_TO_KSEG1(x))
static char *decode_eisa_sig(u8 * sig)
{
static char sig_str[8];
u16 rev;
if (sig[0] & 0x80)
return NULL;
sig_str[0] = ((sig[0] >> 2) & 0x1f) + ('A' - 1);
sig_str[1] = (((sig[0] & 3) << 3) | (sig[1] >> 5)) + ('A' - 1);
sig_str[2] = (sig[1] & 0x1f) + ('A' - 1);
rev = (sig[2] << 8) | sig[3];
sprintf(sig_str + 3, "%04X", rev);
return sig_str;
}
static void ip22_eisa_intr(int irq, void *dev_id, struct pt_regs *regs)
{
u8 eisa_irq;
u8 dma1, dma2;
eisa_irq = EIU_READ_8(EIU_INTRPT_ACK);
dma1 = EISA_READ_8(EISA_DMA1_STATUS);
dma2 = EISA_READ_8(EISA_DMA2_STATUS);
if (eisa_irq >= EISA_MAX_IRQ) {
/* Oops, Bad Stuff Happened... */
printk(KERN_ERR "eisa_irq %d out of bound\n", eisa_irq);
EISA_WRITE_8(EISA_INT2_CTRL, 0x20);
EISA_WRITE_8(EISA_INT1_CTRL, 0x20);
} else
do_IRQ(eisa_irq, regs);
}
static void enable_eisa1_irq(unsigned int irq)
{
unsigned long flags;
u8 mask;
local_irq_save(flags);
mask = EISA_READ_8(EISA_INT1_MASK);
mask &= ~((u8) (1 << irq));
EISA_WRITE_8(EISA_INT1_MASK, mask);
local_irq_restore(flags);
}
static unsigned int startup_eisa1_irq(unsigned int irq)
{
u8 edge;
/* Only use edge interrupts for EISA */
edge = EISA_READ_8(EISA_INT1_EDGE_LEVEL);
edge &= ~((u8) (1 << irq));
EISA_WRITE_8(EISA_INT1_EDGE_LEVEL, edge);
enable_eisa1_irq(irq);
return 0;
}
static void disable_eisa1_irq(unsigned int irq)
{
u8 mask;
mask = EISA_READ_8(EISA_INT1_MASK);
mask |= ((u8) (1 << irq));
EISA_WRITE_8(EISA_INT1_MASK, mask);
}
#define shutdown_eisa1_irq disable_eisa1_irq
static void mask_and_ack_eisa1_irq(unsigned int irq)
{
disable_eisa1_irq(irq);
EISA_WRITE_8(EISA_INT1_CTRL, 0x20);
}
static void end_eisa1_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
enable_eisa1_irq(irq);
}
static struct hw_interrupt_type ip22_eisa1_irq_type = {
.typename = "IP22 EISA",
.startup = startup_eisa1_irq,
.shutdown = shutdown_eisa1_irq,
.enable = enable_eisa1_irq,
.disable = disable_eisa1_irq,
.ack = mask_and_ack_eisa1_irq,
.end = end_eisa1_irq,
};
static void enable_eisa2_irq(unsigned int irq)
{
unsigned long flags;
u8 mask;
local_irq_save(flags);
mask = EISA_READ_8(EISA_INT2_MASK);
mask &= ~((u8) (1 << (irq - 8)));
EISA_WRITE_8(EISA_INT2_MASK, mask);
local_irq_restore(flags);
}
static unsigned int startup_eisa2_irq(unsigned int irq)
{
u8 edge;
/* Only use edge interrupts for EISA */
edge = EISA_READ_8(EISA_INT2_EDGE_LEVEL);
edge &= ~((u8) (1 << (irq - 8)));
EISA_WRITE_8(EISA_INT2_EDGE_LEVEL, edge);
enable_eisa2_irq(irq);
return 0;
}
static void disable_eisa2_irq(unsigned int irq)
{
u8 mask;
mask = EISA_READ_8(EISA_INT2_MASK);
mask |= ((u8) (1 << (irq - 8)));
EISA_WRITE_8(EISA_INT2_MASK, mask);
}
#define shutdown_eisa2_irq disable_eisa2_irq
static void mask_and_ack_eisa2_irq(unsigned int irq)
{
disable_eisa2_irq(irq);
EISA_WRITE_8(EISA_INT2_CTRL, 0x20);
EISA_WRITE_8(EISA_INT1_CTRL, 0x20);
}
static void end_eisa2_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
enable_eisa2_irq(irq);
}
static struct hw_interrupt_type ip22_eisa2_irq_type = {
.typename = "IP22 EISA",
.startup = startup_eisa2_irq,
.shutdown = shutdown_eisa2_irq,
.enable = enable_eisa2_irq,
.disable = disable_eisa2_irq,
.ack = mask_and_ack_eisa2_irq,
.end = end_eisa2_irq,
};
static struct irqaction eisa_action = {
.handler = ip22_eisa_intr,
.name = "EISA",
};
static struct irqaction cascade_action = {
.handler = no_action,
.name = "EISA cascade",
};
int __init ip22_eisa_init(void)
{
int i, c;
char *str;
u8 *slot_addr;
if (!(sgimc->systemid & SGIMC_SYSID_EPRESENT)) {
printk(KERN_INFO "EISA: bus not present.\n");
return 1;
}
printk(KERN_INFO "EISA: Probing bus...\n");
for (c = 0, i = 1; i <= EISA_MAX_SLOTS; i++) {
slot_addr =
(u8 *) EISA_TO_KSEG1((0x1000 * i) +
EISA_VENDOR_ID_OFFSET);
if ((str = decode_eisa_sig(slot_addr))) {
printk(KERN_INFO "EISA: slot %d : %s detected.\n",
i, str);
c++;
}
}
printk(KERN_INFO "EISA: Detected %d card%s.\n", c, c < 2 ? "" : "s");
#ifdef CONFIG_ISA
printk(KERN_INFO "ISA support compiled in.\n");
#endif
/* Warning : BlackMagicAhead(tm).
Please wave your favorite dead chicken over the busses */
/* First say hello to the EIU */
EIU_WRITE_32(EIU_PREMPT_REG, 0x0000FFFF);
EIU_WRITE_32(EIU_QUIET_REG, 1);
EIU_WRITE_32(EIU_MODE_REG, 0x40f3c07F);
/* Now be nice to the EISA chipset */
EISA_WRITE_8(EISA_EXT_NMI_RESET_CTRL, 1);
for (i = 0; i < 10000; i++); /* Wait long enough for the dust to settle */
EISA_WRITE_8(EISA_EXT_NMI_RESET_CTRL, 0);
EISA_WRITE_8(EISA_INT1_CTRL, 0x11);
EISA_WRITE_8(EISA_INT2_CTRL, 0x11);
EISA_WRITE_8(EISA_INT1_MASK, 0);
EISA_WRITE_8(EISA_INT2_MASK, 8);
EISA_WRITE_8(EISA_INT1_MASK, 4);
EISA_WRITE_8(EISA_INT2_MASK, 2);
EISA_WRITE_8(EISA_INT1_MASK, 1);
EISA_WRITE_8(EISA_INT2_MASK, 1);
EISA_WRITE_8(EISA_INT1_MASK, 0xfb);
EISA_WRITE_8(EISA_INT2_MASK, 0xff);
EISA_WRITE_8(EISA_DMA2_WRITE_SINGLE, 0);
for (i = SGINT_EISA; i < (SGINT_EISA + EISA_MAX_IRQ); i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
if (i < (SGINT_EISA + 8))
irq_desc[i].handler = &ip22_eisa1_irq_type;
else
irq_desc[i].handler = &ip22_eisa2_irq_type;
}
/* Cannot use request_irq because of kmalloc not being ready at such
* an early stage. Yes, I've been bitten... */
setup_irq(SGI_EISA_IRQ, &eisa_action);
setup_irq(SGINT_EISA + 2, &cascade_action);
EISA_bus = 1;
return 0;
}
arch/mips/sgi-ip22/ip22-hpc.c 0 → 100644
View file @ 2395133b
/*
* ip22-hpc.c: Routines for generic manipulation of the HPC controllers.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
* Copyright (C) 1998 Ralf Baechle
*/
#include <linux/init.h>
#include <linux/types.h>
#include <asm/addrspace.h>
#include <asm/sgi/hpc3.h>
#include <asm/sgi/ioc.h>
#include <asm/sgi/ip22.h>
struct hpc3_regs *hpc3c0, *hpc3c1;
struct sgioc_regs *sgioc;
/* We need software copies of these because they are write only. */
u8 sgi_ioc_reset, sgi_ioc_write;
extern char *system_type;
void __init sgihpc_init(void)
{
hpc3c0 = (struct hpc3_regs *)(KSEG1 + HPC3_CHIP0_BASE);
hpc3c1 = (struct hpc3_regs *)(KSEG1 + HPC3_CHIP1_BASE);
/* IOC lives in PBUS PIO channel 6 */
sgioc = (struct sgioc_regs *)hpc3c0->pbus_extregs[6];
hpc3c0->pbus_piocfg[6][0] |= HPC3_PIOCFG_DS16;
if (ip22_is_fullhouse()) {
/* Full House comes with INT2 which lives in PBUS PIO
* channel 4 */
sgint = (struct sgint_regs *)hpc3c0->pbus_extregs[4];
system_type = "SGI Indigo2";
} else {
/* Guiness comes with INT3 which is part of IOC */
sgint = &sgioc->int3;
system_type = "SGI Indy";
}
sgi_ioc_reset = (SGIOC_RESET_PPORT | SGIOC_RESET_KBDMOUSE |
SGIOC_RESET_EISA | SGIOC_RESET_ISDN |
SGIOC_RESET_LC0OFF);
sgi_ioc_write = (SGIOC_WRITE_EASEL | SGIOC_WRITE_NTHRESH |
SGIOC_WRITE_TPSPEED | SGIOC_WRITE_EPSEL |
SGIOC_WRITE_U0AMODE | SGIOC_WRITE_U1AMODE);
sgioc->reset = sgi_ioc_reset;
sgioc->write = sgi_ioc_write;
}
arch/mips/sgi/kernel/indy_int.c → arch/mips/sgi-ip22/ip22-int.c
View file @ 2395133b
/*
* indy_int.c: Routines for generic manipulation of the INT[23] ASIC
* found on INDY workstations..
* ip22-int.c: Routines for generic manipulation of the INT[23] ASIC
* found on INDY and Indigo2 workstations.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
* Copyright (C) 1997, 1998 Ralf Baechle (ralf@gnu.org)
* Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu)
* Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu)
* - Indigo2 changes
* - Interrupt handling fixes
* Copyright (C) 2001, 2003 Ladislav Michl (ladis@linux-mips.org)
*/
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/timex.h>
#include <linux/slab.h>
#include <linux/random.h>
#include <linux/smp.h>
#include <linux/smp_lock.h>
#include <asm/bitops.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <linux/irq.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/addrspace.h>
#include <asm/ptrace.h>
#include <asm/processor.h>
#include <asm/sgi/sgi.h>
#include <asm/sgi/sgihpc.h>
#include <asm/sgi/sgint23.h>
#include <asm/sgialib.h>
#include <asm/gdb-stub.h>
/*
* Linux has a controller-independent x86 interrupt architecture.
* every controller has a 'controller-template', that is used
* by the main code to do the right thing. Each driver-visible
* interrupt source is transparently wired to the apropriate
* controller. Thus drivers need not be aware of the
* interrupt-controller.
*
* Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC,
* PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC.
* (IO-APICs assumed to be messaging to Pentium local-APICs)
*
* the code is designed to be easily extended with new/different
* interrupt controllers, without having to do assembly magic.
*/
#include <asm/sgi/ioc.h>
#include <asm/sgi/hpc3.h>
#include <asm/sgi/ip22.h>
/* #define DEBUG_SGINT */
struct sgi_int2_regs *sgi_i2regs;
struct sgi_int3_regs *sgi_i3regs;
struct sgi_ioc_ints *ioc_icontrol;
struct sgi_ioc_timers *ioc_timers;
volatile unsigned char *ioc_tclear;
/* So far nothing hangs here */
#undef USE_LIO3_IRQ
struct sgint_regs *sgint;
static char lc0msk_to_irqnr[256];
static char lc1msk_to_irqnr[256];
......@@ -68,27 +38,23 @@ static char lc2msk_to_irqnr[256];
static char lc3msk_to_irqnr[256];
extern asmlinkage void indyIRQ(void);
extern int ip22_eisa_init(void);
/* Local IRQ's are layed out logically like this:
*
* 0 --> 7 == local 0 interrupts
* 8 --> 15 == local 1 interrupts
* 16 --> 23 == vectored level 2 interrupts
* 24 --> 31 == vectored level 3 interrupts (not used)
*/
static void enable_local0_irq(unsigned int irq)
{
unsigned long flags;
save_and_cli(flags);
ioc_icontrol->imask0 |= (1 << (irq - SGINT_LOCAL0));
restore_flags(flags);
local_irq_save(flags);
/* don't allow mappable interrupt to be enabled from setup_irq,
* we have our own way to do so */
if (irq != SGI_MAP_0_IRQ)
sgint->imask0 |= (1 << (irq - SGINT_LOCAL0));
local_irq_restore(flags);
}
static unsigned int startup_local0_irq(unsigned int irq)
{
enable_local0_irq(irq);
return 0; /* Never anything pending */
}
......@@ -96,9 +62,9 @@ static void disable_local0_irq(unsigned int irq)
{
unsigned long flags;
save_and_cli(flags);
ioc_icontrol->imask0 &= ~(1 << (irq - SGINT_LOCAL0));
restore_flags(flags);
local_irq_save(flags);
sgint->imask0 &= ~(1 << (irq - SGINT_LOCAL0));
local_irq_restore(flags);
}
#define shutdown_local0_irq disable_local0_irq
......@@ -111,29 +77,30 @@ static void end_local0_irq (unsigned int irq)
}
static struct hw_interrupt_type ip22_local0_irq_type = {
"IP22 local 0",
startup_local0_irq,
shutdown_local0_irq,
enable_local0_irq,
disable_local0_irq,
mask_and_ack_local0_irq,
end_local0_irq,
NULL
.typename = "IP22 local 0",
.startup = startup_local0_irq,
.shutdown = shutdown_local0_irq,
.enable = enable_local0_irq,
.disable = disable_local0_irq,
.ack = mask_and_ack_local0_irq,
.end = end_local0_irq,
};
static void enable_local1_irq(unsigned int irq)
{
unsigned long flags;
save_and_cli(flags);
ioc_icontrol->imask1 |= (1 << (irq - SGINT_LOCAL1));
restore_flags(flags);
local_irq_save(flags);
/* don't allow mappable interrupt to be enabled from setup_irq,
* we have our own way to do so */
if (irq != SGI_MAP_1_IRQ)
sgint->imask1 |= (1 << (irq - SGINT_LOCAL1));
local_irq_restore(flags);
}
static unsigned int startup_local1_irq(unsigned int irq)
{
enable_local1_irq(irq);
return 0; /* Never anything pending */
}
......@@ -141,9 +108,9 @@ void disable_local1_irq(unsigned int irq)
{
unsigned long flags;
save_and_cli(flags);
ioc_icontrol->imask1 &= ~(1 << (irq- SGINT_LOCAL1));
restore_flags(flags);
local_irq_save(flags);
sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1));
local_irq_restore(flags);
}
#define shutdown_local1_irq disable_local1_irq
......@@ -156,30 +123,28 @@ static void end_local1_irq (unsigned int irq)
}
static struct hw_interrupt_type ip22_local1_irq_type = {
"IP22 local 1",
startup_local1_irq,
shutdown_local1_irq,
enable_local1_irq,
disable_local1_irq,
mask_and_ack_local1_irq,
end_local1_irq,
NULL
.typename = "IP22 local 1",
.startup = startup_local1_irq,
.shutdown = shutdown_local1_irq,
.enable = enable_local1_irq,
.disable = disable_local1_irq,
.ack = mask_and_ack_local1_irq,
.end = end_local1_irq,
};
static void enable_local2_irq(unsigned int irq)
{
unsigned long flags;
save_and_cli(flags);
enable_local0_irq(7);
ioc_icontrol->cmeimask0 |= (1 << (irq - SGINT_LOCAL2));
restore_flags(flags);
local_irq_save(flags);
sgint->imask0 |= (1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
sgint->cmeimask0 |= (1 << (irq - SGINT_LOCAL2));
local_irq_restore(flags);
}
static unsigned int startup_local2_irq(unsigned int irq)
{
enable_local2_irq(irq);
return 0; /* Never anything pending */
}
......@@ -187,9 +152,11 @@ void disable_local2_irq(unsigned int irq)
{
unsigned long flags;
save_and_cli(flags);
ioc_icontrol->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2));
restore_flags(flags);
local_irq_save(flags);
sgint->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2));
if (!sgint->cmeimask0)
sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
local_irq_restore(flags);
}
#define shutdown_local2_irq disable_local2_irq
......@@ -202,30 +169,28 @@ static void end_local2_irq (unsigned int irq)
}
static struct hw_interrupt_type ip22_local2_irq_type = {
"IP22 local 2",
startup_local2_irq,
shutdown_local2_irq,
enable_local2_irq,
disable_local2_irq,
mask_and_ack_local2_irq,
end_local2_irq,
NULL
.typename = "IP22 local 2",
.startup = startup_local2_irq,
.shutdown = shutdown_local2_irq,
.enable = enable_local2_irq,
.disable = disable_local2_irq,
.ack = mask_and_ack_local2_irq,
.end = end_local2_irq,
};
static void enable_local3_irq(unsigned int irq)
{
unsigned long flags;
save_and_cli(flags);
printk("Yeeee, got passed irq_nr %d at enable_local3_irq\n", irq);
panic("INVALID IRQ level!");
restore_flags(flags);
local_irq_save(flags);
sgint->imask1 |= (1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
sgint->cmeimask1 |= (1 << (irq - SGINT_LOCAL3));
local_irq_restore(flags);
}
static unsigned int startup_local3_irq(unsigned int irq)
{
enable_local3_irq(irq);
return 0; /* Never anything pending */
}
......@@ -233,14 +198,11 @@ void disable_local3_irq(unsigned int irq)
{
unsigned long flags;
save_and_cli(flags);
/*
* This way we'll see if anyone would ever want vectored level 3
* interrupts. Highly unlikely.
*/
printk("Yeeee, got passed irq_nr %d at disable_local3_irq\n", irq);
panic("INVALID IRQ level!");
restore_flags(flags);
local_irq_save(flags);
sgint->cmeimask1 &= ~(1 << (irq - SGINT_LOCAL3));
if (!sgint->cmeimask1)
sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
local_irq_restore(flags);
}
#define shutdown_local3_irq disable_local3_irq
......@@ -253,228 +215,147 @@ static void end_local3_irq (unsigned int irq)
}
static struct hw_interrupt_type ip22_local3_irq_type = {
"IP22 local 3",
startup_local3_irq,
shutdown_local3_irq,
enable_local3_irq,
disable_local3_irq,
mask_and_ack_local3_irq,
end_local3_irq,
NULL
};
void enable_gio_irq(unsigned int irq)
{
/* XXX TODO XXX */
}
static unsigned int startup_gio_irq(unsigned int irq)
{
enable_gio_irq(irq);
return 0; /* Never anything pending */
}
void disable_gio_irq(unsigned int irq)
{
/* XXX TODO XXX */
}
#define shutdown_gio_irq disable_gio_irq
#define mask_and_ack_gio_irq disable_gio_irq
static void end_gio_irq (unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_gio_irq(irq);
}
static struct hw_interrupt_type ip22_gio_irq_type = {
"IP22 GIO",
startup_gio_irq,
shutdown_gio_irq,
enable_gio_irq,
disable_gio_irq,
mask_and_ack_gio_irq,
end_gio_irq,
NULL
};
void enable_hpcdma_irq(unsigned int irq)
{
/* XXX TODO XXX */
}
static unsigned int startup_hpcdma_irq(unsigned int irq)
{
enable_hpcdma_irq(irq);
return 0; /* Never anything pending */
}
void disable_hpcdma_irq(unsigned int irq)
{
/* XXX TODO XXX */
}
#define shutdown_hpcdma_irq disable_hpcdma_irq
#define mask_and_ack_hpcdma_irq disable_hpcdma_irq
static void end_hpcdma_irq (unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_hpcdma_irq(irq);
}
static struct hw_interrupt_type ip22_hpcdma_irq_type = {
"IP22 HPC DMA",
startup_hpcdma_irq,
shutdown_hpcdma_irq,
enable_hpcdma_irq,
disable_hpcdma_irq,
mask_and_ack_hpcdma_irq,
end_hpcdma_irq,
NULL
};
static struct irqaction r4ktimer_action = {
NULL, 0, 0, "R4000 timer/counter", NULL, NULL,
};
static struct irqaction indy_berr_action = {
NULL, 0, 0, "IP22 Bus Error", NULL, NULL,
};
static struct irqaction *irq_action[16] = {
NULL, NULL, NULL, NULL,
NULL, NULL, &indy_berr_action, &r4ktimer_action,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL
.typename = "IP22 local 3",
.startup = startup_local3_irq,
.shutdown = shutdown_local3_irq,
.enable = enable_local3_irq,
.disable = disable_local3_irq,
.ack = mask_and_ack_local3_irq,
.end = end_local3_irq,
};
void indy_local0_irqdispatch(struct pt_regs *regs)
{
unsigned char mask = ioc_icontrol->istat0;
unsigned char mask2 = 0;
u8 mask = sgint->istat0 & sgint->imask0;
u8 mask2;
int irq;
mask &= ioc_icontrol->imask0;
if (mask & ISTAT0_LIO2) {
mask2 = ioc_icontrol->vmeistat;
mask2 &= ioc_icontrol->cmeimask0;
if (mask & SGINT_ISTAT0_LIO2) {
mask2 = sgint->vmeistat & sgint->cmeimask0;
irq = lc2msk_to_irqnr[mask2];
} else {
} else
irq = lc0msk_to_irqnr[mask];
}
/* if irq == 0, then the interrupt has already been cleared */
if (irq == 0)
goto end;
do_IRQ(irq, regs);
goto end;
no_handler:
printk("No handler for local0 irq: %i\n", irq);
end:
if (irq)
do_IRQ(irq, regs);
return;
}
void indy_local1_irqdispatch(struct pt_regs *regs)
{
unsigned char mask = ioc_icontrol->istat1;
unsigned char mask2 = 0;
u8 mask = sgint->istat1 & sgint->imask1;
u8 mask2;
int irq;
mask &= ioc_icontrol->imask1;
if (mask & ISTAT1_LIO3) {
printk("WHee: Got an LIO3 irq, winging it...\n");
mask2 = ioc_icontrol->vmeistat;
mask2 &= ioc_icontrol->cmeimask1;
irq = lc3msk_to_irqnr[ioc_icontrol->vmeistat];
} else {
if (mask & SGINT_ISTAT1_LIO3) {
mask2 = sgint->vmeistat & sgint->cmeimask1;
irq = lc3msk_to_irqnr[mask2];
} else
irq = lc1msk_to_irqnr[mask];
}
/* if irq == 0, then the interrupt has already been cleared */
/* not sure if it is needed here, but it is needed for local0 */
if (irq == 0)
goto end;
do_IRQ(irq, regs);
goto end;
no_handler:
printk("No handler for local1 irq: %i\n", irq);
end:
return;
if (irq)
do_IRQ(irq, regs);
return;
}
extern void ip22_be_interrupt(int irq, struct pt_regs *regs);
void indy_buserror_irq(struct pt_regs *regs)
{
int cpu = smp_processor_id();
int irq = 6;
irq_enter(cpu, irq);
kstat_cpu(0).irqs[irq]++;
printk("Got a bus error IRQ, shouldn't happen yet\n");
show_regs(regs);
printk("Spinning...\n");
while(1);
irq_exit(cpu, irq);
int irq = SGI_BUSERR_IRQ;
irq_enter();
kstat_cpu(cpu).irqs[irq]++;
ip22_be_interrupt(irq, regs);
irq_exit();
}
static struct irqaction local0_cascade = {
.handler = no_action,
.flags = SA_INTERRUPT,
.name = "local0 cascade",
};
static struct irqaction local1_cascade = {
.handler = no_action,
.flags = SA_INTERRUPT,
.name = "local1 cascade",
};
static struct irqaction buserr = {
.handler = no_action,
.flags = SA_INTERRUPT,
.name = "Bus Error",
};
static struct irqaction map0_cascade = {
.handler = no_action,
.flags = SA_INTERRUPT,
.name = "mapable0 cascade",
};
#ifdef USE_LIO3_IRQ
static struct irqaction map1_cascade = {
.handler = no_action,
.flags = SA_INTERRUPT,
.name = "mapable1 cascade",
};
#define SGI_INTERRUPTS SGINT_END
#else
#define SGI_INTERRUPTS SGINT_LOCAL3
#endif
extern void mips_cpu_irq_init(unsigned int irq_base);
void __init init_IRQ(void)
{
int i;
sgi_i2regs = (struct sgi_int2_regs *) (KSEG1 + SGI_INT2_BASE);
sgi_i3regs = (struct sgi_int3_regs *) (KSEG1 + SGI_INT3_BASE);
/* Init local mask --> irq tables. */
for (i = 0; i < 256; i++) {
if (i & 0x80) {
lc0msk_to_irqnr[i] = 7;
lc1msk_to_irqnr[i] = 15;
lc2msk_to_irqnr[i] = 23;
lc3msk_to_irqnr[i] = 31;
lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 7;
lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 7;
lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 7;
lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 7;
} else if (i & 0x40) {
lc0msk_to_irqnr[i] = 6;
lc1msk_to_irqnr[i] = 14;
lc2msk_to_irqnr[i] = 22;
lc3msk_to_irqnr[i] = 30;
lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 6;
lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 6;
lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 6;
lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 6;
} else if (i & 0x20) {
lc0msk_to_irqnr[i] = 5;
lc1msk_to_irqnr[i] = 13;
lc2msk_to_irqnr[i] = 21;
lc3msk_to_irqnr[i] = 29;
lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 5;
lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 5;
lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 5;
lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 5;
} else if (i & 0x10) {
lc0msk_to_irqnr[i] = 4;
lc1msk_to_irqnr[i] = 12;
lc2msk_to_irqnr[i] = 20;
lc3msk_to_irqnr[i] = 28;
lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 4;
lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 4;
lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 4;
lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 4;
} else if (i & 0x08) {
lc0msk_to_irqnr[i] = 3;
lc1msk_to_irqnr[i] = 11;
lc2msk_to_irqnr[i] = 19;
lc3msk_to_irqnr[i] = 27;
lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 3;
lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 3;
lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 3;
lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 3;
} else if (i & 0x04) {
lc0msk_to_irqnr[i] = 2;
lc1msk_to_irqnr[i] = 10;
lc2msk_to_irqnr[i] = 18;
lc3msk_to_irqnr[i] = 26;
lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 2;
lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 2;
lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 2;
lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 2;
} else if (i & 0x02) {
lc0msk_to_irqnr[i] = 1;
lc1msk_to_irqnr[i] = 9;
lc2msk_to_irqnr[i] = 17;
lc3msk_to_irqnr[i] = 25;
lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 1;
lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 1;
lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 1;
lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 1;
} else if (i & 0x01) {
lc0msk_to_irqnr[i] = 0;
lc1msk_to_irqnr[i] = 8;
lc2msk_to_irqnr[i] = 16;
lc3msk_to_irqnr[i] = 24;
lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 0;
lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 0;
lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 0;
lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 0;
} else {
lc0msk_to_irqnr[i] = 0;
lc1msk_to_irqnr[i] = 0;
......@@ -483,28 +364,19 @@ void __init init_IRQ(void)
}
}
/* Indy uses an INT3, Indigo2 uses an INT2 */
if (sgi_guiness) {
ioc_icontrol = &sgi_i3regs->ints;
ioc_timers = &sgi_i3regs->timers;
ioc_tclear = &sgi_i3regs->tclear;
} else {
ioc_icontrol = &sgi_i2regs->ints;
ioc_timers = &sgi_i2regs->timers;
ioc_tclear = &sgi_i2regs->tclear;
}
/* Mask out all interrupts. */
ioc_icontrol->imask0 = 0;
ioc_icontrol->imask1 = 0;
ioc_icontrol->cmeimask0 = 0;
ioc_icontrol->cmeimask1 = 0;
sgint->imask0 = 0;
sgint->imask1 = 0;
sgint->cmeimask0 = 0;
sgint->cmeimask1 = 0;
set_except_vector(0, indyIRQ);
init_generic_irq();
/* init CPU irqs */
mips_cpu_irq_init(SGINT_CPU);
for (i = SGINT_LOCAL0; i < SGINT_END; i++) {
for (i = SGINT_LOCAL0; i < SGI_INTERRUPTS; i++) {
hw_irq_controller *handler;
if (i < SGINT_LOCAL1)
......@@ -513,16 +385,28 @@ void __init init_IRQ(void)
handler = &ip22_local1_irq_type;
else if (i < SGINT_LOCAL3)
handler = &ip22_local2_irq_type;
else if (i < SGINT_GIO)
else
handler = &ip22_local3_irq_type;
else if (i < SGINT_HPCDMA)
handler = &ip22_gio_irq_type;
else if (i < SGINT_END)
handler = &ip22_hpcdma_irq_type;
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
irq_desc[i].handler = handler;
}
/* vector handler. this register the IRQ as non-sharable */
setup_irq(SGI_LOCAL_0_IRQ, &local0_cascade);
setup_irq(SGI_LOCAL_1_IRQ, &local1_cascade);
setup_irq(SGI_BUSERR_IRQ, &buserr);
/* cascade in cascade. i love Indy ;-) */
setup_irq(SGI_MAP_0_IRQ, &map0_cascade);
#ifdef USE_LIO3_IRQ
setup_irq(SGI_MAP_1_IRQ, &map1_cascade);
#endif
#ifdef CONFIG_EISA
if (ip22_is_fullhouse()) /* Only Indigo-2 has EISA stuff */
ip22_eisa_init ();
#endif
}
arch/mips64/sgi-ip22/ip22-irq.S → arch/mips/sgi-ip22/ip22-irq.S
View file @ 2395133b
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* indyIRQ.S: Interrupt exception dispatch code for FullHouse and
* Guiness.
* ip22-irq.S: Interrupt exception dispatch code for FullHouse and
* Guiness.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
*/
#include <asm/asm.h>
#include <asm/mipsregs.h>
#include <asm/regdef.h>
......@@ -68,10 +65,8 @@
andi a0, s0, CAUSEF_IP2 # delay slot, check local level zero
/* Wheee, a timer interrupt. */
move a0, sp
jal indy_timer_interrupt
nop # delay slot
jal indy_r4k_timer_interrupt
move a0, sp # delay slot
j ret_from_irq
nop # delay slot
......@@ -91,38 +86,33 @@
andi a0, s0, CAUSEF_IP6 # delay slot, check bus error
/* Wheee, local level one interrupt. */
move a0, sp
jal indy_local1_irqdispatch
nop
move a0, sp # delay slot
j ret_from_irq
nop
nop # delay slot
1:
beq a0, zero, 1f
nop
andi a0, s0, (CAUSEF_IP4 | CAUSEF_IP5) # delay slot
/* Wheee, an asynchronous bus error... */
move a0, sp
jal indy_buserror_irq
nop
move a0, sp # delay slot
j ret_from_irq
nop
nop # delay slot
1:
/* Here by mistake? This is possible, what can happen
* is that by the time we take the exception the IRQ
* pin goes low, so just leave if this is the case.
/* Here by mistake? It is possible, that by the time we take
* the exception the IRQ pin goes low, so just leave if this
* is the case.
*/
andi a0, s0, (CAUSEF_IP4 | CAUSEF_IP5)
beq a0, zero, 1f
nop # delay slot
/* Must be one of the 8254 timers... */
move a0, sp
jal indy_8254timer_irq
nop
move a0, sp # delay slot
1:
j ret_from_irq
nop
nop # delay slot
END(indyIRQ)
arch/mips/sgi-ip22/ip22-ksyms.c 0 → 100644
View file @ 2395133b
/*
* ip22-ksyms.c: IP22 specific exports
*/
#include <linux/module.h>
#include <asm/sgi/mc.h>
#include <asm/sgi/hpc3.h>
#include <asm/sgi/ioc.h>
#include <asm/sgi/ip22.h>
EXPORT_SYMBOL(sgimc);
EXPORT_SYMBOL(hpc3c0);
EXPORT_SYMBOL(hpc3c1);
EXPORT_SYMBOL(sgioc);
extern void (*indy_volume_button)(int);
EXPORT_SYMBOL(indy_volume_button);
EXPORT_SYMBOL(ip22_eeprom_read);
EXPORT_SYMBOL(ip22_nvram_read);
arch/mips/sgi-ip22/ip22-mc.c 0 → 100644
View file @ 2395133b
/*
* ip22-mc.c: Routines for manipulating SGI Memory Controller.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
* Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) - Indigo2 changes
* Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org)
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/ptrace.h>
#include <asm/sgialib.h>
#include <asm/sgi/mc.h>
#include <asm/sgi/hpc3.h>
#include <asm/sgi/ip22.h>
struct sgimc_regs *sgimc;
static inline unsigned long get_bank_addr(unsigned int memconfig)
{
return ((memconfig & SGIMC_MCONFIG_BASEADDR) <<
((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 24 : 22));
}
static inline unsigned long get_bank_size(unsigned int memconfig)
{
return ((memconfig & SGIMC_MCONFIG_RMASK) + 0x0100) <<
((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 16 : 14);
}
static inline unsigned int get_bank_config(int bank)
{
unsigned int res = bank > 1 ? sgimc->mconfig1 : sgimc->mconfig0;
return bank % 2 ? res & 0xffff : res >> 16;
}
struct mem {
unsigned long addr;
unsigned long size;
};
/*
* Detect installed memory, do some sanity checks and notify kernel about it
*/
static void probe_memory(void)
{
int i, j, found, cnt = 0;
struct mem bank[4];
struct mem space[2] = {{SGIMC_SEG0_BADDR, 0}, {SGIMC_SEG1_BADDR, 0}};
printk(KERN_INFO "MC: Probing memory configuration:\n");
for (i = 0; i < ARRAY_SIZE(bank); i++) {
unsigned int tmp = get_bank_config(i);
if (!(tmp & SGIMC_MCONFIG_BVALID))
continue;
bank[cnt].size = get_bank_size(tmp);
bank[cnt].addr = get_bank_addr(tmp);
printk(KERN_INFO " bank%d: %3ldM @ %08lx\n",
i, bank[cnt].size / 1024 / 1024, bank[cnt].addr);
cnt++;
}
/* And you thought bubble sort is dead algorithm... */
do {
unsigned long addr, size;
found = 0;
for (i = 1; i < cnt; i++)
if (bank[i-1].addr > bank[i].addr) {
addr = bank[i].addr;
size = bank[i].size;
bank[i].addr = bank[i-1].addr;
bank[i].size = bank[i-1].size;
bank[i-1].addr = addr;
bank[i-1].size = size;
found = 1;
}
} while (found);
/* Figure out how are memory banks mapped into spaces */
for (i = 0; i < cnt; i++) {
found = 0;
for (j = 0; j < ARRAY_SIZE(space) && !found; j++)
if (space[j].addr + space[j].size == bank[i].addr) {
space[j].size += bank[i].size;
found = 1;
}
/* There is either hole or overlapping memory */
if (!found)
printk(KERN_CRIT "MC: Memory configuration mismatch "
"(%08lx), expect Bus Error soon\n",
bank[i].addr);
}
for (i = 0; i < ARRAY_SIZE(space); i++)
if (space[i].size)
add_memory_region(space[i].addr, space[i].size,
BOOT_MEM_RAM);
}
void __init sgimc_init(void)
{
u32 tmp;
sgimc = (struct sgimc_regs *)(KSEG1 + SGIMC_BASE);
printk(KERN_INFO "MC: SGI memory controller Revision %d\n",
(int) sgimc->systemid & SGIMC_SYSID_MASKREV);
/* Place the MC into a known state. This must be done before
* interrupts are first enabled etc.
*/
/* Step 0: Make sure we turn off the watchdog in case it's
* still running (which might be the case after a
* soft reboot).
*/
tmp = sgimc->cpuctrl0;
tmp &= ~SGIMC_CCTRL0_WDOG;
sgimc->cpuctrl0 = tmp;
/* Step 1: The CPU/GIO error status registers will not latch
* up a new error status until the register has been
* cleared by the cpu. These status registers are
* cleared by writing any value to them.
*/
sgimc->cstat = sgimc->gstat = 0;
/* Step 2: Enable all parity checking in cpu control register
* zero.
*/
tmp = sgimc->cpuctrl0;
tmp |= (SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM |
SGIMC_CCTRL0_R4KNOCHKPARR);
sgimc->cpuctrl0 = tmp;
/* Step 3: Setup the MC write buffer depth, this is controlled
* in cpu control register 1 in the lower 4 bits.
*/
tmp = sgimc->cpuctrl1;
tmp &= ~0xf;
tmp |= 0xd;
sgimc->cpuctrl1 = tmp;
/* Step 4: Initialize the RPSS divider register to run as fast
* as it can correctly operate. The register is laid
* out as follows:
*
* ----------------------------------------
* | RESERVED | INCREMENT | DIVIDER |
* ----------------------------------------
* 31 16 15 8 7 0
*
* DIVIDER determines how often a 'tick' happens,
* INCREMENT determines by how the RPSS increment
* registers value increases at each 'tick'. Thus,
* for IP22 we get INCREMENT=1, DIVIDER=1 == 0x101
*/
sgimc->divider = 0x101;
/* Step 5: Initialize GIO64 arbitrator configuration register.
*
* NOTE: HPC init code in sgihpc_init() must run before us because
* we need to know Guiness vs. FullHouse and the board
* revision on this machine. You have been warned.
*/
/* First the basic invariants across all GIO64 implementations. */
tmp = SGIMC_GIOPAR_HPC64; /* All 1st HPC's interface at 64bits */
tmp |= SGIMC_GIOPAR_ONEBUS; /* Only one physical GIO bus exists */
if (ip22_is_fullhouse()) {
/* Fullhouse specific settings. */
if (SGIOC_SYSID_BOARDREV(sgioc->sysid) < 2) {
tmp |= SGIMC_GIOPAR_HPC264; /* 2nd HPC at 64bits */
tmp |= SGIMC_GIOPAR_PLINEEXP0; /* exp0 pipelines */
tmp |= SGIMC_GIOPAR_MASTEREXP1; /* exp1 masters */
tmp |= SGIMC_GIOPAR_RTIMEEXP0; /* exp0 is realtime */
} else {
tmp |= SGIMC_GIOPAR_HPC264; /* 2nd HPC 64bits */
tmp |= SGIMC_GIOPAR_PLINEEXP0; /* exp[01] pipelined */
tmp |= SGIMC_GIOPAR_PLINEEXP1;
tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA masters */
tmp |= SGIMC_GIOPAR_GFX64; /* GFX at 64 bits */
}
} else {
/* Guiness specific settings. */
tmp |= SGIMC_GIOPAR_EISA64; /* MC talks to EISA at 64bits */
tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA bus can act as master */
}
sgimc->giopar = tmp; /* poof */
probe_memory();
}
void __init prom_meminit(void) {}
void __init prom_free_prom_memory (void) {}
arch/mips/sgi-ip22/ip22-nvram.c 0 → 100644
View file @ 2395133b
/*
* ip22-nvram.c: NVRAM and serial EEPROM handling.
*
* Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org)
*/
#include <asm/sgi/hpc3.h>
#include <asm/sgi/ip22.h>
/* Control opcode for serial eeprom */
#define EEPROM_READ 0xc000 /* serial memory read */
#define EEPROM_WEN 0x9800 /* write enable before prog modes */
#define EEPROM_WRITE 0xa000 /* serial memory write */
#define EEPROM_WRALL 0x8800 /* write all registers */
#define EEPROM_WDS 0x8000 /* disable all programming */
#define EEPROM_PRREAD 0xc000 /* read protect register */
#define EEPROM_PREN 0x9800 /* enable protect register mode */
#define EEPROM_PRCLEAR 0xffff /* clear protect register */
#define EEPROM_PRWRITE 0xa000 /* write protect register */
#define EEPROM_PRDS 0x8000 /* disable protect register, forever */
#define EEPROM_EPROT 0x01 /* Protect register enable */
#define EEPROM_CSEL 0x02 /* Chip select */
#define EEPROM_ECLK 0x04 /* EEPROM clock */
#define EEPROM_DATO 0x08 /* Data out */
#define EEPROM_DATI 0x10 /* Data in */
/* We need to use this functions early... */
#define delay() ({ \
int x; \
for (x=0; x<100000; x++) __asm__ __volatile__(""); })
#define eeprom_cs_on(ptr) ({ \
*ptr &= ~EEPROM_DATO; \
*ptr &= ~EEPROM_ECLK; \
*ptr &= ~EEPROM_EPROT; \
delay(); \
*ptr |= EEPROM_CSEL; \
*ptr |= EEPROM_ECLK; })
#define eeprom_cs_off(ptr) ({ \
*ptr &= ~EEPROM_ECLK; \
*ptr &= ~EEPROM_CSEL; \
*ptr |= EEPROM_EPROT; \
*ptr |= EEPROM_ECLK; })
#define BITS_IN_COMMAND 11
/*
* clock in the nvram command and the register number. For the
* national semiconductor nv ram chip the op code is 3 bits and
* the address is 6/8 bits.
*/
static inline void eeprom_cmd(volatile unsigned int *ctrl, unsigned cmd,
unsigned reg)
{
unsigned short ser_cmd;
int i;
ser_cmd = cmd | (reg << (16 - BITS_IN_COMMAND));
for (i = 0; i < BITS_IN_COMMAND; i++) {
if (ser_cmd & (1<<15)) /* if high order bit set */
*ctrl |= EEPROM_DATO;
else
*ctrl &= ~EEPROM_DATO;
*ctrl &= ~EEPROM_ECLK;
*ctrl |= EEPROM_ECLK;
ser_cmd <<= 1;
}
*ctrl &= ~EEPROM_DATO; /* see data sheet timing diagram */
}
unsigned short ip22_eeprom_read(volatile unsigned int *ctrl, int reg)
{
unsigned short res = 0;
int i;
*ctrl &= ~EEPROM_EPROT;
eeprom_cs_on(ctrl);
eeprom_cmd(ctrl, EEPROM_READ, reg);
/* clock the data ouf of serial mem */
for (i = 0; i < 16; i++) {
*ctrl &= ~EEPROM_ECLK;
delay();
*ctrl |= EEPROM_ECLK;
delay();
res <<= 1;
if (*ctrl & EEPROM_DATI)
res |= 1;
}
eeprom_cs_off(ctrl);
return res;
}
/*
* Read specified register from main NVRAM
*/
unsigned short ip22_nvram_read(int reg)
{
if (ip22_is_fullhouse())
/* IP22 (Indigo2 aka FullHouse) stores env variables into
* 93CS56 Microwire Bus EEPROM 2048 Bit (128x16) */
return ip22_eeprom_read(&hpc3c0->eeprom, reg);
else {
unsigned short tmp;
/* IP24 (Indy aka Guiness) uses DS1386 8K version */
reg <<= 1;
tmp = hpc3c0->bbram[reg++] & 0xff;
return (tmp << 8) | (hpc3c0->bbram[reg] & 0xff);
}
}
arch/mips/sgi/kernel/reset.c → arch/mips/sgi-ip22/ip22-reset.c
View file @ 2395133b
......@@ -3,23 +3,28 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1997, 1998, 2001 by Ralf Baechle
* Copyright (C) 1997, 1998, 2001, 2003 by Ralf Baechle
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/notifier.h>
#include <linux/timer.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/reboot.h>
#include <asm/ds1286.h>
#include <asm/sgialib.h>
#include <asm/sgi/sgihpc.h>
#include <asm/sgi/sgint23.h>
#include <asm/sgi/ioc.h>
#include <asm/sgi/hpc3.h>
#include <asm/sgi/ip22.h>
/*
* Just powerdown if init hasn't done after POWERDOWN_TIMEOUT seconds.
* I'm not shure if this feature is a good idea, for now it's here just to
* I'm not sure if this feature is a good idea, for now it's here just to
* make the power button make behave just like under IRIX.
*/
#define POWERDOWN_TIMEOUT 120
......@@ -30,10 +35,11 @@
#define POWERDOWN_FREQ (HZ / 4)
#define PANIC_FREQ (HZ / 8)
static unsigned char sgi_volume;
static struct timer_list power_timer, blink_timer, debounce_timer, volume_timer;
static int shuting_down, has_paniced;
#define MACHINE_PANICED 1
#define MACHINE_SHUTTING_DOWN 2
static int machine_state = 0;
static void sgi_machine_restart(char *command) __attribute__((noreturn));
static void sgi_machine_halt(void) __attribute__((noreturn));
......@@ -42,35 +48,37 @@ static void sgi_machine_power_off(void) __attribute__((noreturn));
/* XXX How to pass the reboot command to the firmware??? */
static void sgi_machine_restart(char *command)
{
if (shuting_down)
if (machine_state & MACHINE_SHUTTING_DOWN)
sgi_machine_power_off();
prom_reboot();
ArcReboot();
}
static void sgi_machine_halt(void)
{
if (shuting_down)
if (machine_state & MACHINE_SHUTTING_DOWN)
sgi_machine_power_off();
ArcEnterInteractiveMode();
}
static void sgi_machine_power_off(void)
{
struct indy_clock *clock = (struct indy_clock *)INDY_CLOCK_REGS;
unsigned char val;
cli();
local_irq_disable();
clock->cmd |= 0x08; /* Disable watchdog */
clock->whsec = 0;
clock->wsec = 0;
/* Disable watchdog */
val = CMOS_READ(RTC_CMD);
CMOS_WRITE(val | RTC_WAM, RTC_CMD);
CMOS_WRITE(0, RTC_WSEC);
CMOS_WRITE(0, RTC_WHSEC);
while(1) {
hpc3mregs->panel=0xfe;
sgioc->panel = ~SGIOC_PANEL_POWERON;
/* Good bye cruel world ... */
/* If we're still running, we probably got sent an alarm
interrupt. Read the flag to clear it. */
clock->halarm;
val = CMOS_READ(RTC_HOURS_ALARM);
}
}
......@@ -82,8 +90,8 @@ static void power_timeout(unsigned long data)
static void blink_timeout(unsigned long data)
{
/* XXX fix this for fullhouse */
sgi_hpc_write1 ^= (HPC3_WRITE1_LC0OFF|HPC3_WRITE1_LC1OFF);
hpc3mregs->write1 = sgi_hpc_write1;
sgi_ioc_reset ^= (SGIOC_RESET_LC0OFF|SGIOC_RESET_LC1OFF);
sgioc->reset = sgi_ioc_reset;
mod_timer(&blink_timer, jiffies+data);
}
......@@ -91,32 +99,35 @@ static void blink_timeout(unsigned long data)
static void debounce(unsigned long data)
{
del_timer(&debounce_timer);
if (ioc_icontrol->istat1 & 2) { /* Interrupt still being sent. */
if (sgint->istat1 & SGINT_ISTAT1_PWR) {
/* Interrupt still being sent. */
debounce_timer.expires = jiffies + 5; /* 0.05s */
add_timer(&debounce_timer);
hpc3mregs->panel = 0xf3;
sgioc->panel = SGIOC_PANEL_POWERON | SGIOC_PANEL_POWERINTR |
SGIOC_PANEL_VOLDNINTR | SGIOC_PANEL_VOLDNHOLD |
SGIOC_PANEL_VOLUPINTR | SGIOC_PANEL_VOLUPHOLD;
return;
}
if (has_paniced)
prom_reboot();
if (machine_state & MACHINE_PANICED)
ArcReboot();
enable_irq(SGI_PANEL_IRQ);
}
static inline void power_button(void)
{
if (has_paniced)
if (machine_state & MACHINE_PANICED)
return;
if (shuting_down || kill_proc(1, SIGINT, 1)) {
if ((machine_state & MACHINE_SHUTTING_DOWN) || kill_proc(1,SIGINT,1)) {
/* No init process or button pressed twice. */
sgi_machine_power_off();
}
shuting_down = 1;
machine_state |= MACHINE_SHUTTING_DOWN;
blink_timer.data = POWERDOWN_FREQ;
blink_timeout(POWERDOWN_FREQ);
......@@ -126,60 +137,43 @@ static inline void power_button(void)
add_timer(&power_timer);
}
inline void sgi_volume_set(unsigned char volume)
{
sgi_volume = volume;
hpc3c0->pbus_extregs[2][0] = sgi_volume;
hpc3c0->pbus_extregs[2][1] = sgi_volume;
}
inline void sgi_volume_get(unsigned char *volume)
{
*volume = sgi_volume;
}
void (*indy_volume_button)(int) = NULL;
static inline void volume_up_button(unsigned long data)
{
del_timer(&volume_timer);
if (sgi_volume < 0xff)
sgi_volume++;
hpc3c0->pbus_extregs[2][0] = sgi_volume;
hpc3c0->pbus_extregs[2][1] = sgi_volume;
if (indy_volume_button)
indy_volume_button(1);
if (ioc_icontrol->istat1 & 2) {
if (sgint->istat1 & SGINT_ISTAT1_PWR) {
volume_timer.expires = jiffies + 1;
add_timer(&volume_timer);
}
}
static inline void volume_down_button(unsigned long data)
{
del_timer(&volume_timer);
if (sgi_volume > 0)
sgi_volume--;
hpc3c0->pbus_extregs[2][0] = sgi_volume;
hpc3c0->pbus_extregs[2][1] = sgi_volume;
if (indy_volume_button)
indy_volume_button(-1);
if (ioc_icontrol->istat1 & 2) {
if (sgint->istat1 & SGINT_ISTAT1_PWR) {
volume_timer.expires = jiffies + 1;
add_timer(&volume_timer);
}
}
static void panel_int(int irq, void *dev_id, struct pt_regs *regs)
static irqreturn_t panel_int(int irq, void *dev_id, struct pt_regs *regs)
{
unsigned int buttons;
buttons = hpc3mregs->panel;
hpc3mregs->panel = 3; /* power_interrupt | power_supply_on */
buttons = sgioc->panel;
sgioc->panel = SGIOC_PANEL_POWERON | SGIOC_PANEL_POWERINTR;
if (ioc_icontrol->istat1 & 2) { /* Wait until interrupt goes away */
if (sgint->istat1 & SGINT_ISTAT1_PWR) {
/* Wait until interrupt goes away */
disable_irq(SGI_PANEL_IRQ);
init_timer(&debounce_timer);
debounce_timer.function = debounce;
......@@ -187,28 +181,42 @@ static void panel_int(int irq, void *dev_id, struct pt_regs *regs)
add_timer(&debounce_timer);
}
if (!(buttons & 2)) /* Power button was pressed */
/* Power button was pressed
*
* ioc.ps page 22: "The Panel Register is called Power Control by Full
* House. Only lowest 2 bits are used. Guiness uses upper four bits
* for volume control". This is not true, all bits are pulled high
* on fullhouse
*/
if (ip22_is_fullhouse() || !(buttons & SGIOC_PANEL_POWERINTR)) {
power_button();
if (!(buttons & 0x40)) { /* Volume up button was pressed */
return IRQ_HANDLED;
}
/* TODO: mute/unmute */
/* Volume up button was pressed */
if (!(buttons & SGIOC_PANEL_VOLUPINTR)) {
init_timer(&volume_timer);
volume_timer.function = volume_up_button;
volume_timer.expires = jiffies + 1;
add_timer(&volume_timer);
}
if (!(buttons & 0x10)) { /* Volume down button was pressed */
/* Volume down button was pressed */
if (!(buttons & SGIOC_PANEL_VOLDNINTR)) {
init_timer(&volume_timer);
volume_timer.function = volume_down_button;
volume_timer.expires = jiffies + 1;
add_timer(&volume_timer);
}
return IRQ_HANDLED;
}
static int panic_event(struct notifier_block *this, unsigned long event,
void *ptr)
{
if (has_paniced)
if (machine_state & MACHINE_PANICED)
return NOTIFY_DONE;
has_paniced = 1;
machine_state |= MACHINE_PANICED;
blink_timer.data = PANIC_FREQ;
blink_timeout(PANIC_FREQ);
......@@ -217,19 +225,11 @@ static int panic_event(struct notifier_block *this, unsigned long event,
}
static struct notifier_block panic_block = {
panic_event,
NULL,
0
.notifier_call = panic_event,
};
void indy_reboot_setup(void)
static int __init reboot_setup(void)
{
static int setup_done;
if (setup_done)
return;
setup_done = 1;
_machine_restart = sgi_machine_restart;
_machine_halt = sgi_machine_halt;
_machine_power_off = sgi_machine_power_off;
......@@ -238,4 +238,8 @@ void indy_reboot_setup(void)
init_timer(&blink_timer);
blink_timer.function = blink_timeout;
notifier_chain_register(&panic_notifier_list, &panic_block);
return 0;
}
subsys_initcall(reboot_setup);
arch/mips64/sgi-ip22/ip22-rtc.c → arch/mips/sgi-ip22/ip22-rtc.c
View file @ 2395133b
......@@ -7,30 +7,26 @@
*
* Copyright (C) 1998, 2001 by Ralf Baechle
*/
#include <linux/mc146818rtc.h>
#include <asm/sgi/sgihpc.h>
#include <asm/ds1286.h>
#include <asm/sgi/hpc3.h>
static unsigned char indy_rtc_read_data(unsigned long addr)
static unsigned char ip22_rtc_read_data(unsigned long addr)
{
volatile unsigned int *rtcregs = (void *)INDY_CLOCK_REGS;
return rtcregs[addr];
return hpc3c0->rtcregs[addr];
}
static void indy_rtc_write_data(unsigned char data, unsigned long addr)
static void ip22_rtc_write_data(unsigned char data, unsigned long addr)
{
volatile unsigned int *rtcregs = (void *)INDY_CLOCK_REGS;
rtcregs[addr] = data;
hpc3c0->rtcregs[addr] = data;
}
static int indy_rtc_bcd_mode(void)
static int ip22_rtc_bcd_mode(void)
{
return 0;
}
struct rtc_ops indy_rtc_ops = {
&indy_rtc_read_data,
&indy_rtc_write_data,
&indy_rtc_bcd_mode
struct rtc_ops ip22_rtc_ops = {
&ip22_rtc_read_data,
&ip22_rtc_write_data,
&ip22_rtc_bcd_mode
};
arch/mips/sgi-ip22/ip22-setup.c 0 → 100644
View file @ 2395133b
/*
* ip22-setup.c: SGI specific setup, including init of the feature struct.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
* Copyright (C) 1997, 1998 Ralf Baechle (ralf@gnu.org)
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/kdev_t.h>
#include <linux/types.h>
#include <linux/console.h>
#include <linux/sched.h>
#include <linux/tty.h>
#include <asm/addrspace.h>
#include <asm/bcache.h>
#include <asm/bootinfo.h>
#include <asm/irq.h>
#include <asm/reboot.h>
#include <asm/ds1286.h>
#include <asm/time.h>
#include <asm/gdb-stub.h>
#include <asm/io.h>
#include <asm/traps.h>
#include <asm/sgialib.h>
#include <asm/sgi/mc.h>
#include <asm/sgi/hpc3.h>
#include <asm/sgi/ip22.h>
#ifdef CONFIG_KGDB
extern void rs_kgdb_hook(int);
extern void breakpoint(void);
static int remote_debug = 0;
#endif
#if defined(CONFIG_IP22_SERIAL_CONSOLE) || defined(CONFIG_ARC_CONSOLE)
extern void console_setup(char *);
#endif
extern struct rtc_ops ip22_rtc_ops;
#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
unsigned long sgi_gfxaddr;
/*
* Stop-A is originally a Sun thing that isn't standard on IP22 so to avoid
* accidents it's disabled by default on IP22.
*
* FIXME: provide a mechanism to change the value of stop_a_enabled.
*/
int serial_console;
int stop_a_enabled;
void ip22_do_break(void)
{
if (!stop_a_enabled)
return;
printk("\n");
ArcEnterInteractiveMode();
}
extern void ip22_be_init(void) __init;
extern void ip22_time_init(void) __init;
void __init ip22_setup(void)
{
char *ctype;
#ifdef CONFIG_KGDB
char *kgdb_ttyd;
#endif
board_be_init = ip22_be_init;
ip22_time_init();
/* Init the INDY HPC I/O controller. Need to call this before
* fucking with the memory controller because it needs to know the
* boardID and whether this is a Guiness or a FullHouse machine.
*/
sgihpc_init();
/* Init INDY memory controller. */
sgimc_init();
#ifdef CONFIG_BOARD_SCACHE
/* Now enable boardcaches, if any. */
indy_sc_init();
#endif
#ifdef CONFIG_VT
conswitchp = NULL;
#endif
/* Set the IO space to some sane value */
set_io_port_base (KSEG1ADDR (0x00080000));
/* ARCS console environment variable is set to "g?" for
* graphics console, it is set to "d" for the first serial
* line and "d2" for the second serial line.
*/
ctype = ArcGetEnvironmentVariable("console");
if (ctype && *ctype == 'd') {
#ifdef CONFIG_IP22_SERIAL_CONSOLE
if (*(ctype + 1) == '2')
console_setup("ttyS1");
else
console_setup("ttyS0");
#endif
}
#ifdef CONFIG_ARC_CONSOLE
else if (!ctype || *ctype != 'g') {
/* Use ARC if we don't want serial ('d') or Newport ('g'). */
prom_flags |= PROM_FLAG_USE_AS_CONSOLE;
console_setup("arc");
}
#endif
#ifdef CONFIG_KGDB
kgdb_ttyd = prom_getcmdline();
if ((kgdb_ttyd = strstr(kgdb_ttyd, "kgdb=ttyd")) != NULL) {
int line;
kgdb_ttyd += strlen("kgdb=ttyd");
if (*kgdb_ttyd != '1' && *kgdb_ttyd != '2')
printk(KERN_INFO "KGDB: Uknown serial line /dev/ttyd%c"
", falling back to /dev/ttyd1\n", *kgdb_ttyd);
line = *kgdb_ttyd == '2' ? 0 : 1;
printk(KERN_INFO "KGDB: Using serial line /dev/ttyd%d for "
"session\n", line ? 1 : 2);
rs_kgdb_hook(line);
printk(KERN_INFO "KGDB: Using serial line /dev/ttyd%d for "
"session, please connect your debugger\n", line ? 1:2);
remote_debug = 1;
/* Breakpoints and stuff are in sgi_irq_setup() */
}
#endif
#ifdef CONFIG_VT
#ifdef CONFIG_SGI_NEWPORT_CONSOLE
if (ctype && *ctype == 'g'){
unsigned long *gfxinfo;
long (*__vec)(void) =
(void *) *(long *)(long)((PROMBLOCK)->pvector + 0x20);
gfxinfo = (unsigned long *)__vec();
sgi_gfxaddr = ((gfxinfo[1] >= 0xa0000000
&& gfxinfo[1] <= 0xc0000000)
? gfxinfo[1] - 0xa0000000 : 0);
/* newport addresses? */
if (sgi_gfxaddr == 0x1f0f0000 || sgi_gfxaddr == 0x1f4f0000) {
conswitchp = &newport_con;
screen_info = (struct screen_info) {
0, 0, /* orig-x, orig-y */
0, /* unused */
0, /* orig_video_page */
0, /* orig_video_mode */
160, /* orig_video_cols */
0, 0, 0, /* unused, ega_bx, unused */
64, /* orig_video_lines */
0, /* orig_video_isVGA */
16 /* orig_video_points */
};
}
}
#endif
#ifdef CONFIG_DUMMY_CONSOLE
/* Either if newport console wasn't used or failed to initialize. */
#ifdef CONFIG_SGI_NEWPORT_CONSOLE
if(conswitchp != &newport_con)
#endif
conswitchp = &dummy_con;
#endif
#endif
rtc_ops = &ip22_rtc_ops;
#ifdef CONFIG_PSMOUSE
aux_device_present = 0xaa;
#endif
}
arch/mips/sgi-ip22/ip22-time.c 0 → 100644
View file @ 2395133b
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Time operations for IP22 machines. Original code may come from
* Ralf Baechle or David S. Miller (sorry guys, i'm really not sure)
*
* Copyright (C) 2001 by Ladislav Michl
*/
#include <linux/bcd.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/time.h>
#include <asm/cpu.h>
#include <asm/mipsregs.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/time.h>
#include <asm/ds1286.h>
#include <asm/sgialib.h>
#include <asm/sgi/ioc.h>
#include <asm/sgi/hpc3.h>
#include <asm/sgi/ip22.h>
/*
* note that mktime uses month from 1 to 12 while to_tm
* uses 0 to 11.
*/
static unsigned long indy_rtc_get_time(void)
{
unsigned int yrs, mon, day, hrs, min, sec;
unsigned int save_control;
save_control = hpc3c0->rtcregs[RTC_CMD] & 0xff;
hpc3c0->rtcregs[RTC_CMD] = save_control | RTC_TE;
sec = BCD2BIN(hpc3c0->rtcregs[RTC_SECONDS] & 0xff);
min = BCD2BIN(hpc3c0->rtcregs[RTC_MINUTES] & 0xff);
hrs = BCD2BIN(hpc3c0->rtcregs[RTC_HOURS] & 0x1f);
day = BCD2BIN(hpc3c0->rtcregs[RTC_DATE] & 0xff);
mon = BCD2BIN(hpc3c0->rtcregs[RTC_MONTH] & 0x1f);
yrs = BCD2BIN(hpc3c0->rtcregs[RTC_YEAR] & 0xff);
hpc3c0->rtcregs[RTC_CMD] = save_control;
if (yrs < 45)
yrs += 30;
if ((yrs += 40) < 70)
yrs += 100;
return mktime(yrs + 1900, mon, day, hrs, min, sec);
}
static int indy_rtc_set_time(unsigned long tim)
{
struct rtc_time tm;
unsigned int save_control;
to_tm(tim, &tm);
tm.tm_mon += 1; /* tm_mon starts at zero */
tm.tm_year -= 1940;
if (tm.tm_year >= 100)
tm.tm_year -= 100;
save_control = hpc3c0->rtcregs[RTC_CMD] & 0xff;
hpc3c0->rtcregs[RTC_CMD] = save_control | RTC_TE;
hpc3c0->rtcregs[RTC_YEAR] = BIN2BCD(tm.tm_sec);
hpc3c0->rtcregs[RTC_MONTH] = BIN2BCD(tm.tm_mon);
hpc3c0->rtcregs[RTC_DATE] = BIN2BCD(tm.tm_mday);
hpc3c0->rtcregs[RTC_HOURS] = BIN2BCD(tm.tm_hour);
hpc3c0->rtcregs[RTC_MINUTES] = BIN2BCD(tm.tm_min);
hpc3c0->rtcregs[RTC_SECONDS] = BIN2BCD(tm.tm_sec);
hpc3c0->rtcregs[RTC_HUNDREDTH_SECOND] = 0;
hpc3c0->rtcregs[RTC_CMD] = save_control;
return 0;
}
static unsigned long dosample(void)
{
u32 ct0, ct1;
volatile u8 msb, lsb;
/* Start the counter. */
sgint->tcword = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL |
SGINT_TCWORD_MRGEN);
sgint->tcnt2 = (SGINT_TCSAMP_COUNTER & 0xff);
sgint->tcnt2 = (SGINT_TCSAMP_COUNTER >> 8);
/* Get initial counter invariant */
ct0 = read_c0_count();
/* Latch and spin until top byte of counter2 is zero */
do {
sgint->tcword = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CLAT);
lsb = sgint->tcnt2;
msb = sgint->tcnt2;
ct1 = read_c0_count();
} while (msb);
/* Stop the counter. */
sgint->tcword = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL |
SGINT_TCWORD_MSWST);
/*
* Return the difference, this is how far the r4k counter increments
* for every 1/HZ seconds. We round off the nearest 1 MHz of master
* clock (= 1000000 / 100 / 2 = 5000 count).
*/
return ((ct1 - ct0) / 5000) * 5000;
}
/*
* Here we need to calibrate the cycle counter to at least be close.
*/
static __init void indy_time_init(void)
{
unsigned long r4k_ticks[3];
unsigned long r4k_tick;
/*
* Figure out the r4k offset, the algorithm is very simple
* and works in _all_ cases as long as the 8254 counter
* register itself works ok (as an interrupt driving timer
* it does not because of bug, this is why we are using
* the onchip r4k counter/compare register to serve this
* purpose, but for r4k_offset calculation it will work
* ok for us). There are other very complicated ways
* of performing this calculation but this one works just
* fine so I am not going to futz around. ;-)
*/
printk(KERN_INFO "Calibrating system timer... ");
dosample(); /* Prime cache. */
dosample(); /* Prime cache. */
/* Zero is NOT an option. */
do {
r4k_ticks[0] = dosample();
} while (!r4k_ticks[0]);
do {
r4k_ticks[1] = dosample();
} while (!r4k_ticks[1]);
if (r4k_ticks[0] != r4k_ticks[1]) {
printk("warning: timer counts differ, retrying... ");
r4k_ticks[2] = dosample();
if (r4k_ticks[2] == r4k_ticks[0]
|| r4k_ticks[2] == r4k_ticks[1])
r4k_tick = r4k_ticks[2];
else {
printk("disagreement, using average... ");
r4k_tick = (r4k_ticks[0] + r4k_ticks[1]
+ r4k_ticks[2]) / 3;
}
} else
r4k_tick = r4k_ticks[0];
printk("%d [%d.%02d MHz CPU]\n", (int) r4k_tick,
(int) (r4k_tick / 5000), (int) (r4k_tick % 5000) / 50);
mips_counter_frequency = r4k_tick * HZ;
}
/* Generic SGI handler for (spurious) 8254 interrupts */
void indy_8254timer_irq(struct pt_regs *regs)
{
int cpu = smp_processor_id();
int irq = SGI_8254_0_IRQ;
ULONG cnt;
char c;
irq_enter();
kstat_cpu(cpu).irqs[irq]++;
printk(KERN_ALERT "Oops, got 8254 interrupt.\n");
ArcRead(0, &c, 1, &cnt);
ArcEnterInteractiveMode();
irq_exit();
}
void indy_r4k_timer_interrupt(struct pt_regs *regs)
{
int cpu = smp_processor_id();
int irq = SGI_TIMER_IRQ;
irq_enter();
kstat_cpu(cpu).irqs[irq]++;
timer_interrupt(irq, NULL, regs);
irq_exit();
if (softirq_pending(cpu))
do_softirq();
}
extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
static void indy_timer_setup(struct irqaction *irq)
{
/* over-write the handler, we use our own way */
irq->handler = no_action;
/* setup irqaction */
setup_irq(SGI_TIMER_IRQ, irq);
}
void __init ip22_time_init(void)
{
/* setup hookup functions */
rtc_get_time = indy_rtc_get_time;
rtc_set_time = indy_rtc_set_time;
board_time_init = indy_time_init;
board_timer_setup = indy_timer_setup;
}
arch/mips/sgi/kernel/indyIRQ.S deleted 100644 → 0
View file @ f19e2d9e
/*
* indyIRQ.S: Interrupt exception dispatch code for FullHouse and
* Guiness.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
*/
#include <asm/asm.h>
#include <asm/mipsregs.h>
#include <asm/regdef.h>
#include <asm/stackframe.h>
/* A lot of complication here is taken away because:
*
* 1) We handle one interrupt and return, sitting in a loop
* and moving across all the pending IRQ bits in the cause
* register is _NOT_ the answer, the common case is one
* pending IRQ so optimize in that direction.
*
* 2) We need not check against bits in the status register
* IRQ mask, that would make this routine slow as hell.
*
* 3) Linux only thinks in terms of all IRQs on or all IRQs
* off, nothing in between like BSD spl() brain-damage.
*
* Furthermore, the IRQs on the INDY look basically (barring
* software IRQs which we don't use at all) like:
*
* MIPS IRQ Source
* -------- ------
* 0 Software (ignored)
* 1 Software (ignored)
* 2 Local IRQ level zero
* 3 Local IRQ level one
* 4 8254 Timer zero
* 5 8254 Timer one
* 6 Bus Error
* 7 R4k timer (what we use)
*
* We handle the IRQ according to _our_ priority which is:
*
* Highest ---- R4k Timer
* Local IRQ zero
* Local IRQ one
* Bus Error
* 8254 Timer zero
* Lowest ---- 8254 Timer one
*
* then we just return, if multiple IRQs are pending then
* we will just take another exception, big deal.
*/
.text
.set noreorder
.set noat
.align 5
NESTED(indyIRQ, PT_SIZE, sp)
SAVE_ALL
CLI
.set at
mfc0 s0, CP0_CAUSE # get irq mask
/* First we check for r4k counter/timer IRQ. */
andi a0, s0, CAUSEF_IP7
beq a0, zero, 1f
andi a0, s0, CAUSEF_IP2 # delay slot, check local level zero
/* Wheee, a timer interrupt. */
move a0, sp
jal indy_r4k_timer_interrupt
nop # delay slot
j ret_from_irq
nop # delay slot
1:
beq a0, zero, 1f
andi a0, s0, CAUSEF_IP3 # delay slot, check local level one
/* Wheee, local level zero interrupt. */
jal indy_local0_irqdispatch
move a0, sp # delay slot
j ret_from_irq
nop # delay slot
1:
beq a0, zero, 1f
andi a0, s0, CAUSEF_IP6 # delay slot, check bus error
/* Wheee, local level one interrupt. */
move a0, sp
jal indy_local1_irqdispatch
nop
j ret_from_irq
nop
1:
beq a0, zero, 1f
nop
/* Wheee, an asynchronous bus error... */
move a0, sp
jal indy_buserror_irq
nop
j ret_from_irq
nop
1:
/* Here by mistake? This is possible, what can happen
* is that by the time we take the exception the IRQ
* pin goes low, so just leave if this is the case.
*/
andi a0, s0, (CAUSEF_IP4 | CAUSEF_IP5)
beq a0, zero, 1f
/* Must be one of the 8254 timers... */
move a0, sp
jal indy_8254timer_irq
nop
1:
j ret_from_irq
nop
END(indyIRQ)
arch/mips/sgi/kernel/indy_hpc.c deleted 100644 → 0
View file @ f19e2d9e
/* $Id: indy_hpc.c,v 1.9 1999/12/04 03:59:00 ralf Exp $
*
* indy_hpc.c: Routines for generic manipulation of the HPC controllers.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
* Copyright (C) 1998 Ralf Baechle
*/
#include <linux/init.h>
#include <linux/types.h>
#include <asm/addrspace.h>
#include <asm/sgi/sgihpc.h>
#include <asm/sgi/sgint23.h>
#include <asm/sgialib.h>
#include <asm/bootinfo.h>
/* #define DEBUG_SGIHPC */
struct hpc3_regs *hpc3c0, *hpc3c1;
struct hpc3_miscregs *hpc3mregs;
/* We need software copies of these because they are write only. */
unsigned int sgi_hpc_write1, sgi_hpc_write2;
/* Machine specific identifier knobs. */
int sgi_has_ioc2 = 0;
int sgi_guiness = 0;
int sgi_boardid;
void __init sgihpc_init(void)
{
unsigned long sid, crev, brev;
hpc3c0 = (struct hpc3_regs *) (KSEG1 + HPC3_CHIP0_PBASE);
hpc3c1 = (struct hpc3_regs *) (KSEG1 + HPC3_CHIP1_PBASE);
hpc3mregs = (struct hpc3_miscregs *) (KSEG1 + HPC3_MREGS_PBASE);
sid = hpc3mregs->sysid;
sid &= 0xff;
crev = (sid & 0xe0) >> 5;
brev = (sid & 0x1e) >> 1;
#ifdef DEBUG_SGIHPC
prom_printf("sgihpc_init: crev<%2x> brev<%2x>\n", crev, brev);
prom_printf("sgihpc_init: ");
#endif
/* This test works now thanks to William J. Earl */
if ((sid & 1) == 0 ) {
#ifdef DEBUG_SGIHPC
prom_printf("GUINESS ");
#endif
sgi_guiness = 1;
mips_machtype = MACH_SGI_INDY;
} else {
#ifdef DEBUG_SGIHPC
prom_printf("FULLHOUSE ");
#endif
mips_machtype = MACH_SGI_INDIGO2;
sgi_guiness = 0;
}
sgi_boardid = brev;
#ifdef DEBUG_SGIHPC
prom_printf("sgi_boardid<%d> ", sgi_boardid);
#endif
if(crev == 1) {
if((sid & 1) || (brev >= 2)) {
#ifdef DEBUG_SGIHPC
prom_printf("IOC2 ");
#endif
sgi_has_ioc2 = 1;
} else {
#ifdef DEBUG_SGIHPC
prom_printf("IOC1 revision 1 ");
#endif
}
} else {
#ifdef DEBUG_SGIHPC
prom_printf("IOC1 revision 0 ");
#endif
}
#ifdef DEBUG_SGIHPC
prom_printf("\n");
#endif
sgi_hpc_write1 = (HPC3_WRITE1_PRESET |
HPC3_WRITE1_KMRESET |
HPC3_WRITE1_ERESET |
HPC3_WRITE1_LC0OFF);
sgi_hpc_write2 = (HPC3_WRITE2_EASEL |
HPC3_WRITE2_NTHRESH |
HPC3_WRITE2_TPSPEED |
HPC3_WRITE2_EPSEL |
HPC3_WRITE2_U0AMODE |
HPC3_WRITE2_U1AMODE);
if(!sgi_guiness)
sgi_hpc_write1 |= HPC3_WRITE1_GRESET;
hpc3mregs->write1 = sgi_hpc_write1;
hpc3mregs->write2 = sgi_hpc_write2;
hpc3c0->pbus_piocfgs[0][6] |= HPC3_PIOPCFG_HW;
}
arch/mips/sgi/kernel/indy_mc.c deleted 100644 → 0
View file @ f19e2d9e
/*
* indy_mc.c: Routines for manipulating the INDY memory controller.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
* Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) - Indigo2 changes
*
* $Id: indy_mc.c,v 1.7 1999/12/04 03:59:00 ralf Exp $
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <asm/addrspace.h>
#include <asm/ptrace.h>
#include <asm/sgi/sgimc.h>
#include <asm/sgi/sgihpc.h>
#include <asm/sgialib.h>
/* #define DEBUG_SGIMC */
struct sgimc_misc_ctrl *mcmisc_regs;
u32 *rpsscounter;
struct sgimc_dma_ctrl *dmactrlregs;
static inline char *mconfig_string(unsigned long val)
{
switch(val & SGIMC_MCONFIG_RMASK) {
case SGIMC_MCONFIG_FOURMB:
return "4MB";
case SGIMC_MCONFIG_EIGHTMB:
return "8MB";
case SGIMC_MCONFIG_SXTEENMB:
return "16MB";
case SGIMC_MCONFIG_TTWOMB:
return "32MB";
case SGIMC_MCONFIG_SFOURMB:
return "64MB";
case SGIMC_MCONFIG_OTEIGHTMB:
return "128MB";
default:
return "wheee, unknown";
};
}
void __init sgimc_init(void)
{
unsigned long tmpreg;
mcmisc_regs = (struct sgimc_misc_ctrl *)(KSEG1+0x1fa00000);
rpsscounter = (unsigned int *) (KSEG1 + 0x1fa01004);
dmactrlregs = (struct sgimc_dma_ctrl *) (KSEG1+0x1fa02000);
printk("MC: SGI memory controller Revision %d\n",
(int) mcmisc_regs->systemid & SGIMC_SYSID_MASKREV);
#if 0 /* XXX Until I figure out what this bit really indicates XXX */
/* XXX Is this systemid bit reliable? */
if(mcmisc_regs->systemid & SGIMC_SYSID_EPRESENT) {
EISA_bus = 1;
printk("with EISA\n");
} else {
EISA_bus = 0;
printk("no EISA\n");
}
#endif
#ifdef DEBUG_SGIMC
prom_printf("sgimc_init: memconfig0<%s> mconfig1<%s>\n",
mconfig_string(mcmisc_regs->mconfig0),
mconfig_string(mcmisc_regs->mconfig1));
prom_printf("mcdump: cpuctrl0<%08lx> cpuctrl1<%08lx>\n",
mcmisc_regs->cpuctrl0, mcmisc_regs->cpuctrl1);
prom_printf("mcdump: divider<%08lx>, gioparm<%04x>\n",
mcmisc_regs->divider, mcmisc_regs->gioparm);
#endif
/* Place the MC into a known state. This must be done before
* interrupts are first enabled etc.
*/
/* Step 1: The CPU/GIO error status registers will not latch
* up a new error status until the register has been
* cleared by the cpu. These status registers are
* cleared by writing any value to them.
*/
mcmisc_regs->cstat = mcmisc_regs->gstat = 0;
/* Step 2: Enable all parity checking in cpu control register
* zero.
*/
tmpreg = mcmisc_regs->cpuctrl0;
tmpreg |= (SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM |
SGIMC_CCTRL0_R4KNOCHKPARR);
mcmisc_regs->cpuctrl0 = tmpreg;
/* Step 3: Setup the MC write buffer depth, this is controlled
* in cpu control register 1 in the lower 4 bits.
*/
tmpreg = mcmisc_regs->cpuctrl1;
tmpreg &= ~0xf;
tmpreg |= 0xd;
mcmisc_regs->cpuctrl1 = tmpreg;
/* Step 4: Initialize the RPSS divider register to run as fast
* as it can correctly operate. The register is laid
* out as follows:
*
* ----------------------------------------
* | RESERVED | INCREMENT | DIVIDER |
* ----------------------------------------
* 31 16 15 8 7 0
*
* DIVIDER determines how often a 'tick' happens,
* INCREMENT determines by how the RPSS increment
* registers value increases at each 'tick'. Thus,
* for IP22 we get INCREMENT=1, DIVIDER=1 == 0x101
*/
mcmisc_regs->divider = 0x101;
/* Step 5: Initialize GIO64 arbitrator configuration register.
*
* NOTE: If you dork with startup code the HPC init code in
* sgihpc_init() must run before us because of how we
* need to know Guiness vs. FullHouse and the board
* revision on this machine. You have been warned.
*/
/* First the basic invariants across all gio64 implementations. */
tmpreg = SGIMC_GIOPARM_HPC64; /* All 1st HPC's interface at 64bits. */
tmpreg |= SGIMC_GIOPARM_ONEBUS; /* Only one physical GIO bus exists. */
if(sgi_guiness) {
/* Guiness specific settings. */
tmpreg |= SGIMC_GIOPARM_EISA64; /* MC talks to EISA at 64bits */
tmpreg |= SGIMC_GIOPARM_MASTEREISA; /* EISA bus can act as master */
} else {
/* Fullhouse specific settings. */
if(sgi_boardid < 2) {
tmpreg |= SGIMC_GIOPARM_HPC264; /* 2nd HPC at 64bits */
tmpreg |= SGIMC_GIOPARM_PLINEEXP0; /* exp0 pipelines */
tmpreg |= SGIMC_GIOPARM_MASTEREXP1;/* exp1 masters */
tmpreg |= SGIMC_GIOPARM_RTIMEEXP0; /* exp0 is realtime */
} else {
tmpreg |= SGIMC_GIOPARM_HPC264; /* 2nd HPC 64bits */
tmpreg |= SGIMC_GIOPARM_PLINEEXP0; /* exp[01] pipelined */
tmpreg |= SGIMC_GIOPARM_PLINEEXP1;
tmpreg |= SGIMC_GIOPARM_MASTEREISA;/* EISA masters */
/* someone forgot this poor little guy... */
tmpreg |= SGIMC_GIOPARM_GFX64; /* GFX at 64 bits */
}
}
mcmisc_regs->gioparm = tmpreg; /* poof */
}
arch/mips/sgi/kernel/indy_rtc.c deleted 100644 → 0
View file @ f19e2d9e
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* RTC routines for Indy style attached Dallas chip.
*
* Copyright (C) 1998, 2001 by Ralf Baechle
*/
#include <linux/mc146818rtc.h>
#include <asm/sgi/sgihpc.h>
static unsigned char indy_rtc_read_data(unsigned long addr)
{
volatile unsigned int *rtcregs = (void *)INDY_CLOCK_REGS;
return rtcregs[addr];
}
static void indy_rtc_write_data(unsigned char data, unsigned long addr)
{
volatile unsigned int *rtcregs = (void *)INDY_CLOCK_REGS;
rtcregs[addr] = data;
}
static int indy_rtc_bcd_mode(void)
{
return 0;
}
struct rtc_ops indy_rtc_ops = {
&indy_rtc_read_data,
&indy_rtc_write_data,
&indy_rtc_bcd_mode
};
arch/mips/sgi/kernel/indy_sc.c deleted 100644 → 0
View file @ f19e2d9e
/*
* indy_sc.c: Indy cache management functions.
*
* Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org),
* derived from r4xx0.c by David S. Miller (dm@engr.sgi.com).
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <asm/bcache.h>
#include <asm/sgi/sgi.h>
#include <asm/sgi/sgimc.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/bootinfo.h>
#include <asm/sgialib.h>
#include <asm/mmu_context.h>
/* Secondary cache size in bytes, if present. */
static unsigned long scache_size;
#undef DEBUG_CACHE
#define SC_SIZE 0x00080000
#define SC_LINE 32
#define CI_MASK (SC_SIZE - SC_LINE)
#define SC_INDEX(n) ((n) & CI_MASK)
static inline void indy_sc_wipe(unsigned long first, unsigned long last)
{
unsigned long tmp;
__asm__ __volatile__(
".set\tnoreorder\t\t\t# indy_sc_wipe\n\t"
".set\tmips3\n\t"
".set\tnoat\n\t"
"mfc0\t%2, $12\n\t"
"li\t$1, 0x80\t\t\t# Go 64 bit\n\t"
"mtc0\t$1, $12\n\t"
"dli\t$1, 0x9000000080000000\n\t"
"or\t%0, $1\t\t\t# first line to flush\n\t"
"or\t%1, $1\t\t\t# last line to flush\n\t"
".set\tat\n\t"
"1:\tsw\t$0, 0(%0)\n\t"
"bne\t%0, %1, 1b\n\t"
"daddu\t%0, 32\n\t"
"mtc0\t%2, $12\t\t\t# Back to 32 bit\n\t"
"nop; nop; nop; nop;\n\t"
".set\tmips0\n\t"
".set\treorder"
: "=r" (first), "=r" (last), "=&r" (tmp)
: "0" (first), "1" (last)
: "$1");
}
static void indy_sc_wback_invalidate(unsigned long addr, unsigned long size)
{
unsigned long first_line, last_line;
unsigned int flags;
#ifdef DEBUG_CACHE
printk("indy_sc_wback_invalidate[%08lx,%08lx]", addr, size);
#endif
if (!size)
return;
/* Which lines to flush? */
first_line = SC_INDEX(addr);
last_line = SC_INDEX(addr + size - 1);
local_irq_save(flags);
if (first_line <= last_line) {
indy_sc_wipe(first_line, last_line);
goto out;
}
indy_sc_wipe(first_line, SC_SIZE - SC_LINE);
indy_sc_wipe(0, last_line);
out:
local_irq_restore(flags);
}
static void indy_sc_enable(void)
{
unsigned long addr, tmp1, tmp2;
/* This is really cool... */
#ifdef DEBUG_CACHE
printk("Enabling R4600 SCACHE\n");
#endif
__asm__ __volatile__(
".set\tpush\n\t"
".set\tnoreorder\n\t"
".set\tmips3\n\t"
"mfc0\t%2, $12\n\t"
"nop; nop; nop; nop;\n\t"
"li\t%1, 0x80\n\t"
"mtc0\t%1, $12\n\t"
"nop; nop; nop; nop;\n\t"
"li\t%0, 0x1\n\t"
"dsll\t%0, 31\n\t"
"lui\t%1, 0x9000\n\t"
"dsll32\t%1, 0\n\t"
"or\t%0, %1, %0\n\t"
"sb\t$0, 0(%0)\n\t"
"mtc0\t$0, $12\n\t"
"nop; nop; nop; nop;\n\t"
"mtc0\t%2, $12\n\t"
"nop; nop; nop; nop;\n\t"
".set\tpop"
: "=r" (tmp1), "=r" (tmp2), "=r" (addr));
}
static void indy_sc_disable(void)
{
unsigned long tmp1, tmp2, tmp3;
#ifdef DEBUG_CACHE
printk("Disabling R4600 SCACHE\n");
#endif
__asm__ __volatile__(
".set\tpush\n\t"
".set\tnoreorder\n\t"
".set\tmips3\n\t"
"li\t%0, 0x1\n\t"
"dsll\t%0, 31\n\t"
"lui\t%1, 0x9000\n\t"
"dsll32\t%1, 0\n\t"
"or\t%0, %1, %0\n\t"
"mfc0\t%2, $12\n\t"
"nop; nop; nop; nop\n\t"
"li\t%1, 0x80\n\t"
"mtc0\t%1, $12\n\t"
"nop; nop; nop; nop\n\t"
"sh\t$0, 0(%0)\n\t"
"mtc0\t$0, $12\n\t"
"nop; nop; nop; nop\n\t"
"mtc0\t%2, $12\n\t"
"nop; nop; nop; nop\n\t"
".set\tpop"
: "=r" (tmp1), "=r" (tmp2), "=r" (tmp3));
}
static inline int __init indy_sc_probe(void)
{
volatile unsigned int *cpu_control;
unsigned short cmd = 0xc220;
unsigned long data = 0;
int i, n;
#ifdef __MIPSEB__
cpu_control = (volatile unsigned int *) KSEG1ADDR(0x1fa00034);
#else
cpu_control = (volatile unsigned int *) KSEG1ADDR(0x1fa00030);
#endif
#define DEASSERT(bit) (*(cpu_control) &= (~(bit)))
#define ASSERT(bit) (*(cpu_control) |= (bit))
#define DELAY for(n = 0; n < 100000; n++) __asm__ __volatile__("")
DEASSERT(SGIMC_EEPROM_PRE);
DEASSERT(SGIMC_EEPROM_SDATAO);
DEASSERT(SGIMC_EEPROM_SECLOCK);
DEASSERT(SGIMC_EEPROM_PRE);
DELAY;
ASSERT(SGIMC_EEPROM_CSEL); ASSERT(SGIMC_EEPROM_SECLOCK);
for(i = 0; i < 11; i++) {
if(cmd & (1<<15))
ASSERT(SGIMC_EEPROM_SDATAO);
else
DEASSERT(SGIMC_EEPROM_SDATAO);
DEASSERT(SGIMC_EEPROM_SECLOCK);
ASSERT(SGIMC_EEPROM_SECLOCK);
cmd <<= 1;
}
DEASSERT(SGIMC_EEPROM_SDATAO);
for(i = 0; i < (sizeof(unsigned short) * 8); i++) {
unsigned int tmp;
DEASSERT(SGIMC_EEPROM_SECLOCK);
DELAY;
ASSERT(SGIMC_EEPROM_SECLOCK);
DELAY;
data <<= 1;
tmp = *cpu_control;
if(tmp & SGIMC_EEPROM_SDATAI)
data |= 1;
}
DEASSERT(SGIMC_EEPROM_SECLOCK);
DEASSERT(SGIMC_EEPROM_CSEL);
ASSERT(SGIMC_EEPROM_PRE);
ASSERT(SGIMC_EEPROM_SECLOCK);
data <<= PAGE_SHIFT;
if (data == 0)
return 0;
scache_size = data;
printk("R4600/R5000 SCACHE size %ldK, linesize 32 bytes.\n",
scache_size >> 10);
return 1;
}
/* XXX Check with wje if the Indy caches can differenciate between
writeback + invalidate and just invalidate. */
struct bcache_ops indy_sc_ops = {
indy_sc_enable,
indy_sc_disable,
indy_sc_wback_invalidate,
indy_sc_wback_invalidate
};
void __init indy_sc_init(void)
{
if (indy_sc_probe()) {
indy_sc_enable();
bcops = &indy_sc_ops;
}
}
arch/mips/sgi/kernel/setup.c deleted 100644 → 0
View file @ f19e2d9e
/*
* setup.c: SGI specific setup, including init of the feature struct.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
* Copyright (C) 1997, 1998 Ralf Baechle (ralf@gnu.org)
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/kbd_ll.h>
#include <linux/kernel.h>
#include <linux/kdev_t.h>
#include <linux/types.h>
#include <linux/console.h>
#include <linux/sched.h>
#include <linux/mc146818rtc.h>
#include <linux/pc_keyb.h>
#include <asm/addrspace.h>
#include <asm/bcache.h>
#include <asm/keyboard.h>
#include <asm/irq.h>
#include <asm/reboot.h>
#include <asm/sgialib.h>
#include <asm/sgi/sgimc.h>
#include <asm/sgi/sgihpc.h>
#include <asm/sgi/sgint23.h>
#include <asm/time.h>
#include <asm/gdb-stub.h>
#ifdef CONFIG_REMOTE_DEBUG
extern void rs_kgdb_hook(int);
extern void breakpoint(void);
static int remote_debug = 0;
#endif
#if defined(CONFIG_SERIAL_CONSOLE) || defined(CONFIG_ARC_CONSOLE)
extern void console_setup(char *);
#endif
extern unsigned long r4k_interval; /* Cycle counter ticks per 1/HZ seconds */
extern struct rtc_ops indy_rtc_ops;
void indy_reboot_setup(void);
void sgi_volume_set(unsigned char);
#define sgi_kh ((struct hpc_keyb *) (KSEG1 + 0x1fbd9800 + 64))
#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
static void sgi_request_region(void)
{
/* No I/O ports are being used on the Indy. */
}
static int sgi_request_irq(void (*handler)(int, void *, struct pt_regs *))
{
/* Dirty hack, this get's called as a callback from the keyboard
driver. We piggyback the initialization of the front panel
button handling on it even though they're technically not
related with the keyboard driver in any way. Doing it from
indy_setup wouldn't work since kmalloc isn't initialized yet. */
indy_reboot_setup();
return request_irq(SGI_KEYBOARD_IRQ, handler, 0, "keyboard", NULL);
}
static int sgi_aux_request_irq(void (*handler)(int, void *, struct pt_regs *))
{
/* Nothing to do, interrupt is shared with the keyboard hw */
return 0;
}
static void sgi_aux_free_irq(void)
{
/* Nothing to do, interrupt is shared with the keyboard hw */
}
static unsigned char sgi_read_input(void)
{
return sgi_kh->data;
}
static void sgi_write_output(unsigned char val)
{
int status;
do {
status = sgi_kh->command;
} while (status & KBD_STAT_IBF);
sgi_kh->data = val;
}
static void sgi_write_command(unsigned char val)
{
int status;
do {
status = sgi_kh->command;
} while (status & KBD_STAT_IBF);
sgi_kh->command = val;
}
static unsigned char sgi_read_status(void)
{
return sgi_kh->command;
}
struct kbd_ops sgi_kbd_ops = {
sgi_request_region,
sgi_request_irq,
sgi_aux_request_irq,
sgi_aux_free_irq,
sgi_read_input,
sgi_write_output,
sgi_write_command,
sgi_read_status
};
static unsigned long dosample(volatile unsigned char *tcwp,
volatile unsigned char *tc2p)
{
unsigned long ct0, ct1;
unsigned char msb, lsb;
/* Start the counter. */
*tcwp = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL | SGINT_TCWORD_MRGEN);
*tc2p = (SGINT_TCSAMP_COUNTER & 0xff);
*tc2p = (SGINT_TCSAMP_COUNTER >> 8);
/* Get initial counter invariant */
ct0 = read_32bit_cp0_register(CP0_COUNT);
/* Latch and spin until top byte of counter2 is zero */
do {
*tcwp = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CLAT);
lsb = *tc2p;
msb = *tc2p;
ct1 = read_32bit_cp0_register(CP0_COUNT);
} while(msb);
/* Stop the counter. */
*tcwp = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL | SGINT_TCWORD_MSWST);
/*
* Return the difference, this is how far the r4k counter increments
* for every 1/HZ seconds. We round off the nearest 1 MHz of master
* clock (= 1000000 / 100 / 2 = 5000 count).
*/
return ((ct1 - ct0) / 5000) * 5000;
}
#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
void sgi_time_init (struct irqaction *irq) {
/* Here we need to calibrate the cycle counter to at least be close.
* We don't need to actually register the irq handler because that's
* all done in indyIRQ.S.
*/
struct sgi_ioc_timers *p;
volatile unsigned char *tcwp, *tc2p;
unsigned long r4k_ticks[3];
unsigned long r4k_next;
/* Figure out the r4k offset, the algorithm is very simple
* and works in _all_ cases as long as the 8254 counter
* register itself works ok (as an interrupt driving timer
* it does not because of bug, this is why we are using
* the onchip r4k counter/compare register to serve this
* purpose, but for r4k_offset calculation it will work
* ok for us). There are other very complicated ways
* of performing this calculation but this one works just
* fine so I am not going to futz around. ;-)
*/
p = ioc_timers;
tcwp = &p->tcword;
tc2p = &p->tcnt2;
printk("Calibrating system timer... ");
dosample(tcwp, tc2p); /* Prime cache. */
dosample(tcwp, tc2p); /* Prime cache. */
/* Zero is NOT an option. */
do {
r4k_ticks[0] = dosample (tcwp, tc2p);
} while (!r4k_ticks[0]);
do {
r4k_ticks[1] = dosample (tcwp, tc2p);
} while (!r4k_ticks[1]);
if (r4k_ticks[0] != r4k_ticks[1]) {
printk ("warning: timer counts differ, retrying...");
r4k_ticks[2] = dosample (tcwp, tc2p);
if (r4k_ticks[2] == r4k_ticks[0]
|| r4k_ticks[2] == r4k_ticks[1])
r4k_interval = r4k_ticks[2];
else {
printk ("disagreement, using average...");
r4k_interval = (r4k_ticks[0] + r4k_ticks[1]
+ r4k_ticks[2]) / 3;
}
} else
r4k_interval = r4k_ticks[0];
printk("%d [%d.%02d MHz CPU]\n", (int) r4k_interval,
(int) (r4k_interval / 5000), (int) (r4k_interval % 5000) / 50);
/* Set ourselves up for future interrupts */
r4k_next = (read_32bit_cp0_register(CP0_COUNT) + r4k_interval);
write_32bit_cp0_register(CP0_COMPARE, r4k_next);
change_cp0_status(ST0_IM, ALLINTS);
sti ();
}
void __init sgi_setup(void)
{
#ifdef CONFIG_SERIAL_CONSOLE
char *ctype;
#endif
#ifdef CONFIG_REMOTE_DEBUG
char *kgdb_ttyd;
#endif
board_time_init = sgi_time_init;
/* Init the INDY HPC I/O controller. Need to call this before
* fucking with the memory controller because it needs to know the
* boardID and whether this is a Guiness or a FullHouse machine.
*/
sgihpc_init();
/* Init INDY memory controller. */
sgimc_init();
/* Now enable boardcaches, if any. */
indy_sc_init();
#ifdef CONFIG_SERIAL_CONSOLE
/* ARCS console environment variable is set to "g?" for
* graphics console, it is set to "d" for the first serial
* line and "d2" for the second serial line.
*/
ctype = ArcGetEnvironmentVariable("console");
if(*ctype == 'd') {
if(*(ctype+1)=='2')
console_setup ("ttyS1");
else
console_setup ("ttyS0");
}
#endif
#ifdef CONFIG_REMOTE_DEBUG
kgdb_ttyd = prom_getcmdline();
if ((kgdb_ttyd = strstr(kgdb_ttyd, "kgdb=ttyd")) != NULL) {
int line;
kgdb_ttyd += strlen("kgdb=ttyd");
if (*kgdb_ttyd != '1' && *kgdb_ttyd != '2')
printk("KGDB: Uknown serial line /dev/ttyd%c, "
"falling back to /dev/ttyd1\n", *kgdb_ttyd);
line = *kgdb_ttyd == '2' ? 0 : 1;
printk("KGDB: Using serial line /dev/ttyd%d for session\n",
line ? 1 : 2);
rs_kgdb_hook(line);
printk("KGDB: Using serial line /dev/ttyd%d for session, "
"please connect your debugger\n", line ? 1 : 2);
remote_debug = 1;
/* Breakpoints and stuff are in sgi_irq_setup() */
}
#endif
#ifdef CONFIG_ARC_CONSOLE
console_setup("ttyS0");
#endif
sgi_volume_set(simple_strtoul(ArcGetEnvironmentVariable("volume"), NULL, 10));
#ifdef CONFIG_VT
#ifdef CONFIG_SGI_NEWPORT_CONSOLE
conswitchp = &newport_con;
screen_info = (struct screen_info) {
0, 0, /* orig-x, orig-y */
0, /* unused */
0, /* orig_video_page */
0, /* orig_video_mode */
160, /* orig_video_cols */
0, 0, 0, /* unused, ega_bx, unused */
64, /* orig_video_lines */
0, /* orig_video_isVGA */
16 /* orig_video_points */
};
#else
conswitchp = &dummy_con;
#endif
#endif
rtc_ops = &indy_rtc_ops;
kbd_ops = &sgi_kbd_ops;
#ifdef CONFIG_PSMOUSE
aux_device_present = 0xaa;
#endif
#ifdef CONFIG_VIDEO_VINO
init_vino();
#endif
}
arch/mips/sgi/kernel/system.c deleted 100644 → 0
View file @ f19e2d9e
/*
* system.c: Probe the system type using ARCS prom interface library.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
*
* $Id: system.c,v 1.8 1999/10/09 00:00:59 ralf Exp $
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/string.h>
#include <asm/sgi/sgi.h>
#include <asm/sgialib.h>
#include <asm/bootinfo.h>
enum sgi_mach sgimach;
struct smatch {
char *name;
int type;
};
static struct smatch sgi_cputable[] = {
{ "MIPS-R2000", CPU_R2000 },
{ "MIPS-R3000", CPU_R3000 },
{ "MIPS-R3000A", CPU_R3000A },
{ "MIPS-R4000", CPU_R4000SC },
{ "MIPS-R4400", CPU_R4400SC },
{ "MIPS-R4600", CPU_R4600 },
{ "MIPS-R8000", CPU_R8000 },
{ "MIPS-R5000", CPU_R5000 },
{ "MIPS-R5000A", CPU_R5000A }
};
#define NUM_CPUS 9 /* for now */
static int __init string_to_cpu(char *s)
{
int i;
for(i = 0; i < NUM_CPUS; i++) {
if(!strcmp(s, sgi_cputable[i].name))
return sgi_cputable[i].type;
}
prom_printf("\nYeee, could not determine MIPS cpu type <%s>\n", s);
prom_printf("press a key to reboot\n");
prom_getchar();
romvec->imode();
return 0;
}
/*
* We' call this early before loadmmu(). If we do the other way around
* the firmware will crash and burn.
*/
void __init sgi_sysinit(void)
{
pcomponent *p, *toplev, *cpup = 0;
int cputype = -1;
/* The root component tells us what machine architecture we
* have here.
*/
p = prom_getchild(PROM_NULL_COMPONENT);
/* Now scan for cpu(s). */
toplev = p = prom_getchild(p);
while(p) {
int ncpus = 0;
if(p->type == Cpu) {
if(++ncpus > 1) {
prom_printf("\nYeee, SGI MP not ready yet\n");
prom_printf("press a key to reboot\n");
prom_getchar();
romvec->imode();
}
printk("CPU: %s ", p->iname);
cpup = p;
cputype = string_to_cpu(cpup->iname);
}
p = prom_getsibling(p);
}
if(cputype == -1) {
prom_printf("\nYeee, could not find cpu ARCS component\n");
prom_printf("press a key to reboot\n");
prom_getchar();
romvec->imode();
}
p = prom_getchild(cpup);
while(p) {
switch(p->class) {
case processor:
switch(p->type) {
case Fpu:
printk("FPU<%s> ", p->iname);
break;
default:
break;
};
break;
case cache:
switch(p->type) {
case picache:
printk("ICACHE ");
break;
case pdcache:
printk("DCACHE ");
break;
case sccache:
printk("SCACHE ");
break;
default:
break;
};
break;
default:
break;
};
p = prom_getsibling(p);
}
printk("\n");
}
arch/mips/sgi/kernel/time.c deleted 100644 → 0
View file @ f19e2d9e
/*
* time.c: Generic SGI handler for (spurious) 8254 interrupts
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
*/
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <asm/sgialib.h>
void indy_8254timer_irq(void)
{
int cpu = smp_processor_id();
int irq = 4;
irq_enter(cpu, irq);
kstat_cpu(0).irqs[irq]++;
printk("indy_8254timer_irq: Whoops, should not have gotten this IRQ\n");
prom_getchar();
ArcEnterInteractiveMode();
irq_exit(cpu, irq);
}
arch/mips64/defconfig-ip22
View file @ 2395133b
#
# Automatically generated make config: don't edit
#
CONFIG_MIPS=y
# CONFIG_MIPS32 is not set
CONFIG_MIPS64=y
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
#
# General setup
#
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_EMBEDDED is not set
CONFIG_FUTEX=y
CONFIG_EPOLL=y
#
# Loadable module support
#
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
CONFIG_OBSOLETE_MODPARM=y
CONFIG_MODVERSIONS=y
CONFIG_KMOD=y
#
# Machine selection
#
# CONFIG_ACER_PICA_61 is not set
# CONFIG_CASIO_E55 is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_LASAT is not set
# CONFIG_HP_LASERJET is not set
# CONFIG_IBM_WORKPAD is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MIPS_ATLAS is not set
# CONFIG_MIPS_MAGNUM_4000 is not set
# CONFIG_MIPS_MALTA is not set
# CONFIG_MIPS_SEAD is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_DDB5074 is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_NEC_OSPREY is not set
# CONFIG_NEC_EAGLE is not set
# CONFIG_OLIVETTI_M700 is not set
CONFIG_SGI_IP22=y
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SIBYTE_SB1xxx_SOC is not set
# CONFIG_SNI_RM200_PCI is not set
# CONFIG_TANBAC_TB0226 is not set
# CONFIG_TANBAC_TB0229 is not set
# CONFIG_VICTOR_MPC30X is not set
# CONFIG_ZAO_CAPCELLA is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
CONFIG_ARC=y
CONFIG_GENERIC_ISA_DMA=y
CONFIG_NONCOHERENT_IO=y
# CONFIG_CPU_LITTLE_ENDIAN is not set
CONFIG_IRQ_CPU=y
CONFIG_SWAP_IO_SPACE=y
CONFIG_BOOT_ELF32=y
CONFIG_L1_CACHE_SHIFT=5
CONFIG_ARC32=y
# CONFIG_FB is not set
CONFIG_ARC_CONSOLE=y
CONFIG_ARC_PROMLIB=y
CONFIG_BOARD_SCACHE=y
CONFIG_ARC_MEMORY=y
CONFIG_SGI=y
CONFIG_L1_CACHE_SHIFT=5
# CONFIG_ISA is not set
# CONFIG_EISA is not set
# CONFIG_PCI is not set
# CONFIG_MCA is not set
# CONFIG_SBUS is not set
#
# CPU selection
#
# CONFIG_CPU_MIPS32 is not set
# CONFIG_CPU_MIPS64 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_VR41XX is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_TX49XX is not set
CONFIG_CPU_R5000=y
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_SB1 is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_LLDSCD=y
CONFIG_CPU_HAS_SYNC=y
# CONFIG_PREEMPT is not set
CONFIG_KALLSYMS=y
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
#
# General setup
# Bus options (PCI, PCMCIA, EISA, ISA, TC)
#
# CONFIG_CPU_LITTLE_ENDIAN is not set
# CONFIG_MIPS_FPU_EMULATOR is not set
CONFIG_NET=y
# CONFIG_ISA is not set
CONFIG_MMU=y
# CONFIG_HOTPLUG is not set
# CONFIG_PCMCIA is not set
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
# CONFIG_ARC_CONSOLE is not set
CONFIG_BINFMT_ELF=y
CONFIG_MIPS32_COMPAT=y
CONFIG_BINFMT_ELF32=y
# CONFIG_BINFMT_MISC is not set
#
# Loadable module support
# Executable file formats
#
CONFIG_MODULES=y
# CONFIG_MODVERSIONS is not set
CONFIG_KMOD=y
CONFIG_KCORE_ELF=y
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_MIPS32_COMPAT=y
CONFIG_COMPAT=y
CONFIG_MIPS32_O32=y
CONFIG_MIPS32_N32=y
CONFIG_BINFMT_ELF32=y
#
# Memory Technology Devices (MTD)
......@@ -70,42 +138,91 @@ CONFIG_KMOD=y
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
# CONFIG_PNP is not set
#
# Generic Driver Options
#
# CONFIG_FW_LOADER is not set
#
# Block devices
#
# CONFIG_BLK_DEV_FD is not set
# CONFIG_BLK_DEV_XD is not set
# CONFIG_PARIDE is not set
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_BLK_DEV_INITRD is not set
#
# ATA/ATAPI/MFM/RLL support
#
# CONFIG_IDE is not set
#
# SCSI device support
#
CONFIG_SCSI=y
#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_ST=y
# CONFIG_CHR_DEV_OSST is not set
CONFIG_BLK_DEV_SR=y
# CONFIG_BLK_DEV_SR_VENDOR is not set
# CONFIG_CHR_DEV_SG is not set
#
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
#
# CONFIG_SCSI_MULTI_LUN is not set
# CONFIG_SCSI_REPORT_LUNS is not set
CONFIG_SCSI_CONSTANTS=y
# CONFIG_SCSI_LOGGING is not set
#
# SCSI low-level drivers
#
CONFIG_SGIWD93_SCSI=y
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC7XXX_OLD is not set
# CONFIG_SCSI_DPT_I2O is not set
# CONFIG_SCSI_EATA_PIO is not set
# CONFIG_SCSI_DEBUG is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
# CONFIG_BLK_DEV_MD is not set
# CONFIG_MD_LINEAR is not set
# CONFIG_MD_RAID0 is not set
# CONFIG_MD_RAID1 is not set
# CONFIG_MD_RAID5 is not set
# CONFIG_BLK_DEV_LVM is not set
#
# Fusion MPT device support
#
# CONFIG_FUSION is not set
#
# I2O device support
#
#
# Networking support
#
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_MMAP=y
CONFIG_NETLINK=y
CONFIG_RTNETLINK=y
CONFIG_NETLINK_DEV=y
# CONFIG_NETFILTER is not set
# CONFIG_FILTER is not set
CONFIG_UNIX=y
CONFIG_NET_KEY=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
# CONFIG_IP_ADVANCED_ROUTER is not set
......@@ -119,20 +236,24 @@ CONFIG_IP_PNP_BOOTP=y
# CONFIG_ARPD is not set
# CONFIG_INET_ECN is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_IPV6 is not set
# CONFIG_KHTTPD is not set
# CONFIG_ATM is not set
# CONFIG_XFRM_USER is not set
#
#
# SCTP Configuration (EXPERIMENTAL)
#
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
CONFIG_IPV6_SCTP__=y
# CONFIG_IP_SCTP is not set
# CONFIG_ATM is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_LLC is not set
# CONFIG_DECNET is not set
# CONFIG_BRIDGE is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_LLC is not set
# CONFIG_NET_DIVERT is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
......@@ -145,94 +266,10 @@ CONFIG_IP_PNP_BOOTP=y
# CONFIG_NET_SCHED is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
# CONFIG_PHONE_IXJ is not set
# CONFIG_PHONE_IXJ_PCMCIA is not set
#
# ATA/IDE/MFM/RLL support
#
# CONFIG_IDE is not set
# CONFIG_BLK_DEV_IDE_MODES is not set
# CONFIG_BLK_DEV_HD is not set
#
# SCSI support
#
CONFIG_SCSI=y
#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
CONFIG_SD_EXTRA_DEVS=40
CONFIG_CHR_DEV_ST=y
# CONFIG_CHR_DEV_OSST is not set
CONFIG_BLK_DEV_SR=y
# CONFIG_BLK_DEV_SR_VENDOR is not set
CONFIG_SR_EXTRA_DEVS=2
# CONFIG_CHR_DEV_SG is not set
#
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
#
# CONFIG_SCSI_DEBUG_QUEUES is not set
# CONFIG_SCSI_MULTI_LUN is not set
CONFIG_SCSI_CONSTANTS=y
# CONFIG_SCSI_LOGGING is not set
#
# SCSI low-level drivers
#
CONFIG_SGIWD93_SCSI=y
# CONFIG_SCSI_7000FASST is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AHA152X is not set
# CONFIG_SCSI_AHA1542 is not set
# CONFIG_SCSI_AHA1740 is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC7XXX_OLD is not set
# CONFIG_SCSI_DPT_I2O is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_IN2000 is not set
# CONFIG_SCSI_AM53C974 is not set
# CONFIG_SCSI_MEGARAID is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_DTC3280 is not set
# CONFIG_SCSI_EATA is not set
# CONFIG_SCSI_EATA_DMA is not set
# CONFIG_SCSI_EATA_PIO is not set
# CONFIG_SCSI_FUTURE_DOMAIN is not set
# CONFIG_SCSI_GDTH is not set
# CONFIG_SCSI_GENERIC_NCR5380 is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_NCR53C406A is not set
# CONFIG_SCSI_NCR_D700 is not set
# CONFIG_SCSI_NCR53C7xx is not set
# CONFIG_SCSI_PAS16 is not set
# CONFIG_SCSI_PCI2000 is not set
# CONFIG_SCSI_PCI2220I is not set
# CONFIG_SCSI_PSI240I is not set
# CONFIG_SCSI_QLOGIC_FAS is not set
# CONFIG_SCSI_SIM710 is not set
# CONFIG_SCSI_SYM53C416 is not set
# CONFIG_SCSI_T128 is not set
# CONFIG_SCSI_U14_34F is not set
# CONFIG_SCSI_DEBUG is not set
#
# Network device support
# Network testing
#
# CONFIG_NET_PKTGEN is not set
CONFIG_NETDEVICES=y
#
# ARCnet devices
#
# CONFIG_ARCNET is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
......@@ -243,33 +280,16 @@ CONFIG_NETDEVICES=y
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
# CONFIG_SUNLANCE is not set
# CONFIG_SUNBMAC is not set
# CONFIG_SUNQE is not set
# CONFIG_SUNLANCE is not set
# CONFIG_SUNGEM is not set
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_LANCE is not set
# CONFIG_NET_VENDOR_SMC is not set
# CONFIG_NET_VENDOR_RACAL is not set
# CONFIG_NET_ISA is not set
# CONFIG_NET_PCI is not set
# CONFIG_NET_POCKET is not set
# CONFIG_MII is not set
CONFIG_SGISEEQ=y
#
# Ethernet (1000 Mbit)
#
# CONFIG_ACENIC is not set
# CONFIG_DL2K is not set
# CONFIG_MYRI_SBUS is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_SK98LIN is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_PLIP is not set
#
# Ethernet (10000 Mbit)
#
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
......@@ -279,11 +299,8 @@ CONFIG_SGISEEQ=y
# CONFIG_NET_RADIO is not set
#
# Token Ring devices
# Token Ring devices (depends on LLC=y)
#
# CONFIG_TR is not set
# CONFIG_NET_FC is not set
# CONFIG_RCPCI is not set
# CONFIG_SHAPER is not set
#
......@@ -304,21 +321,69 @@ CONFIG_SGISEEQ=y
#
# ISDN subsystem
#
# CONFIG_ISDN is not set
# CONFIG_ISDN_BOOL is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
#
# Input device support
#
CONFIG_INPUT=y
#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input I/O drivers
#
# CONFIG_GAMEPORT is not set
CONFIG_SOUND_GAMEPORT=y
CONFIG_SERIO=y
CONFIG_SERIO_I8042=y
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_CT82C710 is not set
#
# Old CD-ROM drivers (not SCSI, not IDE)
# Input Device Drivers
#
# CONFIG_CD_NO_IDESCSI is not set
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Character devices
#
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
# CONFIG_SERIAL is not set
# CONFIG_SERIAL_EXTENDED is not set
CONFIG_HW_CONSOLE=y
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_IP22_ZILOG=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_UNIX98_PTY_COUNT=256
......@@ -328,36 +393,58 @@ CONFIG_UNIX98_PTY_COUNT=256
# CONFIG_I2C is not set
#
# Mice
# I2C Hardware Sensors Mainboard support
#
# CONFIG_BUSMOUSE is not set
# CONFIG_MOUSE is not set
#
# Joysticks
# I2C Hardware Sensors Chip support
#
# CONFIG_INPUT_GAMEPORT is not set
# CONFIG_I2C_SENSOR is not set
#
# Input core support is needed for gameports
# Mice
#
# CONFIG_BUSMOUSE is not set
# CONFIG_QIC02_TAPE is not set
#
# Input core support is needed for joysticks
# IPMI
#
# CONFIG_QIC02_TAPE is not set
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_INTEL_RNG is not set
CONFIG_WATCHDOG=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
# CONFIG_SOFT_WATCHDOG is not set
# CONFIG_WDT is not set
# CONFIG_WDTPCI is not set
# CONFIG_PCWATCHDOG is not set
# CONFIG_ACQUIRE_WDT is not set
# CONFIG_ADVANTECH_WDT is not set
# CONFIG_EUROTECH_WDT is not set
# CONFIG_IB700_WDT is not set
# CONFIG_I810_TCO is not set
# CONFIG_MIXCOMWD is not set
# CONFIG_SCx200_WDT is not set
# CONFIG_60XX_WDT is not set
# CONFIG_W83877F_WDT is not set
# CONFIG_MACHZ_WDT is not set
CONFIG_INDYDOG=y
# CONFIG_SC520_WDT is not set
# CONFIG_AMD7XX_TCO is not set
# CONFIG_ALIM7101_WDT is not set
# CONFIG_SC1200_WDT is not set
# CONFIG_WAFER_WDT is not set
# CONFIG_CPU5_WDT is not set
# CONFIG_NVRAM is not set
# CONFIG_RTC is not set
# CONFIG_GEN_RTC is not set
CONFIG_SGI_DS1286=y
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
# CONFIG_SONYPI is not set
#
# Ftape, the floppy tape device driver
......@@ -365,85 +452,101 @@ CONFIG_UNIX98_PTY_COUNT=256
# CONFIG_FTAPE is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_HANGCHECK_TIMER is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# Digital Video Broadcasting Devices
#
# CONFIG_DVB is not set
#
# File systems
#
# CONFIG_EXT2_FS is not set
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_XATTR=y
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
CONFIG_JBD=y
# CONFIG_JBD_DEBUG is not set
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
CONFIG_FS_POSIX_ACL=y
# CONFIG_XFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_QUOTA is not set
CONFIG_AUTOFS_FS=y
CONFIG_AUTOFS4_FS=y
# CONFIG_REISERFS_FS is not set
# CONFIG_REISERFS_CHECK is not set
# CONFIG_REISERFS_PROC_INFO is not set
#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=y
# CONFIG_JOLIET is not set
# CONFIG_ZISOFS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_FAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_DEVFS_FS is not set
CONFIG_DEVPTS_FS=y
CONFIG_DEVPTS_FS_XATTR=y
CONFIG_DEVPTS_FS_SECURITY=y
# CONFIG_TMPFS is not set
CONFIG_RAMFS=y
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_ADFS_FS_RW is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_CMS_FS is not set
# CONFIG_EXT3_FS is not set
# CONFIG_JBD is not set
# CONFIG_JBD_DEBUG is not set
# CONFIG_FAT_FS is not set
# CONFIG_MSDOS_FS is not set
# CONFIG_UMSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS_FS is not set
# CONFIG_JFFS2_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_TMPFS is not set
# CONFIG_RAMFS is not set
CONFIG_ISO9660_FS=y
# CONFIG_JOLIET is not set
# CONFIG_MINIX_FS is not set
# CONFIG_FREEVXFS_FS is not set
# CONFIG_NTFS_FS is not set
# CONFIG_NTFS_DEBUG is not set
# CONFIG_NTFS_RW is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
CONFIG_PROC_FS=y
# CONFIG_DEVFS_FS is not set
# CONFIG_DEVFS_MOUNT is not set
# CONFIG_DEVFS_DEBUG is not set
CONFIG_DEVPTS_FS=y
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX4FS_RW is not set
# CONFIG_ROMFS_FS is not set
CONFIG_EXT2_FS=y
# CONFIG_SYSV_FS is not set
# CONFIG_UDF_FS is not set
# CONFIG_UDF_RW is not set
# CONFIG_UFS_FS is not set
# CONFIG_UFS_FS_WRITE is not set
#
# Network File Systems
#
# CONFIG_CODA_FS is not set
# CONFIG_INTERMEZZO_FS is not set
CONFIG_NFS_FS=y
# CONFIG_NFS_V3 is not set
CONFIG_ROOT_NFS=y
# CONFIG_NFS_V4 is not set
CONFIG_NFSD=y
# CONFIG_NFSD_V3 is not set
CONFIG_SUNRPC=y
# CONFIG_NFSD_TCP is not set
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
CONFIG_EXPORTFS=y
CONFIG_SUNRPC=y
# CONFIG_SUNRPC_GSS is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_NCPFS_PACKET_SIGNING is not set
# CONFIG_NCPFS_IOCTL_LOCKING is not set
# CONFIG_NCPFS_STRONG is not set
# CONFIG_NCPFS_NFS_NS is not set
# CONFIG_NCPFS_OS2_NS is not set
# CONFIG_NCPFS_SMALLDOS is not set
# CONFIG_NCPFS_NLS is not set
# CONFIG_NCPFS_EXTRAS is not set
# CONFIG_CODA_FS is not set
# CONFIG_INTERMEZZO_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
......@@ -460,150 +563,82 @@ CONFIG_MSDOS_PARTITION=y
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set
# CONFIG_NEC98_PARTITION is not set
CONFIG_SGI_PARTITION=y
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_SMB_NLS is not set
# CONFIG_NLS is not set
# CONFIG_EFI_PARTITION is not set
#
# Console drivers
# Graphics support
#
#
# Frame-buffer support
# Console display driver support
#
# CONFIG_FB is not set
# CONFIG_VGA_CONSOLE is not set
# CONFIG_MDA_CONSOLE is not set
CONFIG_SGI_NEWPORT_CONSOLE=y
CONFIG_DUMMY_CONSOLE=y
CONFIG_FONT_8x16=y
CONFIG_KCORE_ELF=y
#
# Sound
# Logo configuration
#
# CONFIG_SOUND is not set
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_LOGO_LINUX_CLUT224 is not set
CONFIG_LOGO_SGI_CLUT224=y
#
# SGI devices
# Sound
#
CONFIG_SGI_SERIAL=y
# CONFIG_SERIAL_CONSOLE is not set
CONFIG_SGI_DS1286=y
# CONFIG_SGI_NEWPORT_GFX is not set
# CONFIG_SOUND is not set
#
# USB support
#
# CONFIG_USB is not set
# CONFIG_USB_GADGET is not set
#
# USB Controllers
# Bluetooth support
#
# CONFIG_USB_UHCI is not set
# CONFIG_USB_UHCI_ALT is not set
# CONFIG_USB_OHCI is not set
# CONFIG_BT is not set
#
# USB Device Class drivers
#
# CONFIG_USB_AUDIO is not set
# CONFIG_USB_BLUETOOTH is not set
# CONFIG_USB_STORAGE is not set
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set
# CONFIG_USB_STORAGE_DPCM is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set
#
# USB Human Interface Devices (HID)
#
#
# Input core support is needed for USB HID
#
#
# USB Imaging devices
#
# CONFIG_USB_DC2XX is not set
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_SCANNER is not set
# CONFIG_USB_MICROTEK is not set
# CONFIG_USB_HPUSBSCSI is not set
#
# USB Multimedia devices
#
#
# Video4Linux support is needed for USB Multimedia device support
#
# CONFIG_USB_DABUSB is not set
#
# USB Network adaptors
#
# CONFIG_USB_PLUSB is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_CATC is not set
# CONFIG_USB_CDCETHER is not set
# CONFIG_USB_USBNET is not set
#
# USB port drivers
#
# CONFIG_USB_USS720 is not set
#
# USB Serial Converter support
# Kernel hacking
#
# CONFIG_USB_SERIAL is not set
# CONFIG_USB_SERIAL_GENERIC is not set
# CONFIG_USB_SERIAL_BELKIN is not set
# CONFIG_USB_SERIAL_WHITEHEAT is not set
# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
# CONFIG_USB_SERIAL_EMPEG is not set
# CONFIG_USB_SERIAL_FTDI_SIO is not set
# CONFIG_USB_SERIAL_VISOR is not set
# CONFIG_USB_SERIAL_EDGEPORT is not set
# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
# CONFIG_USB_SERIAL_KEYSPAN is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
# CONFIG_USB_SERIAL_MCT_U232 is not set
# CONFIG_USB_SERIAL_PL2303 is not set
# CONFIG_USB_SERIAL_CYBERJACK is not set
# CONFIG_USB_SERIAL_OMNINET is not set
CONFIG_CROSSCOMPILE=y
# CONFIG_DEBUG_KERNEL is not set
#
# Miscellaneous USB drivers
# Security options
#
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_ID75 is not set
# CONFIG_SECURITY is not set
#
# Input core support
# Cryptographic options
#
# CONFIG_INPUT is not set
# CONFIG_INPUT_KEYBDEV is not set
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_EVDEV is not set
CONFIG_CRYPTO=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_BLOWFISH=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_SERPENT=y
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_DEFLATE=y
# CONFIG_CRYPTO_TEST is not set
#
# Kernel hacking
# Library routines
#
CONFIG_CROSSCOMPILE=y
# CONFIG_MIPS_FPE_MODULE is not set
# CONFIG_REMOTE_DEBUG is not set
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_MIPS_UNCACHED is not set
# CONFIG_CRC32 is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
arch/mips64/sgi-ip22/Makefile deleted 100644 → 0
View file @ f19e2d9e
#
# Makefile for the SGI specific kernel interface routines
# under Linux.
#
EXTRA_AFLAGS := $(CFLAGS)
lib-y += ip22-berr.o ip22-mc.o ip22-sc.o ip22-hpc.o ip22-int.o ip22-rtc.o \
ip22-setup.o system.o ip22-timer.o ip22-irq.o ip22-reset.o time.o
arch/mips64/sgi-ip22/ip22-berr.c deleted 100644 → 0
View file @ f19e2d9e
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994, 1995, 1996, 1999, 2000 by Ralf Baechle
* Copyright (C) 1999, 2000 by Silicon Graphics
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <asm/module.h>
#include <asm/uaccess.h>
#include <asm/paccess.h>
#include <asm/addrspace.h>
#include <asm/ptrace.h>
extern asmlinkage void handle_ibe(void);
extern asmlinkage void handle_dbe(void);
extern const struct exception_table_entry __start___dbe_table[];
extern const struct exception_table_entry __stop___dbe_table[];
static inline unsigned long
search_one_table(const struct exception_table_entry *first,
const struct exception_table_entry *last,
unsigned long value)
{
while (first <= last) {
const struct exception_table_entry *mid;
long diff;
mid = (last - first) / 2 + first;
diff = mid->insn - value;
if (diff == 0)
return mid->nextinsn;
else if (diff < 0)
first = mid+1;
else
last = mid-1;
}
return 0;
}
extern spinlock_t modlist_lock;
static inline unsigned long
search_dbe_table(unsigned long addr)
{
unsigned long ret = 0;
#ifndef CONFIG_MODULES
/* There is only the kernel to search. */
ret = search_one_table(__start___dbe_table, __stop___dbe_table-1, addr);
return ret;
#else
unsigned long flags;
/* The kernel is the last "module" -- no need to treat it special. */
struct module *mp;
struct archdata *ap;
spin_lock_irqsave(&modlist_lock, flags);
for (mp = module_list; mp != NULL; mp = mp->next) {
if (!mod_member_present(mp, archdata_end) ||
!mod_archdata_member_present(mp, struct archdata,
dbe_table_end))
continue;
ap = (struct archdata *)(mod->archdata_start);
if (ap->dbe_table_start == NULL ||
!(mp->flags & (MOD_RUNNING | MOD_INITIALIZING)))
continue;
ret = search_one_table(ap->dbe_table_start,
ap->dbe_table_end - 1, addr);
if (ret)
break;
}
spin_unlock_irqrestore(&modlist_lock, flags);
return ret;
#endif
}
void do_ibe(struct pt_regs *regs)
{
printk("Got ibe at 0x%lx\n", regs->cp0_epc);
show_regs(regs);
dump_tlb_addr(regs->cp0_epc);
force_sig(SIGBUS, current);
while(1);
}
void do_dbe(struct pt_regs *regs)
{
unsigned long fixup;
fixup = search_dbe_table(regs->cp0_epc);
if (fixup) {
long new_epc;
new_epc = fixup_exception(dpf_reg, fixup, regs->cp0_epc);
regs->cp0_epc = new_epc;
return;
}
printk("Got dbe at 0x%lx\n", regs->cp0_epc);
show_regs(regs);
dump_tlb_all();
while(1);
force_sig(SIGBUS, current);
}
void __init
bus_error_init(void)
{
int dummy;
set_except_vector(6, handle_ibe);
set_except_vector(7, handle_dbe);
/* At this time nothing uses the DBE protection mechanism on the
Indy, so this here is needed to make the kernel link. */
get_dbe(dummy, (int *)KSEG0);
}
arch/mips64/sgi-ip22/ip22-hpc.c deleted 100644 → 0
View file @ f19e2d9e
/*
* ip22-hpc.c: Routines for generic manipulation of the HPC controllers.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
* Copyright (C) 1998, 1999, 2001 Ralf Baechle
*/
#include <linux/init.h>
#include <linux/types.h>
#include <asm/addrspace.h>
#include <asm/sgi/sgihpc.h>
#include <asm/sgi/sgint23.h>
#include <asm/bootinfo.h>
#undef DEBUG_SGIHPC
struct hpc3_regs *hpc3c0, *hpc3c1;
struct hpc3_miscregs *hpc3mregs;
/* We need software copies of these because they are write only. */
unsigned int sgi_hpc_write1, sgi_hpc_write2;
/* Machine specific identifier knobs. */
int sgi_has_ioc2 = 0;
int sgi_guiness = 0;
int sgi_boardid;
void __init sgihpc_init(void)
{
unsigned long sid, crev, brev;
hpc3c0 = (struct hpc3_regs *) (KSEG1 + HPC3_CHIP0_PBASE);
hpc3c1 = (struct hpc3_regs *) (KSEG1 + HPC3_CHIP1_PBASE);
hpc3mregs = (struct hpc3_miscregs *) (KSEG1 + HPC3_MREGS_PBASE);
sid = hpc3mregs->sysid;
sid &= 0xff;
crev = (sid & 0xe0) >> 5;
brev = (sid & 0x1e) >> 1;
#ifdef DEBUG_SGIHPC
prom_printf("sgihpc_init: crev<%2x> brev<%2x>\n", crev, brev);
prom_printf("sgihpc_init: ");
#endif
/* This test works now thanks to William J. Earl */
if ((sid & 1) == 0 ) {
#ifdef DEBUG_SGIHPC
prom_printf("GUINESS ");
#endif
sgi_guiness = 1;
mips_machtype = MACH_SGI_INDY;
} else {
#ifdef DEBUG_SGIHPC
prom_printf("FULLHOUSE ");
#endif
mips_machtype = MACH_SGI_INDIGO2;
sgi_guiness = 0;
}
sgi_boardid = brev;
#ifdef DEBUG_SGIHPC
prom_printf("sgi_boardid<%d> ", sgi_boardid);
#endif
if(crev == 1) {
if((sid & 1) || (brev >= 2)) {
#ifdef DEBUG_SGIHPC
prom_printf("IOC2 ");
#endif
sgi_has_ioc2 = 1;
} else {
#ifdef DEBUG_SGIHPC
prom_printf("IOC1 revision 1 ");
#endif
}
} else {
#ifdef DEBUG_SGIHPC
prom_printf("IOC1 revision 0 ");
#endif
}
#ifdef DEBUG_SGIHPC
prom_printf("\n");
#endif
sgi_hpc_write1 = (HPC3_WRITE1_PRESET |
HPC3_WRITE1_KMRESET |
HPC3_WRITE1_ERESET |
HPC3_WRITE1_LC0OFF);
sgi_hpc_write2 = (HPC3_WRITE2_EASEL |
HPC3_WRITE2_NTHRESH |
HPC3_WRITE2_TPSPEED |
HPC3_WRITE2_EPSEL |
HPC3_WRITE2_U0AMODE |
HPC3_WRITE2_U1AMODE);
if(!sgi_guiness)
sgi_hpc_write1 |= HPC3_WRITE1_GRESET;
hpc3mregs->write1 = sgi_hpc_write1;
hpc3mregs->write2 = sgi_hpc_write2;
hpc3c0->pbus_piocfgs[0][6] |= HPC3_PIOPCFG_HW;
}
arch/mips64/sgi-ip22/ip22-int.c deleted 100644 → 0
View file @ f19e2d9e
/*
* indy_int.c: Routines for generic manipulation of the INT[23] ASIC
* found on INDY workstations..
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
* Copyright (C) 1997, 1998 Ralf Baechle (ralf@gnu.org)
* Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) - Indigo2 changes
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/seq_file.h>
#include <linux/errno.h>
#include <linux/kernel_stat.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/timex.h>
#include <linux/slab.h>
#include <linux/random.h>
#include <linux/smp.h>
#include <linux/smp_lock.h>
#include <asm/bitops.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/ptrace.h>
#include <asm/processor.h>
#include <asm/sgi/sgi.h>
#include <asm/sgi/sgihpc.h>
#include <asm/sgi/sgint23.h>
/*
* Linux has a controller-independent x86 interrupt architecture.
* every controller has a 'controller-template', that is used
* by the main code to do the right thing. Each driver-visible
* interrupt source is transparently wired to the apropriate
* controller. Thus drivers need not be aware of the
* interrupt-controller.
*
* Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC,
* PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC.
* (IO-APICs assumed to be messaging to Pentium local-APICs)
*
* the code is designed to be easily extended with new/different
* interrupt controllers, without having to do assembly magic.
*/
struct sgi_int2_regs *sgi_i2regs;
struct sgi_int3_regs *sgi_i3regs;
struct sgi_ioc_ints *ioc_icontrol;
struct sgi_ioc_timers *ioc_timers;
volatile unsigned char *ioc_tclear;
static char lc0msk_to_irqnr[256];
static char lc1msk_to_irqnr[256];
static char lc2msk_to_irqnr[256];
static char lc3msk_to_irqnr[256];
extern asmlinkage void indyIRQ(void);
#ifdef CONFIG_REMOTE_DEBUG
extern void rs_kgdb_hook(int);
#endif
unsigned long spurious_count = 0;
/* Local IRQ's are layed out logically like this:
*
* 0 --> 7 == local 0 interrupts
* 8 --> 15 == local 1 interrupts
* 16 --> 23 == vectored level 2 interrupts
* 24 --> 31 == vectored level 3 interrupts (not used)
*/
void disable_local_irq(unsigned int irq_nr)
{
unsigned long flags;
save_and_cli(flags);
switch(irq_nr) {
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
ioc_icontrol->imask0 &= ~(1 << irq_nr);
break;
case 8: case 9: case 10: case 11: case 12: case 13: case 14: case 15:
ioc_icontrol->imask1 &= ~(1 << (irq_nr - 8));
break;
case 16: case 17: case 18: case 19: case 20: case 21: case 22: case 23:
ioc_icontrol->cmeimask0 &= ~(1 << (irq_nr - 16));
break;
default:
/* This way we'll see if anyone would ever want vectored
* level 3 interrupts. Highly unlikely.
*/
printk("Yeeee, got passed irq_nr %d at disable_irq\n", irq_nr);
panic("INVALID IRQ level!");
};
restore_flags(flags);
}
void enable_local_irq(unsigned int irq_nr)
{
unsigned long flags;
save_and_cli(flags);
switch(irq_nr) {
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
ioc_icontrol->imask0 |= (1 << irq_nr);
break;
case 8: case 9: case 10: case 11: case 12: case 13: case 14: case 15:
ioc_icontrol->imask1 |= (1 << (irq_nr - 8));
break;
case 16: case 17: case 18: case 19: case 20: case 21: case 22: case 23:
enable_local_irq(7);
ioc_icontrol->cmeimask0 |= (1 << (irq_nr - 16));
break;
default:
printk("Yeeee, got passed irq_nr %d at disable_irq\n", irq_nr);
panic("INVALID IRQ level!");
};
restore_flags(flags);
}
void disable_gio_irq(unsigned int irq_nr)
{
/* XXX TODO XXX */
}
void enable_gio_irq(unsigned int irq_nr)
{
/* XXX TODO XXX */
}
void disable_hpcdma_irq(unsigned int irq_nr)
{
/* XXX TODO XXX */
}
void enable_hpcdma_irq(unsigned int irq_nr)
{
/* XXX TODO XXX */
}
void disable_irq(unsigned int irq_nr)
{
unsigned int n = irq_nr;
if(n >= SGINT_END) {
printk("whee, invalid irq_nr %d\n", irq_nr);
panic("IRQ, you lose...");
}
if(n >= SGINT_LOCAL0 && n < SGINT_GIO) {
disable_local_irq(n - SGINT_LOCAL0);
} else if(n >= SGINT_GIO && n < SGINT_HPCDMA) {
disable_gio_irq(n - SGINT_GIO);
} else if(n >= SGINT_HPCDMA && n < SGINT_END) {
disable_hpcdma_irq(n - SGINT_HPCDMA);
} else {
panic("how did I get here?");
}
}
void enable_irq(unsigned int irq_nr)
{
unsigned int n = irq_nr;
if(n >= SGINT_END) {
printk("whee, invalid irq_nr %d\n", irq_nr);
panic("IRQ, you lose...");
}
if(n >= SGINT_LOCAL0 && n < SGINT_GIO) {
enable_local_irq(n - SGINT_LOCAL0);
} else if(n >= SGINT_GIO && n < SGINT_HPCDMA) {
enable_gio_irq(n - SGINT_GIO);
} else if(n >= SGINT_HPCDMA && n < SGINT_END) {
enable_hpcdma_irq(n - SGINT_HPCDMA);
} else {
panic("how did I get here?");
}
}
#if 0
/*
* Currently unused.
*/
static void local_unex(int irq, void *data, struct pt_regs *regs)
{
printk("Whee: unexpected local IRQ at %08lx\n",
(unsigned long) regs->cp0_epc);
printk("DUMP: stat0<%x> stat1<%x> vmeistat<%x>\n",
ioc_icontrol->istat0, ioc_icontrol->istat1,
ioc_icontrol->vmeistat);
}
#endif
static struct irqaction *local_irq_action[24] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL
};
int setup_indy_irq(int irq, struct irqaction * new)
{
printk("setup_indy_irq: Yeee, don't know how to setup irq<%d> for %s %p\n",
irq, new->name, new->handler);
return 0;
}
static struct irqaction r4ktimer_action = {
NULL, 0, 0, "R4000 timer/counter", NULL, NULL,
};
static struct irqaction indy_berr_action = {
NULL, 0, 0, "IP22 Bus Error", NULL, NULL,
};
static struct irqaction *irq_action[16] = {
NULL, NULL, NULL, NULL,
NULL, NULL, &indy_berr_action, &r4ktimer_action,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL
};
int show_interrupts(struct seq_file *p, void *v)
{
int i;
int num = 0;
struct irqaction * action;
unsigned long flags;
for (i = 0 ; i < 16 ; i++, num++) {
local_irq_save(flags);
action = irq_action[i];
if (!action)
goto skip_1;
seq_printf(p, "%2d: %8d %c %s",
num, kstat_cpu(0).irqs[num],
(action->flags & SA_INTERRUPT) ? '+' : ' ',
action->name);
for (action=action->next; action; action = action->next) {
seq_printf(p, ",%s %s",
(action->flags & SA_INTERRUPT) ? " +" : "",
action->name);
}
seq_puts(p, " [on-chip]\n");
skip_1:
local_irq_restore(flags);
}
for (i = 0 ; i < 24 ; i++, num++) {
local_irq_save(flags);
action = local_irq_action[i];
if (!action)
goto skip_2;
seq_printf(p, "%2d: %8d %c %s",
num, kstat_cpu(0).irqs[num],
(action->flags & SA_INTERRUPT) ? '+' : ' ',
action->name);
for (action=action->next; action; action = action->next) {
seq_printf(p, ",%s %s",
(action->flags & SA_INTERRUPT) ? " +" : "",
action->name);
}
seq_puts(p, " [local]\n");
skip_2:
local_irq_restore(flags);
}
return 0;
}
/*
* do_IRQ handles IRQ's that have been installed without the
* SA_INTERRUPT flag: it uses the full signal-handling return
* and runs with other interrupts enabled. All relatively slow
* IRQ's should use this format: notably the keyboard/timer
* routines.
*/
asmlinkage void do_IRQ(int irq, struct pt_regs * regs)
{
struct irqaction *action;
int do_random, cpu;
cpu = smp_processor_id();
irq_enter(cpu, irq);
kstat_cpu(0).irqs[irq]++;
panic(KERN_DEBUG "Got irq %d, press a key.", irq);
/*
* mask and ack quickly, we don't want the irq controller
* thinking we're snobs just because some other CPU has
* disabled global interrupts (we have already done the
* INT_ACK cycles, it's too late to try to pretend to the
* controller that we aren't taking the interrupt).
*
* Commented out because we've already done this in the
* machinespecific part of the handler. It's reasonable to
* do this here in a highlevel language though because that way
* we could get rid of a good part of duplicated code ...
*/
/* mask_and_ack_irq(irq); */
action = *(irq + irq_action);
if (action) {
if (!(action->flags & SA_INTERRUPT))
local_irq_enable();
action = *(irq + irq_action);
do_random = 0;
do {
do_random |= action->flags;
action->handler(irq, action->dev_id, regs);
action = action->next;
} while (action);
if (do_random & SA_SAMPLE_RANDOM)
add_interrupt_randomness(irq);
local_irq_disable();
}
irq_exit(cpu, irq);
/* unmasking and bottom half handling is done magically for us. */
}
int request_local_irq(unsigned int lirq, void (*func)(int, void *, struct pt_regs *),
unsigned long iflags, const char *dname, void *devid)
{
struct irqaction *action;
lirq -= SGINT_LOCAL0;
if(lirq >= 24 || !func)
return -EINVAL;
action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL);
if(!action)
return -ENOMEM;
action->handler = func;
action->flags = iflags;
action->mask = 0;
action->name = dname;
action->dev_id = devid;
action->next = 0;
local_irq_action[lirq] = action;
enable_irq(lirq + SGINT_LOCAL0);
return 0;
}
void free_local_irq(unsigned int lirq, void *dev_id)
{
struct irqaction *action;
lirq -= SGINT_LOCAL0;
if(lirq >= 24) {
printk("Aieee: trying to free bogus local irq %d\n",
lirq + SGINT_LOCAL0);
return;
}
action = local_irq_action[lirq];
local_irq_action[lirq] = NULL;
disable_irq(lirq + SGINT_LOCAL0);
kfree(action);
}
int request_irq(unsigned int irq,
void (*handler)(int, void *, struct pt_regs *),
unsigned long irqflags,
const char * devname,
void *dev_id)
{
int retval;
struct irqaction * action;
if (irq >= SGINT_END)
return -EINVAL;
if (!handler)
return -EINVAL;
if((irq >= SGINT_LOCAL0) && (irq < SGINT_GIO))
return request_local_irq(irq, handler, irqflags, devname, dev_id);
action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL);
if (!action)
return -ENOMEM;
action->handler = handler;
action->flags = irqflags;
action->mask = 0;
action->name = devname;
action->next = NULL;
action->dev_id = dev_id;
retval = setup_indy_irq(irq, action);
if (retval)
kfree(action);
return retval;
}
void free_irq(unsigned int irq, void *dev_id)
{
struct irqaction * action, **p;
unsigned long flags;
if (irq >= SGINT_END) {
printk("Trying to free IRQ%d\n",irq);
return;
}
if((irq >= SGINT_LOCAL0) && (irq < SGINT_GIO)) {
free_local_irq(irq, dev_id);
return;
}
for (p = irq + irq_action; (action = *p) != NULL; p = &action->next) {
if (action->dev_id != dev_id)
continue;
/* Found it - now free it */
save_and_cli(flags);
*p = action->next;
restore_flags(flags);
kfree(action);
return;
}
printk("Trying to free free IRQ%d\n",irq);
}
void indy_local0_irqdispatch(struct pt_regs *regs)
{
struct irqaction *action;
unsigned char mask = ioc_icontrol->istat0;
unsigned char mask2 = 0;
int irq, cpu = smp_processor_id();;
mask &= ioc_icontrol->imask0;
if(mask & ISTAT0_LIO2) {
mask2 = ioc_icontrol->vmeistat;
mask2 &= ioc_icontrol->cmeimask0;
irq = lc2msk_to_irqnr[mask2];
action = local_irq_action[irq];
} else {
irq = lc0msk_to_irqnr[mask];
action = local_irq_action[irq];
}
irq_enter(cpu, irq);
kstat_cpu(0).irqs[irq + 16]++;
action->handler(irq, action->dev_id, regs);
irq_exit(cpu, irq);
}
void indy_local1_irqdispatch(struct pt_regs *regs)
{
struct irqaction *action;
unsigned char mask = ioc_icontrol->istat1;
unsigned char mask2 = 0;
int irq, cpu = smp_processor_id();;
mask &= ioc_icontrol->imask1;
if(mask & ISTAT1_LIO3) {
printk("WHee: Got an LIO3 irq, winging it...\n");
mask2 = ioc_icontrol->vmeistat;
mask2 &= ioc_icontrol->cmeimask1;
irq = lc3msk_to_irqnr[ioc_icontrol->vmeistat];
action = local_irq_action[irq];
} else {
irq = lc1msk_to_irqnr[mask];
action = local_irq_action[irq];
}
irq_enter(cpu, irq);
kstat_cpu(0).irqs[irq + 24]++;
action->handler(irq, action->dev_id, regs);
irq_exit(cpu, irq);
}
void indy_buserror_irq(struct pt_regs *regs)
{
int cpu = smp_processor_id();
int irq = 6;
irq_enter(cpu, irq);
kstat_cpu(0).irqs[irq]++;
printk("Got a bus error IRQ, shouldn't happen yet\n");
show_regs(regs);
printk("Spinning...\n");
while(1);
irq_exit(cpu, irq);
}
/* Misc. crap just to keep the kernel linking... */
unsigned long probe_irq_on (void)
{
return 0;
}
int probe_irq_off (unsigned long irqs)
{
return 0;
}
static inline void sgint_init(void)
{
int i;
#ifdef CONFIG_REMOTE_DEBUG
char *ctype;
#endif
sgi_i2regs = (struct sgi_int2_regs *) (KSEG1 + SGI_INT2_BASE);
sgi_i3regs = (struct sgi_int3_regs *) (KSEG1 + SGI_INT3_BASE);
/* Init local mask --> irq tables. */
for(i = 0; i < 256; i++) {
if(i & 0x80) {
lc0msk_to_irqnr[i] = 7;
lc1msk_to_irqnr[i] = 15;
lc2msk_to_irqnr[i] = 23;
lc3msk_to_irqnr[i] = 31;
} else if(i & 0x40) {
lc0msk_to_irqnr[i] = 6;
lc1msk_to_irqnr[i] = 14;
lc2msk_to_irqnr[i] = 22;
lc3msk_to_irqnr[i] = 30;
} else if(i & 0x20) {
lc0msk_to_irqnr[i] = 5;
lc1msk_to_irqnr[i] = 13;
lc2msk_to_irqnr[i] = 21;
lc3msk_to_irqnr[i] = 29;
} else if(i & 0x10) {
lc0msk_to_irqnr[i] = 4;
lc1msk_to_irqnr[i] = 12;
lc2msk_to_irqnr[i] = 20;
lc3msk_to_irqnr[i] = 28;
} else if(i & 0x08) {
lc0msk_to_irqnr[i] = 3;
lc1msk_to_irqnr[i] = 11;
lc2msk_to_irqnr[i] = 19;
lc3msk_to_irqnr[i] = 27;
} else if(i & 0x04) {
lc0msk_to_irqnr[i] = 2;
lc1msk_to_irqnr[i] = 10;
lc2msk_to_irqnr[i] = 18;
lc3msk_to_irqnr[i] = 26;
} else if(i & 0x02) {
lc0msk_to_irqnr[i] = 1;
lc1msk_to_irqnr[i] = 9;
lc2msk_to_irqnr[i] = 17;
lc3msk_to_irqnr[i] = 25;
} else if(i & 0x01) {
lc0msk_to_irqnr[i] = 0;
lc1msk_to_irqnr[i] = 8;
lc2msk_to_irqnr[i] = 16;
lc3msk_to_irqnr[i] = 24;
} else {
lc0msk_to_irqnr[i] = 0;
lc1msk_to_irqnr[i] = 0;
lc2msk_to_irqnr[i] = 0;
lc3msk_to_irqnr[i] = 0;
}
}
/* Indy uses an INT3, Indigo2 uses an INT2 */
if (sgi_guiness) {
ioc_icontrol = &sgi_i3regs->ints;
ioc_timers = &sgi_i3regs->timers;
ioc_tclear = &sgi_i3regs->tclear;
} else {
ioc_icontrol = &sgi_i2regs->ints;
ioc_timers = &sgi_i2regs->timers;
ioc_tclear = &sgi_i2regs->tclear;
}
/* Mask out all interrupts. */
ioc_icontrol->imask0 = 0;
ioc_icontrol->imask1 = 0;
ioc_icontrol->cmeimask0 = 0;
ioc_icontrol->cmeimask1 = 0;
/* Now safe to set the exception vector. */
set_except_vector(0, indyIRQ);
#ifdef CONFIG_REMOTE_DEBUG
ctype = prom_getcmdline();
for(i = 0; i < strlen(ctype); i++) {
if(ctype[i]=='k' && ctype[i+1]=='g' &&
ctype[i+2]=='d' && ctype[i+3]=='b' &&
ctype[i+4]=='=' && ctype[i+5]=='t' &&
ctype[i+6]=='t' && ctype[i+7]=='y' &&
ctype[i+8]=='d' &&
(ctype[i+9] == '1' || ctype[i+9] == '2')) {
printk("KGDB: Using serial line /dev/ttyd%d for "
"session\n", (ctype[i+9] - '0'));
if(ctype[i+9]=='1')
rs_kgdb_hook(1);
else if(ctype[i+9]=='2')
rs_kgdb_hook(0);
else {
printk("KGDB: whoops bogon tty line "
"requested, disabling session\n");
}
}
}
#endif
}
void __init init_IRQ(void)
{
sgint_init();
}
arch/mips64/sgi-ip22/ip22-mc.c deleted 100644 → 0
View file @ f19e2d9e
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
* Copyright (C) 2001 Ralf Baechle (ralf@gnu.org)
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <asm/addrspace.h>
#include <asm/ptrace.h>
#include <asm/sgi/sgimc.h>
#include <asm/sgi/sgihpc.h>
/* #define DEBUG_SGIMC */
struct sgimc_misc_ctrl *mcmisc_regs;
u32 *rpsscounter;
struct sgimc_dma_ctrl *dmactrlregs;
static inline char *mconfig_string(unsigned long val)
{
switch(val & SGIMC_MCONFIG_RMASK) {
case SGIMC_MCONFIG_FOURMB:
return "4MB";
case SGIMC_MCONFIG_EIGHTMB:
return "8MB";
case SGIMC_MCONFIG_SXTEENMB:
return "16MB";
case SGIMC_MCONFIG_TTWOMB:
return "32MB";
case SGIMC_MCONFIG_SFOURMB:
return "64MB";
case SGIMC_MCONFIG_OTEIGHTMB:
return "128MB";
default:
return "wheee, unknown";
};
}
void __init sgimc_init(void)
{
unsigned long tmpreg;
mcmisc_regs = (struct sgimc_misc_ctrl *)(KSEG1+0x1fa00000);
rpsscounter = (u32 *) (KSEG1 + 0x1fa01004);
dmactrlregs = (struct sgimc_dma_ctrl *) (KSEG1+0x1fa02000);
printk("MC: SGI memory controller Revision %d\n",
(int) mcmisc_regs->systemid & SGIMC_SYSID_MASKREV);
#if 0 /* XXX Until I figure out what this bit really indicates XXX */
/* XXX Is this systemid bit reliable? */
if(mcmisc_regs->systemid & SGIMC_SYSID_EPRESENT) {
EISA_bus = 1;
printk("with EISA\n");
} else {
EISA_bus = 0;
printk("no EISA\n");
}
#endif
#ifdef DEBUG_SGIMC
prom_printf("sgimc_init: memconfig0<%s> mconfig1<%s>\n",
mconfig_string(mcmisc_regs->mconfig0),
mconfig_string(mcmisc_regs->mconfig1));
prom_printf("mcdump: cpuctrl0<%08lx> cpuctrl1<%08lx>\n",
mcmisc_regs->cpuctrl0, mcmisc_regs->cpuctrl1);
prom_printf("mcdump: divider<%08lx>, gioparm<%04x>\n",
mcmisc_regs->divider, mcmisc_regs->gioparm);
#endif
/* Place the MC into a known state. This must be done before
* interrupts are first enabled etc.
*/
/* Step 1: The CPU/GIO error status registers will not latch
* up a new error status until the register has been
* cleared by the cpu. These status registers are
* cleared by writing any value to them.
*/
mcmisc_regs->cstat = mcmisc_regs->gstat = 0;
/* Step 2: Enable all parity checking in cpu control register
* zero.
*/
tmpreg = mcmisc_regs->cpuctrl0;
tmpreg |= (SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM |
SGIMC_CCTRL0_R4KNOCHKPARR);
mcmisc_regs->cpuctrl0 = tmpreg;
/* Step 3: Setup the MC write buffer depth, this is controlled
* in cpu control register 1 in the lower 4 bits.
*/
tmpreg = mcmisc_regs->cpuctrl1;
tmpreg &= ~0xf;
tmpreg |= 0xd;
mcmisc_regs->cpuctrl1 = tmpreg;
/* Step 4: Initialize the RPSS divider register to run as fast
* as it can correctly operate. The register is laid
* out as follows:
*
* ----------------------------------------
* | RESERVED | INCREMENT | DIVIDER |
* ----------------------------------------
* 31 16 15 8 7 0
*
* DIVIDER determines how often a 'tick' happens,
* INCREMENT determines by how the RPSS increment
* registers value increases at each 'tick'. Thus,
* for IP22 we get INCREMENT=1, DIVIDER=1 == 0x101
*/
mcmisc_regs->divider = 0x101;
/* Step 5: Initialize GIO64 arbitrator configuration register.
*
* NOTE: If you dork with startup code the HPC init code in
* sgihpc_init() must run before us because of how we
* need to know Guiness vs. FullHouse and the board
* revision on this machine. You have been warned.
*/
/* First the basic invariants across all gio64 implementations. */
tmpreg = SGIMC_GIOPARM_HPC64; /* All 1st HPC's interface at 64bits. */
tmpreg |= SGIMC_GIOPARM_ONEBUS; /* Only one physical GIO bus exists. */
if(sgi_guiness) {
/* Guiness specific settings. */
tmpreg |= SGIMC_GIOPARM_EISA64; /* MC talks to EISA at 64bits */
tmpreg |= SGIMC_GIOPARM_MASTEREISA; /* EISA bus can act as master */
} else {
/* Fullhouse specific settings. */
if(sgi_boardid < 2) {
tmpreg |= SGIMC_GIOPARM_HPC264; /* 2nd HPC at 64bits */
tmpreg |= SGIMC_GIOPARM_PLINEEXP0; /* exp0 pipelines */
tmpreg |= SGIMC_GIOPARM_MASTEREXP1;/* exp1 masters */
tmpreg |= SGIMC_GIOPARM_RTIMEEXP0; /* exp0 is realtime */
} else {
tmpreg |= SGIMC_GIOPARM_HPC264; /* 2nd HPC 64bits */
tmpreg |= SGIMC_GIOPARM_PLINEEXP0; /* exp[01] pipelined */
tmpreg |= SGIMC_GIOPARM_PLINEEXP1;
tmpreg |= SGIMC_GIOPARM_MASTEREISA;/* EISA masters */
/* someone forgot this poor little guy... */
tmpreg |= SGIMC_GIOPARM_GFX64; /* GFX at 64 bits */
}
}
mcmisc_regs->gioparm = tmpreg; /* poof */
}
arch/mips64/sgi-ip22/ip22-reset.c deleted 100644 → 0
View file @ f19e2d9e
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Reset an IP22.
*
* Copyright (C) 1997, 1998, 1999, 2001 by Ralf Baechle
*/
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/notifier.h>
#include <linux/timer.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/sgialib.h>
#include <asm/sgi/sgihpc.h>
#include <asm/sgi/sgint23.h>
/*
* Just powerdown if init hasn't done after POWERDOWN_TIMEOUT seconds.
* I'm not shure if this feature is a good idea, for now it's here just to
* make the power button make behave just like under IRIX.
*/
#define POWERDOWN_TIMEOUT 120
/*
* Blink frequency during reboot grace period and when paniced.
*/
#define POWERDOWN_FREQ (HZ / 4)
#define PANIC_FREQ (HZ / 8)
static unsigned char sgi_volume;
static struct timer_list power_timer, blink_timer, debounce_timer, volume_timer;
static int shuting_down, has_paniced;
void machine_restart(char *command) __attribute__((noreturn));
void machine_halt(void) __attribute__((noreturn));
void machine_power_off(void) __attribute__((noreturn));
/* XXX How to pass the reboot command to the firmware??? */
void machine_restart(char *command)
{
if (shuting_down)
machine_power_off();
ArcReboot();
}
void machine_halt(void)
{
if (shuting_down)
machine_power_off();
ArcEnterInteractiveMode();
}
void machine_power_off(void)
{
struct indy_clock *clock = (struct indy_clock *)INDY_CLOCK_REGS;
cli();
clock->cmd |= 0x08; /* Disable watchdog */
clock->whsec = 0;
clock->wsec = 0;
while(1) {
hpc3mregs->panel=0xfe;
/* Good bye cruel world ... */
/* If we're still running, we probably got sent an alarm
interrupt. Read the flag to clear it. */
clock->halarm;
}
}
static void power_timeout(unsigned long data)
{
machine_power_off();
}
static void blink_timeout(unsigned long data)
{
/* XXX Fix this for Fullhouse */
sgi_hpc_write1 ^= (HPC3_WRITE1_LC0OFF|HPC3_WRITE1_LC1OFF);
hpc3mregs->write1 = sgi_hpc_write1;
mod_timer(&blink_timer, jiffies+data);
}
static void debounce(unsigned long data)
{
del_timer(&debounce_timer);
if (ioc_icontrol->istat1 & 2) { /* Interrupt still being sent. */
debounce_timer.expires = jiffies + 5; /* 0.05s */
add_timer(&debounce_timer);
hpc3mregs->panel = 0xf3;
return;
}
if (has_paniced)
ArcReboot();
enable_irq(9);
}
static inline void power_button(void)
{
if (has_paniced)
return;
if (shuting_down || kill_proc(1, SIGINT, 1)) {
/* No init process or button pressed twice. */
machine_power_off();
}
shuting_down = 1;
blink_timer.data = POWERDOWN_FREQ;
blink_timeout(POWERDOWN_FREQ);
init_timer(&power_timer);
power_timer.function = power_timeout;
power_timer.expires = jiffies + POWERDOWN_TIMEOUT * HZ;
add_timer(&power_timer);
}
void inline ip22_volume_set(unsigned char volume)
{
sgi_volume = volume;
hpc3c0->pbus_extregs[2][0] = sgi_volume;
hpc3c0->pbus_extregs[2][1] = sgi_volume;
}
void inline ip22_volume_get(unsigned char *volume)
{
*volume = sgi_volume;
}
static inline void volume_up_button(unsigned long data)
{
del_timer(&volume_timer);
if (sgi_volume < 0xff)
sgi_volume++;
hpc3c0->pbus_extregs[2][0] = sgi_volume;
hpc3c0->pbus_extregs[2][1] = sgi_volume;
if (ioc_icontrol->istat1 & 2) {
volume_timer.expires = jiffies + 1;
add_timer(&volume_timer);
}
}
static inline void volume_down_button(unsigned long data)
{
del_timer(&volume_timer);
if (sgi_volume > 0)
sgi_volume--;
hpc3c0->pbus_extregs[2][0] = sgi_volume;
hpc3c0->pbus_extregs[2][1] = sgi_volume;
if (ioc_icontrol->istat1 & 2) {
volume_timer.expires = jiffies + 1;
add_timer(&volume_timer);
}
}
static void panel_int(int irq, void *dev_id, struct pt_regs *regs)
{
unsigned int buttons;
buttons = hpc3mregs->panel;
hpc3mregs->panel = 3; /* power_interrupt | power_supply_on */
if (ioc_icontrol->istat1 & 2) { /* Wait until interrupt goes away */
disable_irq(9);
init_timer(&debounce_timer);
debounce_timer.function = debounce;
debounce_timer.expires = jiffies + 5;
add_timer(&debounce_timer);
}
if (!(buttons & 2)) /* Power button was pressed */
power_button();
if (!(buttons & 0x40)) { /* Volume up button was pressed */
init_timer(&volume_timer);
volume_timer.function = volume_up_button;
volume_timer.expires = jiffies + 1;
add_timer(&volume_timer);
}
if (!(buttons & 0x10)) { /* Volume down button was pressed */
init_timer(&volume_timer);
volume_timer.function = volume_down_button;
volume_timer.expires = jiffies + 1;
add_timer(&volume_timer);
}
}
static int panic_event(struct notifier_block *this, unsigned long event,
void *ptr)
{
if (has_paniced)
return NOTIFY_DONE;
has_paniced = 1;
blink_timer.data = PANIC_FREQ;
blink_timeout(PANIC_FREQ);
return NOTIFY_DONE;
}
static struct notifier_block panic_block = {
panic_event,
NULL,
0
};
void ip22_reboot_setup(void)
{
static int setup_done;
if (setup_done)
return;
setup_done = 1;
request_irq(9, panel_int, 0, "Front Panel", NULL);
init_timer(&blink_timer);
blink_timer.function = blink_timeout;
notifier_chain_register(&panic_notifier_list, &panic_block);
}
arch/mips64/sgi-ip22/ip22-sc.c deleted 100644 → 0
View file @ f19e2d9e
/*
* indy_sc.c: Indy cache management functions.
*
* Copyright (C) 1997 Ralf Baechle (ralf@gnu.org),
* derived from r4xx0.c by David S. Miller (dm@engr.sgi.com).
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <asm/bcache.h>
#include <asm/sgi/sgimc.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/bootinfo.h>
#include <asm/mmu_context.h>
/* Secondary cache size in bytes, if present. */
static unsigned long scache_size;
#undef DEBUG_CACHE
#define SC_SIZE 0x00080000
#define SC_LINE 32
#define CI_MASK (SC_SIZE - SC_LINE)
#define SC_INDEX(n) ((n) & CI_MASK)
static inline void indy_sc_wipe(unsigned long first, unsigned long last)
{
__asm__ __volatile__(
".set\tnoreorder\n\t"
"or\t%0, %4\t\t\t# first line to flush\n\t"
"or\t%1, %4\t\t\t# last line to flush\n"
"1:\tsw $0, 0(%0)\n\t"
"bne\t%0, %1, 1b\n\t"
"daddu\t%0, 32\n\t"
".set reorder"
: "=r" (first), "=r" (last)
: "0" (first), "1" (last), "r" (0x9000000080000000)
: "$1");
}
static void indy_sc_wback_invalidate(unsigned long addr, unsigned long size)
{
unsigned long first_line, last_line;
unsigned int flags;
#ifdef DEBUG_CACHE
printk("indy_sc_wback_invalidate[%08lx,%08lx]", addr, size);
#endif
if (!size)
return;
/* Which lines to flush? */
first_line = SC_INDEX(addr);
last_line = SC_INDEX(addr + size - 1);
local_irq_save(flags);
if (first_line <= last_line) {
indy_sc_wipe(first_line, last_line);
goto out;
}
indy_sc_wipe(first_line, SC_SIZE - SC_LINE);
indy_sc_wipe(0, last_line);
out:
local_irq_restore(flags);
}
static void inline indy_sc_enable(void)
{
#ifdef DEBUG_CACHE
printk("Enabling R4600 SCACHE\n");
#endif
*(volatile unsigned char *) 0x9000000080000000 = 0;
}
static void indy_sc_disable(void)
{
#ifdef DEBUG_CACHE
printk("Disabling R4600 SCACHE\n");
#endif
*(volatile unsigned short *) 0x9000000080000000 = 0;
}
static inline __init int indy_sc_probe(void)
{
volatile u32 *cpu_control;
unsigned short cmd = 0xc220;
unsigned long data = 0;
int i, n;
#ifdef __MIPSEB__
cpu_control = (volatile u32 *) KSEG1ADDR(0x1fa00034);
#else
cpu_control = (volatile u32 *) KSEG1ADDR(0x1fa00030);
#endif
#define DEASSERT(bit) (*(cpu_control) &= (~(bit)))
#define ASSERT(bit) (*(cpu_control) |= (bit))
#define DELAY for(n = 0; n < 100000; n++) __asm__ __volatile__("")
DEASSERT(SGIMC_EEPROM_PRE);
DEASSERT(SGIMC_EEPROM_SDATAO);
DEASSERT(SGIMC_EEPROM_SECLOCK);
DEASSERT(SGIMC_EEPROM_PRE);
DELAY;
ASSERT(SGIMC_EEPROM_CSEL); ASSERT(SGIMC_EEPROM_SECLOCK);
for(i = 0; i < 11; i++) {
if(cmd & (1<<15))
ASSERT(SGIMC_EEPROM_SDATAO);
else
DEASSERT(SGIMC_EEPROM_SDATAO);
DEASSERT(SGIMC_EEPROM_SECLOCK);
ASSERT(SGIMC_EEPROM_SECLOCK);
cmd <<= 1;
}
DEASSERT(SGIMC_EEPROM_SDATAO);
for(i = 0; i < (sizeof(unsigned short) * 8); i++) {
unsigned int tmp;
DEASSERT(SGIMC_EEPROM_SECLOCK);
DELAY;
ASSERT(SGIMC_EEPROM_SECLOCK);
DELAY;
data <<= 1;
tmp = *cpu_control;
if(tmp & SGIMC_EEPROM_SDATAI)
data |= 1;
}
DEASSERT(SGIMC_EEPROM_SECLOCK);
DEASSERT(SGIMC_EEPROM_CSEL);
ASSERT(SGIMC_EEPROM_PRE);
ASSERT(SGIMC_EEPROM_SECLOCK);
data <<= PAGE_SHIFT;
if (data == 0)
return 0;
scache_size = data;
printk("R4600/R5000 SCACHE size %ldK, linesize 32 bytes.\n",
scache_size >> 10);
return 1;
}
/* XXX Check with wje if the Indy caches can differenciate between
writeback + invalidate and just invalidate. */
static struct bcache_ops indy_sc_ops = {
indy_sc_enable,
indy_sc_disable,
indy_sc_wback_invalidate,
indy_sc_wback_invalidate
};
void __init indy_sc_init(void)
{
if (indy_sc_probe()) {
indy_sc_enable();
bcops = &indy_sc_ops;
}
}
arch/mips64/sgi-ip22/ip22-setup.c deleted 100644 → 0
View file @ f19e2d9e
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* SGI IP22 specific setup.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
* Copyright (C) 1997, 1998, 1999 Ralf Baechle (ralf@gnu.org)
* Copyright (C) 1999 Silcon Graphics, Inc.
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/kbd_ll.h>
#include <linux/kernel.h>
#include <linux/kdev_t.h>
#include <linux/types.h>
#include <linux/console.h>
#include <linux/sched.h>
#include <linux/mc146818rtc.h>
#include <linux/pc_keyb.h>
#include <linux/tty.h>
#include <asm/addrspace.h>
#include <asm/mmu_context.h>
#include <asm/bcache.h>
#include <asm/keyboard.h>
#include <asm/irq.h>
#include <asm/sgialib.h>
#include <asm/sgi/sgi.h>
#include <asm/sgi/sgimc.h>
#include <asm/sgi/sgihpc.h>
#include <asm/sgi/sgint23.h>
extern struct rtc_ops indy_rtc_ops;
extern void ip22_reboot_setup(void);
extern void ip22_volume_set(unsigned char);
#define sgi_kh ((struct hpc_keyb *) (KSEG1 + 0x1fbd9800 + 64))
#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
static void ip22_request_region(void)
{
/* No I/O ports are being used on the Indy. */
}
static int ip22_request_irq(void (*handler)(int, void *, struct pt_regs *))
{
/* Dirty hack, this get's called as a callback from the keyboard
driver. We piggyback the initialization of the front panel
button handling on it even though they're technically not
related with the keyboard driver in any way. Doing it from
indy_setup wouldn't work since kmalloc isn't initialized yet. */
ip22_reboot_setup();
return request_irq(SGI_KEYBOARD_IRQ, handler, 0, "keyboard", NULL);
}
static int ip22_aux_request_irq(void (*handler)(int, void *, struct pt_regs *))
{
/* Nothing to do, interrupt is shared with the keyboard hw */
return 0;
}
static void ip22_aux_free_irq(void)
{
/* Nothing to do, interrupt is shared with the keyboard hw */
}
static unsigned char ip22_read_input(void)
{
return sgi_kh->data;
}
static void ip22_write_output(unsigned char val)
{
int status;
do {
status = sgi_kh->command;
} while (status & KBD_STAT_IBF);
sgi_kh->data = val;
}
static void ip22_write_command(unsigned char val)
{
int status;
do {
status = sgi_kh->command;
} while (status & KBD_STAT_IBF);
sgi_kh->command = val;
}
static unsigned char ip22_read_status(void)
{
return sgi_kh->command;
}
struct kbd_ops sgi_kbd_ops = {
ip22_request_region,
ip22_request_irq,
ip22_aux_request_irq,
ip22_aux_free_irq,
ip22_read_input,
ip22_write_output,
ip22_write_command,
ip22_read_status
};
int __init page_is_ram(unsigned long pagenr)
{
if ((pagenr<<PAGE_SHIFT) < 0x2000UL)
return 1;
if ((pagenr<<PAGE_SHIFT) > 0x08002000)
return 1;
return 0;
}
void __init ip22_setup(void)
{
#ifdef CONFIG_SERIAL_CONSOLE
char *ctype;
#endif
TLBMISS_HANDLER_SETUP();
/* Init the INDY HPC I/O controller. Need to call this before
* fucking with the memory controller because it needs to know the
* boardID and whether this is a Guiness or a FullHouse machine.
*/
sgihpc_init();
/* Init INDY memory controller. */
sgimc_init();
/* Now enable boardcaches, if any. */
indy_sc_init();
#ifdef CONFIG_SERIAL_CONSOLE
/* ARCS console environment variable is set to "g?" for
* graphics console, it is set to "d" for the first serial
* line and "d2" for the second serial line.
*/
ctype = ArcGetEnvironmentVariable("console");
if(*ctype == 'd') {
if(*(ctype+1)=='2')
console_setup ("ttyS1");
else
console_setup ("ttyS0");
}
#endif
#ifdef CONFIG_ARC_CONSOLE
console_setup("ttyS0");
#endif
ip22_volume_set(simple_strtoul(ArcGetEnvironmentVariable("volume"),
NULL, 10));
#ifdef CONFIG_VT
#ifdef CONFIG_SGI_NEWPORT_CONSOLE
conswitchp = &newport_con;
screen_info = (struct screen_info) {
0, 0, /* orig-x, orig-y */
0, /* unused */
0, /* orig_video_page */
0, /* orig_video_mode */
160, /* orig_video_cols */
0, 0, 0, /* unused, ega_bx, unused */
64, /* orig_video_lines */
0, /* orig_video_isVGA */
16 /* orig_video_points */
};
#else
conswitchp = &dummy_con;
#endif
#endif
rtc_ops = &indy_rtc_ops;
kbd_ops = &sgi_kbd_ops;
#ifdef CONFIG_PSMOUSE
aux_device_present = 0xaa;
#endif
#ifdef CONFIG_VIDEO_VINO
init_vino();
#endif
}
arch/mips64/sgi-ip22/ip22-timer.c deleted 100644 → 0
View file @ f19e2d9e
/*
* indy_timer.c: Setting up the clock on the INDY 8254 controller.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
* Copytight (C) 1997, 1998 Ralf Baechle (ralf@gnu.org)
*/
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/time.h>
#include <linux/interrupt.h>
#include <linux/timex.h>
#include <linux/kernel_stat.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/sgi/sgi.h>
#include <asm/sgi/sgihpc.h>
#include <asm/sgi/sgint23.h>
#include <asm/sgialib.h>
/* Because of a bug in the i8254 timer we need to use the onchip r4k
* counter as our system wide timer interrupt running at 100HZ.
*/
static unsigned long r4k_offset; /* Amount to increment compare reg each time */
static unsigned long r4k_cur; /* What counter should be at next timer irq */
static inline void ack_r4ktimer(unsigned long newval)
{
write_32bit_cp0_register(CP0_COMPARE, newval);
}
static int set_rtc_mmss(unsigned long nowtime)
{
struct indy_clock *clock = (struct indy_clock *)INDY_CLOCK_REGS;
int retval = 0;
int real_seconds, real_minutes, clock_minutes;
#define FROB_FROM_CLOCK(x) (((x) & 0xf) | ((((x) & 0xf0) >> 4) * 10));
#define FROB_TO_CLOCK(x) ((((((x) & 0xff) / 10)<<4) | (((x) & 0xff) % 10)) & 0xff)
clock->cmd &= ~(0x80);
clock_minutes = clock->min;
clock->cmd |= (0x80);
clock_minutes = FROB_FROM_CLOCK(clock_minutes);
real_seconds = nowtime % 60;
real_minutes = nowtime / 60;
if(((abs(real_minutes - clock_minutes) + 15)/30) & 1)
real_minutes += 30; /* correct for half hour time zone */
real_minutes %= 60;
if(abs(real_minutes - clock_minutes) < 30) {
/* Force clock oscillator to be on. */
clock->month &= ~(0x80);
/* Write real_seconds and real_minutes into the Dallas. */
clock->cmd &= ~(0x80);
clock->sec = real_seconds;
clock->min = real_minutes;
clock->cmd |= (0x80);
} else
return -1;
#undef FROB_FROM_CLOCK
#undef FROB_TO_CLOCK
return retval;
}
static long last_rtc_update;
unsigned long missed_heart_beats;
void indy_timer_interrupt(struct pt_regs *regs)
{
unsigned long count;
int irq = 7;
write_seqlock(&xtime_lock);
/* Ack timer and compute new compare. */
count = read_32bit_cp0_register(CP0_COUNT);
/* This has races. */
if ((count - r4k_cur) >= r4k_offset) {
/* If this happens to often we'll need to compensate. */
missed_heart_beats++;
r4k_cur = count + r4k_offset;
}
else
r4k_cur += r4k_offset;
ack_r4ktimer(r4k_cur);
kstat_cpu(0).irqs[irq]++;
do_timer(regs);
/* We update the Dallas time of day approx. every 11 minutes,
* because of how the numbers work out we need to make
* absolutely sure we do this update within 500ms before the
* next second starts, thus the following code.
*/
if ((time_status & STA_UNSYNC) == 0 &&
xtime.tv_sec > last_rtc_update + 660 &&
xtime.tv_usec >= 500000 - (tick >> 1) &&
xtime.tv_usec <= 500000 + (tick >> 1)) {
if (set_rtc_mmss(xtime.tv_sec) == 0)
last_rtc_update = xtime.tv_sec;
else
/* do it again in 60s */
last_rtc_update = xtime.tv_sec - 600;
}
write_sequnlock(&xtime_lock);
}
static unsigned long dosample(volatile unsigned char *tcwp,
volatile unsigned char *tc2p)
{
unsigned long ct0, ct1;
unsigned char msb, lsb;
/* Start the counter. */
*tcwp = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL | SGINT_TCWORD_MRGEN);
*tc2p = (SGINT_TCSAMP_COUNTER & 0xff);
*tc2p = (SGINT_TCSAMP_COUNTER >> 8);
/* Get initial counter invariant */
ct0 = read_32bit_cp0_register(CP0_COUNT);
/* Latch and spin until top byte of counter2 is zero */
do {
*tcwp = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CLAT);
lsb = *tc2p;
msb = *tc2p;
ct1 = read_32bit_cp0_register(CP0_COUNT);
} while(msb);
/* Stop the counter. */
*tcwp = (SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL | SGINT_TCWORD_MSWST);
/* Return the difference, this is how far the r4k counter increments
* for every one HZ.
*/
return ct1 - ct0;
}
static unsigned long __init get_indy_time(void)
{
struct indy_clock *clock = (struct indy_clock *)INDY_CLOCK_REGS;
unsigned int year, mon, day, hour, min, sec;
/* Freeze it. */
clock->cmd &= ~(0x80);
/* Read regs. */
sec = clock->sec;
min = clock->min;
hour = (clock->hr & 0x3f);
day = (clock->date & 0x3f);
mon = (clock->month & 0x1f);
year = clock->year;
/* Unfreeze clock. */
clock->cmd |= 0x80;
/* Frob the bits. */
#define FROB1(x) (((x) & 0xf) + ((((x) & 0xf0) >> 4) * 10));
#define FROB2(x) (((x) & 0xf) + (((((x) & 0xf0) >> 4) & 0x3) * 10));
/* XXX Should really check that secs register is the same
* XXX as when we first read it and if not go back and
* XXX read the regs above again.
*/
sec = FROB1(sec); min = FROB1(min); day = FROB1(day);
mon = FROB1(mon); year = FROB1(year);
hour = FROB2(hour);
#undef FROB1
#undef FROB2
/* Wheee... */
if(year < 45)
year += 30;
if ((year += 1940) < 1970)
year += 100;
return mktime(year, mon, day, hour, min, sec);
}
#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
void __init indy_timer_init(void)
{
struct sgi_ioc_timers *p;
volatile unsigned char *tcwp, *tc2p;
/* Figure out the r4k offset, the algorithm is very simple and works
* in _all_ cases as long as the 8254 counter register itself works ok
* (as an interrupt driving timer it does not because of bug, this is
* why we are using the onchip r4k counter/compare register to serve
* this purpose, but for r4k_offset calculation it will work ok for us).
* There are other very complicated ways of performing this calculation
* but this one works just fine so I am not going to futz around. ;-)
*/
p = ioc_timers;
tcwp = &p->tcword;
tc2p = &p->tcnt2;
printk("calculating r4koff... ");
dosample(tcwp, tc2p); /* First sample. */
dosample(tcwp, tc2p); /* Eat one. */
r4k_offset = dosample(tcwp, tc2p); /* Second sample. */
printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
r4k_cur = (read_32bit_cp0_register(CP0_COUNT) + r4k_offset);
write_32bit_cp0_register(CP0_COMPARE, r4k_cur);
set_cp0_status(ST0_IM, ALLINTS);
sti();
write_seqlock_irq(&xtime_lock);
xtime.tv_sec = get_indy_time(); /* Read time from RTC. */
xtime.tv_usec = 0;
write_sequnlock_irq(&xtime_lock);
}
void indy_8254timer_irq(void)
{
int cpu = smp_processor_id();
int irq = 4;
irq_enter(cpu, irq);
kstat_cpu(0).irqs[irq]++;
panic("indy_8254timer_irq: Whoops, should not have gotten this IRQ\n");
irq_exit(cpu, irq);
}
void do_gettimeofday(struct timeval *tv)
{
unsigned long seq;
do {
seq = read_seqbegin(&xtime_lock);
*tv = xtime;
} while (read_seqretry(&xtime_lock, seq));
}
void do_settimeofday(struct timeval *tv)
{
write_seqlock_irq(&xtime_lock);
xtime = *tv;
time_adjust = 0; /* stop active adjtime() */
time_status |= STA_UNSYNC;
time_maxerror = NTP_PHASE_LIMIT;
time_esterror = NTP_PHASE_LIMIT;
write_sequnlock_irq(&xtime_lock);
}
arch/mips64/sgi-ip22/system.c deleted 100644 → 0
View file @ f19e2d9e
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* system.c: Probe the system type using ARCS prom interface library.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
* Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org)
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/string.h>
#include <asm/sgi/sgi.h>
#include <asm/sgialib.h>
#include <asm/bootinfo.h>
struct smatch {
char *name;
int type;
};
static struct smatch sgi_cputable[] = {
{ "MIPS-R2000", CPU_R2000 },
{ "MIPS-R3000", CPU_R3000 },
{ "MIPS-R3000A", CPU_R3000A },
{ "MIPS-R4000", CPU_R4000SC },
{ "MIPS-R4400", CPU_R4400SC },
{ "MIPS-R4600", CPU_R4600 },
{ "MIPS-R8000", CPU_R8000 },
{ "MIPS-R5000", CPU_R5000 },
{ "MIPS-R5000A", CPU_R5000A }
};
#define NUM_CPUS 9 /* for now */
static int __init string_to_cpu(char *s)
{
int i;
for(i = 0; i < NUM_CPUS; i++) {
if(!strcmp(s, sgi_cputable[i].name))
return sgi_cputable[i].type;
}
panic("\nYeee, could not determine MIPS cpu type <%s>", s);
return 0;
}
/*
* We' call this early before loadmmu(). If we do the other way around
* the firmware will crash and burn.
*/
void __init sgi_sysinit(void)
{
pcomponent *p, *toplev, *cpup = 0;
int cputype = -1;
/* The root component tells us what machine architecture we
* have here.
*/
p = ArcGetChild(PROM_NULL_COMPONENT);
/* Now scan for cpu(s). */
toplev = p = ArcGetChild(p);
while(p) {
int ncpus = 0;
if(p->type == Cpu) {
if (++ncpus > 1)
panic("\nYeee, SGI MP not ready yet");
printk("CPU: %s ", p->iname);
cpup = p;
cputype = string_to_cpu(cpup->iname);
}
p = ArcGetPeer(p);
}
if (cputype == -1) {
panic("\nYeee, could not find cpu ARCS component");
}
p = ArcGetChild(cpup);
while(p) {
switch(p->class) {
case processor:
switch(p->type) {
case Fpu:
printk("FPU<%s> ", p->iname);
break;
default:
break;
};
break;
case cache:
switch(p->type) {
case picache:
printk("ICACHE ");
break;
case pdcache:
printk("DCACHE ");
break;
case sccache:
printk("SCACHE ");
break;
default:
break;
};
break;
default:
break;
};
p = ArcGetPeer(p);
}
printk("\n");
}
arch/mips64/sgi-ip22/time.c deleted 100644 → 0
View file @ f19e2d9e
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* time.c: Generic SGI time_init() code, this will dispatch to the
* appropriate per-architecture time/counter init code.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
*/
#include <linux/init.h>
extern void indy_timer_init(void);
void __init time_init(void)
{
/* XXX assume INDY for now XXX */
indy_timer_init();
}
include/asm-mips/ng1hw.h
View file @ 2395133b
/* $Id: ng1hw.h,v 1.4 1999/08/04 06:01:51 ulfc Exp $
*
/*
* ng1hw.h: Tweaks the newport.h structures and definitions to be compatible
* with IRIX. Quite ugly, but it works.
*
* Copyright (C) 1999 Ulf Carlsson (ulfc@thepuffingroup.com)
*
*/
#ifndef _SGI_NG1HW_H
#define _SGI_NG1HW_H
......@@ -77,7 +74,7 @@ typedef struct rex3chip Rex3chip;
#define DM0_XYOFFSET NPORT_DMODE0_XYOFF
#define DM0_CICLAMP NPORT_DMODE0_CLAMP
#define DM0_ENDPTFILTER NPORT_DMODE0_ENDPF
#define DM0_YSTRIDE NPORT_DMODE0_YSTR
#define DM0_YSTRIDE NPORT_DMODE0_YSTR
#define DM1_PLANES_SHIFT 0
/* The rest of the DM1 planes defines are in newport.h */
......@@ -119,7 +116,7 @@ typedef struct rex3chip Rex3chip;
#define DM1_SF_SHIFT 19
#define DM1_SF_MASK NPORT_DMODE1_SFMASK
#define DM1_SF NPORT_DMODE1_SFMASK
#define DM1_SF NPORT_DMODE1_SFMASK
#define DM1_SF_ZERO NPORT_DMODE1_SF0
#define DM1_SF_ONE NPORT_DMODE1_SF1
#define DM1_SF_DC NPORT_DMODE1_SFDC
......@@ -128,8 +125,8 @@ typedef struct rex3chip Rex3chip;
#define DM1_SF_MSA NPORT_DMODE1_SFMSA
#define DM1_DF_SHIFT 22 /* dfactor(2:0) */
#define DM1_DF_MASK NPORT_DMODE1_DFMASK
#define DM1_DF NPORT_DMODE1_DFMASK
#define DM1_DF_MASK NPORT_DMODE1_DFMASK
#define DM1_DF NPORT_DMODE1_DFMASK
#define DM1_DF_ZERO NPORT_DMODE1_DF0
#define DM1_DF_ONE NPORT_DMODE1_DF1
#define DM1_DF_SC NPORT_DMODE1_DFSC
......@@ -177,23 +174,23 @@ typedef struct rex3chip Rex3chip;
#define VRINT NPORT_STAT_VRINT
#define VIDEOINT NPORT_STAT_VIDINT
#define GFIFO_LEVEL_SHIFT 7
#define GFIFO_LEVEL_MASK NPORT_STAT_GLMSK
#define GFIFO_LEVEL_MASK NPORT_STAT_GLMSK
#define BFIFO_LEVEL_SHIFT 13
#define BFIFO_LEVEL_MASK NPORT_STAT_BLMSK
#define BFIFO_LEVEL_MASK NPORT_STAT_BLMSK
#define BFIFO_INT NPORT_STAT_BFIRQ
#define GFIFO_INT NPORT_STAT_GFIRQ
#define GIO32MODE NPORT_CFG_G32MD
#define GIO32MODE NPORT_CFG_G32MD
#define BUSWIDTH NPORT_CFG_BWIDTH
#define EXTREGXCVR NPORT_CFG_ERCVR
#define EXTREGXCVR NPORT_CFG_ERCVR
#define BFIFODEPTH_SHIFT 3
#define BFIFODEPTH_MASK NPORT_CFG_BDMSK
#define BFIFOABOVEINT NPORT_CFG_BFAINT
#define GFIFODEPTH_SHIFT 8
#define GFIFODEPTH_MASK NPORT_CFG_GDMSK
#define GFIFODEPTH_MASK NPORT_CFG_GDMSK
#define GFIFOABOVEINT NPORT_CFG_GFAINT
#define TIMEOUT_SHIFT 14
#define TIMEOUT_MASK NPORT_CFG_TOMSK
#define TIMEOUT_MASK NPORT_CFG_TOMSK
#define VREFRESH_SHIFT 17
#define VREFRESH_MASK NPORT_CFG_VRMSK
#define FB_TYPE NPORT_CFG_FBTYP
......
include/asm-mips/rrm.h deleted 100644 → 0
View file @ f19e2d9e
/*
* SGI Rendering Resource Manager API (?).
*
* written by Miguel de Icaza (miguel@nuclecu.unam.mx)
*
* Ok, even if SGI choosed to do mmap trough ioctls, their
* kernel support for virtualizing the graphics card is nice.
*
* We should be able to make graphic applications on Linux
* fly.
*
* This header file should be included from GNU libc as well.
*/
/* Why like this you say? Well, gdb can print enums */
#define RRM_BASE 1000
#define RRM_CMD_LIMIT (RRM_BASE + 100)
enum {
RRM_OPENRN = RRM_BASE, /* open rendering node */
RRM_CLOSERN,
RRM_BINDPROCTORN, /* set current rendering region for node */
RRM_BINDRNTOCLIP,
RRM_UNBINDRNFROMCLIP,
RRM_SWAPBUF,
RRM_SETSWAPINTERVAL,
RRM_WAITFORRETRACE,
RRM_SETDISPLAYMODE,
RRM_MESSAGE,
RRM_INVALIDATERN,
RRM_VALIDATECLIP,
RRM_VALIDATESWAPBUF,
RRM_SWAPGROUP,
RRM_SWAPUNGROUP,
RRM_VALIDATEMESSAGE,
RRM_GETDISPLAYMODES,
RRM_LOADDISPLAYMODE,
RRM_CUSHIONBUFFER,
RRM_SWAPREADY,
RRM_MGR_SWAPBUF,
RRM_SETVSYNC,
RRM_GETVSYNC,
RRM_WAITVSYNC,
RRM_BINDRNTOREADANDCLIP,
RRM_MAPCLIPTOSWPBUFID
};
/* Parameters for the above ioctls
*
* All of the ioctls take as their first argument the rendering node id.
*
*/
/*
* RRM_OPENRN:
*
* This is called by the IRIX X server with:
* rnid = 0xffffffff rmask = 0
*
* Returns a number like this: 0x10001.
* If you run the X server over and over, you get a value
* that is of the form (n * 0x10000) + 1.
*
* The return value seems to be the RNID.
*/
struct RRM_OpenRN {
int rnid;
unsigned int rmask;
};
struct RRM_CloseRN {
int rnid;
};
/*
* RRM_BINDPROCTORN:
*
* Return value when the X server calls it: 0
*/
struct RRM_BindProcToRN {
int rnid;
};
#ifdef __KERNEL__
int rrm_command (unsigned int cmd, void *arg);
int rrm_close (struct inode *inode, struct file *file);
#endif
include/asm-mips/sgi/gio.h 0 → 100644
View file @ 2395133b
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* gio.h: Definitions for SGI GIO bus
*
* Copyright (C) 2002 Ladislav Michl
*/
#ifndef _SGI_GIO_H
#define _SGI_GIO_H
/*
* GIO bus addresses
*
* The Indigo and Indy have two GIO bus connectors. Indigo2 (all models) have
* three physical connectors, but only two slots, GFX and EXP0.
*
* There is 10MB of GIO address space for GIO64 slot devices
* slot# slot type address range size
* ----- --------- ----------------------- -----
* 0 GFX 0x1f000000 - 0x1f3fffff 4MB
* 1 EXP0 0x1f400000 - 0x1f5fffff 2MB
* 2 EXP1 0x1f600000 - 0x1f9fffff 4MB
*
* There are un-slotted devices, HPC, I/O and misc devices, which are grouped
* into the HPC address space.
* - MISC 0x1fb00000 - 0x1fbfffff 1MB
*
* Following space is reserved and unused
* - RESERVED 0x18000000 - 0x1effffff 112MB
*
* GIO bus IDs
*
* Each GIO bus device identifies itself to the system by answering a
* read with an "ID" value. IDs are either 8 or 32 bits long. IDs less
* than 128 are 8 bits long, with the most significant 24 bits read from
* the slot undefined.
*
* 32-bit IDs are divided into
* bits 0:6 the product ID; ranges from 0x00 to 0x7F.
* bit 7 0=GIO Product ID is 8 bits wide
* 1=GIO Product ID is 32 bits wide.
* bits 8:15 manufacturer version for the product.
* bit 16 0=GIO32 and GIO32-bis, 1=GIO64.
* bit 17 0=no ROM present
* 1=ROM present on this board AND next three words
* space define the ROM.
* bits 18:31 up to manufacturer.
*
* IDs above 0x50/0xd0 are of 3rd party boards.
*
* 8-bit IDs
* 0x01 XPI low cost FDDI
* 0x02 GTR TokenRing
* 0x04 Synchronous ISDN
* 0x05 ATM board [*]
* 0x06 Canon Interface
* 0x07 16 bit SCSI Card [*]
* 0x08 JPEG (Double Wide)
* 0x09 JPEG (Single Wide)
* 0x0a XPI mez. FDDI device 0
* 0x0b XPI mez. FDDI device 1
* 0x0c SMPTE 259M Video [*]
* 0x0d Babblefish Compression [*]
* 0x0e E-Plex 8-port Ethernet
* 0x30 Lyon Lamb IVAS
* 0xb8 GIO 100BaseTX Fast Ethernet (gfe)
*
* [*] Device provide 32-bit ID.
*
*/
#define GIO_ID(x) (x & 0x7f)
#define GIO_32BIT_ID 0x80
#define GIO_REV(x) ((x >> 8) & 0xff)
#define GIO_64BIT_IFACE 0x10000
#define GIO_ROM_PRESENT 0x20000
#define GIO_VENDOR_CODE(x) ((x >> 18) & 0x3fff)
#define GIO_SLOT_GFX_BASE 0x1f000000
#define GIO_SLOT_EXP0_BASE 0x1f400000
#define GIO_SLOT_EXP1_BASE 0x1f600000
#endif /* _SGI_GIO_H */
include/asm-mips64/sgi/sgihpc.h → include/asm-mips/sgi/hpc3.h
View file @ 2395133b
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* sgihpc.h: Various HPC I/O controller defines. The HPC is basically
* the approximate functional equivalent of the Sun SYSIO
* on SGI INDY machines.
* hpc3.h: Definitions for SGI HPC3 controller
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
* Copyright (C) 1998 Ralf Baechle (ralf@gnu.org)
* Copyright (C) 1996 David S. Miller
* Copyright (C) 1998 Ralf Baechle
*/
#ifndef _ASM_SGI_SGIHPC_H
#define _ASM_SGI_SGIHPC_H
#include <asm/page.h>
#ifndef _SGI_HPC3_H
#define _SGI_HPC3_H
extern int sgi_has_ioc2; /* to know if we have older ioc1 or ioc2. */
extern int sgi_guiness; /* GUINESS or FULLHOUSE machine. */
extern int sgi_boardid; /* Board revision. */
#include <linux/types.h>
#include <asm/page.h>
/* An HPC dma descriptor. */
/* An HPC DMA descriptor. */
struct hpc_dma_desc {
int pbuf; /* physical address of data buffer */
int cntinfo; /* counter and info bits */
#define HPCDMA_EOX 0x80000000 /* last desc in chain for tx */
#define HPCDMA_EOR 0x80000000 /* last desc in chain for rx */
#define HPCDMA_EOXP 0x40000000 /* end of packet for tx */
#define HPCDMA_EORP 0x40000000 /* end of packet for rx */
#define HPCDMA_XIE 0x20000000 /* irq generated when at end of this desc */
#define HPCDMA_XIU 0x01000000 /* Tx buffer in use by CPU. */
#define HPCDMA_EIPC 0x00ff0000 /* SEEQ ethernet special xternal bytecount */
#define HPCDMA_ETXD 0x00008000 /* set to one by HPC when packet tx'd */
#define HPCDMA_OWN 0x00004000 /* Denotes ring buffer ownership on rx */
#define HPCDMA_BCNT 0x00003fff /* size in bytes of this dma buffer */
int pnext; /* paddr of next hpc_dma_desc if any */
u32 pbuf; /* physical address of data buffer */
u32 cntinfo; /* counter and info bits */
#define HPCDMA_EOX 0x80000000 /* last desc in chain for tx */
#define HPCDMA_EOR 0x80000000 /* last desc in chain for rx */
#define HPCDMA_EOXP 0x40000000 /* end of packet for tx */
#define HPCDMA_EORP 0x40000000 /* end of packet for rx */
#define HPCDMA_XIE 0x20000000 /* irq generated when at end of this desc */
#define HPCDMA_XIU 0x01000000 /* Tx buffer in use by CPU. */
#define HPCDMA_EIPC 0x00ff0000 /* SEEQ ethernet special xternal bytecount */
#define HPCDMA_ETXD 0x00008000 /* set to one by HPC when packet tx'd */
#define HPCDMA_OWN 0x00004000 /* Denotes ring buffer ownership on rx */
#define HPCDMA_BCNT 0x00003fff /* size in bytes of this dma buffer */
u32 pnext; /* paddr of next hpc_dma_desc if any */
};
typedef volatile unsigned int hpcreg;
/* HPC1 stuff. */
/* HPC3 stuff. */
/* The set of regs for each HPC3 pbus dma channel. */
/* The set of regs for each HPC3 PBUS DMA channel. */
struct hpc3_pbus_dmacregs {
hpcreg pbdma_bptr; /* pbus dma channel buffer ptr */
hpcreg pbdma_dptr; /* pbus dma channel desc ptr */
char _unused1[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */
hpcreg pbdma_ctrl; /* pbus dma channel control reg */
#define HPC3_PDMACTRL_SEL 0x00000002 /* little endian transfer */
#define HPC3_PDMACTRL_RCV 0x00000004 /* direction is receive */
#define HPC3_PDMACTRL_FLSH 0x00000008 /* enable flush for receive DMA */
#define HPC3_PDMACTRL_ACT 0x00000010 /* start dma transfer */
#define HPC3_PDMACTRL_LD 0x00000020 /* load enable for ACT */
#define HPC3_PDMACTRL_RT 0x00000040 /* Use realtime GIO bus servicing */
#define HPC3_PDMACTRL_HW 0x0000ff00 /* DMA High-water mark */
#define HPC3_PDMACTRL_FB 0x003f0000 /* Ptr to beginning of fifo */
#define HPC3_PDMACTRL_FE 0x3f000000 /* Ptr to end of fifo */
char _unused2[PAGE_SIZE - (sizeof(hpcreg))]; /* padding */
volatile u32 pbdma_bptr; /* pbus dma channel buffer ptr */
volatile u32 pbdma_dptr; /* pbus dma channel desc ptr */
u32 _unused0[0x1000/4 - 2]; /* padding */
volatile u32 pbdma_ctrl; /* pbus dma channel control register has
* copletely different meaning for read
* compared with write */
/* read */
#define HPC3_PDMACTRL_INT 0x00000001 /* interrupt (cleared after read) */
#define HPC3_PDMACTRL_ISACT 0x00000002 /* channel active */
/* write */
#define HPC3_PDMACTRL_SEL 0x00000002 /* little endian transfer */
#define HPC3_PDMACTRL_RCV 0x00000004 /* direction is receive */
#define HPC3_PDMACTRL_FLSH 0x00000008 /* enable flush for receive DMA */
#define HPC3_PDMACTRL_ACT 0x00000010 /* start dma transfer */
#define HPC3_PDMACTRL_LD 0x00000020 /* load enable for ACT */
#define HPC3_PDMACTRL_RT 0x00000040 /* Use realtime GIO bus servicing */
#define HPC3_PDMACTRL_HW 0x0000ff00 /* DMA High-water mark */
#define HPC3_PDMACTRL_FB 0x003f0000 /* Ptr to beginning of fifo */
#define HPC3_PDMACTRL_FE 0x3f000000 /* Ptr to end of fifo */
u32 _unused1[0x1000/4 - 1]; /* padding */
};
/* The HPC3 scsi registers, this does not include external ones. */
/* The HPC3 SCSI registers, this does not include external ones. */
struct hpc3_scsiregs {
hpcreg cbptr; /* current dma buffer ptr, diagnostic use only */
hpcreg ndptr; /* next dma descriptor ptr */
char _unused1[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */
hpcreg bcd; /* byte count info */
volatile u32 cbptr; /* current dma buffer ptr, diagnostic use only */
volatile u32 ndptr; /* next dma descriptor ptr */
u32 _unused0[0x1000/4 - 2]; /* padding */
volatile u32 bcd; /* byte count info */
#define HPC3_SBCD_BCNTMSK 0x00003fff /* bytes to transfer from/to memory */
#define HPC3_SBCD_XIE 0x00004000 /* Send IRQ when done with cur buf */
#define HPC3_SBCD_EOX 0x00008000 /* Indicates this is last buf in chain */
hpcreg ctrl; /* control register */
volatile u32 ctrl; /* control register */
#define HPC3_SCTRL_IRQ 0x01 /* IRQ asserted, either dma done or parity */
#define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */
#define HPC3_SCTRL_DIR 0x04 /* DMA direction, 1=dev2mem 0=mem2dev */
......@@ -82,9 +78,9 @@ struct hpc3_scsiregs {
#define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */
#define HPC3_SCTRL_PERR 0x80 /* Bad parity on HPC3 iface to scsi controller */
hpcreg gfptr; /* current GIO fifo ptr */
hpcreg dfptr; /* current device fifo ptr */
hpcreg dconfig; /* DMA configuration register */
volatile u32 gfptr; /* current GIO fifo ptr */
volatile u32 dfptr; /* current device fifo ptr */
volatile u32 dconfig; /* DMA configuration register */
#define HPC3_SDCFG_HCLK 0x00001 /* Enable DMA half clock mode */
#define HPC3_SDCFG_D1 0x00006 /* Cycles to spend in D1 state */
#define HPC3_SDCFG_D2 0x00038 /* Cycles to spend in D2 state */
......@@ -96,7 +92,7 @@ struct hpc3_scsiregs {
#define HPC3_SDCFG_POLL 0x08000 /* hd_dreq polarity control */
#define HPC3_SDCFG_ERLY 0x30000 /* hd_dreq behavior control bits */
hpcreg pconfig; /* PIO configuration register */
volatile u32 pconfig; /* PIO configuration register */
#define HPC3_SPCFG_P3 0x0003 /* Cycles to spend in P3 state */
#define HPC3_SPCFG_P2W 0x001c /* Cycles to spend in P2 state for writes */
#define HPC3_SPCFG_P2R 0x01e0 /* Cycles to spend in P2 state for reads */
......@@ -106,21 +102,21 @@ struct hpc3_scsiregs {
#define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */
#define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */
char _unused2[PAGE_SIZE - (6 * sizeof(hpcreg))]; /* padding */
u32 _unused1[0x1000/4 - 6]; /* padding */
};
/* SEEQ ethernet HPC3 registers, only one seeq per HPC3. */
struct hpc3_ethregs {
/* Receiver registers. */
hpcreg rx_cbptr; /* current dma buffer ptr, diagnostic use only */
hpcreg rx_ndptr; /* next dma descriptor ptr */
char _unused1[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */
hpcreg rx_bcd; /* byte count info */
volatile u32 rx_cbptr; /* current dma buffer ptr, diagnostic use only */
volatile u32 rx_ndptr; /* next dma descriptor ptr */
u32 _unused0[0x1000/4 - 2]; /* padding */
volatile u32 rx_bcd; /* byte count info */
#define HPC3_ERXBCD_BCNTMSK 0x00003fff /* bytes to be sent to memory */
#define HPC3_ERXBCD_XIE 0x20000000 /* HPC3 interrupts cpu at end of this buf */
#define HPC3_ERXBCD_EOX 0x80000000 /* flags this as end of descriptor chain */
hpcreg rx_ctrl; /* control register */
volatile u32 rx_ctrl; /* control register */
#define HPC3_ERXCTRL_STAT50 0x0000003f /* Receive status reg bits of Seeq8003 */
#define HPC3_ERXCTRL_STAT6 0x00000040 /* Rdonly irq status */
#define HPC3_ERXCTRL_STAT7 0x00000080 /* Rdonlt old/new status bit from Seeq */
......@@ -129,15 +125,15 @@ struct hpc3_ethregs {
#define HPC3_ERXCTRL_AMASK 0x00000400 /* Tells if ACTIVE inhibits PIO's to hpc3 */
#define HPC3_ERXCTRL_RBO 0x00000800 /* Receive buffer overflow if set to 1 */
hpcreg rx_gfptr; /* current GIO fifo ptr */
hpcreg rx_dfptr; /* current device fifo ptr */
hpcreg _unused2; /* padding */
hpcreg rx_reset; /* reset register */
#define HPC3_ERXRST_CRESET 0x1 /* Reset dma channel and external controller */
#define HPC3_ERXRST_CLRIRQ 0x2 /* Clear channel interrupt */
#define HPC3_ERXRST_LBACK 0x4 /* Enable diagnostic loopback mode of Seeq8003 */
volatile u32 rx_gfptr; /* current GIO fifo ptr */
volatile u32 rx_dfptr; /* current device fifo ptr */
u32 _unused1; /* padding */
volatile u32 rx_reset; /* reset register */
#define HPC3_ERXRST_CRESET 0x1 /* Reset dma channel and external controller */
#define HPC3_ERXRST_CLRIRQ 0x2 /* Clear channel interrupt */
#define HPC3_ERXRST_LBACK 0x4 /* Enable diagnostic loopback mode of Seeq8003 */
hpcreg rx_dconfig; /* DMA configuration register */
volatile u32 rx_dconfig; /* DMA configuration register */
#define HPC3_ERXDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */
#define HPC3_ERXDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */
#define HPC3_ERXDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO */
......@@ -147,36 +143,36 @@ struct hpc3_ethregs {
#define HPC3_ERXDCFG_FIRQ 0x08000 /* Another bad packet timeout enable */
#define HPC3_ERXDCFG_PTO 0x30000 /* Programmed timeout value for above two */
hpcreg rx_pconfig; /* PIO configuration register */
volatile u32 rx_pconfig; /* PIO configuration register */
#define HPC3_ERXPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */
#define HPC3_ERXPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */
#define HPC3_ERXPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */
#define HPC3_ERXPCFG_TST 0x1000 /* Diagnistic ram test feature bit */
char _unused3[PAGE_SIZE - (8 * sizeof(hpcreg))]; /* padding */
u32 _unused2[0x1000/4 - 8]; /* padding */
/* Transmitter registers. */
hpcreg tx_cbptr; /* current dma buffer ptr, diagnostic use only */
hpcreg tx_ndptr; /* next dma descriptor ptr */
char _unused4[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */
hpcreg tx_bcd; /* byte count info */
#define HPC3_ETXBCD_BCNTMSK 0x00003fff /* bytes to be read from memory */
#define HPC3_ETXBCD_ESAMP 0x10000000 /* if set, too late to add descriptor */
#define HPC3_ETXBCD_XIE 0x20000000 /* Interrupt cpu at end of cur desc */
#define HPC3_ETXBCD_EOP 0x40000000 /* Last byte of cur buf is end of packet */
#define HPC3_ETXBCD_EOX 0x80000000 /* This buf is the end of desc chain */
hpcreg tx_ctrl; /* control register */
#define HPC3_ETXCTRL_STAT30 0x0000000f /* Rdonly copy of seeq tx stat reg */
#define HPC3_ETXCTRL_STAT4 0x00000010 /* Indicate late collision occurred */
#define HPC3_ETXCTRL_STAT75 0x000000e0 /* Rdonly irq status from seeq */
#define HPC3_ETXCTRL_ENDIAN 0x00000100 /* Dma channel endian mode, 1=little 0=big */
#define HPC3_ETXCTRL_ACTIVE 0x00000200 /* DMA tx channel is active */
#define HPC3_ETXCTRL_AMASK 0x00000400 /* Indicates ACTIVE inhibits PIO's */
hpcreg tx_gfptr; /* current GIO fifo ptr */
hpcreg tx_dfptr; /* current device fifo ptr */
char _unused5[PAGE_SIZE - (4 * sizeof(hpcreg))]; /* padding */
volatile u32 tx_cbptr; /* current dma buffer ptr, diagnostic use only */
volatile u32 tx_ndptr; /* next dma descriptor ptr */
u32 _unused3[0x1000/4 - 2]; /* padding */
volatile u32 tx_bcd; /* byte count info */
#define HPC3_ETXBCD_BCNTMSK 0x00003fff /* bytes to be read from memory */
#define HPC3_ETXBCD_ESAMP 0x10000000 /* if set, too late to add descriptor */
#define HPC3_ETXBCD_XIE 0x20000000 /* Interrupt cpu at end of cur desc */
#define HPC3_ETXBCD_EOP 0x40000000 /* Last byte of cur buf is end of packet */
#define HPC3_ETXBCD_EOX 0x80000000 /* This buf is the end of desc chain */
volatile u32 tx_ctrl; /* control register */
#define HPC3_ETXCTRL_STAT30 0x0000000f /* Rdonly copy of seeq tx stat reg */
#define HPC3_ETXCTRL_STAT4 0x00000010 /* Indicate late collision occurred */
#define HPC3_ETXCTRL_STAT75 0x000000e0 /* Rdonly irq status from seeq */
#define HPC3_ETXCTRL_ENDIAN 0x00000100 /* DMA channel endian mode, 1=little 0=big */
#define HPC3_ETXCTRL_ACTIVE 0x00000200 /* DMA tx channel is active */
#define HPC3_ETXCTRL_AMASK 0x00000400 /* Indicates ACTIVE inhibits PIO's */
volatile u32 tx_gfptr; /* current GIO fifo ptr */
volatile u32 tx_dfptr; /* current device fifo ptr */
u32 _unused4[0x1000/4 - 4]; /* padding */
};
struct hpc3_regs {
......@@ -191,9 +187,8 @@ struct hpc3_regs {
/* Here are where the hpc3 fifo's can be directly accessed
* via PIO accesses. Under normal operation we never stick
* our grubby paws in here so it's just padding.
*/
char _unused1[PAGE_SIZE * 24];
* our grubby paws in here so it's just padding. */
u32 _unused0[0x18000/4];
/* HPC3 irq status regs. Due to a peculiar bug you need to
* look at two different register addresses to get at all of
......@@ -202,174 +197,120 @@ struct hpc3_regs {
* reliably report bits 9:5 of the hpc3 irq status. I told
* you it was a peculiar bug. ;-)
*/
hpcreg istat0; /* Irq status, only bits <4:0> reliable. */
#define HPC3_ISTAT_PBIMASK 0x0ff /* irq bits for pbus devs 0 --> 7 */
#define HPC3_ISTAT_SC0MASK 0x100 /* irq bit for scsi channel 0 */
#define HPC3_ISTAT_SC1MASK 0x200 /* irq bit for scsi channel 1 */
hpcreg gio64_misc; /* GIO64 misc control bits. */
#define HPC3_GIOMISC_ERTIME 0x1 /* Enable external timer real time. */
#define HPC3_GIOMISC_DENDIAN 0x2 /* dma descriptor endian, 1=lit 0=big */
hpcreg eeprom_data; /* EEPROM data reg. */
#define HPC3_EEPROM_EPROT 0x01 /* Protect register enable */
#define HPC3_EEPROM_CSEL 0x02 /* Chip select */
#define HPC3_EEPROM_ECLK 0x04 /* EEPROM clock */
#define HPC3_EEPROM_DATO 0x08 /* Data out */
#define HPC3_EEPROM_DATI 0x10 /* Data in */
hpcreg istat1; /* Irq status, only bits <9:5> reliable. */
hpcreg gio64_estat; /* GIO64 error interrupt status reg. */
#define HPC3_GIOESTAT_BLMASK 0x000ff /* Bus lane where bad parity occurred */
#define HPC3_GIOESTAT_CTYPE 0x00100 /* Bus cycle type, 0=PIO 1=DMA */
#define HPC3_GIOESTAT_PIDMSK 0x3f700 /* DMA channel parity identifier */
volatile u32 istat0; /* Irq status, only bits <4:0> reliable. */
#define HPC3_ISTAT_PBIMASK 0x0ff /* irq bits for pbus devs 0 --> 7 */
#define HPC3_ISTAT_SC0MASK 0x100 /* irq bit for scsi channel 0 */
#define HPC3_ISTAT_SC1MASK 0x200 /* irq bit for scsi channel 1 */
volatile u32 gio_misc; /* GIO misc control bits. */
#define HPC3_GIOMISC_ERTIME 0x1 /* Enable external timer real time. */
#define HPC3_GIOMISC_DENDIAN 0x2 /* dma descriptor endian, 1=lit 0=big */
volatile u32 eeprom; /* EEPROM data reg. */
#define HPC3_EEPROM_EPROT 0x01 /* Protect register enable */
#define HPC3_EEPROM_CSEL 0x02 /* Chip select */
#define HPC3_EEPROM_ECLK 0x04 /* EEPROM clock */
#define HPC3_EEPROM_DATO 0x08 /* Data out */
#define HPC3_EEPROM_DATI 0x10 /* Data in */
volatile u32 istat1; /* Irq status, only bits <9:5> reliable. */
volatile u32 gio_estat; /* GIO error interrupt status reg. */
#define HPC3_GIOESTAT_BLMASK 0x000ff /* Bus lane where bad parity occurred */
#define HPC3_GIOESTAT_CTYPE 0x00100 /* Bus cycle type, 0=PIO 1=DMA */
#define HPC3_GIOESTAT_PIDMSK 0x3f700 /* DMA channel parity identifier */
u32 _unused1[0x14000/4 - 5]; /* padding */
/* Now direct PIO per-HPC3 peripheral access to external regs. */
char _unused2[0x13fec]; /* Trust me... */
hpcreg scsi0_ext[256]; /* SCSI channel 0 external regs */
char _unused3[0x07c00]; /* Trust me... */
hpcreg scsi1_ext[256]; /* SCSI channel 1 external regs */
char _unused4[0x07c00]; /* It'll only hurt a little... */
/* Did DaveM forget the ethernet external regs?
* Anyhow, they're not here and we need some padding instead.
*/
char _unused5[0x04000]; /* It'll hurt a lot if you leave this out */
/* Per-peripheral device external registers and dma/pio control. */
hpcreg pbus_extregs[16][256]; /* 2nd indice indexes controller */
hpcreg pbus_dmacfgs[8][128]; /* 2nd indice indexes controller */
#define HPC3_PIODCFG_D3R 0x00000001 /* Cycles to spend in D3 for reads */
#define HPC3_PIODCFG_D4R 0x0000001e /* Cycles to spend in D4 for reads */
#define HPC3_PIODCFG_D5R 0x000001e0 /* Cycles to spend in D5 for reads */
#define HPC3_PIODCFG_D3W 0x00000200 /* Cycles to spend in D3 for writes */
#define HPC3_PIODCFG_D4W 0x00003c00 /* Cycles to spend in D4 for writes */
#define HPC3_PIODCFG_D5W 0x0003c000 /* Cycles to spend in D5 for writes */
#define HPC3_PIODCFG_HWORD 0x00040000 /* Enable 16-bit dma access mode */
#define HPC3_PIODCFG_EHI 0x00080000 /* Places halfwords on high 16 bits of bus */
#define HPC3_PIODCFG_RTIME 0x00200000 /* Make this device real time on GIO bus */
#define HPC3_PIODCFG_BURST 0x07c00000 /* 5 bit burst count for DMA device */
#define HPC3_PIODCFG_DRQLV 0x08000000 /* Use live pbus_dreq unsynchronized signal */
hpcreg pbus_piocfgs[64][10]; /* 2nd indice indexes controller */
#define HPC3_PIOPCFG_RP2 0x00001 /* Cycles to spend in P2 state for reads */
#define HPC3_PIOPCFG_RP3 0x0001e /* Cycles to spend in P3 state for reads */
#define HPC3_PIOPCFG_RP4 0x001e0 /* Cycles to spend in P4 state for reads */
#define HPC3_PIOPCFG_WP2 0x00200 /* Cycles to spend in P2 state for writes */
#define HPC3_PIOPCFG_WP3 0x03c00 /* Cycles to spend in P3 state for writes */
#define HPC3_PIOPCFG_WP4 0x3c000 /* Cycles to spend in P4 state for writes */
#define HPC3_PIOPCFG_HW 0x40000 /* Enable 16-bit PIO accesses */
#define HPC3_PIOPCFG_EHI 0x80000 /* Place even address bits in bits <15:8> */
volatile u32 scsi0_ext[256]; /* SCSI channel 0 external regs */
u32 _unused2[0x7c00/4];
volatile u32 scsi1_ext[256]; /* SCSI channel 1 external regs */
u32 _unused3[0x7c00/4];
volatile u32 eth_ext[320]; /* Ethernet external registers */
u32 _unused4[0x3b00/4];
/* Per-peripheral device external registers and DMA/PIO control. */
volatile u32 pbus_extregs[16][256];
volatile u32 pbus_dmacfg[8][128];
/* Cycles to spend in D3 for reads */
#define HPC3_DMACFG_D3R_MASK 0x00000001
#define HPC3_DMACFG_D3R_SHIFT 0
/* Cycles to spend in D4 for reads */
#define HPC3_DMACFG_D4R_MASK 0x0000001e
#define HPC3_DMACFG_D4R_SHIFT 1
/* Cycles to spend in D5 for reads */
#define HPC3_DMACFG_D5R_MASK 0x000001e0
#define HPC3_DMACFG_D5R_SHIFT 5
/* Cycles to spend in D3 for writes */
#define HPC3_DMACFG_D3W_MASK 0x00000200
#define HPC3_DMACFG_D3W_SHIFT 9
/* Cycles to spend in D4 for writes */
#define HPC3_DMACFG_D4W_MASK 0x00003c00
#define HPC3_DMACFG_D4W_SHIFT 10
/* Cycles to spend in D5 for writes */
#define HPC3_DMACFG_D5W_MASK 0x0003c000
#define HPC3_DMACFG_D5W_SHIFT 14
/* Enable 16-bit DMA access mode */
#define HPC3_DMACFG_DS16 0x00040000
/* Places halfwords on high 16 bits of bus */
#define HPC3_DMACFG_EVENHI 0x00080000
/* Make this device real time */
#define HPC3_DMACFG_RTIME 0x00200000
/* 5 bit burst count for DMA device */
#define HPC3_DMACFG_BURST_MASK 0x07c00000
#define HPC3_DMACFG_BURST_SHIFT 22
/* Use live pbus_dreq unsynchronized signal */
#define HPC3_DMACFG_DRQLIVE 0x08000000
volatile u32 pbus_piocfg[16][64];
/* Cycles to spend in P2 state for reads */
#define HPC3_PIOCFG_P2R_MASK 0x00001
#define HPC3_PIOCFG_P2R_SHIFT 0
/* Cycles to spend in P3 state for reads */
#define HPC3_PIOCFG_P3R_MASK 0x0001e
#define HPC3_PIOCFG_P3R_SHIFT 1
/* Cycles to spend in P4 state for reads */
#define HPC3_PIOCFG_P4R_MASK 0x001e0
#define HPC3_PIOCFG_P4R_SHIFT 5
/* Cycles to spend in P2 state for writes */
#define HPC3_PIOCFG_P2W_MASK 0x00200
#define HPC3_PIOCFG_P2W_SHIFT 9
/* Cycles to spend in P3 state for writes */
#define HPC3_PIOCFG_P3W_MASK 0x03c00
#define HPC3_PIOCFG_P3W_SHIFT 10
/* Cycles to spend in P4 state for writes */
#define HPC3_PIOCFG_P4W_MASK 0x3c000
#define HPC3_PIOCFG_P4W_SHIFT 14
/* Enable 16-bit PIO accesses */
#define HPC3_PIOCFG_DS16 0x40000
/* Place even address bits in bits <15:8> */
#define HPC3_PIOCFG_EVENHI 0x80000
/* PBUS PROM control regs. */
hpcreg pbus_promwe; /* PROM write enable register */
#define HPC3_PROM_WENAB 0x1 /* Enable writes to the PROM */
volatile u32 pbus_promwe; /* PROM write enable register */
#define HPC3_PROM_WENAB 0x1 /* Enable writes to the PROM */
char _unused6[0x800 - sizeof(hpcreg)];
hpcreg pbus_promswap; /* Chip select swap reg */
#define HPC3_PROM_SWAP 0x1 /* invert GIO addr bit to select prom0 or prom1 */
u32 _unused5[0x0800/4 - 1];
volatile u32 pbus_promswap; /* Chip select swap reg */
#define HPC3_PROM_SWAP 0x1 /* invert GIO addr bit to select prom0 or prom1 */
char _unused7[0x800 - sizeof(hpcreg)];
hpcreg pbus_gout; /* PROM general purpose output reg */
#define HPC3_PROM_STAT 0x1 /* General purpose status bit in gout */
u32 _unused6[0x0800/4 - 1];
volatile u32 pbus_gout; /* PROM general purpose output reg */
#define HPC3_PROM_STAT 0x1 /* General purpose status bit in gout */
char _unused8[0x1000 - sizeof(hpcreg)];
hpcreg pbus_promram[16384]; /* 64k of PROM battery backed ram */
u32 _unused7[0x1000/4 - 1];
volatile u32 rtcregs[14]; /* Dallas clock registers */
u32 _unused8[50];
volatile u32 bbram[8192-50-14]; /* Battery backed ram */
};
/* It is possible to have two HPC3's within the address space on
* one machine, though only having one is more likely on an INDY.
* Controller 0 lives at physical address 0x1fb80000 and the controller
* 1 if present lives at address 0x1fb00000.
/*
* It is possible to have two HPC3's within the address space on
* one machine, though only having one is more likely on an Indy.
*/
extern struct hpc3_regs *hpc3c0, *hpc3c1;
#define HPC3_CHIP0_PBASE 0x1fb80000 /* physical */
#define HPC3_CHIP1_PBASE 0x1fb00000 /* physical */
/* Control and misc status information, these live in pbus channel 6. */
struct hpc3_miscregs {
hpcreg pdata, pctrl, pstat, pdmactrl, pistat, pimask;
hpcreg ptimer1, ptimer2, ptimer3, ptimer4;
hpcreg _unused1[2];
hpcreg ser1cmd, ser1data;
hpcreg ser0cmd, ser0data;
hpcreg kbdmouse0, kbdmouse1;
hpcreg gcsel, genctrl, panel;
hpcreg _unused2;
hpcreg sysid;
hpcreg _unused3;
hpcreg read, _unused4;
hpcreg dselect;
#define HPC3_DSELECT_SCLK10MHZ 0x00 /* use 10MHZ serial clock */
#define HPC3_DSELECT_ISDNB 0x01 /* enable isdn B */
#define HPC3_DSELECT_ISDNA 0x02 /* enable isdn A */
#define HPC3_DSELECT_LPR 0x04 /* use parallel DMA */
#define HPC3_DSELECT_SCLK667MHZ 0x10 /* use 6.67MHZ serial clock */
#define HPC3_DSELECT_SCLKEXT 0x20 /* use external serial clock */
hpcreg _unused5;
hpcreg write1;
#define HPC3_WRITE1_PRESET 0x01 /* 0=LPR_RESET, 1=NORMAL */
#define HPC3_WRITE1_KMRESET 0x02 /* 0=KBDMOUSE_RESET, 1=NORMAL */
#define HPC3_WRITE1_ERESET 0x04 /* 0=EISA_RESET, 1=NORMAL */
#define HPC3_WRITE1_GRESET 0x08 /* 0=MAGIC_GIO_RESET, 1=NORMAL */
#define HPC3_WRITE1_LC0OFF 0x10 /* turn led off (guiness=red, else green) */
#define HPC3_WRITE1_LC1OFF 0x20 /* turn led off (guiness=green, else amber) */
hpcreg _unused6;
hpcreg write2;
#define HPC3_WRITE2_NTHRESH 0x01 /* use 4.5db threshhold */
#define HPC3_WRITE2_TPSPEED 0x02 /* use 100ohm TP speed */
#define HPC3_WRITE2_EPSEL 0x04 /* force cable mode: 1=AUI 0=TP */
#define HPC3_WRITE2_EASEL 0x08 /* 1=autoselect 0=manual cable selection */
#define HPC3_WRITE2_U1AMODE 0x10 /* 1=PC 0=MAC UART mode */
#define HPC3_WRITE2_U0AMODE 0x20 /* 1=PC 0=MAC UART mode */
#define HPC3_WRITE2_MLO 0x40 /* 1=4.75V 0=+5V */
#define HPC3_WRITE2_MHI 0x80 /* 1=5.25V 0=+5V */
};
extern struct hpc3_miscregs *hpc3mregs;
#define HPC3_MREGS_PBASE 0x1fbd9800 /* physical */
/* We need software copies of these because they are write only. */
extern unsigned int sgi_hpc_write1, sgi_hpc_write2;
struct hpc_keyb {
#ifdef __MIPSEB__
unsigned char _unused0[3];
volatile unsigned char data;
unsigned char _unused1[3];
volatile unsigned char command;
#else
volatile unsigned char data;
unsigned char _unused0[3];
volatile unsigned char command;
unsigned char _unused1[3];
#endif
};
/* Indy RTC */
/* The layout of registers for the INDY Dallas 1286 clock chipset. */
struct indy_clock {
volatile unsigned int hsec;
volatile unsigned int sec;
volatile unsigned int min;
volatile unsigned int malarm;
volatile unsigned int hr;
volatile unsigned int halarm;
volatile unsigned int day;
volatile unsigned int dalarm;
volatile unsigned int date;
volatile unsigned int month;
volatile unsigned int year;
volatile unsigned int cmd;
volatile unsigned int whsec;
volatile unsigned int wsec;
volatile unsigned int _unused0[50];
};
#define INDY_CLOCK_REGS (KSEG1ADDR(0x1fbe0000))
#define HPC3_CHIP0_BASE 0x1fb80000 /* physical */
#define HPC3_CHIP1_BASE 0x1fb00000 /* physical */
extern void sgihpc_init(void);
#endif /* _ASM_SGI_SGIHPC_H */
#endif /* _SGI_HPC3_H */
include/asm-mips/sgi/ioc.h 0 → 100644
View file @ 2395133b
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* ioc.h: Definitions for SGI I/O Controller
*
* Copyright (C) 1996 David S. Miller
* Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle
* Copyright (C) 2001, 2003 Ladislav Michl
*/
#ifndef _SGI_IOC_H
#define _SGI_IOC_H
#include <linux/types.h>
/*
* All registers are 8-bit wide alligned on 32-bit boundary. Bad things
* happen if you try word access them. You have been warned.
*/
struct sgioc_pport_regs {
u8 _data[3];
volatile u8 data;
u8 _ctrl[3];
volatile u8 ctrl;
#define SGIOC_PCTRL_STROBE 0x01
#define SGIOC_PCTRL_AFD 0x02
#define SGIOC_PCTRL_INIT 0x04
#define SGIOC_PCTRL_SLIN 0x08
#define SGIOC_PCTRL_DIRECTION 0x20
#define SGIOC_PCTRL_SEL 0x40
u8 _status[3];
volatile u8 status;
#define SGIOC_PSTAT_DEVID 0x03
#define SGIOC_PSTAT_NOINK 0x04
#define SGIOC_PSTAT_ERROR 0x08
#define SGIOC_PSTAT_ONLINE 0x10
#define SGIOC_PSTAT_PE 0x20
#define SGIOC_PSTAT_ACK 0x40
#define SGIOC_PSTAT_BUSY 0x80
u8 _dmactrl[3];
volatile u8 dmactrl;
u8 _intrstat[3];
volatile u8 intrstat;
u8 _intrmask[3];
volatile u8 intrmask;
u8 _timer1[3];
volatile u8 timer1;
u8 _timer2[3];
volatile u8 timer2;
u8 _timer3[3];
volatile u8 timer3;
u8 _timer4[3];
volatile u8 timer4;
};
struct sgioc_uart_regs {
u8 _ctrl1[3];
volatile u8 ctrl1;
u8 _data1[3];
volatile u8 data1;
u8 _ctrl2[3];
volatile u8 ctrl2;
u8 _data2[3];
volatile u8 data2;
};
struct sgioc_keyb_regs {
u8 _data[3];
volatile u8 data;
u8 _command[3];
volatile u8 command;
};
struct sgint_regs {
u8 _istat0[3];
volatile u8 istat0; /* Interrupt status zero */
#define SGINT_ISTAT0_FFULL 0x01
#define SGINT_ISTAT0_SCSI0 0x02
#define SGINT_ISTAT0_SCSI1 0x04
#define SGINT_ISTAT0_ENET 0x08
#define SGINT_ISTAT0_GFXDMA 0x10
#define SGINT_ISTAT0_PPORT 0x20
#define SGINT_ISTAT0_HPC2 0x40
#define SGINT_ISTAT0_LIO2 0x80
u8 _imask0[3];
volatile u8 imask0; /* Interrupt mask zero */
u8 _istat1[3];
volatile u8 istat1; /* Interrupt status one */
#define SGINT_ISTAT1_ISDNI 0x01
#define SGINT_ISTAT1_PWR 0x02
#define SGINT_ISTAT1_ISDNH 0x04
#define SGINT_ISTAT1_LIO3 0x08
#define SGINT_ISTAT1_HPC3 0x10
#define SGINT_ISTAT1_AFAIL 0x20
#define SGINT_ISTAT1_VIDEO 0x40
#define SGINT_ISTAT1_GIO2 0x80
u8 _imask1[3];
volatile u8 imask1; /* Interrupt mask one */
u8 _vmeistat[3];
volatile u8 vmeistat; /* VME interrupt status */
u8 _cmeimask0[3];
volatile u8 cmeimask0; /* VME interrupt mask zero */
u8 _cmeimask1[3];
volatile u8 cmeimask1; /* VME interrupt mask one */
u8 _cmepol[3];
volatile u8 cmepol; /* VME polarity */
u8 _tclear[3];
volatile u8 tclear;
u8 _errstat[3];
volatile u8 errstat; /* Error status reg, reserved on INT2 */
u32 _unused0[2];
u8 _tcnt0[3];
volatile u8 tcnt0; /* counter 0 */
u8 _tcnt1[3];
volatile u8 tcnt1; /* counter 1 */
u8 _tcnt2[3];
volatile u8 tcnt2; /* counter 2 */
u8 _tcword[3];
volatile u8 tcword; /* control word */
#define SGINT_TCWORD_BCD 0x01 /* Use BCD mode for counters */
#define SGINT_TCWORD_MMASK 0x0e /* Mode bitmask. */
#define SGINT_TCWORD_MITC 0x00 /* IRQ on terminal count (doesn't work) */
#define SGINT_TCWORD_MOS 0x02 /* One-shot IRQ mode. */
#define SGINT_TCWORD_MRGEN 0x04 /* Normal rate generation */
#define SGINT_TCWORD_MSWGEN 0x06 /* Square wave generator mode */
#define SGINT_TCWORD_MSWST 0x08 /* Software strobe */
#define SGINT_TCWORD_MHWST 0x0a /* Hardware strobe */
#define SGINT_TCWORD_CMASK 0x30 /* Command mask */
#define SGINT_TCWORD_CLAT 0x00 /* Latch command */
#define SGINT_TCWORD_CLSB 0x10 /* LSB read/write */
#define SGINT_TCWORD_CMSB 0x20 /* MSB read/write */
#define SGINT_TCWORD_CALL 0x30 /* Full counter read/write */
#define SGINT_TCWORD_CNT0 0x00 /* Select counter zero */
#define SGINT_TCWORD_CNT1 0x40 /* Select counter one */
#define SGINT_TCWORD_CNT2 0x80 /* Select counter two */
#define SGINT_TCWORD_CRBCK 0xc0 /* Readback command */
};
#define SGINT_TCSAMP_COUNTER 10255
/* We need software copies of these because they are write only. */
extern u8 sgi_ioc_reset, sgi_ioc_write;
struct sgioc_regs {
struct sgioc_pport_regs pport;
u32 _unused0[2];
struct sgioc_uart_regs serport;
struct sgioc_keyb_regs kbdmouse;
u8 _gcsel[3];
volatile u8 gcsel;
u8 _genctrl[3];
volatile u8 genctrl;
u8 _panel[3];
volatile u8 panel;
#define SGIOC_PANEL_POWERON 0x01
#define SGIOC_PANEL_POWERINTR 0x02
#define SGIOC_PANEL_VOLDNINTR 0x10
#define SGIOC_PANEL_VOLDNHOLD 0x20
#define SGIOC_PANEL_VOLUPINTR 0x40
#define SGIOC_PANEL_VOLUPHOLD 0x80
u32 _unused1;
u8 _sysid[3];
volatile u8 sysid;
#define SGIOC_SYSID_FULLHOUSE 0x01
#define SGIOC_SYSID_BOARDREV(x) ((x & 0xe0) > 5)
#define SGIOC_SYSID_CHIPREV(x) ((x & 0x1e) > 1)
u32 _unused2;
u8 _read[3];
volatile u8 read;
u32 _unused3;
u8 _dmasel[3];
volatile u8 dmasel;
#define SGIOC_DMASEL_SCLK10MHZ 0x00 /* use 10MHZ serial clock */
#define SGIOC_DMASEL_ISDNB 0x01 /* enable isdn B */
#define SGIOC_DMASEL_ISDNA 0x02 /* enable isdn A */
#define SGIOC_DMASEL_PPORT 0x04 /* use parallel DMA */
#define SGIOC_DMASEL_SCLK667MHZ 0x10 /* use 6.67MHZ serial clock */
#define SGIOC_DMASEL_SCLKEXT 0x20 /* use external serial clock */
u32 _unused4;
u8 _reset[3];
volatile u8 reset;
#define SGIOC_RESET_PPORT 0x01 /* 0=parport reset, 1=nornal */
#define SGIOC_RESET_KBDMOUSE 0x02 /* 0=kbdmouse reset, 1=normal */
#define SGIOC_RESET_EISA 0x04 /* 0=eisa reset, 1=normal */
#define SGIOC_RESET_ISDN 0x08 /* 0=isdn reset, 1=normal */
#define SGIOC_RESET_LC0OFF 0x10 /* guiness: turn led off (red, else green) */
#define SGIOC_RESET_LC1OFF 0x20 /* guiness: turn led off (green, else amber) */
u32 _unused5;
u8 _write[3];
volatile u8 write;
#define SGIOC_WRITE_NTHRESH 0x01 /* use 4.5db threshhold */
#define SGIOC_WRITE_TPSPEED 0x02 /* use 100ohm TP speed */
#define SGIOC_WRITE_EPSEL 0x04 /* force cable mode: 1=AUI 0=TP */
#define SGIOC_WRITE_EASEL 0x08 /* 1=autoselect 0=manual cable selection */
#define SGIOC_WRITE_U1AMODE 0x10 /* 1=PC 0=MAC UART mode */
#define SGIOC_WRITE_U0AMODE 0x20 /* 1=PC 0=MAC UART mode */
#define SGIOC_WRITE_MLO 0x40 /* 1=4.75V 0=+5V */
#define SGIOC_WRITE_MHI 0x80 /* 1=5.25V 0=+5V */
u32 _unused6;
struct sgint_regs int3;
};
extern struct sgioc_regs *sgioc;
extern struct sgint_regs *sgint;
#endif
include/asm-mips/sgi/ip22.h 0 → 100644
View file @ 2395133b
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* ip22.h: Definitions for SGI IP22 machines
*
* Copyright (C) 1996 David S. Miller
* Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle
*/
#ifndef _SGI_IP22_H
#define _SGI_IP22_H
/*
* These are the virtual IRQ numbers, we divide all IRQ's into
* 'spaces', the 'space' determines where and how to enable/disable
* that particular IRQ on an SGI machine. HPC DMA and MC DMA interrups
* are not supported this way. Driver is supposed to allocate HPC/MC
* interrupt as shareable and then look to proper status bit (see
* HAL2 driver). This will prevent many complications, trust me ;-)
*/
#include <asm/sgi/ioc.h>
#define SGINT_EISA 0 /* INDIGO 2 has 16 EISA irq levels */
#define SGINT_CPU 16 /* MIPS CPU define 8 interrupt sources */
#define SGINT_LOCAL0 24 /* INDY has 8 local0 irq levels */
#define SGINT_LOCAL1 32 /* INDY has 8 local1 irq levels */
#define SGINT_LOCAL2 40 /* INDY has 8 local2 vectored irq levels */
#define SGINT_LOCAL3 48 /* INDY has 8 local3 vectored irq levels */
#define SGINT_END 56 /* End of 'spaces' */
/*
* Individual interrupt definitions for the Indy and Indigo2
*/
#define SGI_SOFT_0_IRQ SGINT_CPU + 0
#define SGI_SOFT_1_IRQ SGINT_CPU + 1
#define SGI_LOCAL_0_IRQ SGINT_CPU + 2
#define SGI_LOCAL_1_IRQ SGINT_CPU + 3
#define SGI_8254_0_IRQ SGINT_CPU + 4
#define SGI_8254_1_IRQ SGINT_CPU + 5
#define SGI_BUSERR_IRQ SGINT_CPU + 6
#define SGI_TIMER_IRQ SGINT_CPU + 7
#define SGI_FIFO_IRQ SGINT_LOCAL0 + 0 /* FIFO full */
#define SGI_GIO_0_IRQ SGI_FIFO_IRQ /* GIO-0 */
#define SGI_WD93_0_IRQ SGINT_LOCAL0 + 1 /* 1st onboard WD93 */
#define SGI_WD93_1_IRQ SGINT_LOCAL0 + 2 /* 2nd onboard WD93 */
#define SGI_ENET_IRQ SGINT_LOCAL0 + 3 /* onboard ethernet */
#define SGI_MCDMA_IRQ SGINT_LOCAL0 + 4 /* MC DMA done */
#define SGI_PARPORT_IRQ SGINT_LOCAL0 + 5 /* Parallel port */
#define SGI_GIO_1_IRQ SGINT_LOCAL0 + 6 /* GE / GIO-1 / 2nd-HPC */
#define SGI_MAP_0_IRQ SGINT_LOCAL0 + 7 /* Mappable interrupt 0 */
#define SGI_GPL0_IRQ SGINT_LOCAL1 + 0 /* General Purpose LOCAL1_N<0> */
#define SGI_PANEL_IRQ SGINT_LOCAL1 + 1 /* front panel */
#define SGI_GPL2_IRQ SGINT_LOCAL1 + 2 /* General Purpose LOCAL1_N<2> */
#define SGI_MAP_1_IRQ SGINT_LOCAL1 + 3 /* Mappable interrupt 1 */
#define SGI_HPCDMA_IRQ SGINT_LOCAL1 + 4 /* HPC DMA done */
#define SGI_ACFAIL_IRQ SGINT_LOCAL1 + 5 /* AC fail */
#define SGI_VINO_IRQ SGINT_LOCAL1 + 6 /* Indy VINO */
#define SGI_GIO_2_IRQ SGINT_LOCAL1 + 7 /* Vert retrace / GIO-2 */
/* Mapped interrupts. These interrupts may be mapped to either 0, or 1 */
#define SGI_VERT_IRQ SGINT_LOCAL2 + 0 /* INT3: newport vertical status */
#define SGI_EISA_IRQ SGINT_LOCAL2 + 3 /* EISA interrupts */
#define SGI_KEYBD_IRQ SGINT_LOCAL2 + 4 /* keyboard */
#define SGI_SERIAL_IRQ SGINT_LOCAL2 + 5 /* onboard serial */
#define ip22_is_fullhouse() (sgioc->sysid & SGIOC_SYSID_FULLHOUSE)
extern unsigned short ip22_eeprom_read(volatile unsigned int *ctrl, int reg);
extern unsigned short ip22_nvram_read(int reg);
#endif
include/asm-mips/sgi/mc.h 0 → 100644
View file @ 2395133b
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* mc.h: Definitions for SGI Memory Controller
*
* Copyright (C) 1996 David S. Miller
* Copyright (C) 1999 Ralf Baechle
* Copyright (C) 1999 Silicon Graphics, Inc.
*/
#ifndef _SGI_MC_H
#define _SGI_MC_H
struct sgimc_regs {
u32 _unused0;
volatile u32 cpuctrl0; /* CPU control register 0, readwrite */
#define SGIMC_CCTRL0_REFS 0x0000000f /* REFS mask */
#define SGIMC_CCTRL0_EREFRESH 0x00000010 /* Memory refresh enable */
#define SGIMC_CCTRL0_EPERRGIO 0x00000020 /* GIO parity error enable */
#define SGIMC_CCTRL0_EPERRMEM 0x00000040 /* Main mem parity error enable */
#define SGIMC_CCTRL0_EPERRCPU 0x00000080 /* CPU bus parity error enable */
#define SGIMC_CCTRL0_WDOG 0x00000100 /* Watchdog timer enable */
#define SGIMC_CCTRL0_SYSINIT 0x00000200 /* System init bit */
#define SGIMC_CCTRL0_GFXRESET 0x00000400 /* Graphics interface reset */
#define SGIMC_CCTRL0_EISALOCK 0x00000800 /* Lock CPU from memory for EISA */
#define SGIMC_CCTRL0_EPERRSCMD 0x00001000 /* SysCMD bus parity error enable */
#define SGIMC_CCTRL0_IENAB 0x00002000 /* Allow interrupts from MC */
#define SGIMC_CCTRL0_ESNOOP 0x00004000 /* Snooping I/O enable */
#define SGIMC_CCTRL0_EPROMWR 0x00008000 /* Prom writes from cpu enable */
#define SGIMC_CCTRL0_WRESETPMEM 0x00010000 /* Perform warm reset, preserves mem */
#define SGIMC_CCTRL0_LENDIAN 0x00020000 /* Put MC in little-endian mode */
#define SGIMC_CCTRL0_WRESETDMEM 0x00040000 /* Warm reset, destroys mem contents */
#define SGIMC_CCTRL0_CMEMBADPAR 0x02000000 /* Generate bad perr from cpu to mem */
#define SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */
#define SGIMC_CCTRL0_GIOBTOB 0x08000000 /* Allow GIO back to back writes */
u32 _unused1;
volatile u32 cpuctrl1; /* CPU control register 1, readwrite */
#define SGIMC_CCTRL1_EGIOTIMEO 0x00000010 /* GIO bus timeout enable */
#define SGIMC_CCTRL1_FIXEDEHPC 0x00001000 /* Fixed HPC endianness */
#define SGIMC_CCTRL1_LITTLEHPC 0x00002000 /* Little endian HPC */
#define SGIMC_CCTRL1_FIXEDEEXP0 0x00004000 /* Fixed EXP0 endianness */
#define SGIMC_CCTRL1_LITTLEEXP0 0x00008000 /* Little endian EXP0 */
#define SGIMC_CCTRL1_FIXEDEEXP1 0x00010000 /* Fixed EXP1 endianness */
#define SGIMC_CCTRL1_LITTLEEXP1 0x00020000 /* Little endian EXP1 */
u32 _unused2;
volatile u32 watchdogt; /* Watchdog reg rdonly, write clears */
u32 _unused3;
volatile u32 systemid; /* MC system ID register, readonly */
#define SGIMC_SYSID_MASKREV 0x0000000f /* Revision of MC controller */
#define SGIMC_SYSID_EPRESENT 0x00000010 /* Indicates presence of EISA bus */
u32 _unused4[3];
volatile u32 divider; /* Divider reg for RPSS */
u32 _unused5;
volatile u32 eeprom; /* EEPROM byte reg for r4k */
#define SGIMC_EEPROM_PRE 0x00000001 /* eeprom chip PRE pin assertion */
#define SGIMC_EEPROM_CSEL 0x00000002 /* Active high, eeprom chip select */
#define SGIMC_EEPROM_SECLOCK 0x00000004 /* EEPROM serial clock */
#define SGIMC_EEPROM_SDATAO 0x00000008 /* Serial EEPROM data-out */
#define SGIMC_EEPROM_SDATAI 0x00000010 /* Serial EEPROM data-in */
u32 _unused6[3];
volatile u32 rcntpre; /* Preload refresh counter */
u32 _unused7;
volatile u32 rcounter; /* Readonly refresh counter */
u32 _unused8[13];
volatile u32 giopar; /* Parameter word for GIO64 */
#define SGIMC_GIOPAR_HPC64 0x00000001 /* HPC talks to GIO using 64-bits */
#define SGIMC_GIOPAR_GFX64 0x00000002 /* GFX talks to GIO using 64-bits */
#define SGIMC_GIOPAR_EXP064 0x00000004 /* EXP(slot0) talks using 64-bits */
#define SGIMC_GIOPAR_EXP164 0x00000008 /* EXP(slot1) talks using 64-bits */
#define SGIMC_GIOPAR_EISA64 0x00000010 /* EISA bus talks 64-bits to GIO */
#define SGIMC_GIOPAR_HPC264 0x00000020 /* 2nd HPX talks 64-bits to GIO */
#define SGIMC_GIOPAR_RTIMEGFX 0x00000040 /* GFX device has realtime attr */
#define SGIMC_GIOPAR_RTIMEEXP0 0x00000080 /* EXP(slot0) has realtime attr */
#define SGIMC_GIOPAR_RTIMEEXP1 0x00000100 /* EXP(slot1) has realtime attr */
#define SGIMC_GIOPAR_MASTEREISA 0x00000200 /* EISA bus can act as bus master */
#define SGIMC_GIOPAR_ONEBUS 0x00000400 /* Exists one GIO64 pipelined bus */
#define SGIMC_GIOPAR_MASTERGFX 0x00000800 /* GFX can act as a bus master */
#define SGIMC_GIOPAR_MASTEREXP0 0x00001000 /* EXP(slot0) can bus master */
#define SGIMC_GIOPAR_MASTEREXP1 0x00002000 /* EXP(slot1) can bus master */
#define SGIMC_GIOPAR_PLINEEXP0 0x00004000 /* EXP(slot0) has pipeline attr */
#define SGIMC_GIOPAR_PLINEEXP1 0x00008000 /* EXP(slot1) has pipeline attr */
u32 _unused9;
volatile u32 cputp; /* CPU bus arb time period */
u32 _unused10[3];
volatile u32 lbursttp; /* Time period for long bursts */
/* MC chip can drive up to 4 bank 4 SIMMs each. All SIMMs in bank must
* be the same size. The size encoding for supported SIMMs is bellow */
u32 _unused11[9];
volatile u32 mconfig0; /* Memory config register zero */
u32 _unused12;
volatile u32 mconfig1; /* Memory config register one */
#define SGIMC_MCONFIG_BASEADDR 0x000000ff /* Base address of bank*/
#define SGIMC_MCONFIG_RMASK 0x00001f00 /* Ram config bitmask */
#define SGIMC_MCONFIG_BVALID 0x00002000 /* Bank is valid */
#define SGIMC_MCONFIG_SBANKS 0x00004000 /* Number of subbanks */
u32 _unused13;
volatile u32 cmacc; /* Mem access config for CPU */
u32 _unused14;
volatile u32 gmacc; /* Mem access config for GIO */
/* This define applies to both cmacc and gmacc registers above. */
#define SGIMC_MACC_ALIASBIG 0x20000000 /* 512MB home for alias */
/* Error address/status regs from GIO and CPU perspectives. */
u32 _unused15;
volatile u32 cerr; /* Error address reg for CPU */
u32 _unused16;
volatile u32 cstat; /* Status reg for CPU */
#define SGIMC_CSTAT_RD 0x00000100 /* read parity error */
#define SGIMC_CSTAT_PAR 0x00000200 /* CPU parity error */
#define SGIMC_CSTAT_ADDR 0x00000400 /* memory bus error bad addr */
#define SGIMC_CSTAT_SYSAD_PAR 0x00000800 /* sysad parity error */
#define SGIMC_CSTAT_SYSCMD_PAR 0x00001000 /* syscmd parity error */
#define SGIMC_CSTAT_BAD_DATA 0x00002000 /* bad data identifier */
#define SGIMC_CSTAT_PAR_MASK 0x00001f00 /* parity error mask */
#define SGIMC_CSTAT_RD_PAR (SGIMC_CSTAT_RD | SGIMC_CSTAT_PAR)
u32 _unused17;
volatile u32 gerr; /* Error address reg for GIO */
u32 _unused18;
volatile u32 gstat; /* Status reg for GIO */
#define SGIMC_GSTAT_RD 0x00000100 /* read parity error */
#define SGIMC_GSTAT_WR 0x00000200 /* write parity error */
#define SGIMC_GSTAT_TIME 0x00000400 /* GIO bus timed out */
#define SGIMC_GSTAT_PROM 0x00000800 /* write to PROM when PROM_EN not set */
#define SGIMC_GSTAT_ADDR 0x00001000 /* parity error on addr cycle */
#define SGIMC_GSTAT_BC 0x00002000 /* parity error on byte count cycle */
#define SGIMC_GSTAT_PIO_RD 0x00004000 /* read data parity on pio */
#define SGIMC_GSTAT_PIO_WR 0x00008000 /* write data parity on pio */
/* Special hard bus locking registers. */
u32 _unused19;
volatile u32 syssembit; /* Uni-bit system semaphore */
u32 _unused20;
volatile u32 mlock; /* Global GIO memory access lock */
u32 _unused21;
volatile u32 elock; /* Locks EISA from GIO accesses */
/* GIO dma control registers. */
u32 _unused22[15];
volatile u32 gio_dma_trans; /* DMA mask to translation GIO addrs */
u32 _unused23;
volatile u32 gio_dma_sbits; /* DMA GIO addr substitution bits */
u32 _unused24;
volatile u32 dma_intr_cause; /* DMA IRQ cause indicator bits */
u32 _unused25;
volatile u32 dma_ctrl; /* Main DMA control reg */
/* DMA TLB entry 0 */
u32 _unused26[5];
volatile u32 dtlb_hi0;
u32 _unused27;
volatile u32 dtlb_lo0;
/* DMA TLB entry 1 */
u32 _unused28;
volatile u32 dtlb_hi1;
u32 _unused29;
volatile u32 dtlb_lo1;
/* DMA TLB entry 2 */
u32 _unused30;
volatile u32 dtlb_hi2;
u32 _unused31;
volatile u32 dtlb_lo2;
/* DMA TLB entry 3 */
u32 _unused32;
volatile u32 dtlb_hi3;
u32 _unused33;
volatile u32 dtlb_lo3;
u32 _unused34[0x0392];
u32 _unused35;
volatile u32 rpsscounter; /* Chirps at 100ns */
u32 _unused36[0x1000/4-2*4];
u32 _unused37;
volatile u32 maddronly; /* Address DMA goes at */
u32 _unused38;
volatile u32 maddrpdeflts; /* Same as above, plus set defaults */
u32 _unused39;
volatile u32 dmasz; /* DMA count */
u32 _unused40;
volatile u32 ssize; /* DMA stride size */
u32 _unused41;
volatile u32 gmaddronly; /* Set GIO DMA but don't start trans */
u32 _unused42;
volatile u32 dmaddnpgo; /* Set GIO DMA addr + start transfer */
u32 _unused43;
volatile u32 dmamode; /* DMA mode config bit settings */
u32 _unused44;
volatile u32 dmaccount; /* Zoom and byte count for DMA */
u32 _unused45;
volatile u32 dmastart; /* Pedal to the metal. */
u32 _unused46;
volatile u32 dmarunning; /* DMA op is in progress */
u32 _unused47;
volatile u32 maddrdefstart; /* Set dma addr, defaults, and kick it */
};
extern struct sgimc_regs *sgimc;
#define SGIMC_BASE 0x1fa00000 /* physical */
/* Base location of the two ram banks found in IP2[0268] machines. */
#define SGIMC_SEG0_BADDR 0x08000000
#define SGIMC_SEG1_BADDR 0x20000000
/* Maximum size of the above banks are per machine. */
#define SGIMC_SEG0_SIZE_ALL 0x10000000 /* 256MB */
#define SGIMC_SEG1_SIZE_IP20_IP22 0x08000000 /* 128MB */
#define SGIMC_SEG1_SIZE_IP26_IP28 0x20000000 /* 512MB */
extern void sgimc_init(void);
#endif /* _SGI_MC_H */
include/asm-mips/sgi/sgi.h
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/* $Id: sgi.h,v 1.1.1.1 1997/06/01 03:17:12 ralf Exp $
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* sgi.h: Definitions specific to SGI machines.
*
* Copyright (C) 1996 David S. Miller (dm@sgi.com)
*/
#ifndef _MIPS_SGI_H
#define _MIPS_SGI_H
#ifndef _ASM_SGI_SGI_H
#define _ASM_SGI_SGI_H
/* UP=UniProcessor MP=MultiProcessor(capable) */
enum sgi_mach {
ip4, /* R2k UP */
ip5, /* R2k MP */
ip6, /* R3k UP */
ip7, /* R3k MP */
ip9, /* R3k UP */
ip12, /* R3kA UP, Indigo */
ip15, /* R3kA MP */
ip17, /* R4K UP */
ip19, /* R4K MP */
ip20, /* R4K UP, Indigo */
ip21, /* TFP MP */
ip22, /* R4x00 UP, Indigo2 */
ip25, /* R10k MP */
ip26, /* TFP UP, Indigo2 */
ip28, /* R10k UP, Indigo2 */
ip4, /* R2k UP */
ip5, /* R2k MP */
ip6, /* R3k UP */
ip7, /* R3k MP */
ip9, /* R3k UP */
ip12, /* R3kA UP, Indigo */
ip15, /* R3kA MP */
ip17, /* R4K UP */
ip19, /* R4K MP */
ip20, /* R4K UP, Indigo */
ip21, /* TFP MP */
ip22, /* R4x00 UP, Indigo2 */
ip25, /* R10k MP */
ip26, /* TFP UP, Indigo2 */
ip27, /* R10k MP, R12k MP, Origin */
ip28, /* R10k UP, Indigo2 */
ip30,
ip32,
};
......@@ -39,4 +44,4 @@ extern void sgi_sysinit(void);
#define SGI_MSB(regaddr) ((regaddr) | 0x3)
#endif
#endif /* !(_MIPS_SGI_H) */
#endif /* _ASM_SGI_SGI_H */
include/asm-mips/sgi/sgihpc.h deleted 100644 → 0
View file @ f19e2d9e
/* $Id: sgihpc.h,v 1.2 1999/12/06 23:13:21 ralf Exp $
*
* sgihpc.h: Various HPC I/O controller defines. The HPC is basically
* the approximate functional equivalent of the Sun SYSIO
* on SGI INDY machines.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
* Copyright (C) 1998 Ralf Baechle (ralf@gnu.org)
*/
#ifndef _MIPS_SGIHPC_H
#define _MIPS_SGIHPC_H
#include <asm/page.h>
extern int sgi_has_ioc2; /* to know if we have older ioc1 or ioc2. */
extern int sgi_guiness; /* GUINESS or FULLHOUSE machine. */
extern int sgi_boardid; /* Board revision. */
/* An HPC dma descriptor. */
struct hpc_dma_desc {
unsigned int pbuf; /* physical address of data buffer */
unsigned int cntinfo; /* counter and info bits */
#define HPCDMA_EOX 0x80000000 /* last desc in chain for tx */
#define HPCDMA_EOR 0x80000000 /* last desc in chain for rx */
#define HPCDMA_EOXP 0x40000000 /* end of packet for tx */
#define HPCDMA_EORP 0x40000000 /* end of packet for rx */
#define HPCDMA_XIE 0x20000000 /* irq generated when at end of this desc */
#define HPCDMA_XIU 0x01000000 /* Tx buffer in use by CPU. */
#define HPCDMA_EIPC 0x00ff0000 /* SEEQ ethernet special xternal bytecount */
#define HPCDMA_ETXD 0x00008000 /* set to one by HPC when packet tx'd */
#define HPCDMA_OWN 0x00004000 /* Denotes ring buffer ownership on rx */
#define HPCDMA_BCNT 0x00003fff /* size in bytes of this dma buffer */
unsigned int pnext; /* paddr of next hpc_dma_desc if any */
};
typedef volatile unsigned int hpcreg;
/* HPC1 stuff. */
/* HPC3 stuff. */
/* The set of regs for each HPC3 pbus dma channel. */
struct hpc3_pbus_dmacregs {
hpcreg pbdma_bptr; /* pbus dma channel buffer ptr */
hpcreg pbdma_dptr; /* pbus dma channel desc ptr */
char _unused1[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */
hpcreg pbdma_ctrl; /* pbus dma channel control reg */
#define HPC3_PDMACTRL_SEL 0x00000002 /* little endian transfer */
#define HPC3_PDMACTRL_RCV 0x00000004 /* direction is receive */
#define HPC3_PDMACTRL_FLSH 0x00000008 /* enable flush for receive DMA */
#define HPC3_PDMACTRL_ACT 0x00000010 /* start dma transfer */
#define HPC3_PDMACTRL_LD 0x00000020 /* load enable for ACT */
#define HPC3_PDMACTRL_RT 0x00000040 /* Use realtime GIO bus servicing */
#define HPC3_PDMACTRL_HW 0x0000ff00 /* DMA High-water mark */
#define HPC3_PDMACTRL_FB 0x003f0000 /* Ptr to beginning of fifo */
#define HPC3_PDMACTRL_FE 0x3f000000 /* Ptr to end of fifo */
char _unused2[PAGE_SIZE - (sizeof(hpcreg))]; /* padding */
};
/* The HPC3 scsi registers, this does not include external ones. */
struct hpc3_scsiregs {
hpcreg cbptr; /* current dma buffer ptr, diagnostic use only */
hpcreg ndptr; /* next dma descriptor ptr */
char _unused1[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */
hpcreg bcd; /* byte count info */
#define HPC3_SBCD_BCNTMSK 0x00003fff /* bytes to transfer from/to memory */
#define HPC3_SBCD_XIE 0x00004000 /* Send IRQ when done with cur buf */
#define HPC3_SBCD_EOX 0x00008000 /* Indicates this is last buf in chain */
hpcreg ctrl; /* control register */
#define HPC3_SCTRL_IRQ 0x01 /* IRQ asserted, either dma done or parity */
#define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */
#define HPC3_SCTRL_DIR 0x04 /* DMA direction, 1=dev2mem 0=mem2dev */
#define HPC3_SCTRL_FLUSH 0x08 /* Tells HPC3 to flush scsi fifos */
#define HPC3_SCTRL_ACTIVE 0x10 /* SCSI DMA channel is active */
#define HPC3_SCTRL_AMASK 0x20 /* DMA active inhibits PIO */
#define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */
#define HPC3_SCTRL_PERR 0x80 /* Bad parity on HPC3 iface to scsi controller */
hpcreg gfptr; /* current GIO fifo ptr */
hpcreg dfptr; /* current device fifo ptr */
hpcreg dconfig; /* DMA configuration register */
#define HPC3_SDCFG_HCLK 0x00001 /* Enable DMA half clock mode */
#define HPC3_SDCFG_D1 0x00006 /* Cycles to spend in D1 state */
#define HPC3_SDCFG_D2 0x00038 /* Cycles to spend in D2 state */
#define HPC3_SDCFG_D3 0x001c0 /* Cycles to spend in D3 state */
#define HPC3_SDCFG_HWAT 0x00e00 /* DMA high water mark */
#define HPC3_SDCFG_HW 0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
#define HPC3_SDCFG_SWAP 0x02000 /* Byte swap all DMA accesses */
#define HPC3_SDCFG_EPAR 0x04000 /* Enable parity checking for DMA */
#define HPC3_SDCFG_POLL 0x08000 /* hd_dreq polarity control */
#define HPC3_SDCFG_ERLY 0x30000 /* hd_dreq behavior control bits */
hpcreg pconfig; /* PIO configuration register */
#define HPC3_SPCFG_P3 0x0003 /* Cycles to spend in P3 state */
#define HPC3_SPCFG_P2W 0x001c /* Cycles to spend in P2 state for writes */
#define HPC3_SPCFG_P2R 0x01e0 /* Cycles to spend in P2 state for reads */
#define HPC3_SPCFG_P1 0x0e00 /* Cycles to spend in P1 state */
#define HPC3_SPCFG_HW 0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
#define HPC3_SPCFG_SWAP 0x2000 /* Byte swap all PIO accesses */
#define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */
#define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */
char _unused2[PAGE_SIZE - (6 * sizeof(hpcreg))]; /* padding */
};
/* SEEQ ethernet HPC3 registers, only one seeq per HPC3. */
struct hpc3_ethregs {
/* Receiver registers. */
hpcreg rx_cbptr; /* current dma buffer ptr, diagnostic use only */
hpcreg rx_ndptr; /* next dma descriptor ptr */
char _unused1[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */
hpcreg rx_bcd; /* byte count info */
#define HPC3_ERXBCD_BCNTMSK 0x00003fff /* bytes to be sent to memory */
#define HPC3_ERXBCD_XIE 0x20000000 /* HPC3 interrupts cpu at end of this buf */
#define HPC3_ERXBCD_EOX 0x80000000 /* flags this as end of descriptor chain */
hpcreg rx_ctrl; /* control register */
#define HPC3_ERXCTRL_STAT50 0x0000003f /* Receive status reg bits of Seeq8003 */
#define HPC3_ERXCTRL_STAT6 0x00000040 /* Rdonly irq status */
#define HPC3_ERXCTRL_STAT7 0x00000080 /* Rdonlt old/new status bit from Seeq */
#define HPC3_ERXCTRL_ENDIAN 0x00000100 /* Endian for dma channel, little=1 big=0 */
#define HPC3_ERXCTRL_ACTIVE 0x00000200 /* Tells if DMA transfer is in progress */
#define HPC3_ERXCTRL_AMASK 0x00000400 /* Tells if ACTIVE inhibits PIO's to hpc3 */
#define HPC3_ERXCTRL_RBO 0x00000800 /* Receive buffer overflow if set to 1 */
hpcreg rx_gfptr; /* current GIO fifo ptr */
hpcreg rx_dfptr; /* current device fifo ptr */
hpcreg _unused2; /* padding */
hpcreg rx_reset; /* reset register */
#define HPC3_ERXRST_CRESET 0x1 /* Reset dma channel and external controller */
#define HPC3_ERXRST_CLRIRQ 0x2 /* Clear channel interrupt */
#define HPC3_ERXRST_LBACK 0x4 /* Enable diagnostic loopback mode of Seeq8003 */
hpcreg rx_dconfig; /* DMA configuration register */
#define HPC3_ERXDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */
#define HPC3_ERXDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */
#define HPC3_ERXDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO */
#define HPC3_ERXDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */
#define HPC3_ERXDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */
#define HPC3_ERXDCFG_FEOP 0x04000 /* Bad packet marker timeout enable */
#define HPC3_ERXDCFG_FIRQ 0x08000 /* Another bad packet timeout enable */
#define HPC3_ERXDCFG_PTO 0x30000 /* Programmed timeout value for above two */
hpcreg rx_pconfig; /* PIO configuration register */
#define HPC3_ERXPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */
#define HPC3_ERXPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */
#define HPC3_ERXPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */
#define HPC3_ERXPCFG_TST 0x1000 /* Diagnistic ram test feature bit */
char _unused3[PAGE_SIZE - (8 * sizeof(hpcreg))]; /* padding */
/* Transmitter registers. */
hpcreg tx_cbptr; /* current dma buffer ptr, diagnostic use only */
hpcreg tx_ndptr; /* next dma descriptor ptr */
char _unused4[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */
hpcreg tx_bcd; /* byte count info */
#define HPC3_ETXBCD_BCNTMSK 0x00003fff /* bytes to be read from memory */
#define HPC3_ETXBCD_ESAMP 0x10000000 /* if set, too late to add descriptor */
#define HPC3_ETXBCD_XIE 0x20000000 /* Interrupt cpu at end of cur desc */
#define HPC3_ETXBCD_EOP 0x40000000 /* Last byte of cur buf is end of packet */
#define HPC3_ETXBCD_EOX 0x80000000 /* This buf is the end of desc chain */
hpcreg tx_ctrl; /* control register */
#define HPC3_ETXCTRL_STAT30 0x0000000f /* Rdonly copy of seeq tx stat reg */
#define HPC3_ETXCTRL_STAT4 0x00000010 /* Indicate late collision occurred */
#define HPC3_ETXCTRL_STAT75 0x000000e0 /* Rdonly irq status from seeq */
#define HPC3_ETXCTRL_ENDIAN 0x00000100 /* Dma channel endian mode, 1=little 0=big */
#define HPC3_ETXCTRL_ACTIVE 0x00000200 /* DMA tx channel is active */
#define HPC3_ETXCTRL_AMASK 0x00000400 /* Indicates ACTIVE inhibits PIO's */
hpcreg tx_gfptr; /* current GIO fifo ptr */
hpcreg tx_dfptr; /* current device fifo ptr */
char _unused5[PAGE_SIZE - (4 * sizeof(hpcreg))]; /* padding */
};
struct hpc3_regs {
/* First regs for the PBUS 8 dma channels. */
struct hpc3_pbus_dmacregs pbdma[8];
/* Now the HPC scsi registers, we get two scsi reg sets. */
struct hpc3_scsiregs scsi_chan0, scsi_chan1;
/* The SEEQ hpc3 ethernet dma/control registers. */
struct hpc3_ethregs ethregs;
/* Here are where the hpc3 fifo's can be directly accessed
* via PIO accesses. Under normal operation we never stick
* our grubby paws in here so it's just padding.
*/
char _unused1[PAGE_SIZE * 24];
/* HPC3 irq status regs. Due to a peculiar bug you need to
* look at two different register addresses to get at all of
* the status bits. The first reg can only reliably report
* bits 4:0 of the status, and the second reg can only
* reliably report bits 9:5 of the hpc3 irq status. I told
* you it was a peculiar bug. ;-)
*/
hpcreg istat0; /* Irq status, only bits <4:0> reliable. */
#define HPC3_ISTAT_PBIMASK 0x0ff /* irq bits for pbus devs 0 --> 7 */
#define HPC3_ISTAT_SC0MASK 0x100 /* irq bit for scsi channel 0 */
#define HPC3_ISTAT_SC1MASK 0x200 /* irq bit for scsi channel 1 */
hpcreg gio64_misc; /* GIO64 misc control bits. */
#define HPC3_GIOMISC_ERTIME 0x1 /* Enable external timer real time. */
#define HPC3_GIOMISC_DENDIAN 0x2 /* dma descriptor endian, 1=lit 0=big */
hpcreg eeprom_data; /* EEPROM data reg. */
#define HPC3_EEPROM_EPROT 0x01 /* Protect register enable */
#define HPC3_EEPROM_CSEL 0x02 /* Chip select */
#define HPC3_EEPROM_ECLK 0x04 /* EEPROM clock */
#define HPC3_EEPROM_DATO 0x08 /* Data out */
#define HPC3_EEPROM_DATI 0x10 /* Data in */
hpcreg istat1; /* Irq status, only bits <9:5> reliable. */
hpcreg gio64_estat; /* GIO64 error interrupt status reg. */
#define HPC3_GIOESTAT_BLMASK 0x000ff /* Bus lane where bad parity occurred */
#define HPC3_GIOESTAT_CTYPE 0x00100 /* Bus cycle type, 0=PIO 1=DMA */
#define HPC3_GIOESTAT_PIDMSK 0x3f700 /* DMA channel parity identifier */
/* Now direct PIO per-HPC3 peripheral access to external regs. */
char _unused2[0x13fec]; /* Trust me... */
hpcreg scsi0_ext[256]; /* SCSI channel 0 external regs */
char _unused3[0x07c00]; /* Trust me... */
hpcreg scsi1_ext[256]; /* SCSI channel 1 external regs */
char _unused4[0x07c00]; /* It'll only hurt a little... */
/* Did DaveM forget the ethernet external regs?
* Anyhow, they're not here and we need some padding instead.
*/
char _unused5[0x04000]; /* It'll hurt a lot if you leave this out */
/* Per-peripheral device external registers and dma/pio control. */
hpcreg pbus_extregs[16][256]; /* 2nd indice indexes controller */
hpcreg pbus_dmacfgs[8][128]; /* 2nd indice indexes controller */
#define HPC3_PIODCFG_D3R 0x00000001 /* Cycles to spend in D3 for reads */
#define HPC3_PIODCFG_D4R 0x0000001e /* Cycles to spend in D4 for reads */
#define HPC3_PIODCFG_D5R 0x000001e0 /* Cycles to spend in D5 for reads */
#define HPC3_PIODCFG_D3W 0x00000200 /* Cycles to spend in D3 for writes */
#define HPC3_PIODCFG_D4W 0x00003c00 /* Cycles to spend in D4 for writes */
#define HPC3_PIODCFG_D5W 0x0003c000 /* Cycles to spend in D5 for writes */
#define HPC3_PIODCFG_HWORD 0x00040000 /* Enable 16-bit dma access mode */
#define HPC3_PIODCFG_EHI 0x00080000 /* Places halfwords on high 16 bits of bus */
#define HPC3_PIODCFG_RTIME 0x00200000 /* Make this device real time on GIO bus */
#define HPC3_PIODCFG_BURST 0x07c00000 /* 5 bit burst count for DMA device */
#define HPC3_PIODCFG_DRQLV 0x08000000 /* Use live pbus_dreq unsynchronized signal */
hpcreg pbus_piocfgs[64][10]; /* 2nd indice indexes controller */
#define HPC3_PIOPCFG_RP2 0x00001 /* Cycles to spend in P2 state for reads */
#define HPC3_PIOPCFG_RP3 0x0001e /* Cycles to spend in P3 state for reads */
#define HPC3_PIOPCFG_RP4 0x001e0 /* Cycles to spend in P4 state for reads */
#define HPC3_PIOPCFG_WP2 0x00200 /* Cycles to spend in P2 state for writes */
#define HPC3_PIOPCFG_WP3 0x03c00 /* Cycles to spend in P3 state for writes */
#define HPC3_PIOPCFG_WP4 0x3c000 /* Cycles to spend in P4 state for writes */
#define HPC3_PIOPCFG_HW 0x40000 /* Enable 16-bit PIO accesses */
#define HPC3_PIOPCFG_EHI 0x80000 /* Place even address bits in bits <15:8> */
/* PBUS PROM control regs. */
hpcreg pbus_promwe; /* PROM write enable register */
#define HPC3_PROM_WENAB 0x1 /* Enable writes to the PROM */
char _unused6[0x800 - sizeof(hpcreg)];
hpcreg pbus_promswap; /* Chip select swap reg */
#define HPC3_PROM_SWAP 0x1 /* invert GIO addr bit to select prom0 or prom1 */
char _unused7[0x800 - sizeof(hpcreg)];
hpcreg pbus_gout; /* PROM general purpose output reg */
#define HPC3_PROM_STAT 0x1 /* General purpose status bit in gout */
char _unused8[0x1000 - sizeof(hpcreg)];
hpcreg pbus_promram[16384]; /* 64k of PROM battery backed ram */
};
/* It is possible to have two HPC3's within the address space on
* one machine, though only having one is more likely on an INDY.
* Controller 0 lives at physical address 0x1fb80000 and the controller
* 1 if present lives at address 0x1fb00000.
*/
extern struct hpc3_regs *hpc3c0, *hpc3c1;
#define HPC3_CHIP0_PBASE 0x1fb80000 /* physical */
#define HPC3_CHIP1_PBASE 0x1fb00000 /* physical */
/* Control and misc status information, these live in pbus channel 6. */
struct hpc3_miscregs {
hpcreg pdata, pctrl, pstat, pdmactrl, pistat, pimask;
hpcreg ptimer1, ptimer2, ptimer3, ptimer4;
hpcreg _unused1[2];
hpcreg ser1cmd, ser1data;
hpcreg ser0cmd, ser0data;
hpcreg kbdmouse0, kbdmouse1;
hpcreg gcsel, genctrl, panel;
hpcreg _unused2;
hpcreg sysid;
hpcreg _unused3;
hpcreg read, _unused4;
hpcreg dselect;
#define HPC3_DSELECT_SCLK10MHZ 0x00 /* use 10MHZ serial clock */
#define HPC3_DSELECT_ISDNB 0x01 /* enable isdn B */
#define HPC3_DSELECT_ISDNA 0x02 /* enable isdn A */
#define HPC3_DSELECT_LPR 0x04 /* use parallel DMA */
#define HPC3_DSELECT_SCLK667MHZ 0x10 /* use 6.67MHZ serial clock */
#define HPC3_DSELECT_SCLKEXT 0x20 /* use external serial clock */
hpcreg _unused5;
hpcreg write1;
#define HPC3_WRITE1_PRESET 0x01 /* 0=LPR_RESET, 1=NORMAL */
#define HPC3_WRITE1_KMRESET 0x02 /* 0=KBDMOUSE_RESET, 1=NORMAL */
#define HPC3_WRITE1_ERESET 0x04 /* 0=EISA_RESET, 1=NORMAL */
#define HPC3_WRITE1_GRESET 0x08 /* 0=MAGIC_GIO_RESET, 1=NORMAL */
#define HPC3_WRITE1_LC0OFF 0x10 /* turn led off (guiness=red, else green) */
#define HPC3_WRITE1_LC1OFF 0x20 /* turn led off (guiness=green, else amber) */
hpcreg _unused6;
hpcreg write2;
#define HPC3_WRITE2_NTHRESH 0x01 /* use 4.5db threshhold */
#define HPC3_WRITE2_TPSPEED 0x02 /* use 100ohm TP speed */
#define HPC3_WRITE2_EPSEL 0x04 /* force cable mode: 1=AUI 0=TP */
#define HPC3_WRITE2_EASEL 0x08 /* 1=autoselect 0=manual cable selection */
#define HPC3_WRITE2_U1AMODE 0x10 /* 1=PC 0=MAC UART mode */
#define HPC3_WRITE2_U0AMODE 0x20 /* 1=PC 0=MAC UART mode */
#define HPC3_WRITE2_MLO 0x40 /* 1=4.75V 0=+5V */
#define HPC3_WRITE2_MHI 0x80 /* 1=5.25V 0=+5V */
};
extern struct hpc3_miscregs *hpc3mregs;
#define HPC3_MREGS_PBASE 0x1fbd9800 /* physical */
/* We need software copies of these because they are write only. */
extern unsigned int sgi_hpc_write1, sgi_hpc_write2;
struct hpc_keyb {
#ifdef __MIPSEB__
unsigned char _unused0[3];
volatile unsigned char data;
unsigned char _unused1[3];
volatile unsigned char command;
#else
volatile unsigned char data;
unsigned char _unused0[3];
volatile unsigned char command;
unsigned char _unused1[3];
#endif
};
/* Indy RTC */
/* The layout of registers for the INDY Dallas 1286 clock chipset. */
struct indy_clock {
volatile unsigned int hsec;
volatile unsigned int sec;
volatile unsigned int min;
volatile unsigned int malarm;
volatile unsigned int hr;
volatile unsigned int halarm;
volatile unsigned int day;
volatile unsigned int dalarm;
volatile unsigned int date;
volatile unsigned int month;
volatile unsigned int year;
volatile unsigned int cmd;
volatile unsigned int whsec;
volatile unsigned int wsec;
volatile unsigned int _unused0[50];
};
#define INDY_CLOCK_REGS (KSEG1ADDR(0x1fbe0000))
extern void sgihpc_init(void);
#endif /* !(_MIPS_SGIHPC_H) */
include/asm-mips/sgi/sgimc.h deleted 100644 → 0
View file @ f19e2d9e
/* $Id: sgimc.h,v 1.1.1.1 1997/06/01 03:17:13 ralf Exp $
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* sgimc.h: Definitions for memory controller hardware found on
* SGI IP20, IP22, IP26, and IP28 machines.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
* Copyright (C) 1999 Ralf Baechle
* Copyright (C) 1999 Silicon Graphics, Inc.
*/
#ifndef _ASM_SGI_SGIMC_H
#define _ASM_SGI_SGIMC_H
struct sgimc_misc_ctrl {
u32 _unused1;
volatile u32 cpuctrl0; /* CPU control register 0, readwrite */
#define SGIMC_CCTRL0_REFS 0x0000000f /* REFS mask */
#define SGIMC_CCTRL0_EREFRESH 0x00000010 /* Memory refresh enable */
#define SGIMC_CCTRL0_EPERRGIO 0x00000020 /* GIO parity error enable */
#define SGIMC_CCTRL0_EPERRMEM 0x00000040 /* Main mem parity error enable */
#define SGIMC_CCTRL0_EPERRCPU 0x00000080 /* CPU bus parity error enable */
#define SGIMC_CCTRL0_WDOG 0x00000100 /* Watchdog timer enable */
#define SGIMC_CCTRL0_SYSINIT 0x00000200 /* System init bit */
#define SGIMC_CCTRL0_GFXRESET 0x00000400 /* Graphics interface reset */
#define SGIMC_CCTRL0_EISALOCK 0x00000800 /* Lock CPU from memory for EISA */
#define SGIMC_CCTRL0_EPERRSCMD 0x00001000 /* SysCMD bus parity error enable */
#define SGIMC_CCTRL0_IENAB 0x00002000 /* Allow interrupts from MC */
#define SGIMC_CCTRL0_ESNOOP 0x00004000 /* Snooping I/O enable */
#define SGIMC_CCTRL0_EPROMWR 0x00008000 /* Prom writes from cpu enable */
#define SGIMC_CCTRL0_WRESETPMEM 0x00010000 /* Perform warm reset, preserves mem */
#define SGIMC_CCTRL0_LENDIAN 0x00020000 /* Put MC in little-endian mode */
#define SGIMC_CCTRL0_WRESETDMEM 0x00040000 /* Warm reset, destroys mem contents */
#define SGIMC_CCTRL0_CMEMBADPAR 0x02000000 /* Generate bad perr from cpu to mem */
#define SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */
#define SGIMC_CCTRL0_GIOBTOB 0x08000000 /* Allow GIO back to back writes */
u32 _unused2;
volatile u32 cpuctrl1; /* CPU control register 1, readwrite */
#define SGIMC_CCTRL1_EGIOTIMEO 0x00000010 /* GIO bus timeout enable */
#define SGIMC_CCTRL1_FIXEDEHPC 0x00001000 /* Fixed HPC endianness */
#define SGIMC_CCTRL1_LITTLEHPC 0x00002000 /* Little endian HPC */
#define SGIMC_CCTRL1_FIXEDEEXP0 0x00004000 /* Fixed EXP0 endianness */
#define SGIMC_CCTRL1_LITTLEEXP0 0x00008000 /* Little endian EXP0 */
#define SGIMC_CCTRL1_FIXEDEEXP1 0x00010000 /* Fixed EXP1 endianness */
#define SGIMC_CCTRL1_LITTLEEXP1 0x00020000 /* Little endian EXP1 */
u32 _unused3;
volatile u32 watchdogt; /* Watchdog reg rdonly, write clears */
u32 _unused4;
volatile u32 systemid; /* MC system ID register, readonly */
#define SGIMC_SYSID_MASKREV 0x0000000f /* Revision of MC controller */
#define SGIMC_SYSID_EPRESENT 0x00000010 /* Indicates presence of EISA bus */
u32 _unused5[3];
volatile u32 divider; /* Divider reg for RPSS */
u32 _unused6;
volatile unsigned char eeprom; /* EEPROM byte reg for r4k */
#define SGIMC_EEPROM_PRE 0x00000001 /* eeprom chip PRE pin assertion */
#define SGIMC_EEPROM_CSEL 0x00000002 /* Active high, eeprom chip select */
#define SGIMC_EEPROM_SECLOCK 0x00000004 /* EEPROM serial clock */
#define SGIMC_EEPROM_SDATAO 0x00000008 /* Serial EEPROM data-out */
#define SGIMC_EEPROM_SDATAI 0x00000010 /* Serial EEPROM data-in */
unsigned char _unused7[3];
u32 _unused8[3];
volatile unsigned short rcntpre; /* Preload refresh counter */
unsigned short _unused9;
u32 _unused9a;
volatile unsigned short rcounter; /* Readonly refresh counter */
unsigned short _unused10;
u32 _unused11[13];
volatile u32 gioparm; /* Parameter word for GIO64 */
#define SGIMC_GIOPARM_HPC64 0x00000001 /* HPC talks to GIO using 64-bits */
#define SGIMC_GIOPARM_GFX64 0x00000002 /* GFX talks to GIO using 64-bits */
#define SGIMC_GIOPARM_EXP064 0x00000004 /* EXP(slot0) talks using 64-bits */
#define SGIMC_GIOPARM_EXP164 0x00000008 /* EXP(slot1) talks using 64-bits */
#define SGIMC_GIOPARM_EISA64 0x00000010 /* EISA bus talks 64-bits to GIO */
#define SGIMC_GIOPARM_HPC264 0x00000020 /* 2nd HPX talks 64-bits to GIO */
#define SGIMC_GIOPARM_RTIMEGFX 0x00000040 /* GFX device has realtime attr */
#define SGIMC_GIOPARM_RTIMEEXP0 0x00000080 /* EXP(slot0) has realtime attr */
#define SGIMC_GIOPARM_RTIMEEXP1 0x00000100 /* EXP(slot1) has realtime attr */
#define SGIMC_GIOPARM_MASTEREISA 0x00000200 /* EISA bus can act as bus master */
#define SGIMC_GIOPARM_ONEBUS 0x00000400 /* Exists one GIO64 pipelined bus */
#define SGIMC_GIOPARM_MASTERGFX 0x00000800 /* GFX can act as a bus master */
#define SGIMC_GIOPARM_MASTEREXP0 0x00001000 /* EXP(slot0) can bus master */
#define SGIMC_GIOPARM_MASTEREXP1 0x00002000 /* EXP(slot1) can bus master */
#define SGIMC_GIOPARM_PLINEEXP0 0x00004000 /* EXP(slot0) has pipeline attr */
#define SGIMC_GIOPARM_PLINEEXP1 0x00008000 /* EXP(slot1) has pipeline attr */
u32 _unused13;
volatile unsigned short cputp; /* CPU bus arb time period */
unsigned short _unused14;
u32 _unused15[3];
volatile unsigned short lbursttp; /* Time period for long bursts */
unsigned short _unused16;
u32 _unused17[9];
volatile u32 mconfig0; /* Memory config register zero */
u32 _unused18;
volatile u32 mconfig1; /* Memory config register one */
/* These defines apply to both mconfig registers above. */
#define SGIMC_MCONFIG_FOURMB 0x00000000 /* Physical ram = 4megs */
#define SGIMC_MCONFIG_EIGHTMB 0x00000100 /* Physical ram = 8megs */
#define SGIMC_MCONFIG_SXTEENMB 0x00000300 /* Physical ram = 16megs */
#define SGIMC_MCONFIG_TTWOMB 0x00000700 /* Physical ram = 32megs */
#define SGIMC_MCONFIG_SFOURMB 0x00000f00 /* Physical ram = 64megs */
#define SGIMC_MCONFIG_OTEIGHTMB 0x00001f00 /* Physical ram = 128megs */
#define SGIMC_MCONFIG_RMASK 0x00001f00 /* Ram config bitmask */
u32 _unused19;
volatile u32 cmacc; /* Mem access config for CPU */
u32 _unused20;
volatile u32 gmacc; /* Mem access config for GIO */
/* This define applies to both cmacc and gmacc registers above. */
#define SGIMC_MACC_ALIASBIG 0x20000000 /* 512MB home for alias */
/* Error address/status regs from GIO and CPU perspectives. */
u32 _unused21;
volatile u32 cerr; /* Error address reg for CPU */
u32 _unused22;
volatile u32 cstat; /* Status reg for CPU */
u32 _unused23;
volatile u32 gerr; /* Error address reg for GIO */
u32 _unused24;
volatile u32 gstat; /* Status reg for GIO */
/* Special hard bus locking registers. */
u32 _unused25;
volatile unsigned char syssembit; /* Uni-bit system semaphore */
unsigned char _unused26[3];
u32 _unused27;
volatile unsigned char mlock; /* Global GIO memory access lock */
unsigned char _unused28[3];
u32 _unused29;
volatile unsigned char elock; /* Locks EISA from GIO accesses */
/* GIO dma control registers. */
unsigned char _unused30[3];
u32 _unused31[14];
volatile u32 gio_dma_trans;/* DMA mask to translation GIO addrs */
u32 _unused32;
volatile u32 gio_dma_sbits;/* DMA GIO addr substitution bits */
u32 _unused33;
volatile u32 dma_intr_cause; /* DMA IRQ cause indicator bits */
u32 _unused34;
volatile u32 dma_ctrl; /* Main DMA control reg */
/* DMA TLB entry 0 */
u32 _unused35;
volatile u32 dtlb_hi0;
u32 _unused36;
volatile u32 dtlb_lo0;
/* DMA TLB entry 1 */
u32 _unused37;
volatile u32 dtlb_hi1;
u32 _unused38;
volatile u32 dtlb_lo1;
/* DMA TLB entry 2 */
u32 _unused39;
volatile u32 dtlb_hi2;
u32 _unused40;
volatile u32 dtlb_lo2;
/* DMA TLB entry 3 */
u32 _unused41;
volatile u32 dtlb_hi3;
u32 _unused42;
volatile u32 dtlb_lo3;
};
/* MC misc control registers live at physical 0x1fa00000. */
extern struct sgimc_misc_ctrl *mcmisc_regs;
extern u32 *rpsscounter; /* Chirps at 100ns */
struct sgimc_dma_ctrl {
u32 _unused1;
volatile u32 maddronly; /* Address DMA goes at */
u32 _unused2;
volatile u32 maddrpdeflts; /* Same as above, plus set defaults */
u32 _unused3;
volatile u32 dmasz; /* DMA count */
u32 _unused4;
volatile u32 ssize; /* DMA stride size */
u32 _unused5;
volatile u32 gmaddronly; /* Set GIO DMA but do not start trans */
u32 _unused6;
volatile u32 dmaddnpgo; /* Set GIO DMA addr + start transfer */
u32 _unused7;
volatile u32 dmamode; /* DMA mode config bit settings */
u32 _unused8;
volatile u32 dmaccount; /* Zoom and byte count for DMA */
u32 _unused9;
volatile u32 dmastart; /* Pedal to the metal. */
u32 _unused10;
volatile u32 dmarunning; /* DMA op is in progress */
u32 _unused11;
/* Set dma addr, defaults, and kick it */
volatile u32 maddr_defl_go; /* go go go! -lm */
};
/* MC controller dma regs live at physical 0x1fa02000. */
extern struct sgimc_dma_ctrl *dmactrlregs;
/* Base location of the two ram banks found in IP2[0268] machines. */
#define SGIMC_SEG0_BADDR 0x08000000
#define SGIMC_SEG1_BADDR 0x20000000
/* Maximum size of the above banks are per machine. */
extern u32 sgimc_seg0_size, sgimc_seg1_size;
#define SGIMC_SEG0_SIZE_ALL 0x10000000 /* 256MB */
#define SGIMC_SEG1_SIZE_IP20_IP22 0x08000000 /* 128MB */
#define SGIMC_SEG1_SIZE_IP26_IP28 0x20000000 /* 512MB */
extern void sgimc_init(void);
#endif /* _ASM_SGI_SGIMC_H */
include/asm-mips/sgi/sgint23.h deleted 100644 → 0
View file @ f19e2d9e
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* sgint23.h: Defines for the SGI INT2 and INT3 chipsets.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
* Copyright (C) 1997, 98, 1999, 2000 Ralf Baechle
* Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) - INT2 corrections
*/
#ifndef _ASM_SGI_SGINT23_H
#define _ASM_SGI_SGINT23_H
/* These are the virtual IRQ numbers, we divide all IRQ's into
* 'spaces', the 'space' determines where and how to enable/disable
* that particular IRQ on an SGI machine. Add new 'spaces' as new
* IRQ hardware is supported.
*/
#define SGINT_LOCAL0 0 /* INDY has 8 local0 irq levels */
#define SGINT_LOCAL1 8 /* INDY has 8 local1 irq levels */
#define SGINT_LOCAL2 16 /* INDY has 8 local2 vectored irq levels */
#define SGINT_LOCAL3 24 /* INDY has 8 local3 vectored irq levels */
#define SGINT_GIO 32 /* INDY has 9 GIO irq levels */
#define SGINT_HPCDMA 41 /* INDY has 11 HPCDMA irq _sources_ */
#define SGINT_END 52 /* End of 'spaces' */
/*
* Individual interrupt definitions for the INDY and Indigo2
*/
#define SGI_WD93_0_IRQ SGINT_LOCAL0 + 1 /* 1st onboard WD93 */
#define SGI_WD93_1_IRQ SGINT_LOCAL0 + 2 /* 2nd onboard WD93 */
#define SGI_ENET_IRQ SGINT_LOCAL0 + 3 /* onboard ethernet */
#define SGI_PANEL_IRQ SGINT_LOCAL1 + 1 /* front panel */
#define SGI_EISA_IRQ SGINT_LOCAL2 + 3 /* EISA interrupts */
#define SGI_KEYBOARD_IRQ SGINT_LOCAL2 + 4 /* keyboard */
#define SGI_SERIAL_IRQ SGINT_LOCAL2 + 5 /* onboard serial */
/* INT2 occupies HPC PBUS slot 4, INT3 uses slot 6. */
#define SGI_INT2_BASE 0x1fbd9000 /* physical */
#define SGI_INT3_BASE 0x1fbd9880 /* physical */
struct sgi_ioc_ints {
#ifdef __MIPSEB__
unsigned char _unused0[3];
volatile unsigned char istat0; /* Interrupt status zero */
#else
volatile unsigned char istat0; /* Interrupt status zero */
unsigned char _unused0[3];
#endif
#define ISTAT0_FFULL 0x01
#define ISTAT0_SCSI0 0x02
#define ISTAT0_SCSI1 0x04
#define ISTAT0_ENET 0x08
#define ISTAT0_GFXDMA 0x10
#define ISTAT0_LPR 0x20
#define ISTAT0_HPC2 0x40
#define ISTAT0_LIO2 0x80
#ifdef __MIPSEB__
unsigned char _unused1[3];
volatile unsigned char imask0; /* Interrupt mask zero */
unsigned char _unused2[3];
volatile unsigned char istat1; /* Interrupt status one */
#else
volatile unsigned char imask0; /* Interrupt mask zero */
unsigned char _unused1[3];
volatile unsigned char istat1; /* Interrupt status one */
unsigned char _unused2[3];
#endif
#define ISTAT1_ISDNI 0x01
#define ISTAT1_PWR 0x02
#define ISTAT1_ISDNH 0x04
#define ISTAT1_LIO3 0x08
#define ISTAT1_HPC3 0x10
#define ISTAT1_AFAIL 0x20
#define ISTAT1_VIDEO 0x40
#define ISTAT1_GIO2 0x80
#ifdef __MIPSEB__
unsigned char _unused3[3];
volatile unsigned char imask1; /* Interrupt mask one */
unsigned char _unused4[3];
volatile unsigned char vmeistat; /* VME interrupt status */
unsigned char _unused5[3];
volatile unsigned char cmeimask0; /* VME interrupt mask zero */
unsigned char _unused6[3];
volatile unsigned char cmeimask1; /* VME interrupt mask one */
unsigned char _unused7[3];
volatile unsigned char cmepol; /* VME polarity */
#else
volatile unsigned char imask1; /* Interrupt mask one */
unsigned char _unused3[3];
volatile unsigned char vmeistat; /* VME interrupt status */
unsigned char _unused4[3];
volatile unsigned char cmeimask0; /* VME interrupt mask zero */
unsigned char _unused5[3];
volatile unsigned char cmeimask1; /* VME interrupt mask one */
unsigned char _unused6[3];
volatile unsigned char cmepol; /* VME polarity */
unsigned char _unused7[3];
#endif
};
struct sgi_ioc_timers {
#ifdef __MIPSEB__
unsigned char _unused0[3];
volatile unsigned char tcnt0; /* counter 0 */
unsigned char _unused1[3];
volatile unsigned char tcnt1; /* counter 1 */
unsigned char _unused2[3];
volatile unsigned char tcnt2; /* counter 2 */
unsigned char _unused3[3];
volatile unsigned char tcword; /* control word */
#else
volatile unsigned char tcnt0; /* counter 0 */
unsigned char _unused0[3];
volatile unsigned char tcnt1; /* counter 1 */
unsigned char _unused1[3];
volatile unsigned char tcnt2; /* counter 2 */
unsigned char _unused2[3];
volatile unsigned char tcword; /* control word */
unsigned char _unused3[3];
#endif
};
/* Timer control word bits. */
#define SGINT_TCWORD_BCD 0x01 /* Use BCD mode for counters */
#define SGINT_TCWORD_MMASK 0x0e /* Mode bitmask. */
#define SGINT_TCWORD_MITC 0x00 /* IRQ on terminal count (doesn't work) */
#define SGINT_TCWORD_MOS 0x02 /* One-shot IRQ mode. */
#define SGINT_TCWORD_MRGEN 0x04 /* Normal rate generation */
#define SGINT_TCWORD_MSWGEN 0x06 /* Square wave generator mode */
#define SGINT_TCWORD_MSWST 0x08 /* Software strobe */
#define SGINT_TCWORD_MHWST 0x0a /* Hardware strobe */
#define SGINT_TCWORD_CMASK 0x30 /* Command mask */
#define SGINT_TCWORD_CLAT 0x00 /* Latch command */
#define SGINT_TCWORD_CLSB 0x10 /* LSB read/write */
#define SGINT_TCWORD_CMSB 0x20 /* MSB read/write */
#define SGINT_TCWORD_CALL 0x30 /* Full counter read/write */
#define SGINT_TCWORD_CNT0 0x00 /* Select counter zero */
#define SGINT_TCWORD_CNT1 0x40 /* Select counter one */
#define SGINT_TCWORD_CNT2 0x80 /* Select counter two */
#define SGINT_TCWORD_CRBCK 0xc0 /* Readback command */
#define SGINT_TCSAMP_COUNTER 10255
/* FIXME: What does this really look like? It was written to have
* 17 registers, but there are only 16 in my Indigo2.
* I guessed at which one to remove... - andrewb
*/
struct sgi_int2_regs {
struct sgi_ioc_ints ints;
volatile u32 ledbits; /* LED control bits */
#define INT2_LED_TXCLK 0x01 /* GPI to TXCLK enable */
#define INT2_LED_SERSLCT0 0x02 /* serial port0: 0=apple 1=pc */
#define INT2_LED_SERSLCT1 0x04 /* serial port1: 0=apple 1=pc */
#define INT2_LED_CHEAPER 0x08 /* 0=cheapernet 1=ethernet */
#define INT2_LED_POWEROFF 0x10 /* Power-off request, active high */
#ifdef __MIPSEB__
unsigned char _unused0[3];
volatile unsigned char tclear; /* Timer clear strobe address */
#else
volatile unsigned char tclear; /* Timer clear strobe address */
unsigned char _unused0[3];
#endif
#define INT2_TCLEAR_T0CLR 0x1 /* Clear timer0 IRQ */
#define INT2_TCLEAR_T1CLR 0x2 /* Clear timer1 IRQ */
/* I am guesing there are only two unused registers here
* but I could be wrong... - andrewb
*/
/* u32 _unused[3]; */
u32 _unused[2];
struct sgi_ioc_timers timers;
};
struct sgi_int3_regs {
struct sgi_ioc_ints ints;
#ifdef __MIPSEB__
unsigned char _unused0[3];
volatile unsigned char tclear; /* Timer clear strobe address */
#else
volatile unsigned char tclear; /* Timer clear strobe address */
unsigned char _unused0[3];
#endif
volatile u32 estatus; /* Error status reg */
u32 _unused1[2];
struct sgi_ioc_timers timers;
};
extern struct sgi_int2_regs *sgi_i2regs;
extern struct sgi_int3_regs *sgi_i3regs;
extern struct sgi_ioc_ints *ioc_icontrol;
extern struct sgi_ioc_timers *ioc_timers;
extern volatile unsigned char *ioc_tclear;
extern void sgint_init(void);
extern void indy_timer_init(void);
#endif /* _ASM_SGI_SGINT23_H */
include/asm-mips64/rrm.h deleted 100644 → 0
View file @ f19e2d9e
/*
* SGI Rendering Resource Manager API (?).
*
* written by Miguel de Icaza (miguel@nuclecu.unam.mx)
*
* Ok, even if SGI choosed to do mmap trough ioctls, their
* kernel support for virtualizing the graphics card is nice.
*
* We should be able to make graphic applications on Linux
* fly.
*
* This header file should be included from GNU libc as well.
*/
/* Why like this you say? Well, gdb can print enums */
#define RRM_BASE 1000
#define RRM_CMD_LIMIT (RRM_BASE + 100)
enum {
RRM_OPENRN = RRM_BASE, /* open rendering node */
RRM_CLOSERN,
RRM_BINDPROCTORN, /* set current rendering region for node */
RRM_BINDRNTOCLIP,
RRM_UNBINDRNFROMCLIP,
RRM_SWAPBUF,
RRM_SETSWAPINTERVAL,
RRM_WAITFORRETRACE,
RRM_SETDISPLAYMODE,
RRM_MESSAGE,
RRM_INVALIDATERN,
RRM_VALIDATECLIP,
RRM_VALIDATESWAPBUF,
RRM_SWAPGROUP,
RRM_SWAPUNGROUP,
RRM_VALIDATEMESSAGE,
RRM_GETDISPLAYMODES,
RRM_LOADDISPLAYMODE,
RRM_CUSHIONBUFFER,
RRM_SWAPREADY,
RRM_MGR_SWAPBUF,
RRM_SETVSYNC,
RRM_GETVSYNC,
RRM_WAITVSYNC,
RRM_BINDRNTOREADANDCLIP,
RRM_MAPCLIPTOSWPBUFID
};
/* Parameters for the above ioctls
*
* All of the ioctls take as their first argument the rendering node id.
*
*/
/*
* RRM_OPENRN:
*
* This is called by the IRIX X server with:
* rnid = 0xffffffff rmask = 0
*
* Returns a number like this: 0x10001.
* If you run the X server over and over, you get a value
* that is of the form (n * 0x10000) + 1.
*
* The return value seems to be the RNID.
*/
struct RRM_OpenRN {
int rnid;
unsigned int rmask;
};
struct RRM_CloseRN {
int rnid;
};
/*
* RRM_BINDPROCTORN:
*
* Return value when the X server calls it: 0
*/
struct RRM_BindProcToRN {
int rnid;
};
#ifdef __KERNEL__
int rrm_command (unsigned int cmd, void *arg);
int rrm_close (struct inode *inode, struct file *file);
#endif
include/asm-mips64/sgi/gio.h 0 → 100644
View file @ 2395133b
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* gio.h: Definitions for SGI GIO bus
*
* Copyright (C) 2002 Ladislav Michl
*/
#ifndef _SGI_GIO_H
#define _SGI_GIO_H
/*
* GIO bus addresses
*
* The Indigo and Indy have two GIO bus connectors. Indigo2 (all models) have
* three physical connectors, but only two slots, GFX and EXP0.
*
* There is 10MB of GIO address space for GIO64 slot devices
* slot# slot type address range size
* ----- --------- ----------------------- -----
* 0 GFX 0x1f000000 - 0x1f3fffff 4MB
* 1 EXP0 0x1f400000 - 0x1f5fffff 2MB
* 2 EXP1 0x1f600000 - 0x1f9fffff 4MB
*
* There are un-slotted devices, HPC, I/O and misc devices, which are grouped
* into the HPC address space.
* - MISC 0x1fb00000 - 0x1fbfffff 1MB
*
* Following space is reserved and unused
* - RESERVED 0x18000000 - 0x1effffff 112MB
*
* GIO bus IDs
*
* Each GIO bus device identifies itself to the system by answering a
* read with an "ID" value. IDs are either 8 or 32 bits long. IDs less
* than 128 are 8 bits long, with the most significant 24 bits read from
* the slot undefined.
*
* 32-bit IDs are divided into
* bits 0:6 the product ID; ranges from 0x00 to 0x7F.
* bit 7 0=GIO Product ID is 8 bits wide
* 1=GIO Product ID is 32 bits wide.
* bits 8:15 manufacturer version for the product.
* bit 16 0=GIO32 and GIO32-bis, 1=GIO64.
* bit 17 0=no ROM present
* 1=ROM present on this board AND next three words
* space define the ROM.
* bits 18:31 up to manufacturer.
*
* IDs above 0x50/0xd0 are of 3rd party boards.
*
* 8-bit IDs
* 0x01 XPI low cost FDDI
* 0x02 GTR TokenRing
* 0x04 Synchronous ISDN
* 0x05 ATM board [*]
* 0x06 Canon Interface
* 0x07 16 bit SCSI Card [*]
* 0x08 JPEG (Double Wide)
* 0x09 JPEG (Single Wide)
* 0x0a XPI mez. FDDI device 0
* 0x0b XPI mez. FDDI device 1
* 0x0c SMPTE 259M Video [*]
* 0x0d Babblefish Compression [*]
* 0x0e E-Plex 8-port Ethernet
* 0x30 Lyon Lamb IVAS
* 0xb8 GIO 100BaseTX Fast Ethernet (gfe)
*
* [*] Device provide 32-bit ID.
*
*/
#define GIO_ID(x) (x & 0x7f)
#define GIO_32BIT_ID 0x80
#define GIO_REV(x) ((x >> 8) & 0xff)
#define GIO_64BIT_IFACE 0x10000
#define GIO_ROM_PRESENT 0x20000
#define GIO_VENDOR_CODE(x) ((x >> 18) & 0x3fff)
#define GIO_SLOT_GFX_BASE 0x1f000000
#define GIO_SLOT_EXP0_BASE 0x1f400000
#define GIO_SLOT_EXP1_BASE 0x1f600000
#endif /* _SGI_GIO_H */
include/asm-mips64/sgi/hpc3.h 0 → 100644
View file @ 2395133b
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* hpc3.h: Definitions for SGI HPC3 controller
*
* Copyright (C) 1996 David S. Miller
* Copyright (C) 1998 Ralf Baechle
*/
#ifndef _SGI_HPC3_H
#define _SGI_HPC3_H
#include <linux/types.h>
#include <asm/page.h>
/* An HPC DMA descriptor. */
struct hpc_dma_desc {
u32 pbuf; /* physical address of data buffer */
u32 cntinfo; /* counter and info bits */
#define HPCDMA_EOX 0x80000000 /* last desc in chain for tx */
#define HPCDMA_EOR 0x80000000 /* last desc in chain for rx */
#define HPCDMA_EOXP 0x40000000 /* end of packet for tx */
#define HPCDMA_EORP 0x40000000 /* end of packet for rx */
#define HPCDMA_XIE 0x20000000 /* irq generated when at end of this desc */
#define HPCDMA_XIU 0x01000000 /* Tx buffer in use by CPU. */
#define HPCDMA_EIPC 0x00ff0000 /* SEEQ ethernet special xternal bytecount */
#define HPCDMA_ETXD 0x00008000 /* set to one by HPC when packet tx'd */
#define HPCDMA_OWN 0x00004000 /* Denotes ring buffer ownership on rx */
#define HPCDMA_BCNT 0x00003fff /* size in bytes of this dma buffer */
u32 pnext; /* paddr of next hpc_dma_desc if any */
};
/* The set of regs for each HPC3 PBUS DMA channel. */
struct hpc3_pbus_dmacregs {
volatile u32 pbdma_bptr; /* pbus dma channel buffer ptr */
volatile u32 pbdma_dptr; /* pbus dma channel desc ptr */
u32 _unused0[0x1000/4 - 2]; /* padding */
volatile u32 pbdma_ctrl; /* pbus dma channel control register has
* copletely different meaning for read
* compared with write */
/* read */
#define HPC3_PDMACTRL_INT 0x00000001 /* interrupt (cleared after read) */
#define HPC3_PDMACTRL_ISACT 0x00000002 /* channel active */
/* write */
#define HPC3_PDMACTRL_SEL 0x00000002 /* little endian transfer */
#define HPC3_PDMACTRL_RCV 0x00000004 /* direction is receive */
#define HPC3_PDMACTRL_FLSH 0x00000008 /* enable flush for receive DMA */
#define HPC3_PDMACTRL_ACT 0x00000010 /* start dma transfer */
#define HPC3_PDMACTRL_LD 0x00000020 /* load enable for ACT */
#define HPC3_PDMACTRL_RT 0x00000040 /* Use realtime GIO bus servicing */
#define HPC3_PDMACTRL_HW 0x0000ff00 /* DMA High-water mark */
#define HPC3_PDMACTRL_FB 0x003f0000 /* Ptr to beginning of fifo */
#define HPC3_PDMACTRL_FE 0x3f000000 /* Ptr to end of fifo */
u32 _unused1[0x1000/4 - 1]; /* padding */
};
/* The HPC3 SCSI registers, this does not include external ones. */
struct hpc3_scsiregs {
volatile u32 cbptr; /* current dma buffer ptr, diagnostic use only */
volatile u32 ndptr; /* next dma descriptor ptr */
u32 _unused0[0x1000/4 - 2]; /* padding */
volatile u32 bcd; /* byte count info */
#define HPC3_SBCD_BCNTMSK 0x00003fff /* bytes to transfer from/to memory */
#define HPC3_SBCD_XIE 0x00004000 /* Send IRQ when done with cur buf */
#define HPC3_SBCD_EOX 0x00008000 /* Indicates this is last buf in chain */
volatile u32 ctrl; /* control register */
#define HPC3_SCTRL_IRQ 0x01 /* IRQ asserted, either dma done or parity */
#define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */
#define HPC3_SCTRL_DIR 0x04 /* DMA direction, 1=dev2mem 0=mem2dev */
#define HPC3_SCTRL_FLUSH 0x08 /* Tells HPC3 to flush scsi fifos */
#define HPC3_SCTRL_ACTIVE 0x10 /* SCSI DMA channel is active */
#define HPC3_SCTRL_AMASK 0x20 /* DMA active inhibits PIO */
#define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */
#define HPC3_SCTRL_PERR 0x80 /* Bad parity on HPC3 iface to scsi controller */
volatile u32 gfptr; /* current GIO fifo ptr */
volatile u32 dfptr; /* current device fifo ptr */
volatile u32 dconfig; /* DMA configuration register */
#define HPC3_SDCFG_HCLK 0x00001 /* Enable DMA half clock mode */
#define HPC3_SDCFG_D1 0x00006 /* Cycles to spend in D1 state */
#define HPC3_SDCFG_D2 0x00038 /* Cycles to spend in D2 state */
#define HPC3_SDCFG_D3 0x001c0 /* Cycles to spend in D3 state */
#define HPC3_SDCFG_HWAT 0x00e00 /* DMA high water mark */
#define HPC3_SDCFG_HW 0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
#define HPC3_SDCFG_SWAP 0x02000 /* Byte swap all DMA accesses */
#define HPC3_SDCFG_EPAR 0x04000 /* Enable parity checking for DMA */
#define HPC3_SDCFG_POLL 0x08000 /* hd_dreq polarity control */
#define HPC3_SDCFG_ERLY 0x30000 /* hd_dreq behavior control bits */
volatile u32 pconfig; /* PIO configuration register */
#define HPC3_SPCFG_P3 0x0003 /* Cycles to spend in P3 state */
#define HPC3_SPCFG_P2W 0x001c /* Cycles to spend in P2 state for writes */
#define HPC3_SPCFG_P2R 0x01e0 /* Cycles to spend in P2 state for reads */
#define HPC3_SPCFG_P1 0x0e00 /* Cycles to spend in P1 state */
#define HPC3_SPCFG_HW 0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
#define HPC3_SPCFG_SWAP 0x2000 /* Byte swap all PIO accesses */
#define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */
#define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */
u32 _unused1[0x1000/4 - 6]; /* padding */
};
/* SEEQ ethernet HPC3 registers, only one seeq per HPC3. */
struct hpc3_ethregs {
/* Receiver registers. */
volatile u32 rx_cbptr; /* current dma buffer ptr, diagnostic use only */
volatile u32 rx_ndptr; /* next dma descriptor ptr */
u32 _unused0[0x1000/4 - 2]; /* padding */
volatile u32 rx_bcd; /* byte count info */
#define HPC3_ERXBCD_BCNTMSK 0x00003fff /* bytes to be sent to memory */
#define HPC3_ERXBCD_XIE 0x20000000 /* HPC3 interrupts cpu at end of this buf */
#define HPC3_ERXBCD_EOX 0x80000000 /* flags this as end of descriptor chain */
volatile u32 rx_ctrl; /* control register */
#define HPC3_ERXCTRL_STAT50 0x0000003f /* Receive status reg bits of Seeq8003 */
#define HPC3_ERXCTRL_STAT6 0x00000040 /* Rdonly irq status */
#define HPC3_ERXCTRL_STAT7 0x00000080 /* Rdonlt old/new status bit from Seeq */
#define HPC3_ERXCTRL_ENDIAN 0x00000100 /* Endian for dma channel, little=1 big=0 */
#define HPC3_ERXCTRL_ACTIVE 0x00000200 /* Tells if DMA transfer is in progress */
#define HPC3_ERXCTRL_AMASK 0x00000400 /* Tells if ACTIVE inhibits PIO's to hpc3 */
#define HPC3_ERXCTRL_RBO 0x00000800 /* Receive buffer overflow if set to 1 */
volatile u32 rx_gfptr; /* current GIO fifo ptr */
volatile u32 rx_dfptr; /* current device fifo ptr */
u32 _unused1; /* padding */
volatile u32 rx_reset; /* reset register */
#define HPC3_ERXRST_CRESET 0x1 /* Reset dma channel and external controller */
#define HPC3_ERXRST_CLRIRQ 0x2 /* Clear channel interrupt */
#define HPC3_ERXRST_LBACK 0x4 /* Enable diagnostic loopback mode of Seeq8003 */
volatile u32 rx_dconfig; /* DMA configuration register */
#define HPC3_ERXDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */
#define HPC3_ERXDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */
#define HPC3_ERXDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO */
#define HPC3_ERXDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */
#define HPC3_ERXDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */
#define HPC3_ERXDCFG_FEOP 0x04000 /* Bad packet marker timeout enable */
#define HPC3_ERXDCFG_FIRQ 0x08000 /* Another bad packet timeout enable */
#define HPC3_ERXDCFG_PTO 0x30000 /* Programmed timeout value for above two */
volatile u32 rx_pconfig; /* PIO configuration register */
#define HPC3_ERXPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */
#define HPC3_ERXPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */
#define HPC3_ERXPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */
#define HPC3_ERXPCFG_TST 0x1000 /* Diagnistic ram test feature bit */
u32 _unused2[0x1000/4 - 8]; /* padding */
/* Transmitter registers. */
volatile u32 tx_cbptr; /* current dma buffer ptr, diagnostic use only */
volatile u32 tx_ndptr; /* next dma descriptor ptr */
u32 _unused3[0x1000/4 - 2]; /* padding */
volatile u32 tx_bcd; /* byte count info */
#define HPC3_ETXBCD_BCNTMSK 0x00003fff /* bytes to be read from memory */
#define HPC3_ETXBCD_ESAMP 0x10000000 /* if set, too late to add descriptor */
#define HPC3_ETXBCD_XIE 0x20000000 /* Interrupt cpu at end of cur desc */
#define HPC3_ETXBCD_EOP 0x40000000 /* Last byte of cur buf is end of packet */
#define HPC3_ETXBCD_EOX 0x80000000 /* This buf is the end of desc chain */
volatile u32 tx_ctrl; /* control register */
#define HPC3_ETXCTRL_STAT30 0x0000000f /* Rdonly copy of seeq tx stat reg */
#define HPC3_ETXCTRL_STAT4 0x00000010 /* Indicate late collision occurred */
#define HPC3_ETXCTRL_STAT75 0x000000e0 /* Rdonly irq status from seeq */
#define HPC3_ETXCTRL_ENDIAN 0x00000100 /* DMA channel endian mode, 1=little 0=big */
#define HPC3_ETXCTRL_ACTIVE 0x00000200 /* DMA tx channel is active */
#define HPC3_ETXCTRL_AMASK 0x00000400 /* Indicates ACTIVE inhibits PIO's */
volatile u32 tx_gfptr; /* current GIO fifo ptr */
volatile u32 tx_dfptr; /* current device fifo ptr */
u32 _unused4[0x1000/4 - 4]; /* padding */
};
struct hpc3_regs {
/* First regs for the PBUS 8 dma channels. */
struct hpc3_pbus_dmacregs pbdma[8];
/* Now the HPC scsi registers, we get two scsi reg sets. */
struct hpc3_scsiregs scsi_chan0, scsi_chan1;
/* The SEEQ hpc3 ethernet dma/control registers. */
struct hpc3_ethregs ethregs;
/* Here are where the hpc3 fifo's can be directly accessed
* via PIO accesses. Under normal operation we never stick
* our grubby paws in here so it's just padding. */
u32 _unused0[0x18000/4];
/* HPC3 irq status regs. Due to a peculiar bug you need to
* look at two different register addresses to get at all of
* the status bits. The first reg can only reliably report
* bits 4:0 of the status, and the second reg can only
* reliably report bits 9:5 of the hpc3 irq status. I told
* you it was a peculiar bug. ;-)
*/
volatile u32 istat0; /* Irq status, only bits <4:0> reliable. */
#define HPC3_ISTAT_PBIMASK 0x0ff /* irq bits for pbus devs 0 --> 7 */
#define HPC3_ISTAT_SC0MASK 0x100 /* irq bit for scsi channel 0 */
#define HPC3_ISTAT_SC1MASK 0x200 /* irq bit for scsi channel 1 */
volatile u32 gio_misc; /* GIO misc control bits. */
#define HPC3_GIOMISC_ERTIME 0x1 /* Enable external timer real time. */
#define HPC3_GIOMISC_DENDIAN 0x2 /* dma descriptor endian, 1=lit 0=big */
volatile u32 eeprom; /* EEPROM data reg. */
#define HPC3_EEPROM_EPROT 0x01 /* Protect register enable */
#define HPC3_EEPROM_CSEL 0x02 /* Chip select */
#define HPC3_EEPROM_ECLK 0x04 /* EEPROM clock */
#define HPC3_EEPROM_DATO 0x08 /* Data out */
#define HPC3_EEPROM_DATI 0x10 /* Data in */
volatile u32 istat1; /* Irq status, only bits <9:5> reliable. */
volatile u32 gio_estat; /* GIO error interrupt status reg. */
#define HPC3_GIOESTAT_BLMASK 0x000ff /* Bus lane where bad parity occurred */
#define HPC3_GIOESTAT_CTYPE 0x00100 /* Bus cycle type, 0=PIO 1=DMA */
#define HPC3_GIOESTAT_PIDMSK 0x3f700 /* DMA channel parity identifier */
u32 _unused1[0x14000/4 - 5]; /* padding */
/* Now direct PIO per-HPC3 peripheral access to external regs. */
volatile u32 scsi0_ext[256]; /* SCSI channel 0 external regs */
u32 _unused2[0x7c00/4];
volatile u32 scsi1_ext[256]; /* SCSI channel 1 external regs */
u32 _unused3[0x7c00/4];
volatile u32 eth_ext[320]; /* Ethernet external registers */
u32 _unused4[0x3b00/4];
/* Per-peripheral device external registers and DMA/PIO control. */
volatile u32 pbus_extregs[16][256];
volatile u32 pbus_dmacfg[8][128];
/* Cycles to spend in D3 for reads */
#define HPC3_DMACFG_D3R_MASK 0x00000001
#define HPC3_DMACFG_D3R_SHIFT 0
/* Cycles to spend in D4 for reads */
#define HPC3_DMACFG_D4R_MASK 0x0000001e
#define HPC3_DMACFG_D4R_SHIFT 1
/* Cycles to spend in D5 for reads */
#define HPC3_DMACFG_D5R_MASK 0x000001e0
#define HPC3_DMACFG_D5R_SHIFT 5
/* Cycles to spend in D3 for writes */
#define HPC3_DMACFG_D3W_MASK 0x00000200
#define HPC3_DMACFG_D3W_SHIFT 9
/* Cycles to spend in D4 for writes */
#define HPC3_DMACFG_D4W_MASK 0x00003c00
#define HPC3_DMACFG_D4W_SHIFT 10
/* Cycles to spend in D5 for writes */
#define HPC3_DMACFG_D5W_MASK 0x0003c000
#define HPC3_DMACFG_D5W_SHIFT 14
/* Enable 16-bit DMA access mode */
#define HPC3_DMACFG_DS16 0x00040000
/* Places halfwords on high 16 bits of bus */
#define HPC3_DMACFG_EVENHI 0x00080000
/* Make this device real time */
#define HPC3_DMACFG_RTIME 0x00200000
/* 5 bit burst count for DMA device */
#define HPC3_DMACFG_BURST_MASK 0x07c00000
#define HPC3_DMACFG_BURST_SHIFT 22
/* Use live pbus_dreq unsynchronized signal */
#define HPC3_DMACFG_DRQLIVE 0x08000000
volatile u32 pbus_piocfg[16][64];
/* Cycles to spend in P2 state for reads */
#define HPC3_PIOCFG_P2R_MASK 0x00001
#define HPC3_PIOCFG_P2R_SHIFT 0
/* Cycles to spend in P3 state for reads */
#define HPC3_PIOCFG_P3R_MASK 0x0001e
#define HPC3_PIOCFG_P3R_SHIFT 1
/* Cycles to spend in P4 state for reads */
#define HPC3_PIOCFG_P4R_MASK 0x001e0
#define HPC3_PIOCFG_P4R_SHIFT 5
/* Cycles to spend in P2 state for writes */
#define HPC3_PIOCFG_P2W_MASK 0x00200
#define HPC3_PIOCFG_P2W_SHIFT 9
/* Cycles to spend in P3 state for writes */
#define HPC3_PIOCFG_P3W_MASK 0x03c00
#define HPC3_PIOCFG_P3W_SHIFT 10
/* Cycles to spend in P4 state for writes */
#define HPC3_PIOCFG_P4W_MASK 0x3c000
#define HPC3_PIOCFG_P4W_SHIFT 14
/* Enable 16-bit PIO accesses */
#define HPC3_PIOCFG_DS16 0x40000
/* Place even address bits in bits <15:8> */
#define HPC3_PIOCFG_EVENHI 0x80000
/* PBUS PROM control regs. */
volatile u32 pbus_promwe; /* PROM write enable register */
#define HPC3_PROM_WENAB 0x1 /* Enable writes to the PROM */
u32 _unused5[0x0800/4 - 1];
volatile u32 pbus_promswap; /* Chip select swap reg */
#define HPC3_PROM_SWAP 0x1 /* invert GIO addr bit to select prom0 or prom1 */
u32 _unused6[0x0800/4 - 1];
volatile u32 pbus_gout; /* PROM general purpose output reg */
#define HPC3_PROM_STAT 0x1 /* General purpose status bit in gout */
u32 _unused7[0x1000/4 - 1];
volatile u32 rtcregs[14]; /* Dallas clock registers */
u32 _unused8[50];
volatile u32 bbram[8192-50-14]; /* Battery backed ram */
};
/*
* It is possible to have two HPC3's within the address space on
* one machine, though only having one is more likely on an Indy.
*/
extern struct hpc3_regs *hpc3c0, *hpc3c1;
#define HPC3_CHIP0_BASE 0x1fb80000 /* physical */
#define HPC3_CHIP1_BASE 0x1fb00000 /* physical */
extern void sgihpc_init(void);
#endif /* _SGI_HPC3_H */
include/asm-mips64/sgi/ioc.h 0 → 100644
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* ioc.h: Definitions for SGI I/O Controller
*
* Copyright (C) 1996 David S. Miller
* Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle
* Copyright (C) 2001, 2003 Ladislav Michl
*/
#ifndef _SGI_IOC_H
#define _SGI_IOC_H
#include <linux/types.h>
/*
* All registers are 8-bit wide alligned on 32-bit boundary. Bad things
* happen if you try word access them. You have been warned.
*/
struct sgioc_pport_regs {
u8 _data[3];
volatile u8 data;
u8 _ctrl[3];
volatile u8 ctrl;
#define SGIOC_PCTRL_STROBE 0x01
#define SGIOC_PCTRL_AFD 0x02
#define SGIOC_PCTRL_INIT 0x04
#define SGIOC_PCTRL_SLIN 0x08
#define SGIOC_PCTRL_DIRECTION 0x20
#define SGIOC_PCTRL_SEL 0x40
u8 _status[3];
volatile u8 status;
#define SGIOC_PSTAT_DEVID 0x03
#define SGIOC_PSTAT_NOINK 0x04
#define SGIOC_PSTAT_ERROR 0x08
#define SGIOC_PSTAT_ONLINE 0x10
#define SGIOC_PSTAT_PE 0x20
#define SGIOC_PSTAT_ACK 0x40
#define SGIOC_PSTAT_BUSY 0x80
u8 _dmactrl[3];
volatile u8 dmactrl;
u8 _intrstat[3];
volatile u8 intrstat;
u8 _intrmask[3];
volatile u8 intrmask;
u8 _timer1[3];
volatile u8 timer1;
u8 _timer2[3];
volatile u8 timer2;
u8 _timer3[3];
volatile u8 timer3;
u8 _timer4[3];
volatile u8 timer4;
};
struct sgioc_uart_regs {
u8 _ctrl1[3];
volatile u8 ctrl1;
u8 _data1[3];
volatile u8 data1;
u8 _ctrl2[3];
volatile u8 ctrl2;
u8 _data2[3];
volatile u8 data2;
};
struct sgioc_keyb_regs {
u8 _data[3];
volatile u8 data;
u8 _command[3];
volatile u8 command;
};
struct sgint_regs {
u8 _istat0[3];
volatile u8 istat0; /* Interrupt status zero */
#define SGINT_ISTAT0_FFULL 0x01
#define SGINT_ISTAT0_SCSI0 0x02
#define SGINT_ISTAT0_SCSI1 0x04
#define SGINT_ISTAT0_ENET 0x08
#define SGINT_ISTAT0_GFXDMA 0x10
#define SGINT_ISTAT0_PPORT 0x20
#define SGINT_ISTAT0_HPC2 0x40
#define SGINT_ISTAT0_LIO2 0x80
u8 _imask0[3];
volatile u8 imask0; /* Interrupt mask zero */
u8 _istat1[3];
volatile u8 istat1; /* Interrupt status one */
#define SGINT_ISTAT1_ISDNI 0x01
#define SGINT_ISTAT1_PWR 0x02
#define SGINT_ISTAT1_ISDNH 0x04
#define SGINT_ISTAT1_LIO3 0x08
#define SGINT_ISTAT1_HPC3 0x10
#define SGINT_ISTAT1_AFAIL 0x20
#define SGINT_ISTAT1_VIDEO 0x40
#define SGINT_ISTAT1_GIO2 0x80
u8 _imask1[3];
volatile u8 imask1; /* Interrupt mask one */
u8 _vmeistat[3];
volatile u8 vmeistat; /* VME interrupt status */
u8 _cmeimask0[3];
volatile u8 cmeimask0; /* VME interrupt mask zero */
u8 _cmeimask1[3];
volatile u8 cmeimask1; /* VME interrupt mask one */
u8 _cmepol[3];
volatile u8 cmepol; /* VME polarity */
u8 _tclear[3];
volatile u8 tclear;
u8 _errstat[3];
volatile u8 errstat; /* Error status reg, reserved on INT2 */
u32 _unused0[2];
u8 _tcnt0[3];
volatile u8 tcnt0; /* counter 0 */
u8 _tcnt1[3];
volatile u8 tcnt1; /* counter 1 */
u8 _tcnt2[3];
volatile u8 tcnt2; /* counter 2 */
u8 _tcword[3];
volatile u8 tcword; /* control word */
#define SGINT_TCWORD_BCD 0x01 /* Use BCD mode for counters */
#define SGINT_TCWORD_MMASK 0x0e /* Mode bitmask. */
#define SGINT_TCWORD_MITC 0x00 /* IRQ on terminal count (doesn't work) */
#define SGINT_TCWORD_MOS 0x02 /* One-shot IRQ mode. */
#define SGINT_TCWORD_MRGEN 0x04 /* Normal rate generation */
#define SGINT_TCWORD_MSWGEN 0x06 /* Square wave generator mode */
#define SGINT_TCWORD_MSWST 0x08 /* Software strobe */
#define SGINT_TCWORD_MHWST 0x0a /* Hardware strobe */
#define SGINT_TCWORD_CMASK 0x30 /* Command mask */
#define SGINT_TCWORD_CLAT 0x00 /* Latch command */
#define SGINT_TCWORD_CLSB 0x10 /* LSB read/write */
#define SGINT_TCWORD_CMSB 0x20 /* MSB read/write */
#define SGINT_TCWORD_CALL 0x30 /* Full counter read/write */
#define SGINT_TCWORD_CNT0 0x00 /* Select counter zero */
#define SGINT_TCWORD_CNT1 0x40 /* Select counter one */
#define SGINT_TCWORD_CNT2 0x80 /* Select counter two */
#define SGINT_TCWORD_CRBCK 0xc0 /* Readback command */
};
#define SGINT_TCSAMP_COUNTER 10255
/* We need software copies of these because they are write only. */
extern u8 sgi_ioc_reset, sgi_ioc_write;
struct sgioc_regs {
struct sgioc_pport_regs pport;
u32 _unused0[2];
struct sgioc_uart_regs serport;
struct sgioc_keyb_regs kbdmouse;
u8 _gcsel[3];
volatile u8 gcsel;
u8 _genctrl[3];
volatile u8 genctrl;
u8 _panel[3];
volatile u8 panel;
#define SGIOC_PANEL_POWERON 0x01
#define SGIOC_PANEL_POWERINTR 0x02
#define SGIOC_PANEL_VOLDNINTR 0x10
#define SGIOC_PANEL_VOLDNHOLD 0x20
#define SGIOC_PANEL_VOLUPINTR 0x40
#define SGIOC_PANEL_VOLUPHOLD 0x80
u32 _unused1;
u8 _sysid[3];
volatile u8 sysid;
#define SGIOC_SYSID_FULLHOUSE 0x01
#define SGIOC_SYSID_BOARDREV(x) ((x & 0xe0) > 5)
#define SGIOC_SYSID_CHIPREV(x) ((x & 0x1e) > 1)
u32 _unused2;
u8 _read[3];
volatile u8 read;
u32 _unused3;
u8 _dmasel[3];
volatile u8 dmasel;
#define SGIOC_DMASEL_SCLK10MHZ 0x00 /* use 10MHZ serial clock */
#define SGIOC_DMASEL_ISDNB 0x01 /* enable isdn B */
#define SGIOC_DMASEL_ISDNA 0x02 /* enable isdn A */
#define SGIOC_DMASEL_PPORT 0x04 /* use parallel DMA */
#define SGIOC_DMASEL_SCLK667MHZ 0x10 /* use 6.67MHZ serial clock */
#define SGIOC_DMASEL_SCLKEXT 0x20 /* use external serial clock */
u32 _unused4;
u8 _reset[3];
volatile u8 reset;
#define SGIOC_RESET_PPORT 0x01 /* 0=parport reset, 1=nornal */
#define SGIOC_RESET_KBDMOUSE 0x02 /* 0=kbdmouse reset, 1=normal */
#define SGIOC_RESET_EISA 0x04 /* 0=eisa reset, 1=normal */
#define SGIOC_RESET_ISDN 0x08 /* 0=isdn reset, 1=normal */
#define SGIOC_RESET_LC0OFF 0x10 /* guiness: turn led off (red, else green) */
#define SGIOC_RESET_LC1OFF 0x20 /* guiness: turn led off (green, else amber) */
u32 _unused5;
u8 _write[3];
volatile u8 write;
#define SGIOC_WRITE_NTHRESH 0x01 /* use 4.5db threshhold */
#define SGIOC_WRITE_TPSPEED 0x02 /* use 100ohm TP speed */
#define SGIOC_WRITE_EPSEL 0x04 /* force cable mode: 1=AUI 0=TP */
#define SGIOC_WRITE_EASEL 0x08 /* 1=autoselect 0=manual cable selection */
#define SGIOC_WRITE_U1AMODE 0x10 /* 1=PC 0=MAC UART mode */
#define SGIOC_WRITE_U0AMODE 0x20 /* 1=PC 0=MAC UART mode */
#define SGIOC_WRITE_MLO 0x40 /* 1=4.75V 0=+5V */
#define SGIOC_WRITE_MHI 0x80 /* 1=5.25V 0=+5V */
u32 _unused6;
struct sgint_regs int3;
};
extern struct sgioc_regs *sgioc;
extern struct sgint_regs *sgint;
#endif
include/asm-mips64/sgi/ip22.h 0 → 100644
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* ip22.h: Definitions for SGI IP22 machines
*
* Copyright (C) 1996 David S. Miller
* Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle
*/
#ifndef _SGI_IP22_H
#define _SGI_IP22_H
/*
* These are the virtual IRQ numbers, we divide all IRQ's into
* 'spaces', the 'space' determines where and how to enable/disable
* that particular IRQ on an SGI machine. HPC DMA and MC DMA interrups
* are not supported this way. Driver is supposed to allocate HPC/MC
* interrupt as shareable and then look to proper status bit (see
* HAL2 driver). This will prevent many complications, trust me ;-)
*/
#include <asm/sgi/ioc.h>
#define SGINT_EISA 0 /* INDIGO 2 has 16 EISA irq levels */
#define SGINT_CPU 16 /* MIPS CPU define 8 interrupt sources */
#define SGINT_LOCAL0 24 /* INDY has 8 local0 irq levels */
#define SGINT_LOCAL1 32 /* INDY has 8 local1 irq levels */
#define SGINT_LOCAL2 40 /* INDY has 8 local2 vectored irq levels */
#define SGINT_LOCAL3 48 /* INDY has 8 local3 vectored irq levels */
#define SGINT_END 56 /* End of 'spaces' */
/*
* Individual interrupt definitions for the Indy and Indigo2
*/
#define SGI_SOFT_0_IRQ SGINT_CPU + 0
#define SGI_SOFT_1_IRQ SGINT_CPU + 1
#define SGI_LOCAL_0_IRQ SGINT_CPU + 2
#define SGI_LOCAL_1_IRQ SGINT_CPU + 3
#define SGI_8254_0_IRQ SGINT_CPU + 4
#define SGI_8254_1_IRQ SGINT_CPU + 5
#define SGI_BUSERR_IRQ SGINT_CPU + 6
#define SGI_TIMER_IRQ SGINT_CPU + 7
#define SGI_FIFO_IRQ SGINT_LOCAL0 + 0 /* FIFO full */
#define SGI_GIO_0_IRQ SGI_FIFO_IRQ /* GIO-0 */
#define SGI_WD93_0_IRQ SGINT_LOCAL0 + 1 /* 1st onboard WD93 */
#define SGI_WD93_1_IRQ SGINT_LOCAL0 + 2 /* 2nd onboard WD93 */
#define SGI_ENET_IRQ SGINT_LOCAL0 + 3 /* onboard ethernet */
#define SGI_MCDMA_IRQ SGINT_LOCAL0 + 4 /* MC DMA done */
#define SGI_PARPORT_IRQ SGINT_LOCAL0 + 5 /* Parallel port */
#define SGI_GIO_1_IRQ SGINT_LOCAL0 + 6 /* GE / GIO-1 / 2nd-HPC */
#define SGI_MAP_0_IRQ SGINT_LOCAL0 + 7 /* Mappable interrupt 0 */
#define SGI_GPL0_IRQ SGINT_LOCAL1 + 0 /* General Purpose LOCAL1_N<0> */
#define SGI_PANEL_IRQ SGINT_LOCAL1 + 1 /* front panel */
#define SGI_GPL2_IRQ SGINT_LOCAL1 + 2 /* General Purpose LOCAL1_N<2> */
#define SGI_MAP_1_IRQ SGINT_LOCAL1 + 3 /* Mappable interrupt 1 */
#define SGI_HPCDMA_IRQ SGINT_LOCAL1 + 4 /* HPC DMA done */
#define SGI_ACFAIL_IRQ SGINT_LOCAL1 + 5 /* AC fail */
#define SGI_VINO_IRQ SGINT_LOCAL1 + 6 /* Indy VINO */
#define SGI_GIO_2_IRQ SGINT_LOCAL1 + 7 /* Vert retrace / GIO-2 */
/* Mapped interrupts. These interrupts may be mapped to either 0, or 1 */
#define SGI_VERT_IRQ SGINT_LOCAL2 + 0 /* INT3: newport vertical status */
#define SGI_EISA_IRQ SGINT_LOCAL2 + 3 /* EISA interrupts */
#define SGI_KEYBD_IRQ SGINT_LOCAL2 + 4 /* keyboard */
#define SGI_SERIAL_IRQ SGINT_LOCAL2 + 5 /* onboard serial */
#define ip22_is_fullhouse() (sgioc->sysid & SGIOC_SYSID_FULLHOUSE)
extern unsigned short ip22_eeprom_read(volatile unsigned int *ctrl, int reg);
extern unsigned short ip22_nvram_read(int reg);
#endif
include/asm-mips64/sgi/mc.h 0 → 100644
View file @ 2395133b
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* mc.h: Definitions for SGI Memory Controller
*
* Copyright (C) 1996 David S. Miller
* Copyright (C) 1999 Ralf Baechle
* Copyright (C) 1999 Silicon Graphics, Inc.
*/
#ifndef _SGI_MC_H
#define _SGI_MC_H
struct sgimc_regs {
u32 _unused0;
volatile u32 cpuctrl0; /* CPU control register 0, readwrite */
#define SGIMC_CCTRL0_REFS 0x0000000f /* REFS mask */
#define SGIMC_CCTRL0_EREFRESH 0x00000010 /* Memory refresh enable */
#define SGIMC_CCTRL0_EPERRGIO 0x00000020 /* GIO parity error enable */
#define SGIMC_CCTRL0_EPERRMEM 0x00000040 /* Main mem parity error enable */
#define SGIMC_CCTRL0_EPERRCPU 0x00000080 /* CPU bus parity error enable */
#define SGIMC_CCTRL0_WDOG 0x00000100 /* Watchdog timer enable */
#define SGIMC_CCTRL0_SYSINIT 0x00000200 /* System init bit */
#define SGIMC_CCTRL0_GFXRESET 0x00000400 /* Graphics interface reset */
#define SGIMC_CCTRL0_EISALOCK 0x00000800 /* Lock CPU from memory for EISA */
#define SGIMC_CCTRL0_EPERRSCMD 0x00001000 /* SysCMD bus parity error enable */
#define SGIMC_CCTRL0_IENAB 0x00002000 /* Allow interrupts from MC */
#define SGIMC_CCTRL0_ESNOOP 0x00004000 /* Snooping I/O enable */
#define SGIMC_CCTRL0_EPROMWR 0x00008000 /* Prom writes from cpu enable */
#define SGIMC_CCTRL0_WRESETPMEM 0x00010000 /* Perform warm reset, preserves mem */
#define SGIMC_CCTRL0_LENDIAN 0x00020000 /* Put MC in little-endian mode */
#define SGIMC_CCTRL0_WRESETDMEM 0x00040000 /* Warm reset, destroys mem contents */
#define SGIMC_CCTRL0_CMEMBADPAR 0x02000000 /* Generate bad perr from cpu to mem */
#define SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */
#define SGIMC_CCTRL0_GIOBTOB 0x08000000 /* Allow GIO back to back writes */
u32 _unused1;
volatile u32 cpuctrl1; /* CPU control register 1, readwrite */
#define SGIMC_CCTRL1_EGIOTIMEO 0x00000010 /* GIO bus timeout enable */
#define SGIMC_CCTRL1_FIXEDEHPC 0x00001000 /* Fixed HPC endianness */
#define SGIMC_CCTRL1_LITTLEHPC 0x00002000 /* Little endian HPC */
#define SGIMC_CCTRL1_FIXEDEEXP0 0x00004000 /* Fixed EXP0 endianness */
#define SGIMC_CCTRL1_LITTLEEXP0 0x00008000 /* Little endian EXP0 */
#define SGIMC_CCTRL1_FIXEDEEXP1 0x00010000 /* Fixed EXP1 endianness */
#define SGIMC_CCTRL1_LITTLEEXP1 0x00020000 /* Little endian EXP1 */
u32 _unused2;
volatile u32 watchdogt; /* Watchdog reg rdonly, write clears */
u32 _unused3;
volatile u32 systemid; /* MC system ID register, readonly */
#define SGIMC_SYSID_MASKREV 0x0000000f /* Revision of MC controller */
#define SGIMC_SYSID_EPRESENT 0x00000010 /* Indicates presence of EISA bus */
u32 _unused4[3];
volatile u32 divider; /* Divider reg for RPSS */
u32 _unused5;
volatile u32 eeprom; /* EEPROM byte reg for r4k */
#define SGIMC_EEPROM_PRE 0x00000001 /* eeprom chip PRE pin assertion */
#define SGIMC_EEPROM_CSEL 0x00000002 /* Active high, eeprom chip select */
#define SGIMC_EEPROM_SECLOCK 0x00000004 /* EEPROM serial clock */
#define SGIMC_EEPROM_SDATAO 0x00000008 /* Serial EEPROM data-out */
#define SGIMC_EEPROM_SDATAI 0x00000010 /* Serial EEPROM data-in */
u32 _unused6[3];
volatile u32 rcntpre; /* Preload refresh counter */
u32 _unused7;
volatile u32 rcounter; /* Readonly refresh counter */
u32 _unused8[13];
volatile u32 giopar; /* Parameter word for GIO64 */
#define SGIMC_GIOPAR_HPC64 0x00000001 /* HPC talks to GIO using 64-bits */
#define SGIMC_GIOPAR_GFX64 0x00000002 /* GFX talks to GIO using 64-bits */
#define SGIMC_GIOPAR_EXP064 0x00000004 /* EXP(slot0) talks using 64-bits */
#define SGIMC_GIOPAR_EXP164 0x00000008 /* EXP(slot1) talks using 64-bits */
#define SGIMC_GIOPAR_EISA64 0x00000010 /* EISA bus talks 64-bits to GIO */
#define SGIMC_GIOPAR_HPC264 0x00000020 /* 2nd HPX talks 64-bits to GIO */
#define SGIMC_GIOPAR_RTIMEGFX 0x00000040 /* GFX device has realtime attr */
#define SGIMC_GIOPAR_RTIMEEXP0 0x00000080 /* EXP(slot0) has realtime attr */
#define SGIMC_GIOPAR_RTIMEEXP1 0x00000100 /* EXP(slot1) has realtime attr */
#define SGIMC_GIOPAR_MASTEREISA 0x00000200 /* EISA bus can act as bus master */
#define SGIMC_GIOPAR_ONEBUS 0x00000400 /* Exists one GIO64 pipelined bus */
#define SGIMC_GIOPAR_MASTERGFX 0x00000800 /* GFX can act as a bus master */
#define SGIMC_GIOPAR_MASTEREXP0 0x00001000 /* EXP(slot0) can bus master */
#define SGIMC_GIOPAR_MASTEREXP1 0x00002000 /* EXP(slot1) can bus master */
#define SGIMC_GIOPAR_PLINEEXP0 0x00004000 /* EXP(slot0) has pipeline attr */
#define SGIMC_GIOPAR_PLINEEXP1 0x00008000 /* EXP(slot1) has pipeline attr */
u32 _unused9;
volatile u32 cputp; /* CPU bus arb time period */
u32 _unused10[3];
volatile u32 lbursttp; /* Time period for long bursts */
/* MC chip can drive up to 4 bank 4 SIMMs each. All SIMMs in bank must
* be the same size. The size encoding for supported SIMMs is bellow */
u32 _unused11[9];
volatile u32 mconfig0; /* Memory config register zero */
u32 _unused12;
volatile u32 mconfig1; /* Memory config register one */
#define SGIMC_MCONFIG_BASEADDR 0x000000ff /* Base address of bank*/
#define SGIMC_MCONFIG_RMASK 0x00001f00 /* Ram config bitmask */
#define SGIMC_MCONFIG_BVALID 0x00002000 /* Bank is valid */
#define SGIMC_MCONFIG_SBANKS 0x00004000 /* Number of subbanks */
u32 _unused13;
volatile u32 cmacc; /* Mem access config for CPU */
u32 _unused14;
volatile u32 gmacc; /* Mem access config for GIO */
/* This define applies to both cmacc and gmacc registers above. */
#define SGIMC_MACC_ALIASBIG 0x20000000 /* 512MB home for alias */
/* Error address/status regs from GIO and CPU perspectives. */
u32 _unused15;
volatile u32 cerr; /* Error address reg for CPU */
u32 _unused16;
volatile u32 cstat; /* Status reg for CPU */
#define SGIMC_CSTAT_RD 0x00000100 /* read parity error */
#define SGIMC_CSTAT_PAR 0x00000200 /* CPU parity error */
#define SGIMC_CSTAT_ADDR 0x00000400 /* memory bus error bad addr */
#define SGIMC_CSTAT_SYSAD_PAR 0x00000800 /* sysad parity error */
#define SGIMC_CSTAT_SYSCMD_PAR 0x00001000 /* syscmd parity error */
#define SGIMC_CSTAT_BAD_DATA 0x00002000 /* bad data identifier */
#define SGIMC_CSTAT_PAR_MASK 0x00001f00 /* parity error mask */
#define SGIMC_CSTAT_RD_PAR (SGIMC_CSTAT_RD | SGIMC_CSTAT_PAR)
u32 _unused17;
volatile u32 gerr; /* Error address reg for GIO */
u32 _unused18;
volatile u32 gstat; /* Status reg for GIO */
#define SGIMC_GSTAT_RD 0x00000100 /* read parity error */
#define SGIMC_GSTAT_WR 0x00000200 /* write parity error */
#define SGIMC_GSTAT_TIME 0x00000400 /* GIO bus timed out */
#define SGIMC_GSTAT_PROM 0x00000800 /* write to PROM when PROM_EN not set */
#define SGIMC_GSTAT_ADDR 0x00001000 /* parity error on addr cycle */
#define SGIMC_GSTAT_BC 0x00002000 /* parity error on byte count cycle */
#define SGIMC_GSTAT_PIO_RD 0x00004000 /* read data parity on pio */
#define SGIMC_GSTAT_PIO_WR 0x00008000 /* write data parity on pio */
/* Special hard bus locking registers. */
u32 _unused19;
volatile u32 syssembit; /* Uni-bit system semaphore */
u32 _unused20;
volatile u32 mlock; /* Global GIO memory access lock */
u32 _unused21;
volatile u32 elock; /* Locks EISA from GIO accesses */
/* GIO dma control registers. */
u32 _unused22[15];
volatile u32 gio_dma_trans; /* DMA mask to translation GIO addrs */
u32 _unused23;
volatile u32 gio_dma_sbits; /* DMA GIO addr substitution bits */
u32 _unused24;
volatile u32 dma_intr_cause; /* DMA IRQ cause indicator bits */
u32 _unused25;
volatile u32 dma_ctrl; /* Main DMA control reg */
/* DMA TLB entry 0 */
u32 _unused26[5];
volatile u32 dtlb_hi0;
u32 _unused27;
volatile u32 dtlb_lo0;
/* DMA TLB entry 1 */
u32 _unused28;
volatile u32 dtlb_hi1;
u32 _unused29;
volatile u32 dtlb_lo1;
/* DMA TLB entry 2 */
u32 _unused30;
volatile u32 dtlb_hi2;
u32 _unused31;
volatile u32 dtlb_lo2;
/* DMA TLB entry 3 */
u32 _unused32;
volatile u32 dtlb_hi3;
u32 _unused33;
volatile u32 dtlb_lo3;
u32 _unused34[0x0392];
u32 _unused35;
volatile u32 rpsscounter; /* Chirps at 100ns */
u32 _unused36[0x1000/4-2*4];
u32 _unused37;
volatile u32 maddronly; /* Address DMA goes at */
u32 _unused38;
volatile u32 maddrpdeflts; /* Same as above, plus set defaults */
u32 _unused39;
volatile u32 dmasz; /* DMA count */
u32 _unused40;
volatile u32 ssize; /* DMA stride size */
u32 _unused41;
volatile u32 gmaddronly; /* Set GIO DMA but don't start trans */
u32 _unused42;
volatile u32 dmaddnpgo; /* Set GIO DMA addr + start transfer */
u32 _unused43;
volatile u32 dmamode; /* DMA mode config bit settings */
u32 _unused44;
volatile u32 dmaccount; /* Zoom and byte count for DMA */
u32 _unused45;
volatile u32 dmastart; /* Pedal to the metal. */
u32 _unused46;
volatile u32 dmarunning; /* DMA op is in progress */
u32 _unused47;
volatile u32 maddrdefstart; /* Set dma addr, defaults, and kick it */
};
extern struct sgimc_regs *sgimc;
#define SGIMC_BASE 0x1fa00000 /* physical */
/* Base location of the two ram banks found in IP2[0268] machines. */
#define SGIMC_SEG0_BADDR 0x08000000
#define SGIMC_SEG1_BADDR 0x20000000
/* Maximum size of the above banks are per machine. */
#define SGIMC_SEG0_SIZE_ALL 0x10000000 /* 256MB */
#define SGIMC_SEG1_SIZE_IP20_IP22 0x08000000 /* 128MB */
#define SGIMC_SEG1_SIZE_IP26_IP28 0x20000000 /* 512MB */
extern void sgimc_init(void);
#endif /* _SGI_MC_H */
include/asm-mips64/sgi/sgimc.h deleted 100644 → 0
View file @ f19e2d9e
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* sgimc.h: Definitions for memory controller hardware found on
* SGI IP20, IP22, IP26, and IP28 machines.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
* Copyright (C) 1999 Ralf Baechle
* Copyright (C) 1999 Silicon Graphics, Inc.
*/
#ifndef _ASM_SGI_SGIMC_H
#define _ASM_SGI_SGIMC_H
struct sgimc_misc_ctrl {
u32 _unused1;
volatile u32 cpuctrl0; /* CPU control register 0, readwrite */
#define SGIMC_CCTRL0_REFS 0x0000000f /* REFS mask */
#define SGIMC_CCTRL0_EREFRESH 0x00000010 /* Memory refresh enable */
#define SGIMC_CCTRL0_EPERRGIO 0x00000020 /* GIO parity error enable */
#define SGIMC_CCTRL0_EPERRMEM 0x00000040 /* Main mem parity error enable */
#define SGIMC_CCTRL0_EPERRCPU 0x00000080 /* CPU bus parity error enable */
#define SGIMC_CCTRL0_WDOG 0x00000100 /* Watchdog timer enable */
#define SGIMC_CCTRL0_SYSINIT 0x00000200 /* System init bit */
#define SGIMC_CCTRL0_GFXRESET 0x00000400 /* Graphics interface reset */
#define SGIMC_CCTRL0_EISALOCK 0x00000800 /* Lock CPU from memory for EISA */
#define SGIMC_CCTRL0_EPERRSCMD 0x00001000 /* SysCMD bus parity error enable */
#define SGIMC_CCTRL0_IENAB 0x00002000 /* Allow interrupts from MC */
#define SGIMC_CCTRL0_ESNOOP 0x00004000 /* Snooping I/O enable */
#define SGIMC_CCTRL0_EPROMWR 0x00008000 /* Prom writes from cpu enable */
#define SGIMC_CCTRL0_WRESETPMEM 0x00010000 /* Perform warm reset, preserves mem */
#define SGIMC_CCTRL0_LENDIAN 0x00020000 /* Put MC in little-endian mode */
#define SGIMC_CCTRL0_WRESETDMEM 0x00040000 /* Warm reset, destroys mem contents */
#define SGIMC_CCTRL0_CMEMBADPAR 0x02000000 /* Generate bad perr from cpu to mem */
#define SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */
#define SGIMC_CCTRL0_GIOBTOB 0x08000000 /* Allow GIO back to back writes */
u32 _unused2;
volatile u32 cpuctrl1; /* CPU control register 1, readwrite */
#define SGIMC_CCTRL1_EGIOTIMEO 0x00000010 /* GIO bus timeout enable */
#define SGIMC_CCTRL1_FIXEDEHPC 0x00001000 /* Fixed HPC endianness */
#define SGIMC_CCTRL1_LITTLEHPC 0x00002000 /* Little endian HPC */
#define SGIMC_CCTRL1_FIXEDEEXP0 0x00004000 /* Fixed EXP0 endianness */
#define SGIMC_CCTRL1_LITTLEEXP0 0x00008000 /* Little endian EXP0 */
#define SGIMC_CCTRL1_FIXEDEEXP1 0x00010000 /* Fixed EXP1 endianness */
#define SGIMC_CCTRL1_LITTLEEXP1 0x00020000 /* Little endian EXP1 */
u32 _unused3;
volatile u32 watchdogt; /* Watchdog reg rdonly, write clears */
u32 _unused4;
volatile u32 systemid; /* MC system ID register, readonly */
#define SGIMC_SYSID_MASKREV 0x0000000f /* Revision of MC controller */
#define SGIMC_SYSID_EPRESENT 0x00000010 /* Indicates presence of EISA bus */
u32 _unused5[3];
volatile u32 divider; /* Divider reg for RPSS */
u32 _unused6;
volatile unsigned char eeprom; /* EEPROM byte reg for r4k */
#define SGIMC_EEPROM_PRE 0x00000001 /* eeprom chip PRE pin assertion */
#define SGIMC_EEPROM_CSEL 0x00000002 /* Active high, eeprom chip select */
#define SGIMC_EEPROM_SECLOCK 0x00000004 /* EEPROM serial clock */
#define SGIMC_EEPROM_SDATAO 0x00000008 /* Serial EEPROM data-out */
#define SGIMC_EEPROM_SDATAI 0x00000010 /* Serial EEPROM data-in */
unsigned char _unused7[3];
u32 _unused8[3];
volatile unsigned short rcntpre; /* Preload refresh counter */
unsigned short _unused9;
u32 _unused9a;
volatile unsigned short rcounter; /* Readonly refresh counter */
unsigned short _unused10;
u32 _unused11[13];
volatile u32 gioparm; /* Parameter word for GIO64 */
#define SGIMC_GIOPARM_HPC64 0x00000001 /* HPC talks to GIO using 64-bits */
#define SGIMC_GIOPARM_GFX64 0x00000002 /* GFX talks to GIO using 64-bits */
#define SGIMC_GIOPARM_EXP064 0x00000004 /* EXP(slot0) talks using 64-bits */
#define SGIMC_GIOPARM_EXP164 0x00000008 /* EXP(slot1) talks using 64-bits */
#define SGIMC_GIOPARM_EISA64 0x00000010 /* EISA bus talks 64-bits to GIO */
#define SGIMC_GIOPARM_HPC264 0x00000020 /* 2nd HPX talks 64-bits to GIO */
#define SGIMC_GIOPARM_RTIMEGFX 0x00000040 /* GFX device has realtime attr */
#define SGIMC_GIOPARM_RTIMEEXP0 0x00000080 /* EXP(slot0) has realtime attr */
#define SGIMC_GIOPARM_RTIMEEXP1 0x00000100 /* EXP(slot1) has realtime attr */
#define SGIMC_GIOPARM_MASTEREISA 0x00000200 /* EISA bus can act as bus master */
#define SGIMC_GIOPARM_ONEBUS 0x00000400 /* Exists one GIO64 pipelined bus */
#define SGIMC_GIOPARM_MASTERGFX 0x00000800 /* GFX can act as a bus master */
#define SGIMC_GIOPARM_MASTEREXP0 0x00001000 /* EXP(slot0) can bus master */
#define SGIMC_GIOPARM_MASTEREXP1 0x00002000 /* EXP(slot1) can bus master */
#define SGIMC_GIOPARM_PLINEEXP0 0x00004000 /* EXP(slot0) has pipeline attr */
#define SGIMC_GIOPARM_PLINEEXP1 0x00008000 /* EXP(slot1) has pipeline attr */
u32 _unused13;
volatile unsigned short cputp; /* CPU bus arb time period */
unsigned short _unused14;
u32 _unused15[3];
volatile unsigned short lbursttp; /* Time period for long bursts */
unsigned short _unused16;
u32 _unused17[9];
volatile u32 mconfig0; /* Memory config register zero */
u32 _unused18;
volatile u32 mconfig1; /* Memory config register one */
/* These defines apply to both mconfig registers above. */
#define SGIMC_MCONFIG_FOURMB 0x00000000 /* Physical ram = 4megs */
#define SGIMC_MCONFIG_EIGHTMB 0x00000100 /* Physical ram = 8megs */
#define SGIMC_MCONFIG_SXTEENMB 0x00000300 /* Physical ram = 16megs */
#define SGIMC_MCONFIG_TTWOMB 0x00000700 /* Physical ram = 32megs */
#define SGIMC_MCONFIG_SFOURMB 0x00000f00 /* Physical ram = 64megs */
#define SGIMC_MCONFIG_OTEIGHTMB 0x00001f00 /* Physical ram = 128megs */
#define SGIMC_MCONFIG_RMASK 0x00001f00 /* Ram config bitmask */
u32 _unused19;
volatile u32 cmacc; /* Mem access config for CPU */
u32 _unused20;
volatile u32 gmacc; /* Mem access config for GIO */
/* This define applies to both cmacc and gmacc registers above. */
#define SGIMC_MACC_ALIASBIG 0x20000000 /* 512MB home for alias */
/* Error address/status regs from GIO and CPU perspectives. */
u32 _unused21;
volatile u32 cerr; /* Error address reg for CPU */
u32 _unused22;
volatile u32 cstat; /* Status reg for CPU */
u32 _unused23;
volatile u32 gerr; /* Error address reg for GIO */
u32 _unused24;
volatile u32 gstat; /* Status reg for GIO */
/* Special hard bus locking registers. */
u32 _unused25;
volatile unsigned char syssembit; /* Uni-bit system semaphore */
unsigned char _unused26[3];
u32 _unused27;
volatile unsigned char mlock; /* Global GIO memory access lock */
unsigned char _unused28[3];
u32 _unused29;
volatile unsigned char elock; /* Locks EISA from GIO accesses */
/* GIO dma control registers. */
unsigned char _unused30[3];
u32 _unused31[14];
volatile u32 gio_dma_trans;/* DMA mask to translation GIO addrs */
u32 _unused32;
volatile u32 gio_dma_sbits;/* DMA GIO addr substitution bits */
u32 _unused33;
volatile u32 dma_intr_cause; /* DMA IRQ cause indicator bits */
u32 _unused34;
volatile u32 dma_ctrl; /* Main DMA control reg */
/* DMA TLB entry 0 */
u32 _unused35;
volatile u32 dtlb_hi0;
u32 _unused36;
volatile u32 dtlb_lo0;
/* DMA TLB entry 1 */
u32 _unused37;
volatile u32 dtlb_hi1;
u32 _unused38;
volatile u32 dtlb_lo1;
/* DMA TLB entry 2 */
u32 _unused39;
volatile u32 dtlb_hi2;
u32 _unused40;
volatile u32 dtlb_lo2;
/* DMA TLB entry 3 */
u32 _unused41;
volatile u32 dtlb_hi3;
u32 _unused42;
volatile u32 dtlb_lo3;
};
/* MC misc control registers live at physical 0x1fa00000. */
extern struct sgimc_misc_ctrl *mcmisc_regs;
extern u32 *rpsscounter; /* Chirps at 100ns */
struct sgimc_dma_ctrl {
u32 _unused1;
volatile u32 maddronly; /* Address DMA goes at */
u32 _unused2;
volatile u32 maddrpdeflts; /* Same as above, plus set defaults */
u32 _unused3;
volatile u32 dmasz; /* DMA count */
u32 _unused4;
volatile u32 ssize; /* DMA stride size */
u32 _unused5;
volatile u32 gmaddronly; /* Set GIO DMA but do not start trans */
u32 _unused6;
volatile u32 dmaddnpgo; /* Set GIO DMA addr + start transfer */
u32 _unused7;
volatile u32 dmamode; /* DMA mode config bit settings */
u32 _unused8;
volatile u32 dmacount; /* Zoom and byte count for DMA */
u32 _unused9;
volatile u32 dmastart; /* Pedal to the metal. */
u32 _unused10;
volatile u32 dmarunning; /* DMA op is in progress */
u32 _unused11;
/* Set dma addr, defaults, and kick it */
volatile u32 maddr_defl_go; /* go go go! -lm */
};
/* MC controller dma regs live at physical 0x1fa02000. */
extern struct sgimc_dma_ctrl *dmactrlregs;
/* Base location of the two ram banks found in IP2[0268] machines. */
#define SGIMC_SEG0_BADDR 0x08000000
#define SGIMC_SEG1_BADDR 0x20000000
/* Maximum size of the above banks are per machine. */
extern u32 sgimc_seg0_size, sgimc_seg1_size;
#define SGIMC_SEG0_SIZE_ALL 0x10000000 /* 256MB */
#define SGIMC_SEG1_SIZE_IP20_IP22 0x08000000 /* 128MB */
#define SGIMC_SEG1_SIZE_IP26_IP28 0x20000000 /* 512MB */
extern void sgimc_init(void);
#endif /* _ASM_SGI_SGIMC_H */
include/asm-mips64/sgi/sgint23.h deleted 100644 → 0
View file @ f19e2d9e
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* sgint23.h: Defines for the SGI INT2 and INT3 chipsets.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
* Copyright (C) 1997, 98, 1999, 2000 Ralf Baechle
* Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) - INT2 corrections
*/
#ifndef _ASM_SGI_SGINT23_H
#define _ASM_SGI_SGINT23_H
/* These are the virtual IRQ numbers, we divide all IRQ's into
* 'spaces', the 'space' determines where and how to enable/disable
* that particular IRQ on an SGI machine. Add new 'spaces' as new
* IRQ hardware is supported.
*/
#define SGINT_LOCAL0 0 /* INDY has 8 local0 irq levels */
#define SGINT_LOCAL1 8 /* INDY has 8 local1 irq levels */
#define SGINT_LOCAL2 16 /* INDY has 8 local2 vectored irq levels */
#define SGINT_LOCAL3 24 /* INDY has 8 local3 vectored irq levels */
#define SGINT_GIO 32 /* INDY has 9 GIO irq levels */
#define SGINT_HPCDMA 41 /* INDY has 11 HPCDMA irq _sources_ */
#define SGINT_END 52 /* End of 'spaces' */
/*
* Individual interrupt definitions for the INDY and Indigo2
*/
#define SGI_WD93_0_IRQ SGINT_LOCAL0 + 1 /* 1st onboard WD93 */
#define SGI_WD93_1_IRQ SGINT_LOCAL0 + 2 /* 2nd onboard WD93 */
#define SGI_ENET_IRQ SGINT_LOCAL0 + 3 /* onboard ethernet */
#define SGI_PANEL_IRQ SGINT_LOCAL1 + 1 /* front panel */
#define SGI_EISA_IRQ SGINT_LOCAL2 + 3 /* EISA interrupts */
#define SGI_KEYBOARD_IRQ SGINT_LOCAL2 + 4 /* keyboard */
#define SGI_SERIAL_IRQ SGINT_LOCAL2 + 5 /* onboard serial */
/* INT2 occupies HPC PBUS slot 4, INT3 uses slot 6. */
#define SGI_INT2_BASE 0x1fbd9000 /* physical */
#define SGI_INT3_BASE 0x1fbd9880 /* physical */
struct sgi_ioc_ints {
#ifdef __MIPSEB__
unsigned char _unused0[3];
volatile unsigned char istat0; /* Interrupt status zero */
#else
volatile unsigned char istat0; /* Interrupt status zero */
unsigned char _unused0[3];
#endif
#define ISTAT0_FFULL 0x01
#define ISTAT0_SCSI0 0x02
#define ISTAT0_SCSI1 0x04
#define ISTAT0_ENET 0x08
#define ISTAT0_GFXDMA 0x10
#define ISTAT0_LPR 0x20
#define ISTAT0_HPC2 0x40
#define ISTAT0_LIO2 0x80
#ifdef __MIPSEB__
unsigned char _unused1[3];
volatile unsigned char imask0; /* Interrupt mask zero */
unsigned char _unused2[3];
volatile unsigned char istat1; /* Interrupt status one */
#else
volatile unsigned char imask0; /* Interrupt mask zero */
unsigned char _unused1[3];
volatile unsigned char istat1; /* Interrupt status one */
unsigned char _unused2[3];
#endif
#define ISTAT1_ISDNI 0x01
#define ISTAT1_PWR 0x02
#define ISTAT1_ISDNH 0x04
#define ISTAT1_LIO3 0x08
#define ISTAT1_HPC3 0x10
#define ISTAT1_AFAIL 0x20
#define ISTAT1_VIDEO 0x40
#define ISTAT1_GIO2 0x80
#ifdef __MIPSEB__
unsigned char _unused3[3];
volatile unsigned char imask1; /* Interrupt mask one */
unsigned char _unused4[3];
volatile unsigned char vmeistat; /* VME interrupt status */
unsigned char _unused5[3];
volatile unsigned char cmeimask0; /* VME interrupt mask zero */
unsigned char _unused6[3];
volatile unsigned char cmeimask1; /* VME interrupt mask one */
unsigned char _unused7[3];
volatile unsigned char cmepol; /* VME polarity */
#else
volatile unsigned char imask1; /* Interrupt mask one */
unsigned char _unused3[3];
volatile unsigned char vmeistat; /* VME interrupt status */
unsigned char _unused4[3];
volatile unsigned char cmeimask0; /* VME interrupt mask zero */
unsigned char _unused5[3];
volatile unsigned char cmeimask1; /* VME interrupt mask one */
unsigned char _unused6[3];
volatile unsigned char cmepol; /* VME polarity */
unsigned char _unused7[3];
#endif
};
struct sgi_ioc_timers {
#ifdef __MIPSEB__
unsigned char _unused0[3];
volatile unsigned char tcnt0; /* counter 0 */
unsigned char _unused1[3];
volatile unsigned char tcnt1; /* counter 1 */
unsigned char _unused2[3];
volatile unsigned char tcnt2; /* counter 2 */
unsigned char _unused3[3];
volatile unsigned char tcword; /* control word */
#else
volatile unsigned char tcnt0; /* counter 0 */
unsigned char _unused0[3];
volatile unsigned char tcnt1; /* counter 1 */
unsigned char _unused1[3];
volatile unsigned char tcnt2; /* counter 2 */
unsigned char _unused2[3];
volatile unsigned char tcword; /* control word */
unsigned char _unused3[3];
#endif
};
/* Timer control word bits. */
#define SGINT_TCWORD_BCD 0x01 /* Use BCD mode for counters */
#define SGINT_TCWORD_MMASK 0x0e /* Mode bitmask. */
#define SGINT_TCWORD_MITC 0x00 /* IRQ on terminal count (doesn't work) */
#define SGINT_TCWORD_MOS 0x02 /* One-shot IRQ mode. */
#define SGINT_TCWORD_MRGEN 0x04 /* Normal rate generation */
#define SGINT_TCWORD_MSWGEN 0x06 /* Square wave generator mode */
#define SGINT_TCWORD_MSWST 0x08 /* Software strobe */
#define SGINT_TCWORD_MHWST 0x0a /* Hardware strobe */
#define SGINT_TCWORD_CMASK 0x30 /* Command mask */
#define SGINT_TCWORD_CLAT 0x00 /* Latch command */
#define SGINT_TCWORD_CLSB 0x10 /* LSB read/write */
#define SGINT_TCWORD_CMSB 0x20 /* MSB read/write */
#define SGINT_TCWORD_CALL 0x30 /* Full counter read/write */
#define SGINT_TCWORD_CNT0 0x00 /* Select counter zero */
#define SGINT_TCWORD_CNT1 0x40 /* Select counter one */
#define SGINT_TCWORD_CNT2 0x80 /* Select counter two */
#define SGINT_TCWORD_CRBCK 0xc0 /* Readback command */
#define SGINT_TCSAMP_COUNTER 10255
/* FIXME: What does this really look like? It was written to have
* 17 registers, but there are only 16 in my Indigo2.
* I guessed at which one to remove... - andrewb
*/
struct sgi_int2_regs {
struct sgi_ioc_ints ints;
volatile u32 ledbits; /* LED control bits */
#define INT2_LED_TXCLK 0x01 /* GPI to TXCLK enable */
#define INT2_LED_SERSLCT0 0x02 /* serial port0: 0=apple 1=pc */
#define INT2_LED_SERSLCT1 0x04 /* serial port1: 0=apple 1=pc */
#define INT2_LED_CHEAPER 0x08 /* 0=cheapernet 1=ethernet */
#define INT2_LED_POWEROFF 0x10 /* Power-off request, active high */
#ifdef __MIPSEB__
unsigned char _unused0[3];
volatile unsigned char tclear; /* Timer clear strobe address */
#else
volatile unsigned char tclear; /* Timer clear strobe address */
unsigned char _unused0[3];
#endif
#define INT2_TCLEAR_T0CLR 0x1 /* Clear timer0 IRQ */
#define INT2_TCLEAR_T1CLR 0x2 /* Clear timer1 IRQ */
/* I am guessing there are only two unused registers here
* but I could be wrong... - andrewb
*/
/* u32 _unused[3]; */
u32 _unused[2];
struct sgi_ioc_timers timers;
};
struct sgi_int3_regs {
struct sgi_ioc_ints ints;
#ifdef __MIPSEB__
unsigned char _unused0[3];
volatile unsigned char tclear; /* Timer clear strobe address */
#else
volatile unsigned char tclear; /* Timer clear strobe address */
unsigned char _unused0[3];
#endif
volatile u32 estatus; /* Error status reg */
u32 _unused1[2];
struct sgi_ioc_timers timers;
};
extern struct sgi_int2_regs *sgi_i2regs;
extern struct sgi_int3_regs *sgi_i3regs;
extern struct sgi_ioc_ints *ioc_icontrol;
extern struct sgi_ioc_timers *ioc_timers;
extern volatile unsigned char *ioc_tclear;
extern void indy_timer_init(void);
#endif /* _ASM_SGI_SGINT23_H */
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