MIPS: OCTEON: Add semaphore to serialize bootbus accesses.

Some hardware blocks attached to the OCTEON bootbus run asynchronously
to accesses from the CPUs.  These include MMC/SD host, CF(when using
DMA), and NAND controller.  A bus error, or corrupt data may occur if
a CPU is trying to access a bootbus connected device at the same time
the bus is running asynchronous operations.

To work around these problems we add this semaphore that must be
acquired before initiating bootbus activity.  Subsequent patches will
add users for this.
Signed-off-by: David Daney <david.daney@cavium.com>
[aleksey.makarov@auriga.com: combine the patches]
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9459/Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

arch/mips/cavium-octeon/setup.c

@@ -51,6 +51,9 @@ extern void pci_console_init(const char *arg);
 
 static unsigned long long MAX_MEMORY = 512ull << 20;
 
+DEFINE_SEMAPHORE(octeon_bootbus_sem);
+EXPORT_SYMBOL(octeon_bootbus_sem);
+
 struct octeon_boot_descriptor *octeon_boot_desc_ptr;
 
 struct cvmx_bootinfo *octeon_bootinfo;

arch/mips/include/asm/octeon/octeon.h

@@ -335,4 +335,6 @@ void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t);
 
 extern void octeon_fixup_irqs(void);
 
+extern struct semaphore octeon_bootbus_sem;
+
 #endif /* __ASM_OCTEON_OCTEON_H */