Commit 24d79ce0 authored by David S. Miller's avatar David S. Miller

Merge branch 'xgene-v2'

Iyappan Subramanian says:

====================
drivers: net: xgene-v2: Add RGMII based 1G driver

This patch set adds support for RGMII based 1GbE hardware which uses a linked
list of DMA descriptor architecture (v2) for APM X-Gene SoCs.

v4: Address review comments from v3
	- fixed local variable declarations to reverse christmas tree order

v3: Address review comments from v2
	- fixed kbuild warnings (this 'if' clause does not guard)

v2: Address review comments from v1
	- moved create_desc_ring and delete_desc_ring to open() and close()
	  respectively
	- changed to use dma_zalloc APIs
	- fixed tx_timeout()
	- removed tx completion polling upper bound
	- added error checking on rx packets
	- added netif_stop_queue() and netif_wake_queue()

v1:
	- Initial version
====================
Signed-off-by: default avatarIyappan Subramanian <isubramanian@apm.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 35ae57ea 70dbd9b2
...@@ -902,6 +902,12 @@ F: drivers/net/phy/mdio-xgene.c ...@@ -902,6 +902,12 @@ F: drivers/net/phy/mdio-xgene.c
F: Documentation/devicetree/bindings/net/apm-xgene-enet.txt F: Documentation/devicetree/bindings/net/apm-xgene-enet.txt
F: Documentation/devicetree/bindings/net/apm-xgene-mdio.txt F: Documentation/devicetree/bindings/net/apm-xgene-mdio.txt
APPLIED MICRO (APM) X-GENE SOC ETHERNET (V2) DRIVER
M: Iyappan Subramanian <isubramanian@apm.com>
M: Keyur Chudgar <kchudgar@apm.com>
S: Supported
F: drivers/net/ethernet/apm/xgene-v2/
APPLIED MICRO (APM) X-GENE SOC PMU APPLIED MICRO (APM) X-GENE SOC PMU
M: Tai Nguyen <ttnguyen@apm.com> M: Tai Nguyen <ttnguyen@apm.com>
S: Supported S: Supported
......
source "drivers/net/ethernet/apm/xgene/Kconfig" source "drivers/net/ethernet/apm/xgene/Kconfig"
source "drivers/net/ethernet/apm/xgene-v2/Kconfig"
...@@ -3,3 +3,4 @@ ...@@ -3,3 +3,4 @@
# #
obj-$(CONFIG_NET_XGENE) += xgene/ obj-$(CONFIG_NET_XGENE) += xgene/
obj-$(CONFIG_NET_XGENE_V2) += xgene-v2/
config NET_XGENE_V2
tristate "APM X-Gene SoC Ethernet-v2 Driver"
depends on HAS_DMA
depends on ARCH_XGENE || COMPILE_TEST
help
This is the Ethernet driver for the on-chip ethernet interface
which uses a linked list of DMA descriptor architecture (v2) for
APM X-Gene SoCs.
To compile this driver as a module, choose M here. This module will
be called xgene-enet-v2.
#
# Makefile for APM X-Gene Ethernet v2 driver
#
xgene-enet-v2-objs := main.o mac.o enet.o ring.o
obj-$(CONFIG_NET_XGENE_V2) += xgene-enet-v2.o
/*
* Applied Micro X-Gene SoC Ethernet v2 Driver
*
* Copyright (c) 2017, Applied Micro Circuits Corporation
* Author(s): Iyappan Subramanian <isubramanian@apm.com>
* Keyur Chudgar <kchudgar@apm.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "main.h"
void xge_wr_csr(struct xge_pdata *pdata, u32 offset, u32 val)
{
void __iomem *addr = pdata->resources.base_addr + offset;
iowrite32(val, addr);
}
u32 xge_rd_csr(struct xge_pdata *pdata, u32 offset)
{
void __iomem *addr = pdata->resources.base_addr + offset;
return ioread32(addr);
}
int xge_port_reset(struct net_device *ndev)
{
struct xge_pdata *pdata = netdev_priv(ndev);
xge_wr_csr(pdata, ENET_SRST, 0x3);
xge_wr_csr(pdata, ENET_SRST, 0x2);
xge_wr_csr(pdata, ENET_SRST, 0x0);
xge_wr_csr(pdata, ENET_SHIM, DEVM_ARAUX_COH | DEVM_AWAUX_COH);
return 0;
}
static void xge_traffic_resume(struct net_device *ndev)
{
struct xge_pdata *pdata = netdev_priv(ndev);
xge_wr_csr(pdata, CFG_FORCE_LINK_STATUS_EN, 1);
xge_wr_csr(pdata, FORCE_LINK_STATUS, 1);
xge_wr_csr(pdata, CFG_LINK_AGGR_RESUME, 1);
xge_wr_csr(pdata, RX_DV_GATE_REG, 1);
}
int xge_port_init(struct net_device *ndev)
{
struct xge_pdata *pdata = netdev_priv(ndev);
pdata->phy_speed = SPEED_1000;
xge_mac_init(pdata);
xge_traffic_resume(ndev);
return 0;
}
/*
* Applied Micro X-Gene SoC Ethernet v2 Driver
*
* Copyright (c) 2017, Applied Micro Circuits Corporation
* Author(s): Iyappan Subramanian <isubramanian@apm.com>
* Keyur Chudgar <kchudgar@apm.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __XGENE_ENET_V2_ENET_H__
#define __XGENE_ENET_V2_ENET_H__
#define ENET_CLKEN 0xc008
#define ENET_SRST 0xc000
#define ENET_SHIM 0xc010
#define CFG_MEM_RAM_SHUTDOWN 0xd070
#define BLOCK_MEM_RDY 0xd074
#define DEVM_ARAUX_COH BIT(19)
#define DEVM_AWAUX_COH BIT(3)
#define CFG_FORCE_LINK_STATUS_EN 0x229c
#define FORCE_LINK_STATUS 0x22a0
#define CFG_LINK_AGGR_RESUME 0x27c8
#define RX_DV_GATE_REG 0x2dfc
void xge_wr_csr(struct xge_pdata *pdata, u32 offset, u32 val);
u32 xge_rd_csr(struct xge_pdata *pdata, u32 offset);
int xge_port_reset(struct net_device *ndev);
#endif /* __XGENE_ENET_V2_ENET__H__ */
/*
* Applied Micro X-Gene SoC Ethernet v2 Driver
*
* Copyright (c) 2017, Applied Micro Circuits Corporation
* Author(s): Iyappan Subramanian <isubramanian@apm.com>
* Keyur Chudgar <kchudgar@apm.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "main.h"
void xge_mac_reset(struct xge_pdata *pdata)
{
xge_wr_csr(pdata, MAC_CONFIG_1, SOFT_RESET);
xge_wr_csr(pdata, MAC_CONFIG_1, 0);
}
static void xge_mac_set_speed(struct xge_pdata *pdata)
{
u32 icm0, icm2, ecm0, mc2;
u32 intf_ctrl, rgmii;
icm0 = xge_rd_csr(pdata, ICM_CONFIG0_REG_0);
icm2 = xge_rd_csr(pdata, ICM_CONFIG2_REG_0);
ecm0 = xge_rd_csr(pdata, ECM_CONFIG0_REG_0);
rgmii = xge_rd_csr(pdata, RGMII_REG_0);
mc2 = xge_rd_csr(pdata, MAC_CONFIG_2);
intf_ctrl = xge_rd_csr(pdata, INTERFACE_CONTROL);
icm2 |= CFG_WAITASYNCRD_EN;
switch (pdata->phy_speed) {
case SPEED_10:
SET_REG_BITS(&mc2, INTF_MODE, 1);
SET_REG_BITS(&intf_ctrl, HD_MODE, 0);
SET_REG_BITS(&icm0, CFG_MACMODE, 0);
SET_REG_BITS(&icm2, CFG_WAITASYNCRD, 500);
SET_REG_BIT(&rgmii, CFG_SPEED_125, 0);
break;
case SPEED_100:
SET_REG_BITS(&mc2, INTF_MODE, 1);
SET_REG_BITS(&intf_ctrl, HD_MODE, 1);
SET_REG_BITS(&icm0, CFG_MACMODE, 1);
SET_REG_BITS(&icm2, CFG_WAITASYNCRD, 80);
SET_REG_BIT(&rgmii, CFG_SPEED_125, 0);
break;
default:
SET_REG_BITS(&mc2, INTF_MODE, 2);
SET_REG_BITS(&intf_ctrl, HD_MODE, 2);
SET_REG_BITS(&icm0, CFG_MACMODE, 2);
SET_REG_BITS(&icm2, CFG_WAITASYNCRD, 16);
SET_REG_BIT(&rgmii, CFG_SPEED_125, 1);
break;
}
mc2 |= FULL_DUPLEX | CRC_EN | PAD_CRC;
SET_REG_BITS(&ecm0, CFG_WFIFOFULLTHR, 0x32);
xge_wr_csr(pdata, MAC_CONFIG_2, mc2);
xge_wr_csr(pdata, INTERFACE_CONTROL, intf_ctrl);
xge_wr_csr(pdata, RGMII_REG_0, rgmii);
xge_wr_csr(pdata, ICM_CONFIG0_REG_0, icm0);
xge_wr_csr(pdata, ICM_CONFIG2_REG_0, icm2);
xge_wr_csr(pdata, ECM_CONFIG0_REG_0, ecm0);
}
void xge_mac_set_station_addr(struct xge_pdata *pdata)
{
u8 *dev_addr = pdata->ndev->dev_addr;
u32 addr0, addr1;
addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
(dev_addr[1] << 8) | dev_addr[0];
addr1 = (dev_addr[5] << 24) | (dev_addr[4] << 16);
xge_wr_csr(pdata, STATION_ADDR0, addr0);
xge_wr_csr(pdata, STATION_ADDR1, addr1);
}
void xge_mac_init(struct xge_pdata *pdata)
{
xge_mac_reset(pdata);
xge_mac_set_speed(pdata);
xge_mac_set_station_addr(pdata);
}
void xge_mac_enable(struct xge_pdata *pdata)
{
u32 data;
data = xge_rd_csr(pdata, MAC_CONFIG_1);
data |= TX_EN | RX_EN;
xge_wr_csr(pdata, MAC_CONFIG_1, data);
data = xge_rd_csr(pdata, MAC_CONFIG_1);
}
void xge_mac_disable(struct xge_pdata *pdata)
{
u32 data;
data = xge_rd_csr(pdata, MAC_CONFIG_1);
data &= ~(TX_EN | RX_EN);
xge_wr_csr(pdata, MAC_CONFIG_1, data);
}
/*
* Applied Micro X-Gene SoC Ethernet v2 Driver
*
* Copyright (c) 2017, Applied Micro Circuits Corporation
* Author(s): Iyappan Subramanian <isubramanian@apm.com>
* Keyur Chudgar <kchudgar@apm.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __XGENE_ENET_V2_MAC_H__
#define __XGENE_ENET_V2_MAC_H__
/* Register offsets */
#define MAC_CONFIG_1 0xa000
#define MAC_CONFIG_2 0xa004
#define MII_MGMT_CONFIG 0xa020
#define MII_MGMT_COMMAND 0xa024
#define MII_MGMT_ADDRESS 0xa028
#define MII_MGMT_CONTROL 0xa02c
#define MII_MGMT_STATUS 0xa030
#define MII_MGMT_INDICATORS 0xa034
#define INTERFACE_CONTROL 0xa038
#define STATION_ADDR0 0xa040
#define STATION_ADDR1 0xa044
#define RBYT 0xa09c
#define RPKT 0xa0a0
#define RFCS 0xa0a4
#define RGMII_REG_0 0x27e0
#define ICM_CONFIG0_REG_0 0x2c00
#define ICM_CONFIG2_REG_0 0x2c08
#define ECM_CONFIG0_REG_0 0x2d00
/* Register fields */
#define SOFT_RESET BIT(31)
#define TX_EN BIT(0)
#define RX_EN BIT(2)
#define PAD_CRC BIT(2)
#define CRC_EN BIT(1)
#define FULL_DUPLEX BIT(0)
#define INTF_MODE_POS 8
#define INTF_MODE_LEN 2
#define HD_MODE_POS 25
#define HD_MODE_LEN 2
#define CFG_MACMODE_POS 18
#define CFG_MACMODE_LEN 2
#define CFG_WAITASYNCRD_POS 0
#define CFG_WAITASYNCRD_LEN 16
#define CFG_SPEED_125_POS 24
#define CFG_WFIFOFULLTHR_POS 0
#define CFG_WFIFOFULLTHR_LEN 7
#define MGMT_CLOCK_SEL_POS 0
#define MGMT_CLOCK_SEL_LEN 3
#define PHY_ADDR_POS 8
#define PHY_ADDR_LEN 5
#define REG_ADDR_POS 0
#define REG_ADDR_LEN 5
#define MII_MGMT_BUSY BIT(0)
#define MII_READ_CYCLE BIT(0)
#define CFG_WAITASYNCRD_EN BIT(16)
static inline void xgene_set_reg_bits(u32 *var, int pos, int len, u32 val)
{
u32 mask = GENMASK(pos + len, pos);
*var &= ~mask;
*var |= ((val << pos) & mask);
}
static inline u32 xgene_get_reg_bits(u32 var, int pos, int len)
{
u32 mask = GENMASK(pos + len, pos);
return (var & mask) >> pos;
}
#define SET_REG_BITS(var, field, val) \
xgene_set_reg_bits(var, field ## _POS, field ## _LEN, val)
#define SET_REG_BIT(var, field, val) \
xgene_set_reg_bits(var, field ## _POS, 1, val)
#define GET_REG_BITS(var, field) \
xgene_get_reg_bits(var, field ## _POS, field ## _LEN)
#define GET_REG_BIT(var, field) ((var) & (field))
struct xge_pdata;
void xge_mac_reset(struct xge_pdata *pdata);
void xge_mac_enable(struct xge_pdata *pdata);
void xge_mac_disable(struct xge_pdata *pdata);
void xge_mac_init(struct xge_pdata *pdata);
int xge_port_init(struct net_device *ndev);
void xge_mac_set_station_addr(struct xge_pdata *pdata);
#endif /* __XGENE_ENET_V2_MAC_H__ */
This diff is collapsed.
/*
* Applied Micro X-Gene SoC Ethernet v2 Driver
*
* Copyright (c) 2017, Applied Micro Circuits Corporation
* Author(s): Iyappan Subramanian <isubramanian@apm.com>
* Keyur Chudgar <kchudgar@apm.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __XGENE_ENET_V2_MAIN_H__
#define __XGENE_ENET_V2_MAIN_H__
#include <linux/acpi.h>
#include <linux/clk.h>
#include <linux/efi.h>
#include <linux/if_vlan.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/of_net.h>
#include <linux/of_mdio.h>
#include <linux/prefetch.h>
#include <linux/phy.h>
#include <net/ip.h>
#include "mac.h"
#include "enet.h"
#include "ring.h"
#define XGENE_ENET_V2_VERSION "v1.0"
#define XGENE_ENET_STD_MTU 1536
#define XGENE_ENET_MIN_FRAME 60
#define IRQ_ID_SIZE 16
struct xge_resource {
void __iomem *base_addr;
int phy_mode;
u32 irq;
};
struct xge_stats {
u64 tx_packets;
u64 tx_bytes;
u64 rx_packets;
u64 rx_bytes;
u64 rx_errors;
};
/* ethernet private data */
struct xge_pdata {
struct xge_resource resources;
struct xge_desc_ring *tx_ring;
struct xge_desc_ring *rx_ring;
struct platform_device *pdev;
char irq_name[IRQ_ID_SIZE];
struct net_device *ndev;
struct napi_struct napi;
struct xge_stats stats;
int phy_speed;
u8 nbufs;
};
#endif /* __XGENE_ENET_V2_MAIN_H__ */
/*
* Applied Micro X-Gene SoC Ethernet v2 Driver
*
* Copyright (c) 2017, Applied Micro Circuits Corporation
* Author(s): Iyappan Subramanian <isubramanian@apm.com>
* Keyur Chudgar <kchudgar@apm.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "main.h"
/* create circular linked list of descriptors */
void xge_setup_desc(struct xge_desc_ring *ring)
{
struct xge_raw_desc *raw_desc;
dma_addr_t dma_h, next_dma;
u16 offset;
int i;
for (i = 0; i < XGENE_ENET_NUM_DESC; i++) {
raw_desc = &ring->raw_desc[i];
offset = (i + 1) & (XGENE_ENET_NUM_DESC - 1);
next_dma = ring->dma_addr + (offset * XGENE_ENET_DESC_SIZE);
raw_desc->m0 = cpu_to_le64(SET_BITS(E, 1) |
SET_BITS(PKT_SIZE, SLOT_EMPTY));
dma_h = upper_32_bits(next_dma);
raw_desc->m1 = cpu_to_le64(SET_BITS(NEXT_DESC_ADDRL, next_dma) |
SET_BITS(NEXT_DESC_ADDRH, dma_h));
}
}
void xge_update_tx_desc_addr(struct xge_pdata *pdata)
{
struct xge_desc_ring *ring = pdata->tx_ring;
dma_addr_t dma_addr = ring->dma_addr;
xge_wr_csr(pdata, DMATXDESCL, dma_addr);
xge_wr_csr(pdata, DMATXDESCH, upper_32_bits(dma_addr));
ring->head = 0;
ring->tail = 0;
}
void xge_update_rx_desc_addr(struct xge_pdata *pdata)
{
struct xge_desc_ring *ring = pdata->rx_ring;
dma_addr_t dma_addr = ring->dma_addr;
xge_wr_csr(pdata, DMARXDESCL, dma_addr);
xge_wr_csr(pdata, DMARXDESCH, upper_32_bits(dma_addr));
ring->head = 0;
ring->tail = 0;
}
void xge_intr_enable(struct xge_pdata *pdata)
{
u32 data;
data = RX_PKT_RCVD | TX_PKT_SENT;
xge_wr_csr(pdata, DMAINTRMASK, data);
}
void xge_intr_disable(struct xge_pdata *pdata)
{
xge_wr_csr(pdata, DMAINTRMASK, 0);
}
/*
* Applied Micro X-Gene SoC Ethernet v2 Driver
*
* Copyright (c) 2017, Applied Micro Circuits Corporation
* Author(s): Iyappan Subramanian <isubramanian@apm.com>
* Keyur Chudgar <kchudgar@apm.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __XGENE_ENET_V2_RING_H__
#define __XGENE_ENET_V2_RING_H__
#define XGENE_ENET_DESC_SIZE 64
#define XGENE_ENET_NUM_DESC 256
#define NUM_BUFS 8
#define SLOT_EMPTY 0xfff
#define DMATXCTRL 0xa180
#define DMATXDESCL 0xa184
#define DMATXDESCH 0xa1a0
#define DMATXSTATUS 0xa188
#define DMARXCTRL 0xa18c
#define DMARXDESCL 0xa190
#define DMARXDESCH 0xa1a4
#define DMARXSTATUS 0xa194
#define DMAINTRMASK 0xa198
#define DMAINTERRUPT 0xa19c
#define D_POS 62
#define D_LEN 2
#define E_POS 63
#define E_LEN 1
#define PKT_ADDRL_POS 0
#define PKT_ADDRL_LEN 32
#define PKT_ADDRH_POS 32
#define PKT_ADDRH_LEN 10
#define PKT_SIZE_POS 32
#define PKT_SIZE_LEN 12
#define NEXT_DESC_ADDRL_POS 0
#define NEXT_DESC_ADDRL_LEN 32
#define NEXT_DESC_ADDRH_POS 48
#define NEXT_DESC_ADDRH_LEN 10
#define TXPKTCOUNT_POS 16
#define TXPKTCOUNT_LEN 8
#define RXPKTCOUNT_POS 16
#define RXPKTCOUNT_LEN 8
#define TX_PKT_SENT BIT(0)
#define TX_BUS_ERROR BIT(3)
#define RX_PKT_RCVD BIT(4)
#define RX_BUS_ERROR BIT(7)
#define RXSTATUS_RXPKTRCVD BIT(0)
struct xge_raw_desc {
__le64 m0;
__le64 m1;
__le64 m2;
__le64 m3;
__le64 m4;
__le64 m5;
__le64 m6;
__le64 m7;
};
struct pkt_info {
struct sk_buff *skb;
dma_addr_t dma_addr;
void *pkt_buf;
};
/* software context of a descriptor ring */
struct xge_desc_ring {
struct net_device *ndev;
dma_addr_t dma_addr;
u8 head;
u8 tail;
union {
void *desc_addr;
struct xge_raw_desc *raw_desc;
};
struct pkt_info (*pkt_info);
};
static inline u64 xge_set_desc_bits(int pos, int len, u64 val)
{
return (val & ((1ULL << len) - 1)) << pos;
}
static inline u64 xge_get_desc_bits(int pos, int len, u64 src)
{
return (src >> pos) & ((1ULL << len) - 1);
}
#define SET_BITS(field, val) \
xge_set_desc_bits(field ## _POS, field ## _LEN, val)
#define GET_BITS(field, src) \
xge_get_desc_bits(field ## _POS, field ## _LEN, src)
void xge_setup_desc(struct xge_desc_ring *ring);
void xge_update_tx_desc_addr(struct xge_pdata *pdata);
void xge_update_rx_desc_addr(struct xge_pdata *pdata);
void xge_intr_enable(struct xge_pdata *pdata);
void xge_intr_disable(struct xge_pdata *pdata);
#endif /* __XGENE_ENET_V2_RING_H__ */
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