Commit 26bfe3d0 authored by Dave Jiang's avatar Dave Jiang Committed by Jon Mason

ntb: intel: Add Icelake (gen4) support for Intel NTB

Adding 4th generation Intel NTB support bits. There are a lot of common
parts that the gen4 NTB has with gen3 NTB on Skylake. The commonalities are
reused in gen4 Icelake NTB.
Signed-off-by: default avatarDave Jiang <dave.jiang@intel.com>
Signed-off-by: default avatarJon Mason <jdmason@kudzu.us>
parent a0348a4d
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_NTB_INTEL) += ntb_hw_intel.o
ntb_hw_intel-y := ntb_hw_gen1.o ntb_hw_gen3.o
ntb_hw_intel-y := ntb_hw_gen1.o ntb_hw_gen3.o ntb_hw_gen4.o
......@@ -60,6 +60,7 @@
#include "ntb_hw_intel.h"
#include "ntb_hw_gen1.h"
#include "ntb_hw_gen3.h"
#include "ntb_hw_gen4.h"
#define NTB_NAME "ntb_hw_intel"
#define NTB_DESC "Intel(R) PCI-E Non-Transparent Bridge Driver"
......@@ -762,6 +763,8 @@ static ssize_t ndev_debugfs_read(struct file *filp, char __user *ubuf,
return ndev_ntb_debugfs_read(filp, ubuf, count, offp);
else if (pdev_is_gen3(ndev->ntb.pdev))
return ndev_ntb3_debugfs_read(filp, ubuf, count, offp);
else if (pdev_is_gen4(ndev->ntb.pdev))
return ndev_ntb4_debugfs_read(filp, ubuf, count, offp);
return -ENXIO;
}
......@@ -1858,8 +1861,6 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev,
int rc, node;
node = dev_to_node(&pdev->dev);
if (pdev_is_gen1(pdev)) {
ndev = kzalloc_node(sizeof(*ndev), GFP_KERNEL, node);
if (!ndev) {
rc = -ENOMEM;
......@@ -1868,6 +1869,7 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev,
ndev_init_struct(ndev, pdev);
if (pdev_is_gen1(pdev)) {
rc = intel_ntb_init_pci(ndev, pdev);
if (rc)
goto err_init_pci;
......@@ -1875,17 +1877,8 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev,
rc = xeon_init_dev(ndev);
if (rc)
goto err_init_dev;
} else if (pdev_is_gen3(pdev)) {
ndev = kzalloc_node(sizeof(*ndev), GFP_KERNEL, node);
if (!ndev) {
rc = -ENOMEM;
goto err_ndev;
}
ndev_init_struct(ndev, pdev);
ndev->ntb.ops = &intel_ntb3_ops;
rc = intel_ntb_init_pci(ndev, pdev);
if (rc)
goto err_init_pci;
......@@ -1893,7 +1886,15 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev,
rc = gen3_init_dev(ndev);
if (rc)
goto err_init_dev;
} else if (pdev_is_gen4(pdev)) {
ndev->ntb.ops = &intel_ntb4_ops;
rc = intel_ntb_init_pci(ndev, pdev);
if (rc)
goto err_init_pci;
rc = gen4_init_dev(ndev);
if (rc)
goto err_init_dev;
} else {
rc = -EINVAL;
goto err_ndev;
......@@ -1915,7 +1916,7 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev,
err_register:
ndev_deinit_debugfs(ndev);
if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev))
if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev) || pdev_is_gen4(pdev))
xeon_deinit_dev(ndev);
err_init_dev:
intel_ntb_deinit_pci(ndev);
......@@ -1931,7 +1932,7 @@ static void intel_ntb_pci_remove(struct pci_dev *pdev)
ntb_unregister_device(&ndev->ntb);
ndev_deinit_debugfs(ndev);
if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev))
if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev) || pdev_is_gen4(pdev))
xeon_deinit_dev(ndev);
intel_ntb_deinit_pci(ndev);
kfree(ndev);
......@@ -2036,6 +2037,7 @@ static const struct file_operations intel_ntb_debugfs_info = {
};
static const struct pci_device_id intel_ntb_pci_tbl[] = {
/* GEN1 */
{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_JSF)},
{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_SNB)},
{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_IVT)},
......@@ -2051,7 +2053,12 @@ static const struct pci_device_id intel_ntb_pci_tbl[] = {
{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_IVT)},
{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_HSX)},
{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_BDX)},
/* GEN3 */
{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_SKX)},
/* GEN4 */
{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_ICX)},
{0}
};
MODULE_DEVICE_TABLE(pci, intel_ntb_pci_tbl);
......
......@@ -415,8 +415,7 @@ ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf,
return ret;
}
static int intel_ntb3_link_enable(struct ntb_dev *ntb,
enum ntb_speed max_speed,
int intel_ntb3_link_enable(struct ntb_dev *ntb, enum ntb_speed max_speed,
enum ntb_width max_width)
{
struct intel_ntb_dev *ndev;
......@@ -532,7 +531,7 @@ static int intel_ntb3_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx,
return 0;
}
static int intel_ntb3_peer_db_addr(struct ntb_dev *ntb, phys_addr_t *db_addr,
int intel_ntb3_peer_db_addr(struct ntb_dev *ntb, phys_addr_t *db_addr,
resource_size_t *db_size,
u64 *db_data, int db_bit)
{
......@@ -563,7 +562,7 @@ static int intel_ntb3_peer_db_addr(struct ntb_dev *ntb, phys_addr_t *db_addr,
return 0;
}
static int intel_ntb3_peer_db_set(struct ntb_dev *ntb, u64 db_bits)
int intel_ntb3_peer_db_set(struct ntb_dev *ntb, u64 db_bits)
{
struct intel_ntb_dev *ndev = ntb_ndev(ntb);
int bit;
......@@ -581,7 +580,7 @@ static int intel_ntb3_peer_db_set(struct ntb_dev *ntb, u64 db_bits)
return 0;
}
static u64 intel_ntb3_db_read(struct ntb_dev *ntb)
u64 intel_ntb3_db_read(struct ntb_dev *ntb)
{
struct intel_ntb_dev *ndev = ntb_ndev(ntb);
......@@ -590,7 +589,7 @@ static u64 intel_ntb3_db_read(struct ntb_dev *ntb)
ndev->self_reg->db_clear);
}
static int intel_ntb3_db_clear(struct ntb_dev *ntb, u64 db_bits)
int intel_ntb3_db_clear(struct ntb_dev *ntb, u64 db_bits)
{
struct intel_ntb_dev *ndev = ntb_ndev(ntb);
......
......@@ -104,6 +104,14 @@ static inline void gen3_db_iowrite(u64 bits, void __iomem *mmio)
ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf,
size_t count, loff_t *offp);
int gen3_init_dev(struct intel_ntb_dev *ndev);
int intel_ntb3_link_enable(struct ntb_dev *ntb, enum ntb_speed max_speed,
enum ntb_width max_width);
u64 intel_ntb3_db_read(struct ntb_dev *ntb);
int intel_ntb3_db_clear(struct ntb_dev *ntb, u64 db_bits);
int intel_ntb3_peer_db_set(struct ntb_dev *ntb, u64 db_bits);
int intel_ntb3_peer_db_addr(struct ntb_dev *ntb, phys_addr_t *db_addr,
resource_size_t *db_size,
u64 *db_data, int db_bit);
extern const struct ntb_dev_ops intel_ntb3_ops;
......
This diff is collapsed.
/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
#ifndef _NTB_INTEL_GEN4_H_
#define _NTB_INTEL_GEN4_H_
#include "ntb_hw_intel.h"
/* Intel Gen4 NTB hardware */
/* PCIe config space */
#define GEN4_IMBAR23SZ_OFFSET 0x00c4
#define GEN4_IMBAR45SZ_OFFSET 0x00c5
#define GEN4_EMBAR23SZ_OFFSET 0x00c6
#define GEN4_EMBAR45SZ_OFFSET 0x00c7
#define GEN4_DEVCTRL_OFFSET 0x0048
#define GEN4_DEVSTS_OFFSET 0x004a
#define GEN4_UNCERRSTS_OFFSET 0x0104
#define GEN4_CORERRSTS_OFFSET 0x0110
/* BAR0 MMIO */
#define GEN4_NTBCNTL_OFFSET 0x0000
#define GEN4_IM23XBASE_OFFSET 0x0010 /* IMBAR1XBASE */
#define GEN4_IM23XLMT_OFFSET 0x0018 /* IMBAR1XLMT */
#define GEN4_IM45XBASE_OFFSET 0x0020 /* IMBAR2XBASE */
#define GEN4_IM45XLMT_OFFSET 0x0028 /* IMBAR2XLMT */
#define GEN4_IM_INT_STATUS_OFFSET 0x0040
#define GEN4_IM_INT_DISABLE_OFFSET 0x0048
#define GEN4_INTVEC_OFFSET 0x0050 /* 0-32 vecs */
#define GEN4_IM23XBASEIDX_OFFSET 0x0074
#define GEN4_IM45XBASEIDX_OFFSET 0x0076
#define GEN4_IM_SPAD_OFFSET 0x0080 /* 0-15 SPADs */
#define GEN4_IM_SPAD_SEM_OFFSET 0x00c0 /* SPAD hw semaphore */
#define GEN4_IM_SPAD_STICKY_OFFSET 0x00c4 /* sticky SPAD */
#define GEN4_IM_DOORBELL_OFFSET 0x0100 /* 0-31 doorbells */
#define GEN4_EM_SPAD_OFFSET 0x8080
/* note, link status is now in MMIO and not config space for NTB */
#define GEN4_LINK_CTRL_OFFSET 0xb050
#define GEN4_LINK_STATUS_OFFSET 0xb052
#define GEN4_PPD0_OFFSET 0xb0d4
#define GEN4_PPD1_OFFSET 0xb4c0
#define GEN4_LTSSMSTATEJMP 0xf040
#define GEN4_PPD_CLEAR_TRN 0x0001
#define GEN4_PPD_LINKTRN 0x0008
#define GEN4_PPD_CONN_MASK 0x0300
#define GEN4_PPD_CONN_B2B 0x0200
#define GEN4_PPD_DEV_MASK 0x1000
#define GEN4_PPD_DEV_DSD 0x1000
#define GEN4_PPD_DEV_USD 0x0000
#define GEN4_LINK_CTRL_LINK_DISABLE 0x0010
#define GEN4_SLOTSTS 0xb05a
#define GEN4_SLOTSTS_DLLSCS 0x100
#define GEN4_PPD_TOPO_MASK (GEN4_PPD_CONN_MASK | GEN4_PPD_DEV_MASK)
#define GEN4_PPD_TOPO_B2B_USD (GEN4_PPD_CONN_B2B | GEN4_PPD_DEV_USD)
#define GEN4_PPD_TOPO_B2B_DSD (GEN4_PPD_CONN_B2B | GEN4_PPD_DEV_DSD)
#define GEN4_DB_COUNT 32
#define GEN4_DB_LINK 32
#define GEN4_DB_LINK_BIT BIT_ULL(GEN4_DB_LINK)
#define GEN4_DB_MSIX_VECTOR_COUNT 33
#define GEN4_DB_MSIX_VECTOR_SHIFT 1
#define GEN4_DB_TOTAL_SHIFT 33
#define GEN4_SPAD_COUNT 16
#define NTB_CTL_E2I_BAR23_SNOOP 0x000004
#define NTB_CTL_E2I_BAR23_NOSNOOP 0x000008
#define NTB_CTL_I2E_BAR23_SNOOP 0x000010
#define NTB_CTL_I2E_BAR23_NOSNOOP 0x000020
#define NTB_CTL_E2I_BAR45_SNOOP 0x000040
#define NTB_CTL_E2I_BAR45_NOSNOO 0x000080
#define NTB_CTL_I2E_BAR45_SNOOP 0x000100
#define NTB_CTL_I2E_BAR45_NOSNOOP 0x000200
#define NTB_CTL_BUSNO_DIS_INC 0x000400
#define NTB_CTL_LINK_DOWN 0x010000
#define NTB_SJC_FORCEDETECT 0x000004
ssize_t ndev_ntb4_debugfs_read(struct file *filp, char __user *ubuf,
size_t count, loff_t *offp);
int gen4_init_dev(struct intel_ntb_dev *ndev);
ssize_t ndev_ntb4_debugfs_read(struct file *filp, char __user *ubuf,
size_t count, loff_t *offp);
extern const struct ntb_dev_ops intel_ntb4_ops;
#endif
......@@ -72,6 +72,7 @@
#define PCI_DEVICE_ID_INTEL_NTB_PS_BDX 0x6F0E
#define PCI_DEVICE_ID_INTEL_NTB_SS_BDX 0x6F0F
#define PCI_DEVICE_ID_INTEL_NTB_B2B_SKX 0x201C
#define PCI_DEVICE_ID_INTEL_NTB_B2B_ICX 0x347e
/* Ntb control and link status */
#define NTB_CTL_CFG_LOCK BIT(0)
......@@ -120,6 +121,7 @@ struct intel_ntb_xlat_reg {
unsigned long bar0_base;
unsigned long bar2_xlat;
unsigned long bar2_limit;
unsigned short bar2_idx;
};
struct intel_b2b_addr {
......@@ -182,6 +184,9 @@ struct intel_ntb_dev {
struct dentry *debugfs_dir;
struct dentry *debugfs_info;
/* gen4 entries */
int dev_up;
};
#define ntb_ndev(__ntb) container_of(__ntb, struct intel_ntb_dev, ntb)
......@@ -219,4 +224,11 @@ static inline int pdev_is_gen3(struct pci_dev *pdev)
return 0;
}
static inline int pdev_is_gen4(struct pci_dev *pdev)
{
if (pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_ICX)
return 1;
return 0;
}
#endif
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