Commit 28165ec7 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Arnd Bergmann:
 "This is a first set of bug fixes on top of what was merged for 4.7.

  Two patches for lpc32xx address a harmless build warning that was just
  introduced, one patch for the mediatek soc driver fixes a warning for
  arm64, and the pxa changes are minor cleanups that should have been
  part of the original pull requests but that I forgot to apply to the
  cleanup-fixes branch earlier"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: lpc32xx: fix NR_IRQS confict
  ARM: lpc32xx: remove legacy irq controller driver
  soc: mtk-pmic-wrap: avoid integer overflow warning
  ARM: pxa: Remove CLK_IS_ROOT
  ARM: pxa: activate pinctrl for device-tree machines
parents 08344f3b 09564b7d
...@@ -2,6 +2,6 @@ ...@@ -2,6 +2,6 @@
# Makefile for the linux kernel. # Makefile for the linux kernel.
# #
obj-y := irq.o common.o serial.o obj-y := common.o serial.o
obj-y += pm.o suspend.o obj-y += pm.o suspend.o
obj-y += phy3250.o obj-y += phy3250.o
...@@ -112,6 +112,6 @@ ...@@ -112,6 +112,6 @@
#define IRQ_LPC32XX_GPI_06 LPC32XX_SIC2_IRQ(28) #define IRQ_LPC32XX_GPI_06 LPC32XX_SIC2_IRQ(28)
#define IRQ_LPC32XX_SYSCLK LPC32XX_SIC2_IRQ(31) #define IRQ_LPC32XX_SYSCLK LPC32XX_SIC2_IRQ(31)
#define NR_IRQS 96 #define LPC32XX_NR_IRQS 96
#endif #endif
This diff is collapsed.
...@@ -6,6 +6,7 @@ comment "Intel/Marvell Dev Platforms (sorted by hardware release time)" ...@@ -6,6 +6,7 @@ comment "Intel/Marvell Dev Platforms (sorted by hardware release time)"
config MACH_PXA27X_DT config MACH_PXA27X_DT
bool "Support PXA27x platforms from device tree" bool "Support PXA27x platforms from device tree"
select PINCTRL
select POWER_SUPPLY select POWER_SUPPLY
select PXA27x select PXA27x
select USE_OF select USE_OF
...@@ -17,6 +18,7 @@ config MACH_PXA27X_DT ...@@ -17,6 +18,7 @@ config MACH_PXA27X_DT
config MACH_PXA3XX_DT config MACH_PXA3XX_DT
bool "Support PXA3xx platforms from device tree" bool "Support PXA3xx platforms from device tree"
select CPU_PXA300 select CPU_PXA300
select PINCTRL
select POWER_SUPPLY select POWER_SUPPLY
select PXA3xx select PXA3xx
select USE_OF select USE_OF
......
...@@ -128,7 +128,7 @@ struct resource eseries_tmio_resources[] = { ...@@ -128,7 +128,7 @@ struct resource eseries_tmio_resources[] = {
/* Some e-series hardware cannot control the 32K clock */ /* Some e-series hardware cannot control the 32K clock */
static void __init __maybe_unused eseries_register_clks(void) static void __init __maybe_unused eseries_register_clks(void)
{ {
clk_register_fixed_rate(NULL, "CLK_CK32K", NULL, CLK_IS_ROOT, 32768); clk_register_fixed_rate(NULL, "CLK_CK32K", NULL, 0, 32768);
} }
#ifdef CONFIG_MACH_E330 #ifdef CONFIG_MACH_E330
......
...@@ -1059,7 +1059,7 @@ static const struct pmic_wrapper_type pwrap_mt2701 = { ...@@ -1059,7 +1059,7 @@ static const struct pmic_wrapper_type pwrap_mt2701 = {
.regs = mt2701_regs, .regs = mt2701_regs,
.type = PWRAP_MT2701, .type = PWRAP_MT2701,
.arb_en_all = 0x3f, .arb_en_all = 0x3f,
.int_en_all = ~(BIT(31) | BIT(2)), .int_en_all = ~(u32)(BIT(31) | BIT(2)),
.spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW, .spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW,
.wdt_src = PWRAP_WDT_SRC_MASK_ALL, .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
.has_bridge = 0, .has_bridge = 0,
...@@ -1071,7 +1071,7 @@ static struct pmic_wrapper_type pwrap_mt8135 = { ...@@ -1071,7 +1071,7 @@ static struct pmic_wrapper_type pwrap_mt8135 = {
.regs = mt8135_regs, .regs = mt8135_regs,
.type = PWRAP_MT8135, .type = PWRAP_MT8135,
.arb_en_all = 0x1ff, .arb_en_all = 0x1ff,
.int_en_all = ~(BIT(31) | BIT(1)), .int_en_all = ~(u32)(BIT(31) | BIT(1)),
.spi_w = PWRAP_MAN_CMD_SPI_WRITE, .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
.wdt_src = PWRAP_WDT_SRC_MASK_ALL, .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
.has_bridge = 1, .has_bridge = 1,
...@@ -1083,7 +1083,7 @@ static struct pmic_wrapper_type pwrap_mt8173 = { ...@@ -1083,7 +1083,7 @@ static struct pmic_wrapper_type pwrap_mt8173 = {
.regs = mt8173_regs, .regs = mt8173_regs,
.type = PWRAP_MT8173, .type = PWRAP_MT8173,
.arb_en_all = 0x3f, .arb_en_all = 0x3f,
.int_en_all = ~(BIT(31) | BIT(1)), .int_en_all = ~(u32)(BIT(31) | BIT(1)),
.spi_w = PWRAP_MAN_CMD_SPI_WRITE, .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
.wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD, .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
.has_bridge = 0, .has_bridge = 0,
......
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