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Commit 2836f684 authored by Dave Jones's avatar Dave Jones
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Merge tetrachloride.(none):/mnt/raid/src/kernel/2.5/bk-linus 

into tetrachloride.(none):/mnt/raid/src/kernel/2.5/agpgart
parents afbf875b efeb6b50
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Showing with 1812 additions and 1843 deletions
drivers/char/agp/Kconfig
View file @ 2836f684
......@@ -31,7 +31,7 @@ config AGP_GART
config AGP_INTEL
tristate "Intel 440LX/BX/GX, I8xx and E7x05 support"
depends on AGP && !X86_64
depends on AGP && X86 && !X86_64
help
This option gives you AGP support for the GLX component of the
XFree86 4.x on Intel 440LX/BX/GX, 815, 820, 830, 840, 845, 850, 860
......@@ -44,7 +44,7 @@ config AGP_INTEL
#config AGP_I810
# tristate "Intel I810/I815/I830M (on-board) support"
# depends on AGP && !X86_64
# depends on AGP && X86 && !X86_64
# help
# This option gives you AGP support for the Xserver on the Intel 810
# 815 and 830m chipset boards for their on-board integrated graphics. This
......@@ -52,7 +52,7 @@ config AGP_INTEL
config AGP_VIA
tristate "VIA chipset support"
depends on AGP && !X86_64
depends on AGP && X86 & !X86_64
help
This option gives you AGP support for the GLX component of the
XFree86 4.x on VIA MPV3/Apollo Pro chipsets.
......@@ -62,7 +62,7 @@ config AGP_VIA
config AGP_AMD
tristate "AMD Irongate, 761, and 762 support"
depends on AGP && !X86_64
depends on AGP && X86 && !X86_64
help
This option gives you AGP support for the GLX component of the
XFree86 4.x on AMD Irongate, 761, and 762 chipsets.
......@@ -72,7 +72,7 @@ config AGP_AMD
config AGP_SIS
tristate "Generic SiS support"
depends on AGP && !X86_64
depends on AGP && X86 && !X86_64
help
This option gives you AGP support for the GLX component of the "soon
to be released" XFree86 4.x on Silicon Integrated Systems [SiS]
......@@ -85,7 +85,7 @@ config AGP_SIS
config AGP_ALI
tristate "ALI chipset support"
depends on AGP && !X86_64
depends on AGP && X86 && !X86_64
---help---
This option gives you AGP support for the GLX component of the
XFree86 4.x on the following ALi chipsets. The supported chipsets
......@@ -103,14 +103,22 @@ config AGP_ALI
config AGP_SWORKS
tristate "Serverworks LE/HE support"
depends on AGP && !X86_64
depends on AGP && X86 && !X86_64
help
Say Y here to support the Serverworks AGP card. See
<http://www.serverworks.com/> for product descriptions and images.
config AGP_NVIDIA
tristate "NVIDIA nForce/nForce2 chipset support"
depends on AGP && X86 && !X86_64
help
This option gives you AGP support for the GLX component of the
XFree86 4.x on the following NVIDIA chipsets. The supported chipsets
include nForce and nForce2
config AGP_AMD_8151
tristate "AMD 8151 support"
depends on AGP
depends on AGP && X86
default GART_IOMMU
help
Say Y here to support the AMD 8151 AGP bridge and the builtin
......
drivers/char/agp/Makefile
View file @ 2836f684
#
# Makefile for the agpgart device driver. This driver adds a user
# space ioctl interface to use agp memory. It also adds a kernel interface
# that other drivers could use to manipulate agp memory.
agpgart-y := backend.o frontend.o generic.o generic-3.0.o
agpgart-objs := $(agpgart-y)
obj-$(CONFIG_AGP) += agpgart.o
obj-$(CONFIG_AGP_INTEL) += intel-agp.o
obj-$(CONFIG_AGP_VIA) += via-agp.o
obj-$(CONFIG_AGP_AMD) += amd-k7-agp.o
obj-$(CONFIG_AGP_SIS) += sis-agp.o
obj-$(CONFIG_AGP) += agpgart.o
obj-$(CONFIG_AGP_ALI) += ali-agp.o
obj-$(CONFIG_AGP_SWORKS) += sworks-agp.o
obj-$(CONFIG_AGP_I460) += i460-agp.o
obj-$(CONFIG_AGP_HP_ZX1) += hp-agp.o
obj-$(CONFIG_AGP_AMD) += amd-k7-agp.o
obj-$(CONFIG_AGP_AMD_8151) += amd-k8-agp.o
obj-$(CONFIG_AGP_ALPHA_CORE) += alpha-agp.o
obj-$(CONFIG_AGP_HP_ZX1) += hp-agp.o
obj-$(CONFIG_AGP_I460) += i460-agp.o
obj-$(CONFIG_AGP_INTEL) += intel-agp.o
obj-$(CONFIG_AGP_NVIDIA) += nvidia-agp.o
obj-$(CONFIG_AGP_SIS) += sis-agp.o
obj-$(CONFIG_AGP_SWORKS) += sworks-agp.o
obj-$(CONFIG_AGP_VIA) += via-agp.o
drivers/char/agp/agp.h
View file @ 2836f684
......@@ -34,24 +34,6 @@ extern struct agp_bridge_data *agp_bridge;
#define PFX "agpgart: "
#ifdef CONFIG_SMP
static void ipi_handler(void *null)
{
flush_agp_cache();
}
static void __attribute__((unused)) global_cache_flush(void)
{
if (on_each_cpu(ipi_handler, NULL, 1, 1) != 0)
panic(PFX "timed out waiting for the other CPUs!\n");
}
#else
static void global_cache_flush(void)
{
flush_agp_cache();
}
#endif /* !CONFIG_SMP */
enum aper_size_type {
U8_APER_SIZE,
U16_APER_SIZE,
......@@ -165,20 +147,17 @@ struct agp_bridge_data {
#define MB(x) (KB (KB (x)))
#define GB(x) (MB (KB (x)))
#define CACHE_FLUSH agp_bridge->cache_flush
#define A_SIZE_8(x) ((struct aper_size_info_8 *) x)
#define A_SIZE_16(x) ((struct aper_size_info_16 *) x)
#define A_SIZE_32(x) ((struct aper_size_info_32 *) x)
#define A_SIZE_LVL2(x) ((struct aper_size_info_lvl2 *) x)
#define A_SIZE_FIX(x) ((struct aper_size_info_fixed *) x)
#define A_IDX8() (A_SIZE_8(agp_bridge->aperture_sizes) + i)
#define A_IDX16() (A_SIZE_16(agp_bridge->aperture_sizes) + i)
#define A_IDX32() (A_SIZE_32(agp_bridge->aperture_sizes) + i)
#define A_IDXLVL2() (A_SIZE_LVL2(agp_bridge->aperture_sizes) + i)
#define A_IDXFIX() (A_SIZE_FIX(agp_bridge->aperture_sizes) + i)
#define A_IDX8(bridge) (A_SIZE_8((bridge)->aperture_sizes) + i)
#define A_IDX16(bridge) (A_SIZE_16((bridge)->aperture_sizes) + i)
#define A_IDX32(bridge) (A_SIZE_32((bridge)->aperture_sizes) + i)
#define MAXKEY (4096 * 32)
#define PGE_EMPTY(p) (!(p) || (p) == (unsigned long) agp_bridge->scratch_page)
#define PGE_EMPTY(b, p) (!(p) || (p) == (unsigned long) (b)->scratch_page)
/* intel register */
#define INTEL_APBASE 0x10
......@@ -358,6 +337,17 @@ struct agp_bridge_data {
#define SVWRKS_POSTFLUSH 0x14
#define SVWRKS_DIRFLUSH 0x0c
/* NVIDIA registers */
#define NVIDIA_0_APBASE 0x10
#define NVIDIA_0_APSIZE 0x80
#define NVIDIA_1_WBC 0xf0
#define NVIDIA_2_GARTCTRL 0xd0
#define NVIDIA_2_APBASE 0xd8
#define NVIDIA_2_APLIMIT 0xdc
#define NVIDIA_2_ATTBASE(i) (0xe0 + (i) * 4)
#define NVIDIA_3_APBASE 0x50
#define NVIDIA_3_APLIMIT 0x54
/* HP ZX1 SBA registers */
#define HP_ZX1_CTRL 0x200
#define HP_ZX1_IBASE 0x300
......@@ -380,6 +370,14 @@ struct agp_driver {
};
/* Frontend routines. */
int agp_frontend_initialize(void);
void agp_frontend_cleanup(void);
/* Backend routines. */
int agp_register_driver (struct agp_driver *drv);
int agp_unregister_driver(struct agp_driver *drv);
/* Generic routines. */
void agp_generic_enable(u32 mode);
int agp_generic_create_gatt_table(void);
......@@ -395,10 +393,29 @@ int agp_generic_suspend(void);
void agp_generic_resume(void);
void agp_free_key(int key);
int agp_num_entries(void);
int agp_register_driver (struct agp_driver *drv);
int agp_unregister_driver(struct agp_driver *drv);
u32 agp_collect_device_status(u32 mode, u32 command);
void agp_device_command(u32 command, int agp_v3);
int agp_3_0_node_enable(u32 mode, u32 minor);
void global_cache_flush(void);
/* Standard agp registers */
#define AGPSTAT 0x4
#define AGPCMD 0x8
#define AGPNEPG 0x16
#define AGP_MAJOR_VERSION_SHIFT (20)
#define AGP_MINOR_VERSION_SHIFT (16)
#define AGPSTAT_RQ_DEPTH (0xff000000)
#define AGPSTAT_ARQSZ_SHIFT 13
#define AGPSTAT_AGP_ENABLE (1<<8)
#define AGPSTAT_SBA (1<<9)
#define AGPSTAT2_1X (1<<0)
#define AGPSTAT2_2X (1<<1)
#define AGPSTAT2_4X (1<<2)
#define AGPSTAT_FW (1<<4)
#endif /* _AGP_BACKEND_PRIV_H */
drivers/char/agp/ali-agp.c
View file @ 2836f684
This diff is collapsed.
drivers/char/agp/alpha-agp.c
View file @ 2836f684
......@@ -130,20 +130,52 @@ static struct agp_driver alpha_core_agp_driver = {
.owner = THIS_MODULE,
};
struct agp_bridge_data alpha_core_agp_bridge = {
.type = ALPHA_CORE_AGP,
.masks = alpha_core_agp_masks,
.aperture_sizes = aper_size,
.current_size = aper_size, /* only one entry */
.size_type = FIXED_APER_SIZE,
.num_aperture_sizes = 1,
.dev_private_data = agp,
.configure = alpha_core_agp_configure,
.fetch_size = alpha_core_agp_fetch_size,
.cleanup = alpha_core_agp_cleanup,
.tlb_flush = alpha_core_agp_tlbflush,
.mask_memory = alpha_core_agp_mask_memory,
.agp_enable = alpha_core_agp_enable,
.cache_flush = global_cache_flush,
.create_gatt_table = alpha_core_agp_nop,
.free_gatt_table = alpha_core_agp_nop,
.insert_memory = alpha_core_agp_insert_memory,
.remove_memory = alpha_core_agp_remove_memory,
.alloc_by_type = agp_generic_alloc_by_type,
.free_by_type = agp_generic_free_by_type,
.agp_alloc_page = agp_generic_alloc_page,
.agp_destroy_page = agp_generic_destroy_page,
.mode = agp->capability.lw,
.cant_use_aperture = 1,
.vm_ops = &alpha_core_agp_vm_ops,
};
int __init
alpha_core_agp_setup(void)
{
alpha_agp_info *agp = alpha_mv.agp_info();
struct pci_dev *pdev; /* faked */
struct aper_size_info_fixed *aper_size;
if (!agp) return -ENODEV;
if (agp->ops->setup(agp)) return -ENODEV;
if (!agp)
return -ENODEV;
if (agp->ops->setup(agp))
return -ENODEV;
/*
* Build the aperture size descriptor
*/
aper_size = alpha_core_agp_sizes;
if (!aper_size) return -ENOMEM;
if (!aper_size)
return -ENOMEM;
aper_size->size = agp->aperture.size / (1024 * 1024);
aper_size->num_entries = agp->aperture.size / PAGE_SIZE;
aper_size->page_order = ffs(aper_size->num_entries / 1024) - 1;
......@@ -151,43 +183,18 @@ alpha_core_agp_setup(void)
/*
* Build a fake pci_dev struct
*/
if (!(agp_bridge->dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL))) {
pdev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
if (!pdev)
return -ENOMEM;
}
agp_bridge->dev->vendor = 0xffff;
agp_bridge->dev->device = 0xffff;
agp_bridge->dev->sysdata = agp->hose;
pdev->vendor = 0xffff;
pdev->device = 0xffff;
pdev->sysdata = agp->hose;
/*
* Fill in the rest of the agp_bridge struct
*/
agp_bridge->masks = alpha_core_agp_masks;
agp_bridge->aperture_sizes = aper_size;
agp_bridge->current_size = aper_size; /* only one entry */
agp_bridge->size_type = FIXED_APER_SIZE;
agp_bridge->num_aperture_sizes = 1;
agp_bridge->dev_private_data = agp;
agp_bridge->needs_scratch_page = FALSE;
agp_bridge->configure = alpha_core_agp_configure;
agp_bridge->fetch_size = alpha_core_agp_fetch_size;
agp_bridge->cleanup = alpha_core_agp_cleanup;
agp_bridge->tlb_flush = alpha_core_agp_tlbflush;
agp_bridge->mask_memory = alpha_core_agp_mask_memory;
agp_bridge->agp_enable = alpha_core_agp_enable;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = alpha_core_agp_nop;
agp_bridge->free_gatt_table = alpha_core_agp_nop;
agp_bridge->insert_memory = alpha_core_agp_insert_memory;
agp_bridge->remove_memory = alpha_core_agp_remove_memory;
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
agp_bridge->mode = agp->capability.lw;
agp_bridge->cant_use_aperture = 1;
agp_bridge->vm_ops = &alpha_core_agp_vm_ops;
alpha_core_agp_driver.dev = agp_bridge->dev;
alpha_core_agp_bridge.dev = pdev;
memcpy(agp_bridge, &alpha_core_agp_bridge,
sizeof(struct agp_bridge_data));
alpha_core_agp_driver.dev = pdev;
agp_register_driver(&alpha_core_agp_driver);
printk(KERN_INFO "Detected AGP on hose %d\n", agp->hose->index);
return 0;
......@@ -195,13 +202,9 @@ alpha_core_agp_setup(void)
static int __init agp_alpha_core_init(void)
{
int ret_val = -ENODEV;
if (alpha_mv.agp_info) {
agp_bridge->type = ALPHA_CORE_AGP;
ret_val = alpha_core_agp_setup();
}
return ret_val;
if (alpha_mv.agp_info)
return alpha_core_agp_setup();
return -ENODEV;
}
static void __exit agp_alpha_core_cleanup(void)
......
drivers/char/agp/amd-k7-agp.c
View file @ 2836f684
......@@ -33,7 +33,7 @@ static int amd_create_page_map(struct amd_page_map *page_map)
return -ENOMEM;
}
SetPageReserved(virt_to_page(page_map->real));
CACHE_FLUSH();
global_cache_flush();
page_map->remapped = ioremap_nocache(virt_to_phys(page_map->real),
PAGE_SIZE);
if (page_map->remapped == NULL) {
......@@ -42,7 +42,7 @@ static int amd_create_page_map(struct amd_page_map *page_map)
page_map->real = NULL;
return -ENOMEM;
}
CACHE_FLUSH();
global_cache_flush();
for(i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) {
page_map->remapped[i] = agp_bridge->scratch_page;
......@@ -297,14 +297,13 @@ static int amd_insert_memory(agp_memory * mem,
while (j < (pg_start + mem->page_count)) {
addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
cur_gatt = GET_GATT(addr);
if (!PGE_EMPTY(cur_gatt[GET_GATT_OFF(addr)])) {
if (!PGE_EMPTY(agp_bridge, cur_gatt[GET_GATT_OFF(addr)]))
return -EBUSY;
}
j++;
}
if (mem->is_flushed == FALSE) {
CACHE_FLUSH();
global_cache_flush();
mem->is_flushed = TRUE;
}
......@@ -355,115 +354,98 @@ static struct gatt_mask amd_irongate_masks[] =
{.mask = 0x00000001, .type = 0}
};
static int __init amd_irongate_setup (struct pci_dev *pdev)
{
agp_bridge->masks = amd_irongate_masks;
agp_bridge->aperture_sizes = (void *) amd_irongate_sizes;
agp_bridge->size_type = LVL2_APER_SIZE;
agp_bridge->num_aperture_sizes = 7;
agp_bridge->dev_private_data = (void *) &amd_irongate_private;
agp_bridge->needs_scratch_page = FALSE;
agp_bridge->configure = amd_irongate_configure;
agp_bridge->fetch_size = amd_irongate_fetch_size;
agp_bridge->cleanup = amd_irongate_cleanup;
agp_bridge->tlb_flush = amd_irongate_tlbflush;
agp_bridge->mask_memory = amd_irongate_mask_memory;
agp_bridge->agp_enable = agp_generic_enable;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = amd_create_gatt_table;
agp_bridge->free_gatt_table = amd_free_gatt_table;
agp_bridge->insert_memory = amd_insert_memory;
agp_bridge->remove_memory = amd_remove_memory;
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
agp_bridge->suspend = agp_generic_suspend;
agp_bridge->resume = agp_generic_resume;
agp_bridge->cant_use_aperture = 0;
return 0;
}
struct agp_bridge_data amd_irongate_bridge = {
.type = AMD_GENERIC,
.masks = amd_irongate_masks,
.aperture_sizes = (void *)amd_irongate_sizes,
.size_type = LVL2_APER_SIZE,
.num_aperture_sizes = 7,
.dev_private_data = (void *)&amd_irongate_private,
.configure = amd_irongate_configure,
.fetch_size = amd_irongate_fetch_size,
.cleanup = amd_irongate_cleanup,
.tlb_flush = amd_irongate_tlbflush,
.mask_memory = amd_irongate_mask_memory,
.agp_enable = agp_generic_enable,
.cache_flush = global_cache_flush,
.create_gatt_table = amd_create_gatt_table,
.free_gatt_table = amd_free_gatt_table,
.insert_memory = amd_insert_memory,
.remove_memory = amd_remove_memory,
.alloc_by_type = agp_generic_alloc_by_type,
.free_by_type = agp_generic_free_by_type,
.agp_alloc_page = agp_generic_alloc_page,
.agp_destroy_page = agp_generic_destroy_page,
.suspend = agp_generic_suspend,
.resume = agp_generic_resume,
};
struct agp_device_ids amd_agp_device_ids[] __initdata =
{
{
.device_id = PCI_DEVICE_ID_AMD_FE_GATE_7006,
.chipset = AMD_IRONGATE,
.chipset_name = "Irongate",
},
{
.device_id = PCI_DEVICE_ID_AMD_FE_GATE_700E,
.chipset = AMD_761,
.chipset_name = "761",
},
{
.device_id = PCI_DEVICE_ID_AMD_FE_GATE_700C,
.chipset = AMD_762,
.chipset_name = "760MP",
},
{ }, /* dummy final entry, always present */
};
static struct agp_driver amd_k7_agp_driver = {
.owner = THIS_MODULE,
};
/* scan table above for supported devices */
static int __init agp_lookup_host_bridge (struct pci_dev *pdev)
static int __init agp_amdk7_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
int j=0;
struct agp_device_ids *devs;
struct agp_device_ids *devs = amd_agp_device_ids;
u8 cap_ptr;
int j;
devs = amd_agp_device_ids;
cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
if (!cap_ptr)
return -ENODEV;
while (devs[j].chipset_name != NULL) {
for (j = 0; devs[j].chipset_name; j++) {
if (pdev->device == devs[j].device_id) {
printk (KERN_INFO PFX "Detected AMD %s chipset\n", devs[j].chipset_name);
agp_bridge->type = devs[j].chipset;
if (devs[j].chipset_setup != NULL)
return devs[j].chipset_setup(pdev);
else
return amd_irongate_setup(pdev);
}
j++;
printk (KERN_INFO PFX "Detected AMD %s chipset\n",
devs[j].chipset_name);
amd_irongate_bridge.type = devs[j].chipset;
goto found;
}
/* try init anyway, if user requests it */
if (agp_try_unsupported) {
printk(KERN_WARNING PFX "Trying generic AMD routines"
" for device id: %04x\n", pdev->device);
agp_bridge->type = AMD_GENERIC;
return amd_irongate_setup(pdev);
}
printk(KERN_ERR PFX "Unsupported AMD chipset (device id: %04x),"
" you might want to try agp_try_unsupported=1.\n", pdev->device);
if (!agp_try_unsupported) {
printk(KERN_ERR PFX
"Unsupported AMD chipset (device id: %04x),"
" you might want to try agp_try_unsupported=1.\n",
pdev->device);
return -ENODEV;
}
}
static struct agp_driver amd_k7_agp_driver = {
.owner = THIS_MODULE,
};
printk(KERN_WARNING PFX "Trying generic AMD routines"
" for device id: %04x\n", pdev->device);
/* Supported Device Scanning routine */
found:
amd_irongate_bridge.dev = pdev;
amd_irongate_bridge.capndx = cap_ptr;
static int __init agp_amdk7_probe (struct pci_dev *dev, const struct pci_device_id *ent)
{
u8 cap_ptr = 0;
/* Fill in the mode register */
pci_read_config_dword(pdev,
amd_irongate_bridge.capndx+PCI_AGP_STATUS,
&amd_irongate_bridge.mode);
cap_ptr = pci_find_capability(dev, PCI_CAP_ID_AGP);
if (cap_ptr == 0)
return -ENODEV;
memcpy(agp_bridge, &amd_irongate_bridge, sizeof(struct agp_bridge_data));
if (agp_lookup_host_bridge(dev) != -ENODEV) {
agp_bridge->dev = dev;
agp_bridge->capndx = cap_ptr;
/* Fill in the mode register */
pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
amd_k7_agp_driver.dev = dev;
amd_k7_agp_driver.dev = pdev;
agp_register_driver(&amd_k7_agp_driver);
return 0;
}
return -ENODEV;
}
static struct pci_device_id agp_amdk7_pci_table[] __initdata = {
......@@ -488,13 +470,7 @@ static struct __initdata pci_driver agp_amdk7_pci_driver = {
static int __init agp_amdk7_init(void)
{
int ret_val;
ret_val = pci_module_init(&agp_amdk7_pci_driver);
if (ret_val)
agp_bridge->type = NOT_SUPPORTED;
return ret_val;
return pci_module_init(&agp_amdk7_pci_driver);
}
static void __exit agp_amdk7_cleanup(void)
......
drivers/char/agp/amd-k8-agp.c
View file @ 2836f684
......@@ -50,13 +50,13 @@ static int x86_64_insert_memory(agp_memory * mem, off_t pg_start, int type)
/* gatt table should be empty. */
while (j < (pg_start + mem->page_count)) {
if (!PGE_EMPTY(agp_bridge->gatt_table[j]))
if (!PGE_EMPTY(agp_bridge, agp_bridge->gatt_table[j]))
return -EBUSY;
j++;
}
if (mem->is_flushed == FALSE) {
CACHE_FLUSH();
global_cache_flush();
mem->is_flushed = TRUE;
}
......@@ -227,130 +227,78 @@ static struct gatt_mask amd_8151_masks[] =
{.mask = 0x00000001, .type = 0}
};
struct agp_bridge_data amd_8151_bridge = {
.masks = amd_8151_masks,
.aperture_sizes = (void *)amd_8151_sizes,
.size_type = U32_APER_SIZE,
.num_aperture_sizes = 7,
.configure = amd_8151_configure,
.fetch_size = amd_x86_64_fetch_size,
.cleanup = amd_8151_cleanup,
.tlb_flush = amd_x86_64_tlbflush,
.mask_memory = amd_8151_mask_memory,
.agp_enable = agp_generic_enable,
.cache_flush = global_cache_flush,
.create_gatt_table = agp_generic_create_gatt_table,
.free_gatt_table = agp_generic_free_gatt_table,
.insert_memory = x86_64_insert_memory,
.remove_memory = agp_generic_remove_memory,
.alloc_by_type = agp_generic_alloc_by_type,
.free_by_type = agp_generic_free_by_type,
.agp_alloc_page = agp_generic_alloc_page,
.agp_destroy_page = agp_generic_destroy_page,
.suspend = agp_generic_suspend,
.resume = agp_generic_resume,
};
/*
* Try to configure an AGP v3 capable setup.
* If we fail (typically because we don't have an AGP v3
* card in the system) we fall back to the generic AGP v2
* routines.
*/
static void agp_x86_64_agp_enable(u32 mode)
static struct agp_driver amd_k8_agp_driver = {
.owner = THIS_MODULE,
};
static int __init agp_amdk8_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
struct pci_dev *device = NULL;
u32 command, scratch;
struct pci_dev *loop_dev;
u8 cap_ptr;
u8 v3_devs=0;
/* FIXME: If 'mode' is x1/x2/x4 should we call the AGPv2 routines directly ?
* Messy, as some AGPv3 cards can only do x4 as a minimum.
*/
/* PASS1: Count # of devs capable of AGPv3 mode. */
pci_for_each_dev(device) {
cap_ptr = pci_find_capability(device, PCI_CAP_ID_AGP);
if (cap_ptr != 0x00) {
pci_read_config_dword(device, cap_ptr, &scratch);
scratch &= (1<<20|1<<21|1<<22|1<<23);
scratch = scratch>>20;
/* AGP v3 capable ? */
if (scratch>=3) {
v3_devs++;
printk (KERN_INFO "AGP: Found AGPv3 capable device at %d:%d:%d\n",
device->bus->number, PCI_FUNC(device->devfn), PCI_SLOT(device->devfn));
} else {
printk (KERN_INFO "AGP: Meh. version %x AGP device found.\n", scratch);
}
}
}
/* If not enough, go to AGP v2 setup */
if (v3_devs<2) {
printk (KERN_INFO "AGP: Only %d devices found, not enough, trying AGPv2\n", v3_devs);
return agp_generic_enable(mode);
} else {
printk (KERN_INFO "AGP: Enough AGPv3 devices found, setting up...\n");
}
pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &command);
command = agp_collect_device_status(mode, command);
command |= 0x100;
int i = 0;
pci_write_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_COMMAND, command);
agp_device_command(command, 1);
}
cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
if (!cap_ptr)
return -ENODEV;
printk(KERN_INFO PFX "Detected Opteron/Athlon64 on-CPU GART\n");
static int __init amd_8151_setup (struct pci_dev *pdev)
{
struct pci_dev *dev;
int i=0;
agp_bridge->masks = amd_8151_masks;
agp_bridge->aperture_sizes = (void *) amd_8151_sizes;
agp_bridge->size_type = U32_APER_SIZE;
agp_bridge->num_aperture_sizes = 7;
agp_bridge->dev_private_data = NULL;
agp_bridge->needs_scratch_page = FALSE;
agp_bridge->configure = amd_8151_configure;
agp_bridge->fetch_size = amd_x86_64_fetch_size;
agp_bridge->cleanup = amd_8151_cleanup;
agp_bridge->tlb_flush = amd_x86_64_tlbflush;
agp_bridge->mask_memory = amd_8151_mask_memory;
agp_bridge->agp_enable = agp_x86_64_agp_enable;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
agp_bridge->insert_memory = x86_64_insert_memory;
agp_bridge->remove_memory = agp_generic_remove_memory;
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
agp_bridge->suspend = agp_generic_suspend;
agp_bridge->resume = agp_generic_resume;
agp_bridge->cant_use_aperture = 0;
amd_8151_bridge.dev = pdev;
amd_8151_bridge.capndx = cap_ptr;
/* Fill in the mode register */
pci_read_config_dword(pdev,
amd_8151_bridge.capndx+PCI_AGP_STATUS,
&amd_8151_bridge.mode);
/* cache pci_devs of northbridges. */
pci_for_each_dev(dev) {
if (dev->bus->number==0 && PCI_FUNC(dev->devfn)==3 &&
(PCI_SLOT(dev->devfn) >=24) && (PCI_SLOT(dev->devfn) <=31)) {
hammers[i++] = dev;
pci_for_each_dev(loop_dev) {
if (loop_dev->bus->number == 0 &&
PCI_FUNC(loop_dev->devfn) == 3 &&
PCI_SLOT(loop_dev->devfn) >=24 &&
PCI_SLOT(loop_dev->devfn) <=31) {
hammers[i++] = loop_dev;
nr_garts = i;
if (i==MAX_HAMMER_GARTS)
if (i == MAX_HAMMER_GARTS)
return 0;
}
}
memcpy(agp_bridge, &amd_8151_bridge, sizeof(struct agp_bridge_data));
amd_k8_agp_driver.dev = pdev;
agp_register_driver(&amd_k8_agp_driver);
return 0;
}
static struct agp_driver amd_k8_agp_driver = {
.owner = THIS_MODULE,
};
static int __init agp_amdk8_probe (struct pci_dev *dev, const struct pci_device_id *ent)
static void __exit agp_amdk8_remove(struct pci_dev *pdev)
{
u8 cap_ptr = 0;
cap_ptr = pci_find_capability(dev, PCI_CAP_ID_AGP);
if (cap_ptr == 0)
return -ENODEV;
printk (KERN_INFO PFX "Detected Opteron/Athlon64 on-CPU GART\n");
agp_bridge->dev = dev;
agp_bridge->capndx = cap_ptr;
/* Fill in the mode register */
pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
amd_8151_setup(dev);
amd_k8_agp_driver.dev = dev;
agp_register_driver(&amd_k8_agp_driver);
return 0;
agp_unregister_driver(&amd_k8_agp_driver);
}
static struct pci_device_id agp_amdk8_pci_table[] __initdata = {
......@@ -371,25 +319,17 @@ static struct __initdata pci_driver agp_amdk8_pci_driver = {
.name = "agpgart-amd-k8",
.id_table = agp_amdk8_pci_table,
.probe = agp_amdk8_probe,
.remove = agp_amdk8_remove,
};
/* Not static due to IOMMU code calling it early. */
int __init agp_amdk8_init(void)
{
int ret_val;
ret_val = pci_module_init(&agp_amdk8_pci_driver);
if (ret_val)
agp_bridge->type = NOT_SUPPORTED;
agp_bridge->type = AMD_8151;
return ret_val;
return pci_module_init(&agp_amdk8_pci_driver);
}
static void __exit agp_amdk8_cleanup(void)
{
agp_unregister_driver(&amd_k8_agp_driver);
pci_unregister_driver(&agp_amdk8_pci_driver);
}
......
drivers/char/agp/backend.c
View file @ 2836f684
......@@ -43,10 +43,25 @@
* past 0.99 at all due to some boolean logic error. */
#define AGPGART_VERSION_MAJOR 0
#define AGPGART_VERSION_MINOR 100
static struct agp_version agp_current_version =
{
.major = AGPGART_VERSION_MAJOR,
.minor = AGPGART_VERSION_MINOR,
};
static int agp_count=0;
struct agp_bridge_data agp_bridge_dummy = { .type = NOT_SUPPORTED };
struct agp_bridge_data *agp_bridge = &agp_bridge_dummy;
EXPORT_SYMBOL(agp_bridge);
/**
* agp_backend_acquire - attempt to acquire the agp backend.
*
* returns -EBUSY if agp is in use,
* returns 0 if the caller owns the agp backend
*/
int agp_backend_acquire(void)
{
if (agp_bridge->type == NOT_SUPPORTED)
......@@ -58,7 +73,15 @@ int agp_backend_acquire(void)
atomic_inc(&agp_bridge->agp_in_use);
return 0;
}
EXPORT_SYMBOL(agp_backend_acquire);
/**
* agp_backend_release - release the lock on the agp backend.
*
* The caller must insure that the graphics aperture translation table is read for use
* by another entity. (Ensure that all memory it bound is unbound.)
*/
void agp_backend_release(void)
{
if (agp_bridge->type == NOT_SUPPORTED)
......@@ -66,6 +89,8 @@ void agp_backend_release(void)
atomic_dec(&agp_bridge->agp_in_use);
}
EXPORT_SYMBOL(agp_backend_release);
struct agp_max_table {
int mem;
......@@ -105,11 +130,6 @@ static int agp_find_max (void)
return result;
}
static struct agp_version agp_current_version =
{
.major = AGPGART_VERSION_MAJOR,
.minor = AGPGART_VERSION_MINOR,
};
static int agp_backend_initialize(struct pci_dev *dev)
{
......@@ -194,10 +214,10 @@ static void agp_backend_cleanup(void)
agp_bridge->agp_destroy_page(phys_to_virt(agp_bridge->scratch_page_real));
}
static int agp_power(struct pm_dev *dev, pm_request_t rq, void *data)
{
switch(rq)
{
switch(rq) {
case PM_SUSPEND:
return agp_bridge->suspend();
case PM_RESUME:
......@@ -207,8 +227,6 @@ static int agp_power(struct pm_dev *dev, pm_request_t rq, void *data)
return 0;
}
extern int agp_frontend_initialize(void);
extern void agp_frontend_cleanup(void);
static const drm_agp_t drm_agp = {
&agp_free_memory,
......@@ -221,7 +239,6 @@ static const drm_agp_t drm_agp = {
&agp_copy_info
};
static int agp_count=0;
int agp_register_driver (struct agp_driver *drv)
{
......@@ -264,6 +281,8 @@ int agp_register_driver (struct agp_driver *drv)
drv->dev = NULL;
return ret_val;
}
EXPORT_SYMBOL_GPL(agp_register_driver);
int agp_unregister_driver(struct agp_driver *drv)
{
......@@ -279,6 +298,7 @@ int agp_unregister_driver(struct agp_driver *drv)
module_put(drv->owner);
return 0;
}
EXPORT_SYMBOL_GPL(agp_unregister_driver);
int __init agp_init(void)
......@@ -298,6 +318,7 @@ int __init agp_init(void)
return 0;
}
void __exit agp_exit(void)
{
if (agp_count!=0)
......@@ -309,10 +330,5 @@ module_init(agp_init);
module_exit(agp_exit);
#endif
EXPORT_SYMBOL(agp_backend_acquire);
EXPORT_SYMBOL(agp_backend_release);
EXPORT_SYMBOL_GPL(agp_register_driver);
EXPORT_SYMBOL_GPL(agp_unregister_driver);
MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
MODULE_LICENSE("GPL and additional rights");
drivers/char/agp/frontend.c
View file @ 2836f684
......@@ -586,7 +586,7 @@ static int agp_mmap(struct file *file, struct vm_area_struct *vma)
agp_file_private *priv = (agp_file_private *) file->private_data;
agp_kern_info kerninfo;
AGP_LOCK();
down(&(agp_fe.agp_mutex));
if (agp_fe.backend_acquired != TRUE)
goto out_eperm;
......@@ -619,7 +619,7 @@ static int agp_mmap(struct file *file, struct vm_area_struct *vma)
size, vma->vm_page_prot)) {
goto out_again;
}
AGP_UNLOCK();
up(&(agp_fe.agp_mutex));
return 0;
}
......@@ -634,20 +634,20 @@ static int agp_mmap(struct file *file, struct vm_area_struct *vma)
size, vma->vm_page_prot)) {
goto out_again;
}
AGP_UNLOCK();
up(&(agp_fe.agp_mutex));
return 0;
}
out_eperm:
AGP_UNLOCK();
up(&(agp_fe.agp_mutex));
return -EPERM;
out_inval:
AGP_UNLOCK();
up(&(agp_fe.agp_mutex));
return -EINVAL;
out_again:
AGP_UNLOCK();
up(&(agp_fe.agp_mutex));
return -EAGAIN;
}
......@@ -655,7 +655,7 @@ static int agp_release(struct inode *inode, struct file *file)
{
agp_file_private *priv = (agp_file_private *) file->private_data;
AGP_LOCK();
down(&(agp_fe.agp_mutex));
if (test_bit(AGP_FF_IS_CONTROLLER, &priv->access_flags)) {
agp_controller *controller;
......@@ -675,7 +675,7 @@ static int agp_release(struct inode *inode, struct file *file)
}
agp_remove_file_private(priv);
kfree(priv);
AGP_UNLOCK();
up(&(agp_fe.agp_mutex));
return 0;
}
......@@ -686,7 +686,7 @@ static int agp_open(struct inode *inode, struct file *file)
agp_client *client;
int rc = -ENXIO;
AGP_LOCK();
down(&(agp_fe.agp_mutex));
if (minor != AGPGART_MINOR)
goto err_out;
......@@ -711,13 +711,13 @@ static int agp_open(struct inode *inode, struct file *file)
}
file->private_data = (void *) priv;
agp_insert_file_private(priv);
AGP_UNLOCK();
up(&(agp_fe.agp_mutex));
return 0;
err_out_nomem:
rc = -ENOMEM;
err_out:
AGP_UNLOCK();
up(&(agp_fe.agp_mutex));
return rc;
}
......@@ -965,7 +965,7 @@ static int agp_ioctl(struct inode *inode, struct file *file,
agp_file_private *curr_priv = (agp_file_private *) file->private_data;
int ret_val = -ENOTTY;
AGP_LOCK();
down(&(agp_fe.agp_mutex));
if ((agp_fe.current_controller == NULL) &&
(cmd != AGPIOC_ACQUIRE)) {
......@@ -1034,7 +1034,7 @@ static int agp_ioctl(struct inode *inode, struct file *file,
}
ioctl_out:
AGP_UNLOCK();
up(&(agp_fe.agp_mutex));
return ret_val;
}
......@@ -1060,7 +1060,7 @@ static struct miscdevice agp_miscdev =
int agp_frontend_initialize(void)
{
memset(&agp_fe, 0, sizeof(struct agp_front_data));
AGP_LOCK_INIT();
sema_init(&(agp_fe.agp_mutex), 1);
if (misc_register(&agp_miscdev)) {
printk(KERN_ERR PFX "unable to get minor: %d\n", AGPGART_MINOR);
......
drivers/char/agp/generic-3.0.c
View file @ 2836f684
......@@ -18,7 +18,7 @@ struct agp_3_0_dev {
struct pci_dev *dev;
};
static int agp_3_0_dev_list_insert(struct list_head *head, struct list_head *new)
static void agp_3_0_dev_list_insert(struct list_head *head, struct list_head *new)
{
struct agp_3_0_dev *cur, *n = list_entry(new, struct agp_3_0_dev, list);
struct list_head *pos;
......@@ -29,11 +29,9 @@ static int agp_3_0_dev_list_insert(struct list_head *head, struct list_head *new
break;
}
list_add_tail(new, pos);
return 0;
}
static int agp_3_0_dev_list_sort(struct agp_3_0_dev *list, unsigned int ndevs)
static void agp_3_0_dev_list_sort(struct agp_3_0_dev *list, unsigned int ndevs)
{
struct agp_3_0_dev *cur;
struct pci_dev *dev;
......@@ -53,7 +51,6 @@ static int agp_3_0_dev_list_sort(struct agp_3_0_dev *list, unsigned int ndevs)
pos = pos->next;
agp_3_0_dev_list_insert(head, tmp);
}
return 0;
}
/*
......@@ -114,11 +111,10 @@ static int agp_3_0_isochronous_node_enable(struct agp_3_0_dev *dev_list, unsigne
* transfers are enabled and consequently whether maxbw will mean
* anything.
*/
if((ret = agp_3_0_dev_list_sort(dev_list, ndevs)) != 0)
goto free_and_exit;
agp_3_0_dev_list_sort(dev_list, ndevs);
pci_read_config_dword(td, agp_bridge->capndx + 0x0c, &tnistat);
pci_read_config_dword(td, agp_bridge->capndx + 0x04, &tstatus);
pci_read_config_dword(td, agp_bridge->capndx+AGPSTAT, &tstatus);
/* Extract power-on defaults from the target */
target.maxbw = (tnistat >> 16) & 0xff;
......@@ -260,7 +256,7 @@ static int agp_3_0_isochronous_node_enable(struct agp_3_0_dev *dev_list, unsigne
? (rem_async + rem_isoch) : step;
pci_read_config_word(dev, cur->capndx + 0x20, &mnicmd);
pci_read_config_dword(dev, cur->capndx + 0x08, &mcmd);
pci_read_config_dword(dev, cur->capndx+AGPCMD, &mcmd);
mnicmd &= ~(0xff << 8);
mnicmd &= ~(0x3 << 6);
......@@ -270,7 +266,7 @@ static int agp_3_0_isochronous_node_enable(struct agp_3_0_dev *dev_list, unsigne
mnicmd |= master[cdev].y << 6;
mcmd |= master[cdev].rq << 24;
pci_write_config_dword(dev, cur->capndx + 0x08, mcmd);
pci_write_config_dword(dev, cur->capndx+AGPCMD, mcmd);
pci_write_config_word(dev, cur->capndx + 0x20, mnicmd);
}
......@@ -288,7 +284,7 @@ static int agp_3_0_isochronous_node_enable(struct agp_3_0_dev *dev_list, unsigne
* target by ndevs. Distribute this many slots to each AGP 3.0 device,
* giving any left over slots to the last device in dev_list.
*/
static int agp_3_0_nonisochronous_node_enable(struct agp_3_0_dev *dev_list, unsigned int ndevs)
static void agp_3_0_nonisochronous_node_enable(struct agp_3_0_dev *dev_list, unsigned int ndevs)
{
struct agp_3_0_dev *cur;
struct list_head *head = &dev_list->list, *pos;
......@@ -306,13 +302,11 @@ static int agp_3_0_nonisochronous_node_enable(struct agp_3_0_dev *dev_list, unsi
for(pos = head->next; cdev < ndevs; cdev++, pos = pos->next) {
cur = list_entry(pos, struct agp_3_0_dev, list);
pci_read_config_dword(cur->dev, cur->capndx + 0x08, &mcmd);
pci_read_config_dword(cur->dev, cur->capndx+AGPCMD, &mcmd);
mcmd &= ~(0xff << 24);
mcmd |= ((cdev == ndevs - 1) ? rem : mrq) << 24;
pci_write_config_dword(cur->dev, cur->capndx + 0x08, mcmd);
pci_write_config_dword(cur->dev, cur->capndx+AGPCMD, mcmd);
}
return 0;
}
/*
......@@ -345,12 +339,22 @@ int agp_3_0_node_enable(u32 mode, u32 minor)
/* Find all AGP devices, and add them to dev_list. */
pci_for_each_dev(dev) {
mcapndx = pci_find_capability(dev, PCI_CAP_ID_AGP);
switch ((dev->class >>8) & 0xff00) {
case 0x0600: /* Bridge */
/* Skip bridges. We should call this function for each one. */
continue;
case 0x0001: /* Unclassified device */
/* Don't know what this is, but log it for investigation. */
if (mcapndx != 0) {
printk (KERN_INFO PFX "Wacky, found unclassified AGP device. %x:%x\n",
dev->vendor, dev->device);
}
continue;
case 0x0300: /* Display controller */
case 0x0400: /* Multimedia controller */
case 0x0600: /* Bridge */
mcapndx = pci_find_capability(dev, PCI_CAP_ID_AGP);
if (mcapndx == 0)
continue;
......@@ -409,8 +413,8 @@ int agp_3_0_node_enable(u32 mode, u32 minor)
goto free_and_exit;
}
mmajor = (ncapid >> 20) & 0xf;
mminor = (ncapid >> 16) & 0xf;
mmajor = (ncapid >> AGP_MAJOR_VERSION_SHIFT) & 0xf;
mminor = (ncapid >> AGP_MINOR_VERSION_SHIFT) & 0xf;
if(mmajor < 3) {
printk(KERN_ERR PFX "woah! AGP 2.0 device "
......@@ -464,11 +468,13 @@ int agp_3_0_node_enable(u32 mode, u32 minor)
* whether isochronous transfers are supported.
*/
if(isoch != 0) {
if((ret = agp_3_0_isochronous_node_enable(dev_list, ndevs)) != 0)
goto free_and_exit;
if((ret = agp_3_0_isochronous_node_enable(dev_list, ndevs)) != 0) {
printk (KERN_INFO PFX "Something bad happened setting up isochronous xfers. "
"Falling back to non-isochronous xfer mode.\n");
agp_3_0_nonisochronous_node_enable(dev_list,ndevs);
}
} else {
if((ret = agp_3_0_nonisochronous_node_enable(dev_list,ndevs)) != 0)
goto free_and_exit;
agp_3_0_nonisochronous_node_enable(dev_list,ndevs);
}
/*
......@@ -477,7 +483,7 @@ int agp_3_0_node_enable(u32 mode, u32 minor)
* Also set the AGP_ENABLE bit, effectively 'turning on' the
* target (this has to be done _before_ turning on the masters).
*/
pci_read_config_dword(td, agp_bridge->capndx + 0x08, &tcmd);
pci_read_config_dword(td, agp_bridge->capndx+AGPCMD, &tcmd);
tcmd &= ~(0x7 << 10);
tcmd &= ~0x7;
......@@ -486,7 +492,7 @@ int agp_3_0_node_enable(u32 mode, u32 minor)
tcmd |= 0x1 << 8;
tcmd |= rate;
pci_write_config_dword(td, agp_bridge->capndx + 0x08, tcmd);
pci_write_config_dword(td, agp_bridge->capndx+AGPCMD, tcmd);
/*
* Set the target's advertised arqsz value, the minimum supported
......@@ -499,16 +505,16 @@ int agp_3_0_node_enable(u32 mode, u32 minor)
mcapndx = cur->capndx;
pci_read_config_dword(dev, cur->capndx + 0x08, &mcmd);
pci_read_config_dword(dev, cur->capndx+AGPCMD, &mcmd);
mcmd &= ~(0x7 << 13);
mcmd &= ~(0x7 << AGPSTAT_ARQSZ_SHIFT);
mcmd &= ~0x7;
mcmd |= arqsz << 13;
mcmd |= 0x1 << 8;
mcmd |= AGPSTAT_AGP_ENABLE;
mcmd |= rate;
pci_write_config_dword(dev, cur->capndx + 0x08, mcmd);
pci_write_config_dword(dev, cur->capndx+AGPCMD, mcmd);
}
free_and_exit:
......
drivers/char/agp/generic.c
View file @ 2836f684
This diff is collapsed.
drivers/char/agp/hp-agp.c
View file @ 2836f684
......@@ -285,7 +285,7 @@ static int hp_zx1_insert_memory(agp_memory * mem, off_t pg_start, int type)
}
if (mem->is_flushed == FALSE) {
CACHE_FLUSH();
global_cache_flush();
mem->is_flushed = TRUE;
}
......@@ -328,58 +328,54 @@ static unsigned long hp_zx1_mask_memory(unsigned long addr, int type)
return HP_ZX1_PDIR_VALID_BIT | addr;
}
static int __init hp_zx1_setup (struct pci_dev *pdev __attribute__((unused)))
{
agp_bridge->masks = hp_zx1_masks;
agp_bridge->dev_private_data = NULL;
agp_bridge->size_type = FIXED_APER_SIZE;
agp_bridge->needs_scratch_page = FALSE;
agp_bridge->configure = hp_zx1_configure;
agp_bridge->fetch_size = hp_zx1_fetch_size;
agp_bridge->cleanup = hp_zx1_cleanup;
agp_bridge->tlb_flush = hp_zx1_tlbflush;
agp_bridge->mask_memory = hp_zx1_mask_memory;
agp_bridge->agp_enable = agp_generic_enable;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = hp_zx1_create_gatt_table;
agp_bridge->free_gatt_table = hp_zx1_free_gatt_table;
agp_bridge->insert_memory = hp_zx1_insert_memory;
agp_bridge->remove_memory = hp_zx1_remove_memory;
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
agp_bridge->cant_use_aperture = 1;
return hp_zx1_ioc_init();
}
struct agp_bridge_data hp_zx1_bridge = {
.type = HP_ZX1,
.masks = hp_zx1_masks,
.size_type = FIXED_APER_SIZE,
.configure = hp_zx1_configure,
.fetch_size = hp_zx1_fetch_size,
.cleanup = hp_zx1_cleanup,
.tlb_flush = hp_zx1_tlbflush,
.mask_memory = hp_zx1_mask_memory,
.agp_enable = agp_generic_enable,
.cache_flush = global_cache_flush,
.create_gatt_table = hp_zx1_create_gatt_table,
.free_gatt_table = hp_zx1_free_gatt_table,
.insert_memory = hp_zx1_insert_memory,
.remove_memory = hp_zx1_remove_memory,
.alloc_by_type = agp_generic_alloc_by_type,
.free_by_type = agp_generic_free_by_type,
.agp_alloc_page = agp_generic_alloc_page,
.agp_destroy_page = agp_generic_destroy_page,
.cant_use_aperture = 1,
};
static int __init agp_find_supported_device(struct pci_dev *dev)
static struct agp_driver hp_agp_driver = {
.owner = THIS_MODULE,
};
static int __init agp_hp_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
agp_bridge->dev = dev;
int error;
/* ZX1 LBAs can be either PCI or AGP bridges */
if (pci_find_capability(dev, PCI_CAP_ID_AGP)) {
printk(KERN_INFO PFX "Detected HP ZX1 AGP chipset at %s\n",
dev->slot_name);
agp_bridge->type = HP_ZX1;
agp_bridge->dev = dev;
return hp_zx1_setup(dev);
}
if (!pci_find_capability(pdev, PCI_CAP_ID_AGP))
return -ENODEV;
}
static struct agp_driver hp_agp_driver = {
.owner = THIS_MODULE,
};
printk(KERN_INFO PFX "Detected HP ZX1 AGP chipset at %s\n",
pdev->slot_name);
static int __init agp_hp_probe (struct pci_dev *dev, const struct pci_device_id *ent)
{
if (agp_find_supported_device(dev) == 0) {
hp_agp_driver.dev = dev;
error = hp_zx1_ioc_init();
if (error)
return error;
hp_zx1_bridge.dev = pdev;
memcpy(agp_bridge, &hp_zx1_bridge, sizeof(struct agp_bridge_data));
hp_agp_driver.dev = pdev;
agp_register_driver(&hp_agp_driver);
return 0;
}
return -ENODEV;
}
static struct pci_device_id agp_hp_pci_table[] __initdata = {
......@@ -404,13 +400,7 @@ static struct __initdata pci_driver agp_hp_pci_driver = {
static int __init agp_hp_init(void)
{
int ret_val;
ret_val = pci_module_init(&agp_hp_pci_driver);
if (ret_val)
agp_bridge->type = NOT_SUPPORTED;
return ret_val;
return pci_module_init(&agp_hp_pci_driver);
}
static void __exit agp_hp_cleanup(void)
......
drivers/char/agp/i460-agp.c
View file @ 2836f684
......@@ -294,7 +294,7 @@ static int i460_insert_memory_small_io_page (agp_memory *mem, off_t pg_start, in
j = io_pg_start;
while (j < (io_pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count)) {
if (!PGE_EMPTY(RD_GATT(j))) {
if (!PGE_EMPTY(agp_bridge, RD_GATT(j))) {
pr_debug("i460_insert_memory_small_io_page: GATT[%d]=0x%x is busy\n",
j, RD_GATT(j));
return -EBUSY;
......@@ -523,58 +523,57 @@ static unsigned long i460_mask_memory (unsigned long addr, int type)
| (((addr & ~((1 << I460_IO_PAGE_SHIFT) - 1)) & 0xffffff000) >> 12));
}
static int __init intel_i460_setup (struct pci_dev *pdev __attribute__((unused)))
{
agp_bridge->masks = i460_masks;
agp_bridge->aperture_sizes = (void *) i460_sizes;
agp_bridge->size_type = U8_APER_SIZE;
agp_bridge->num_aperture_sizes = 3;
agp_bridge->dev_private_data = NULL;
agp_bridge->needs_scratch_page = FALSE;
agp_bridge->configure = i460_configure;
agp_bridge->fetch_size = i460_fetch_size;
agp_bridge->cleanup = i460_cleanup;
agp_bridge->tlb_flush = i460_tlb_flush;
agp_bridge->mask_memory = i460_mask_memory;
agp_bridge->agp_enable = agp_generic_enable;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = i460_create_gatt_table;
agp_bridge->free_gatt_table = i460_free_gatt_table;
struct agp_bridge_data intel_i460_bridge = {
.masks = i460_masks,
.aperture_sizes = (void *)i460_sizes,
.size_type = U8_APER_SIZE,
.num_aperture_sizes = 3,
.configure = i460_configure,
.fetch_size = i460_fetch_size,
.cleanup = i460_cleanup,
.tlb_flush = i460_tlb_flush,
.mask_memory = i460_mask_memory,
.agp_enable = agp_generic_enable,
.cache_flush = global_cache_flush,
.create_gatt_table = i460_create_gatt_table,
.free_gatt_table = i460_free_gatt_table,
#if I460_LARGE_IO_PAGES
agp_bridge->insert_memory = i460_insert_memory;
agp_bridge->remove_memory = i460_remove_memory;
agp_bridge->agp_alloc_page = i460_alloc_page;
agp_bridge->agp_destroy_page = i460_destroy_page;
.insert_memory = i460_insert_memory,
.remove_memory = i460_remove_memory,
.agp_alloc_page = i460_alloc_page,
.agp_destroy_page = i460_destroy_page,
#else
agp_bridge->insert_memory = i460_insert_memory_small_io_page;
agp_bridge->remove_memory = i460_remove_memory_small_io_page;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
.insert_memory = i460_insert_memory_small_io_page,
.remove_memory = i460_remove_memory_small_io_page,
.agp_alloc_page = agp_generic_alloc_page,
.agp_destroy_page = agp_generic_destroy_page,
#endif
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->suspend = agp_generic_suspend;
agp_bridge->resume = agp_generic_resume;
agp_bridge->cant_use_aperture = 1;
return 0;
}
.alloc_by_type = agp_generic_alloc_by_type,
.free_by_type = agp_generic_free_by_type,
.suspend = agp_generic_suspend,
.resume = agp_generic_resume,
.cant_use_aperture = 1,
};
static struct agp_driver i460_agp_driver = {
.owner = THIS_MODULE,
};
static int __init agp_intel_i460_probe (struct pci_dev *dev, const struct pci_device_id *ent)
static int __init agp_intel_i460_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
u8 cap_ptr = 0;
u8 cap_ptr;
cap_ptr = pci_find_capability(dev, PCI_CAP_ID_AGP);
if (cap_ptr == 0)
cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
if (!cap_ptr)
return -ENODEV;
agp_bridge->dev = dev;
agp_bridge->capndx = cap_ptr;
intel_i460_setup(dev);
i460_agp_driver.dev = dev;
intel_i460_bridge.dev = pdev;
intel_i460_bridge.capndx = cap_ptr;
memcpy(agp_bridge, &intel_i460_bridge, sizeof(struct agp_bridge_data));
i460_agp_driver.dev = pdev;
agp_register_driver(&i460_agp_driver);
return 0;
}
......@@ -601,13 +600,7 @@ static struct __initdata pci_driver agp_intel_i460_pci_driver = {
static int __init agp_intel_i460_init(void)
{
int ret_val;
ret_val = pci_module_init(&agp_intel_i460_pci_driver);
if (ret_val)
agp_bridge->type = NOT_SUPPORTED;
return ret_val;
return pci_module_init(&agp_intel_i460_pci_driver);
}
static void __exit agp_intel_i460_cleanup(void)
......
drivers/char/agp/intel-agp.c
View file @ 2836f684
This diff is collapsed.
drivers/char/agp/nvidia-agp.c 0 → 100644
View file @ 2836f684
This diff is collapsed.
drivers/char/agp/sis-agp.c
View file @ 2836f684
......@@ -86,164 +86,136 @@ static struct gatt_mask sis_generic_masks[] =
{.mask = 0x00000000, .type = 0}
};
static int __init sis_generic_setup (struct pci_dev *pdev)
{
agp_bridge->masks = sis_generic_masks;
agp_bridge->aperture_sizes = (void *) sis_generic_sizes;
agp_bridge->size_type = U8_APER_SIZE;
agp_bridge->num_aperture_sizes = 7;
agp_bridge->dev_private_data = NULL;
agp_bridge->needs_scratch_page = FALSE;
agp_bridge->configure = sis_configure;
agp_bridge->fetch_size = sis_fetch_size;
agp_bridge->cleanup = sis_cleanup;
agp_bridge->tlb_flush = sis_tlbflush;
agp_bridge->mask_memory = sis_mask_memory;
agp_bridge->agp_enable = agp_generic_enable;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
agp_bridge->insert_memory = agp_generic_insert_memory;
agp_bridge->remove_memory = agp_generic_remove_memory;
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
agp_bridge->suspend = agp_generic_suspend;
agp_bridge->resume = agp_generic_resume;
agp_bridge->cant_use_aperture = 0;
return 0;
}
struct agp_bridge_data sis_generic_bridge = {
.type = SIS_GENERIC,
.masks = sis_generic_masks,
.aperture_sizes = (void *)sis_generic_sizes,
.size_type = U8_APER_SIZE,
.num_aperture_sizes = 7,
.configure = sis_configure,
.fetch_size = sis_fetch_size,
.cleanup = sis_cleanup,
.tlb_flush = sis_tlbflush,
.mask_memory = sis_mask_memory,
.agp_enable = agp_generic_enable,
.cache_flush = global_cache_flush,
.create_gatt_table = agp_generic_create_gatt_table,
.free_gatt_table = agp_generic_free_gatt_table,
.insert_memory = agp_generic_insert_memory,
.remove_memory = agp_generic_remove_memory,
.alloc_by_type = agp_generic_alloc_by_type,
.free_by_type = agp_generic_free_by_type,
.agp_alloc_page = agp_generic_alloc_page,
.agp_destroy_page = agp_generic_destroy_page,
.suspend = agp_generic_suspend,
.resume = agp_generic_resume,
};
struct agp_device_ids sis_agp_device_ids[] __initdata =
{
{
.device_id = PCI_DEVICE_ID_SI_740,
.chipset = SIS_GENERIC,
.chipset_name = "740",
},
{
.device_id = PCI_DEVICE_ID_SI_650,
.chipset = SIS_GENERIC,
.chipset_name = "650",
},
{
.device_id = PCI_DEVICE_ID_SI_651,
.chipset = SIS_GENERIC,
.chipset_name = "651",
},
{
.device_id = PCI_DEVICE_ID_SI_645,
.chipset = SIS_GENERIC,
.chipset_name = "645",
},
{
.device_id = PCI_DEVICE_ID_SI_646,
.chipset = SIS_GENERIC,
.chipset_name = "646",
},
{
.device_id = PCI_DEVICE_ID_SI_735,
.chipset = SIS_GENERIC,
.chipset_name = "735",
},
{
.device_id = PCI_DEVICE_ID_SI_745,
.chipset = SIS_GENERIC,
.chipset_name = "745",
},
{
.device_id = PCI_DEVICE_ID_SI_730,
.chipset = SIS_GENERIC,
.chipset_name = "730",
},
{
.device_id = PCI_DEVICE_ID_SI_630,
.chipset = SIS_GENERIC,
.chipset_name = "630",
},
{
.device_id = PCI_DEVICE_ID_SI_540,
.chipset = SIS_GENERIC,
.chipset_name = "540",
},
{
.device_id = PCI_DEVICE_ID_SI_620,
.chipset = SIS_GENERIC,
.chipset_name = "620",
},
{
.device_id = PCI_DEVICE_ID_SI_530,
.chipset = SIS_GENERIC,
.chipset_name = "530",
},
{
.device_id = PCI_DEVICE_ID_SI_550,
.chipset = SIS_GENERIC,
.chipset_name = "550",
},
{ }, /* dummy final entry, always present */
};
/* scan table above for supported devices */
static int __init agp_lookup_host_bridge (struct pci_dev *pdev)
static struct agp_driver sis_agp_driver = {
.owner = THIS_MODULE,
};
static int __init agp_sis_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
int j=0;
struct agp_device_ids *devs;
struct agp_device_ids *devs = sis_agp_device_ids;
u8 cap_ptr;
int j;
devs = sis_agp_device_ids;
cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
if (!cap_ptr)
return -ENODEV;
while (devs[j].chipset_name != NULL) {
/* probe for known chipsets */
for (j = 0; devs[j].chipset_name; j++) {
if (pdev->device == devs[j].device_id) {
printk (KERN_INFO PFX "Detected SiS %s chipset\n",
printk(KERN_INFO PFX "Detected SiS %s chipset\n",
devs[j].chipset_name);
agp_bridge->type = devs[j].chipset;
if (devs[j].chipset_setup != NULL)
return devs[j].chipset_setup(pdev);
else
return sis_generic_setup(pdev);
goto found;
}
j++;
}
/* try init anyway, if user requests it */
if (agp_try_unsupported) {
printk(KERN_WARNING PFX "Trying generic SiS routines"
" for device id: %04x\n", pdev->device);
agp_bridge->type = SIS_GENERIC;
return sis_generic_setup(pdev);
}
printk(KERN_ERR PFX "Unsupported SiS chipset (device id: %04x),"
" you might want to try agp_try_unsupported=1.\n", pdev->device);
if (!agp_try_unsupported) {
printk(KERN_ERR PFX
"Unsupported SiS chipset (device id: %04x),"
" you might want to try agp_try_unsupported=1.\n",
pdev->device);
return -ENODEV;
}
static struct agp_driver sis_agp_driver = {
.owner = THIS_MODULE,
};
}
static int __init agp_sis_probe (struct pci_dev *dev, const struct pci_device_id *ent)
{
u8 cap_ptr = 0;
printk(KERN_WARNING PFX "Trying generic SiS routines"
" for device id: %04x\n", pdev->device);
cap_ptr = pci_find_capability(dev, PCI_CAP_ID_AGP);
if (cap_ptr == 0)
return -ENODEV;
found:
sis_generic_bridge.dev = pdev;
sis_generic_bridge.capndx = cap_ptr;
/* probe for known chipsets */
if (agp_lookup_host_bridge(dev) != -ENODEV) {
agp_bridge->dev = dev;
agp_bridge->capndx = cap_ptr;
/* Fill in the mode register */
pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
sis_agp_driver.dev = dev;
pci_read_config_dword(pdev, sis_generic_bridge.capndx+PCI_AGP_STATUS,
&sis_generic_bridge.mode);
memcpy(agp_bridge, &sis_generic_bridge,
sizeof(struct agp_bridge_data));
sis_agp_driver.dev = pdev;
agp_register_driver(&sis_agp_driver);
return 0;
}
return -ENODEV;
}
static struct pci_device_id agp_sis_pci_table[] __initdata = {
......@@ -268,13 +240,7 @@ static struct __initdata pci_driver agp_sis_pci_driver = {
static int __init agp_sis_init(void)
{
int ret_val;
ret_val = pci_module_init(&agp_sis_pci_driver);
if (ret_val)
agp_bridge->type = NOT_SUPPORTED;
return ret_val;
return pci_module_init(&agp_sis_pci_driver);
}
static void __exit agp_sis_cleanup(void)
......
drivers/char/agp/sworks-agp.c
View file @ 2836f684
......@@ -35,7 +35,7 @@ static int serverworks_create_page_map(struct serverworks_page_map *page_map)
return -ENOMEM;
}
SetPageReserved(virt_to_page(page_map->real));
CACHE_FLUSH();
global_cache_flush();
page_map->remapped = ioremap_nocache(virt_to_phys(page_map->real),
PAGE_SIZE);
if (page_map->remapped == NULL) {
......@@ -44,7 +44,7 @@ static int serverworks_create_page_map(struct serverworks_page_map *page_map)
page_map->real = NULL;
return -ENOMEM;
}
CACHE_FLUSH();
global_cache_flush();
for(i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) {
page_map->remapped[i] = agp_bridge->scratch_page;
......@@ -336,14 +336,14 @@ static int serverworks_insert_memory(agp_memory * mem,
while (j < (pg_start + mem->page_count)) {
addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
cur_gatt = SVRWRKS_GET_GATT(addr);
if (!PGE_EMPTY(cur_gatt[GET_GATT_OFF(addr)])) {
if (!PGE_EMPTY(agp_bridge, cur_gatt[GET_GATT_OFF(addr)])) {
return -EBUSY;
}
j++;
}
if (mem->is_flushed == FALSE) {
CACHE_FLUSH();
global_cache_flush();
mem->is_flushed = TRUE;
}
......@@ -368,7 +368,7 @@ static int serverworks_remove_memory(agp_memory * mem, off_t pg_start,
return -EINVAL;
}
CACHE_FLUSH();
global_cache_flush();
agp_bridge->tlb_flush(mem);
for (i = pg_start; i < (mem->page_count + pg_start); i++) {
......@@ -420,123 +420,95 @@ static void serverworks_agp_enable(u32 mode)
agp_device_command(command, 0);
}
static int __init serverworks_setup (struct pci_dev *pdev)
{
u32 temp;
u32 temp2;
serverworks_private.svrwrks_dev = pdev;
agp_bridge->masks = serverworks_masks;
agp_bridge->aperture_sizes = (void *) serverworks_sizes;
agp_bridge->size_type = LVL2_APER_SIZE;
agp_bridge->num_aperture_sizes = 7;
agp_bridge->dev_private_data = (void *) &serverworks_private;
agp_bridge->needs_scratch_page = TRUE;
agp_bridge->configure = serverworks_configure;
agp_bridge->fetch_size = serverworks_fetch_size;
agp_bridge->cleanup = serverworks_cleanup;
agp_bridge->tlb_flush = serverworks_tlbflush;
agp_bridge->mask_memory = serverworks_mask_memory;
agp_bridge->agp_enable = serverworks_agp_enable;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = serverworks_create_gatt_table;
agp_bridge->free_gatt_table = serverworks_free_gatt_table;
agp_bridge->insert_memory = serverworks_insert_memory;
agp_bridge->remove_memory = serverworks_remove_memory;
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
agp_bridge->suspend = agp_generic_suspend;
agp_bridge->resume = agp_generic_resume;
agp_bridge->cant_use_aperture = 0;
pci_read_config_dword(agp_bridge->dev,
SVWRKS_APSIZE,
&temp);
serverworks_private.gart_addr_ofs = 0x10;
if(temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
pci_read_config_dword(agp_bridge->dev,
SVWRKS_APSIZE + 4,
&temp2);
if(temp2 != 0) {
printk("Detected 64 bit aperture address, but top "
"bits are not zero. Disabling agp\n");
return -ENODEV;
}
serverworks_private.mm_addr_ofs = 0x18;
} else {
serverworks_private.mm_addr_ofs = 0x14;
}
pci_read_config_dword(agp_bridge->dev,
serverworks_private.mm_addr_ofs,
&temp);
if(temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
pci_read_config_dword(agp_bridge->dev,
serverworks_private.mm_addr_ofs + 4,
&temp2);
if(temp2 != 0) {
printk("Detected 64 bit MMIO address, but top "
"bits are not zero. Disabling agp\n");
return -ENODEV;
}
}
return 0;
}
struct agp_bridge_data sworks_bridge = {
.type = SVWRKS_GENERIC,
.masks = serverworks_masks,
.aperture_sizes = (void *)serverworks_sizes,
.size_type = LVL2_APER_SIZE,
.num_aperture_sizes = 7,
.dev_private_data = &serverworks_private,
.configure = serverworks_configure,
.fetch_size = serverworks_fetch_size,
.cleanup = serverworks_cleanup,
.tlb_flush = serverworks_tlbflush,
.mask_memory = serverworks_mask_memory,
.agp_enable = serverworks_agp_enable,
.cache_flush = global_cache_flush,
.create_gatt_table = serverworks_create_gatt_table,
.free_gatt_table = serverworks_free_gatt_table,
.insert_memory = serverworks_insert_memory,
.remove_memory = serverworks_remove_memory,
.alloc_by_type = agp_generic_alloc_by_type,
.free_by_type = agp_generic_free_by_type,
.agp_alloc_page = agp_generic_alloc_page,
.agp_destroy_page = agp_generic_destroy_page,
.suspend = agp_generic_suspend,
.resume = agp_generic_resume,
};
static struct agp_driver serverworks_agp_driver = {
.owner = THIS_MODULE,
};
static int __init agp_find_supported_device(struct pci_dev *dev)
static int __init agp_serverworks_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
struct pci_dev *bridge_dev;
u32 temp, temp2;
/* Everything is on func 1 here so we are hardcoding function one */
bridge_dev = pci_find_slot ((unsigned int)dev->bus->number, PCI_DEVFN(0, 1));
if(bridge_dev == NULL) {
bridge_dev = pci_find_slot((unsigned int)pdev->bus->number,
PCI_DEVFN(0, 1));
if (!bridge_dev) {
printk(KERN_INFO PFX "agpgart: Detected a Serverworks "
"Chipset, but could not find the secondary "
"device.\n");
return -ENODEV;
}
agp_bridge->dev = dev;
sworks_bridge.dev = pdev;
switch (dev->device) {
switch (pdev->device) {
case PCI_DEVICE_ID_SERVERWORKS_HE:
agp_bridge->type = SVWRKS_HE;
return serverworks_setup(bridge_dev);
case PCI_DEVICE_ID_SERVERWORKS_LE:
case 0x0007:
agp_bridge->type = SVWRKS_LE;
return serverworks_setup(bridge_dev);
break;
default:
if(agp_try_unsupported) {
agp_bridge->type = SVWRKS_GENERIC;
return serverworks_setup(bridge_dev);
}
if (!agp_try_unsupported)
return -ENODEV;
break;
}
serverworks_private.svrwrks_dev = bridge_dev;
serverworks_private.gart_addr_ofs = 0x10;
pci_read_config_dword(pdev, SVWRKS_APSIZE, &temp);
if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
pci_read_config_dword(pdev, SVWRKS_APSIZE + 4, &temp2);
if (temp2 != 0) {
printk("Detected 64 bit aperture address, but top "
"bits are not zero. Disabling agp\n");
return -ENODEV;
}
}
serverworks_private.mm_addr_ofs = 0x18;
} else
serverworks_private.mm_addr_ofs = 0x14;
static struct agp_driver serverworks_agp_driver = {
.owner = THIS_MODULE,
};
pci_read_config_dword(pdev, serverworks_private.mm_addr_ofs, &temp);
if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
pci_read_config_dword(pdev,
serverworks_private.mm_addr_ofs + 4, &temp2);
if (temp2 != 0) {
printk("Detected 64 bit MMIO address, but top "
"bits are not zero. Disabling agp\n");
return -ENODEV;
}
}
static int __init agp_serverworks_probe (struct pci_dev *dev, const struct pci_device_id *ent)
{
if (agp_find_supported_device(dev) == 0) {
serverworks_agp_driver.dev = dev;
memcpy(agp_bridge, &sworks_bridge, sizeof(struct agp_bridge_data));
serverworks_agp_driver.dev = pdev;
agp_register_driver(&serverworks_agp_driver);
return 0;
}
return -ENODEV;
}
static struct pci_device_id agp_serverworks_pci_table[] __initdata = {
......@@ -561,13 +533,7 @@ static struct __initdata pci_driver agp_serverworks_pci_driver = {
static int __init agp_serverworks_init(void)
{
int ret_val;
ret_val = pci_module_init(&agp_serverworks_pci_driver);
if (ret_val)
agp_bridge->type = NOT_SUPPORTED;
return ret_val;
return pci_module_init(&agp_serverworks_pci_driver);
}
static void __exit agp_serverworks_cleanup(void)
......
drivers/char/agp/via-agp.c
View file @ 2836f684
......@@ -174,99 +174,55 @@ static struct aper_size_info_16 via_generic_agp3_sizes[11] =
{ 2048, 524288, 9, 1<<11} /* 2GB <- Max supported */
};
struct agp_bridge_data via_generic_agp3_bridge = {
.type = VIA_GENERIC,
.masks = via_generic_masks,
.aperture_sizes = (void *)via_generic_agp3_sizes,
.size_type = U8_APER_SIZE,
.num_aperture_sizes = 10,
.configure = via_configure_agp3,
.fetch_size = via_fetch_size_agp3,
.cleanup = via_cleanup_agp3,
.tlb_flush = via_tlbflush_agp3,
.mask_memory = via_mask_memory,
.agp_enable = agp_generic_enable,
.cache_flush = global_cache_flush,
.create_gatt_table = agp_generic_create_gatt_table,
.free_gatt_table = agp_generic_free_gatt_table,
.insert_memory = agp_generic_insert_memory,
.remove_memory = agp_generic_remove_memory,
.alloc_by_type = agp_generic_alloc_by_type,
.free_by_type = agp_generic_free_by_type,
.agp_alloc_page = agp_generic_alloc_page,
.agp_destroy_page = agp_generic_destroy_page,
.suspend = agp_generic_suspend,
.resume = agp_generic_resume,
};
static int __init via_generic_agp3_setup (struct pci_dev *pdev)
{
agp_bridge->dev = pdev;
agp_bridge->type = VIA_GENERIC;
agp_bridge->masks = via_generic_masks;
agp_bridge->aperture_sizes = (void *) via_generic_agp3_sizes;
agp_bridge->size_type = U16_APER_SIZE;
agp_bridge->num_aperture_sizes = 10;
agp_bridge->dev_private_data = NULL;
agp_bridge->needs_scratch_page = FALSE;
agp_bridge->agp_enable = agp_generic_enable;
agp_bridge->configure = via_configure_agp3;
agp_bridge->fetch_size = via_fetch_size_agp3;
agp_bridge->cleanup = via_cleanup_agp3;
agp_bridge->tlb_flush = via_tlbflush_agp3;
agp_bridge->mask_memory = via_mask_memory;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
agp_bridge->insert_memory = agp_generic_insert_memory;
agp_bridge->remove_memory = agp_generic_remove_memory;
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
agp_bridge->suspend = agp_generic_suspend;
agp_bridge->resume = agp_generic_resume;
agp_bridge->cant_use_aperture = 0;
return 0;
}
static int __init via_generic_setup (struct pci_dev *pdev)
{
/* Garg, there are KT400s with KT266 IDs. */
if (pdev->device == PCI_DEVICE_ID_VIA_8367_0) {
/* Is there a KT400 subsystem ? */
if (pdev->subsystem_device==PCI_DEVICE_ID_VIA_8377_0) {
u8 reg;
printk (KERN_INFO PFX "Found KT400 in disguise as a KT266.\n");
/* Check AGP compatibility mode. */
pci_read_config_byte(pdev, VIA_AGPSEL, &reg);
if ((reg & (1<<1))==0)
return via_generic_agp3_setup(pdev);
/* Its in 2.0 mode, drop through. */
}
}
agp_bridge->masks = via_generic_masks;
agp_bridge->aperture_sizes = (void *) via_generic_sizes;
agp_bridge->size_type = U8_APER_SIZE;
agp_bridge->num_aperture_sizes = 7;
agp_bridge->dev_private_data = NULL;
agp_bridge->needs_scratch_page = FALSE;
agp_bridge->configure = via_configure;
agp_bridge->fetch_size = via_fetch_size;
agp_bridge->cleanup = via_cleanup;
agp_bridge->tlb_flush = via_tlbflush;
agp_bridge->mask_memory = via_mask_memory;
agp_bridge->agp_enable = agp_generic_enable;
agp_bridge->cache_flush = global_cache_flush;
agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
agp_bridge->insert_memory = agp_generic_insert_memory;
agp_bridge->remove_memory = agp_generic_remove_memory;
agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
agp_bridge->free_by_type = agp_generic_free_by_type;
agp_bridge->agp_alloc_page = agp_generic_alloc_page;
agp_bridge->agp_destroy_page = agp_generic_destroy_page;
agp_bridge->suspend = agp_generic_suspend;
agp_bridge->resume = agp_generic_resume;
agp_bridge->cant_use_aperture = 0;
return 0;
}
/* The KT400 does magick to put the AGP bridge compliant with the same
* standards version as the graphics card. */
static int __init via_kt400_setup(struct pci_dev *pdev)
{
u8 reg;
pci_read_config_byte(pdev, VIA_AGPSEL, &reg);
/* Check AGP 2.0 compatibility mode. */
if ((reg & (1<<1))==0)
return via_generic_agp3_setup(pdev);
return via_generic_setup(pdev);
}
struct agp_bridge_data via_generic_bridge = {
.type = VIA_GENERIC,
.masks = via_generic_masks,
.aperture_sizes = (void *)via_generic_sizes,
.size_type = U8_APER_SIZE,
.num_aperture_sizes = 7,
.configure = via_configure,
.fetch_size = via_fetch_size,
.cleanup = via_cleanup,
.tlb_flush = via_tlbflush,
.mask_memory = via_mask_memory,
.agp_enable = agp_generic_enable,
.cache_flush = global_cache_flush,
.create_gatt_table = agp_generic_create_gatt_table,
.free_gatt_table = agp_generic_free_gatt_table,
.insert_memory = agp_generic_insert_memory,
.remove_memory = agp_generic_remove_memory,
.alloc_by_type = agp_generic_alloc_by_type,
.free_by_type = agp_generic_free_by_type,
.agp_alloc_page = agp_generic_alloc_page,
.agp_destroy_page = agp_generic_destroy_page,
.suspend = agp_generic_suspend,
.resume = agp_generic_resume,
};
static struct agp_device_ids via_agp_device_ids[] __initdata =
{
......@@ -310,7 +266,7 @@ static struct agp_device_ids via_agp_device_ids[] __initdata =
/* VT8361 */
{
.device_id = PCI_DEVICE_ID_VIA_8361, // 0x3112
.device_id = PCI_DEVICE_ID_VIA_8361,
.chipset_name = "Apollo KLE133",
},
......@@ -353,7 +309,6 @@ static struct agp_device_ids via_agp_device_ids[] __initdata =
{
.device_id = PCI_DEVICE_ID_VIA_8377_0,
.chipset_name = "Apollo Pro KT400",
.chipset_setup = via_kt400_setup,
},
/* VT8604 / VT8605 / VT8603 / TwisterT
......@@ -402,75 +357,89 @@ static struct agp_device_ids via_agp_device_ids[] __initdata =
/* P4M400 */
{
.device_id = PCI_DEVICE_ID_VIA_P4M400,
.chipset_name = "PM400",
.chipset_name = "P4M400",
},
{ }, /* dummy final entry, always present */
};
static struct agp_driver via_agp_driver = {
.owner = THIS_MODULE,
};
/* scan table above for supported devices */
static int __init agp_lookup_host_bridge (struct pci_dev *pdev)
static int __init agp_via_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
int j=0;
struct agp_device_ids *devs;
struct agp_device_ids *devs = via_agp_device_ids;
struct agp_bridge_data *bridge = &via_generic_bridge;
int j = 0;
u8 cap_ptr, reg;
devs = via_agp_device_ids;
cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
if (!cap_ptr)
return -ENODEV;
while (devs[j].chipset_name != NULL) {
/* probe for known chipsets */
for (j = 0; devs[j].chipset_name; j++) {
if (pdev->device == devs[j].device_id) {
printk (KERN_INFO PFX "Detected VIA %s chipset\n", devs[j].chipset_name);
agp_bridge->type = VIA_GENERIC;
if (devs[j].chipset_setup != NULL)
return devs[j].chipset_setup(pdev);
else
return via_generic_setup(pdev);
printk (KERN_INFO PFX "Detected VIA %s chipset\n",
devs[j].chipset_name);
goto found;
}
j++;
}
/* try init anyway, if user requests it */
if (agp_try_unsupported) {
printk(KERN_WARNING PFX "Trying generic VIA routines"
" for device id: %04x\n", pdev->device);
agp_bridge->type = VIA_GENERIC;
return via_generic_setup(pdev);
printk(KERN_ERR PFX
"Unsupported VIA chipset (device id: %04x),"
" you might want to try agp_try_unsupported=1.\n",
pdev->device);
return -ENODEV;
}
printk(KERN_ERR PFX "Unsupported VIA chipset (device id: %04x),"
" you might want to try agp_try_unsupported=1.\n", pdev->device);
return -ENODEV;
}
printk(KERN_WARNING PFX "Trying generic VIA routines"
" for device id: %04x\n", pdev->device);
found:
switch (pdev->device) {
case PCI_DEVICE_ID_VIA_8367_0:
/*
* Garg, there are KT400s with KT266 IDs.
*/
/* Is there a KT400 subsystem ? */
if (pdev->subsystem_device != PCI_DEVICE_ID_VIA_8377_0)
break;
printk(KERN_INFO PFX "Found KT400 in disguise as a KT266.\n");
/*FALLTHROUGH*/
case PCI_DEVICE_ID_VIA_8377_0:
/*
* The KT400 does magick to put the AGP bridge compliant
* with the same standards version as the graphics card.
*/
pci_read_config_byte(pdev, VIA_AGPSEL, &reg);
/* Check AGP 2.0 compatibility mode. */
if ((reg & (1<<1))==0) {
bridge = &via_generic_agp3_bridge;
break;
}
}
static struct agp_driver via_agp_driver = {
.owner = THIS_MODULE,
};
bridge->dev = pdev;
bridge->capndx = cap_ptr;
static int __init agp_via_probe (struct pci_dev *dev, const struct pci_device_id *ent)
{
u8 cap_ptr = 0;
/* Fill in the mode register */
pci_read_config_dword(pdev,
bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
cap_ptr = pci_find_capability(dev, PCI_CAP_ID_AGP);
if (cap_ptr == 0)
return -ENODEV;
memcpy(agp_bridge, bridge, sizeof(struct agp_bridge_data));
/* probe for known chipsets */
if (agp_lookup_host_bridge (dev) != -ENODEV) {
agp_bridge->dev = dev;
agp_bridge->capndx = cap_ptr;
/* Fill in the mode register */
pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
via_agp_driver.dev = dev;
via_agp_driver.dev = pdev;
agp_register_driver(&via_agp_driver);
return 0;
}
return -ENODEV;
}
static struct pci_device_id agp_via_pci_table[] __initdata = {
{
.class = (PCI_CLASS_BRIDGE_HOST << 8),
......@@ -495,13 +464,7 @@ static struct __initdata pci_driver agp_via_pci_driver = {
static int __init agp_via_init(void)
{
int ret_val;
ret_val = pci_module_init(&agp_via_pci_driver);
if (ret_val)
agp_bridge->type = NOT_SUPPORTED;
return ret_val;
return pci_module_init(&agp_via_pci_driver);
}
......
include/linux/agp_backend.h
View file @ 2836f684
/*
* AGPGART module version 0.99
* AGPGART module version 0.100
* Copyright (C) 2002-2003 Dave Jones
* Copyright (C) 1999 Jeff Hartmann
* Copyright (C) 1999 Precision Insight, Inc.
* Copyright (C) 1999 Xi Graphics, Inc.
......@@ -38,44 +39,17 @@
enum chipset_type {
NOT_SUPPORTED,
INTEL_GENERIC,
INTEL_LX,
INTEL_BX,
INTEL_GX,
INTEL_I810,
INTEL_I815,
INTEL_I820,
INTEL_I830_M,
INTEL_I845_G,
INTEL_I855_PM,
INTEL_I865_G,
INTEL_I840,
INTEL_I845,
INTEL_I850,
INTEL_I860,
INTEL_460GX,
INTEL_E7505,
VIA_GENERIC,
SIS_GENERIC,
AMD_GENERIC,
AMD_IRONGATE,
AMD_761,
AMD_762,
AMD_8151,
ALI_M1541,
ALI_M1621,
ALI_M1631,
ALI_M1632,
ALI_M1641,
ALI_M1644,
ALI_M1647,
ALI_M1651,
ALI_M1671,
ALI_GENERIC,
SVWRKS_HE,
SVWRKS_LE,
SVWRKS_GENERIC,
HP_ZX1,
ALPHA_CORE_AGP,
NVIDIA_GENERIC,
NVIDIA_NFORCE,
NVIDIA_NFORCE2,
};
struct agp_version {
......@@ -98,16 +72,11 @@ typedef struct _agp_kern_info {
} agp_kern_info;
/*
* The agp_memory structure has information
* about the block of agp memory allocated.
* A caller may manipulate the next and prev
* pointers to link each allocated item into
* a list. These pointers are ignored by the
* backend. Everything else should never be
* written to, but the caller may read any of
* the items to detrimine the status of this
* block of agp memory.
*
* The agp_memory structure has information about the block of agp memory
* allocated. A caller may manipulate the next and prev pointers to link
* each allocated item into a list. These pointers are ignored by the backend.
* Everything else should never be written to, but the caller may read any of
* the items to detrimine the status of this block of agp memory.
*/
typedef struct _agp_memory {
......@@ -127,126 +96,19 @@ typedef struct _agp_memory {
#define AGP_NORMAL_MEMORY 0
extern void agp_free_memory(agp_memory *);
/*
* agp_free_memory :
*
* This function frees memory associated with
* an agp_memory pointer. It is the only function
* that can be called when the backend is not owned
* by the caller. (So it can free memory on client
* death.)
*
* It takes an agp_memory pointer as an argument.
*
*/
extern agp_memory *agp_allocate_memory(size_t, u32);
/*
* agp_allocate_memory :
*
* This function allocates a group of pages of
* a certain type.
*
* It takes a size_t argument of the number of pages, and
* an u32 argument of the type of memory to be allocated.
* Every agp bridge device will allow you to allocate
* AGP_NORMAL_MEMORY which maps to physical ram. Any other
* type is device dependent.
*
* It returns NULL whenever memory is unavailable.
*
*/
extern int agp_copy_info(agp_kern_info *);
/*
* agp_copy_info :
*
* This function copies information about the
* agp bridge device and the state of the agp
* backend into an agp_kern_info pointer.
*
* It takes an agp_kern_info pointer as an
* argument. The caller should insure that
* this pointer is valid.
*
*/
extern int agp_bind_memory(agp_memory *, off_t);
/*
* agp_bind_memory :
*
* This function binds an agp_memory structure
* into the graphics aperture translation table.
*
* It takes an agp_memory pointer and an offset into
* the graphics aperture translation table as arguments
*
* It returns -EINVAL if the pointer == NULL.
* It returns -EBUSY if the area of the table
* requested is already in use.
*
*/
extern int agp_unbind_memory(agp_memory *);
/*
* agp_unbind_memory :
*
* This function removes an agp_memory structure
* from the graphics aperture translation table.
*
* It takes an agp_memory pointer as an argument.
*
* It returns -EINVAL if this piece of agp_memory
* is not currently bound to the graphics aperture
* translation table or if the agp_memory
* pointer == NULL
*
*/
extern void agp_enable(u32);
/*
* agp_enable :
*
* This function initializes the agp point-to-point
* connection.
*
* It takes an agp mode register as an argument
*
*/
extern int agp_backend_acquire(void);
/*
* agp_backend_acquire :
*
* This Function attempts to acquire the agp
* backend.
*
* returns -EBUSY if agp is in use,
* returns 0 if the caller owns the agp backend
*/
extern void agp_backend_release(void);
/*
* agp_backend_release :
*
* This Function releases the lock on the agp
* backend.
*
* The caller must insure that the graphics
* aperture translation table is read for use
* by another entity. (Ensure that all memory
* it bound is unbound.)
*
* Interface between drm and agp code. When agp initializes, it makes
* the below structure available via inter_module_register(), drm might
* use it. Keith Owens <kaos@ocs.com.au> 28 Oct 2000.
*/
typedef struct {
void (*free_memory)(agp_memory *);
agp_memory *(*allocate_memory)(size_t, u32);
......@@ -260,10 +122,4 @@ typedef struct {
extern const drm_agp_t *drm_agp_p;
/*
* Interface between drm and agp code. When agp initializes, it makes
* the above structure available via inter_module_register(), drm might
* use it. Keith Owens <kaos@ocs.com.au> 28 Oct 2000.
*/
#endif /* _AGP_BACKEND_H */
include/linux/agpgart.h
View file @ 2836f684
......@@ -112,10 +112,6 @@ typedef struct _agp_unbind {
#define AGPGART_MINOR 175
#define AGP_UNLOCK() up(&(agp_fe.agp_mutex));
#define AGP_LOCK() down(&(agp_fe.agp_mutex));
#define AGP_LOCK_INIT() sema_init(&(agp_fe.agp_mutex), 1)
#ifndef _AGP_BACKEND_H
struct _agp_version {
u16 major;
......
include/linux/pci_ids.h
View file @ 2836f684
......@@ -1007,7 +1007,9 @@
#define PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL 0x017B
#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL 0x017C
#define PCI_DEVICE_ID_NVIDIA_IGEFORCE2 0x01a0
#define PCI_DEVICE_ID_NVIDIA_NFORCE 0x01a4
#define PCI_DEVICE_ID_NVIDIA_NFORCE_IDE 0x01bc
#define PCI_DEVICE_ID_NVIDIA_NFORCE2 0x01e0
#define PCI_DEVICE_ID_NVIDIA_GEFORCE3 0x0200
#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_1 0x0201
#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_2 0x0202
......@@ -1902,10 +1904,11 @@
#define PCI_DEVICE_ID_INTEL_82845G_IG 0x2562
#define PCI_DEVICE_ID_INTEL_82865_HB 0x2570
#define PCI_DEVICE_ID_INTEL_82865_IG 0x2572
#define PCI_DEVICE_ID_INTEL_82855PM_HB 0x3340
#define PCI_DEVICE_ID_INTEL_82830_HB 0x3575
#define PCI_DEVICE_ID_INTEL_82830_CGC 0x3577
#define PCI_DEVICE_ID_INTEL_82855_HB 0x3580
#define PCI_DEVICE_ID_INTEL_82855_IG 0x3582
#define PCI_DEVICE_ID_INTEL_82855GM_HB 0x3580
#define PCI_DEVICE_ID_INTEL_82855GM_IG 0x3582
#define PCI_DEVICE_ID_INTEL_80310 0x530d
#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
......
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