Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Support
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in / Register
Toggle navigation
L
linux
Project overview
Project overview
Details
Activity
Releases
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Issues
0
Issues
0
List
Boards
Labels
Milestones
Merge Requests
0
Merge Requests
0
Analytics
Analytics
Repository
Value Stream
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Create a new issue
Commits
Issue Boards
Open sidebar
nexedi
linux
Commits
28681d62
Commit
28681d62
authored
Jan 13, 2003
by
Bjorn Helgaas
Committed by
Dave Jones
Jan 13, 2003
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
[AGP] factor device capability collection
parent
f458c23a
Changes
3
Show whitespace changes
Inline
Side-by-side
Showing
3 changed files
with
72 additions
and
195 deletions
+72
-195
drivers/char/agp/amd-k8-agp.c
drivers/char/agp/amd-k8-agp.c
+1
-52
drivers/char/agp/generic.c
drivers/char/agp/generic.c
+66
-72
drivers/char/agp/sworks-agp.c
drivers/char/agp/sworks-agp.c
+5
-71
No files found.
drivers/char/agp/amd-k8-agp.c
View file @
28681d62
...
@@ -370,62 +370,11 @@ static void agp_x86_64_agp_enable(u32 mode)
...
@@ -370,62 +370,11 @@ static void agp_x86_64_agp_enable(u32 mode)
pci_read_config_dword
(
agp_bridge
.
dev
,
agp_bridge
.
capndx
+
4
,
&
command
);
pci_read_config_dword
(
agp_bridge
.
dev
,
agp_bridge
.
capndx
+
4
,
&
command
);
/*
command
=
agp_collect_device_status
(
mode
,
command
);
* PASS2: go through all devices that claim to be
* AGP devices and collect their data.
*/
pci_for_each_dev
(
device
)
{
cap_ptr
=
pci_find_capability
(
device
,
PCI_CAP_ID_AGP
);
if
(
cap_ptr
!=
0x00
)
{
/*
* Ok, here we have a AGP device. Disable impossible
* settings, and adjust the readqueue to the minimum.
*/
pci_read_config_dword
(
device
,
cap_ptr
+
4
,
&
scratch
);
/* adjust RQ depth */
command
=
((
command
&
~
0xff000000
)
|
min_t
(
u32
,
(
mode
&
0xff000000
),
min_t
(
u32
,
(
command
&
0xff000000
),
(
scratch
&
0xff000000
))));
/* disable SBA if it's not supported */
if
(
!
((
command
&
0x200
)
&&
(
scratch
&
0x200
)
&&
(
mode
&
0x200
)))
command
&=
~
0x200
;
/* disable FW if it's not supported */
if
(
!
((
command
&
0x10
)
&&
(
scratch
&
0x10
)
&&
(
mode
&
0x10
)))
command
&=
~
0x10
;
if
(
!
((
command
&
2
)
&&
(
scratch
&
2
)
&&
(
mode
&
2
)))
command
&=
~
2
;
/* 8x */
if
(
!
((
command
&
1
)
&&
(
scratch
&
1
)
&&
(
mode
&
1
)))
command
&=
~
1
;
/* 4x */
}
}
/*
* PASS3: Figure out the 8X/4X setting and enable the
* target (our motherboard chipset).
*/
if
(
command
&
2
)
command
&=
~
5
;
/* 8X */
if
(
command
&
1
)
command
&=
~
6
;
/* 4X */
command
|=
0x100
;
command
|=
0x100
;
pci_write_config_dword
(
agp_bridge
.
dev
,
agp_bridge
.
capndx
+
8
,
command
);
pci_write_config_dword
(
agp_bridge
.
dev
,
agp_bridge
.
capndx
+
8
,
command
);
/*
* PASS4: Go through all AGP devices and update the
* command registers.
*/
agp_device_command
(
command
,
1
);
agp_device_command
(
command
,
1
);
}
}
...
...
drivers/char/agp/generic.c
View file @
28681d62
...
@@ -314,48 +314,22 @@ int agp_unbind_memory(agp_memory * curr)
...
@@ -314,48 +314,22 @@ int agp_unbind_memory(agp_memory * curr)
/* Generic Agp routines - Start */
/* Generic Agp routines - Start */
void
agp_device_command
(
u32
command
,
int
agp_v3
)
u32
agp_collect_device_status
(
u32
mode
,
u32
command
)
{
{
struct
pci_dev
*
device
;
struct
pci_dev
*
device
;
int
mode
;
u8
agp
;
u32
scratch
;
mode
=
command
&
0x7
;
if
(
agp_v3
)
mode
*=
4
;
pci_for_each_dev
(
device
)
{
pci_for_each_dev
(
device
)
{
u8
agp
=
pci_find_capability
(
device
,
PCI_CAP_ID_AGP
);
agp
=
pci_find_capability
(
device
,
PCI_CAP_ID_AGP
);
if
(
!
agp
)
if
(
!
agp
)
continue
;
continue
;
printk
(
KERN_INFO
PFX
"Putting AGP V%d device at %s into %dx mode
\n
"
,
agp_v3
?
3
:
2
,
device
->
slot_name
,
mode
);
pci_write_config_dword
(
device
,
agp
+
8
,
command
);
}
}
void
agp_generic_agp_enable
(
u32
mode
)
{
struct
pci_dev
*
device
=
NULL
;
u32
command
,
scratch
;
u8
cap_ptr
;
pci_read_config_dword
(
agp_bridge
.
dev
,
agp_bridge
.
capndx
+
4
,
&
command
);
/*
* PASS1: go through all devices that claim to be
* AGP devices and collect their data.
*/
pci_for_each_dev
(
device
)
{
cap_ptr
=
pci_find_capability
(
device
,
PCI_CAP_ID_AGP
);
if
(
cap_ptr
!=
0x00
)
{
/*
/*
* Ok, here we have a AGP device. Disable impossible
* Ok, here we have a AGP device. Disable impossible
* settings, and adjust the readqueue to the minimum.
* settings, and adjust the readqueue to the minimum.
*/
*/
pci_read_config_dword
(
device
,
agp
+
4
,
&
scratch
);
pci_read_config_dword
(
device
,
cap_ptr
+
4
,
&
scratch
);
/* adjust RQ depth */
/* adjust RQ depth */
command
=
((
command
&
~
0xff000000
)
|
command
=
((
command
&
~
0xff000000
)
|
...
@@ -390,32 +364,52 @@ void agp_generic_agp_enable(u32 mode)
...
@@ -390,32 +364,52 @@ void agp_generic_agp_enable(u32 mode)
(
mode
&
1
)))
(
mode
&
1
)))
command
&=
~
0x00000001
;
command
&=
~
0x00000001
;
}
}
}
/*
* PASS2: Figure out the 4X/2X/1X setting and enable the
* target (our motherboard chipset).
*/
if
(
command
&
4
)
if
(
command
&
4
)
command
&=
~
3
;
/* 4X */
command
&=
~
3
;
/* 4X */
if
(
command
&
2
)
if
(
command
&
2
)
command
&=
~
5
;
/* 2X */
command
&=
~
5
;
/* 2X
(8X for AGP3.0)
*/
if
(
command
&
1
)
if
(
command
&
1
)
command
&=
~
6
;
/* 1X */
command
&=
~
6
;
/* 1X (4X for AGP3.0) */
return
command
;
}
command
|=
0x00000100
;
void
agp_device_command
(
u32
command
,
int
agp_v3
)
{
struct
pci_dev
*
device
;
int
mode
;
mode
=
command
&
0x7
;
if
(
agp_v3
)
mode
*=
4
;
pci_for_each_dev
(
device
)
{
u8
agp
=
pci_find_capability
(
device
,
PCI_CAP_ID_AGP
);
if
(
!
agp
)
continue
;
printk
(
KERN_INFO
PFX
"Putting AGP V%d device at %s into %dx mode
\n
"
,
agp_v3
?
3
:
2
,
device
->
slot_name
,
mode
);
pci_write_config_dword
(
device
,
agp
+
8
,
command
);
}
}
void
agp_generic_agp_enable
(
u32
mode
)
{
u32
command
;
pci_read_config_dword
(
agp_bridge
.
dev
,
agp_bridge
.
capndx
+
4
,
&
command
);
command
=
agp_collect_device_status
(
mode
,
command
);
command
|=
0x100
;
pci_write_config_dword
(
agp_bridge
.
dev
,
pci_write_config_dword
(
agp_bridge
.
dev
,
agp_bridge
.
capndx
+
8
,
agp_bridge
.
capndx
+
8
,
command
);
command
);
/*
* PASS3: Go throu all AGP devices and update the
* command registers.
*/
agp_device_command
(
command
,
0
);
agp_device_command
(
command
,
0
);
}
}
...
...
drivers/char/agp/sworks-agp.c
View file @
28681d62
...
@@ -413,89 +413,23 @@ static struct aper_size_info_lvl2 serverworks_sizes[7] =
...
@@ -413,89 +413,23 @@ static struct aper_size_info_lvl2 serverworks_sizes[7] =
static
void
serverworks_agp_enable
(
u32
mode
)
static
void
serverworks_agp_enable
(
u32
mode
)
{
{
struct
pci_dev
*
device
=
NULL
;
u32
command
;
u32
command
,
scratch
,
cap_id
;
u8
cap_ptr
;
pci_read_config_dword
(
serverworks_private
.
svrwrks_dev
,
pci_read_config_dword
(
serverworks_private
.
svrwrks_dev
,
agp_bridge
.
capndx
+
4
,
agp_bridge
.
capndx
+
4
,
&
command
);
&
command
);
/*
command
=
agp_collect_device_status
(
mode
,
command
);
* PASS1: go throu all devices that claim to be
* AGP devices and collect their data.
*/
pci_for_each_dev
(
device
)
{
cap_ptr
=
pci_find_capability
(
device
,
PCI_CAP_ID_AGP
);
if
(
cap_ptr
!=
0x00
)
{
/*
* Ok, here we have a AGP device. Disable impossible
* settings, and adjust the readqueue to the minimum.
*/
pci_read_config_dword
(
device
,
cap_ptr
+
4
,
&
scratch
);
/* adjust RQ depth */
command
=
((
command
&
~
0xff000000
)
|
min_t
(
u32
,
(
mode
&
0xff000000
),
min_t
(
u32
,
(
command
&
0xff000000
),
(
scratch
&
0xff000000
))));
/* disable SBA if it's not supported */
if
(
!
((
command
&
0x00000200
)
&&
(
scratch
&
0x00000200
)
&&
(
mode
&
0x00000200
)))
command
&=
~
0x00000200
;
/* disable FW */
command
&=
~
0x00000010
;
command
&=
~
0x00000008
;
if
(
!
((
command
&
4
)
&&
command
&=
~
0x10
;
/* disable FW */
(
scratch
&
4
)
&&
command
&=
~
0x08
;
(
mode
&
4
)))
command
&=
~
0x00000004
;
if
(
!
((
command
&
2
)
&&
command
|=
0x100
;
(
scratch
&
2
)
&&
(
mode
&
2
)))
command
&=
~
0x00000002
;
if
(
!
((
command
&
1
)
&&
(
scratch
&
1
)
&&
(
mode
&
1
)))
command
&=
~
0x00000001
;
}
}
/*
* PASS2: Figure out the 4X/2X/1X setting and enable the
* target (our motherboard chipset).
*/
if
(
command
&
4
)
{
command
&=
~
3
;
/* 4X */
}
if
(
command
&
2
)
{
command
&=
~
5
;
/* 2X */
}
if
(
command
&
1
)
{
command
&=
~
6
;
/* 1X */
}
command
|=
0x00000100
;
pci_write_config_dword
(
serverworks_private
.
svrwrks_dev
,
pci_write_config_dword
(
serverworks_private
.
svrwrks_dev
,
agp_bridge
.
capndx
+
8
,
agp_bridge
.
capndx
+
8
,
command
);
command
);
/*
* PASS3: Go throu all AGP devices and update the
* command registers.
*/
agp_device_command
(
command
,
0
);
agp_device_command
(
command
,
0
);
}
}
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment