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Commit 2a85927c authored by Sascha Hauer's avatar Sascha Hauer
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Merge branch 'imx-for-2.6.38' of git://git.pengutronix.de/git/ukl/linux-2.6 into imx-for-2.6.38

parents 3561d43f 124bf94a
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arch/arm/Makefile
View file @ 2a85927c
......@@ -154,7 +154,7 @@ machine-$(CONFIG_ARCH_MSM) := msm
machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0
machine-$(CONFIG_ARCH_MX1) := imx
machine-$(CONFIG_ARCH_MX2) := imx
machine-$(CONFIG_ARCH_MX25) := mx25
machine-$(CONFIG_ARCH_MX25) := imx
machine-$(CONFIG_ARCH_MX3) := mx3
machine-$(CONFIG_ARCH_MX5) := mx5
machine-$(CONFIG_ARCH_MXC91231) := mxc91231
......
arch/arm/configs/mx3_defconfig
View file @ 2a85927c
......@@ -84,6 +84,7 @@ CONFIG_SERIAL_IMX_CONSOLE=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_IMX=y
CONFIG_SPI=y
CONFIG_W1=y
CONFIG_W1_MASTER_MXC=y
CONFIG_W1_SLAVE_THERM=y
......
arch/arm/mach-imx/Kconfig
View file @ 2a85927c
config IMX_HAVE_DMA_V1
bool
if ARCH_MX1
config SOC_IMX1
bool
select CPU_ARM920T
select IMX_HAVE_DMA_V1
select IMX_HAVE_IOMUX_V1
config SOC_IMX21
bool
select CPU_ARM926T
select ARCH_MXC_AUDMUX_V1
select IMX_HAVE_DMA_V1
select IMX_HAVE_IOMUX_V1
config SOC_IMX25
bool
select CPU_ARM926T
select ARCH_MXC_AUDMUX_V2
select ARCH_MXC_IOMUX_V3
config SOC_IMX27
bool
select CPU_ARM926T
select ARCH_MXC_AUDMUX_V1
select IMX_HAVE_DMA_V1
select IMX_HAVE_IOMUX_V1
if ARCH_MX1
comment "MX1 platforms:"
config MACH_MXLADS
......@@ -31,33 +51,17 @@ endif
if ARCH_MX2
config SOC_IMX21
select CPU_ARM926T
select ARCH_MXC_AUDMUX_V1
select IMX_HAVE_DMA_V1
select IMX_HAVE_IOMUX_V1
bool
config SOC_IMX27
select CPU_ARM926T
select ARCH_MXC_AUDMUX_V1
select IMX_HAVE_DMA_V1
select IMX_HAVE_IOMUX_V1
bool
choice
prompt "CPUs:"
default MACH_MX21
config MACH_MX21
bool "i.MX21 support"
select SOC_IMX21
help
This enables support for Freescale's MX2 based i.MX21 processor.
config MACH_MX27
bool "i.MX27 support"
select SOC_IMX27
help
This enables support for Freescale's MX2 based i.MX27 processor.
......@@ -71,7 +75,10 @@ comment "MX21 platforms:"
config MACH_MX21ADS
bool "MX21ADS platform"
select SOC_IMX21
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
help
Include support for MX21ADS platform. This includes specific
......@@ -79,24 +86,78 @@ config MACH_MX21ADS
endif
if ARCH_MX25
comment "MX25 platforms:"
config MACH_MX25_3DS
bool "Support MX25PDK (3DS) Platform"
select SOC_IMX25
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMXDI_RTC
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_IMX_KEYPAD
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
config MACH_EUKREA_CPUIMX25
bool "Support Eukrea CPUIMX25 Platform"
select SOC_IMX25
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMXDI_RTC
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select MXC_ULPI if USB_ULPI
choice
prompt "Baseboard"
depends on MACH_EUKREA_CPUIMX25
default MACH_EUKREA_MBIMXSD25_BASEBOARD
config MACH_EUKREA_MBIMXSD25_BASEBOARD
bool "Eukrea MBIMXSD development board"
select IMX_HAVE_PLATFORM_IMX_SSI
help
This adds board specific devices that can be found on Eukrea's
MBIMXSD evaluation board.
endchoice
endif
if MACH_MX27
comment "MX27 platforms:"
config MACH_MX27ADS
bool "MX27ADS platform"
select SOC_IMX27
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_W1
help
Include support for MX27ADS platform. This includes specific
configurations for the board and its peripherals.
config MACH_PCM038
bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
select SOC_IMX27
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_W1
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
......@@ -109,8 +170,9 @@ choice
default MACH_PCM970_BASEBOARD
config MACH_PCM970_BASEBOARD
prompt "PHYTEC PCM970 development board"
bool
bool "PHYTEC PCM970 development board"
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_MXC_MMC
help
This adds board specific devices that can be found on Phytec's
PCM970 evaluation board.
......@@ -119,9 +181,14 @@ endchoice
config MACH_CPUIMX27
bool "Eukrea CPUIMX27 module"
select SOC_IMX27
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_W1
select MXC_ULPI if USB_ULPI
help
Include support for Eukrea CPUIMX27 platform. This includes
......@@ -130,6 +197,7 @@ config MACH_CPUIMX27
config MACH_EUKREA_CPUIMX27_USESDHC2
bool "CPUIMX27 integrates SDHC2 module"
depends on MACH_CPUIMX27
select IMX_HAVE_PLATFORM_MXC_MMC
help
This adds support for the internal SDHC2 used on CPUIMX27
for wifi or eMMC.
......@@ -148,8 +216,11 @@ choice
config MACH_EUKREA_MBIMX27_BASEBOARD
bool "Eukrea MBIMX27 development board"
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_IMX_KEYPAD
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_SPI_IMX
help
This adds board specific devices that can be found on Eukrea's
......@@ -159,15 +230,21 @@ endchoice
config MACH_MX27_3DS
bool "MX27PDK platform"
select SOC_IMX27
select IMX_HAVE_PLATFORM_IMX_KEYPAD
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_MMC
help
Include support for MX27PDK platform. This includes specific
configurations for the board and its peripherals.
config MACH_IMX27_VISSTRIM_M10
bool "Vista Silicon i.MX27 Visstrim_m10"
select SOC_IMX27
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_EHCI
help
Include support for Visstrim_m10 platform and its different variants.
This includes specific configurations for the board and its
......@@ -175,6 +252,7 @@ config MACH_IMX27_VISSTRIM_M10
config MACH_IMX27LITE
bool "LogicPD MX27 LITEKIT platform"
select SOC_IMX27
select IMX_HAVE_PLATFORM_IMX_UART
help
Include support for MX27 LITEKIT platform. This includes specific
......@@ -182,10 +260,17 @@ config MACH_IMX27LITE
config MACH_PCA100
bool "Phytec phyCARD-s (pca100)"
select SOC_IMX27
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_W1
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
......@@ -194,8 +279,11 @@ config MACH_PCA100
config MACH_MXT_TD60
bool "Maxtrack i-MXT TD60"
select SOC_IMX27
select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
help
Include support for i-MXT (aka td60) platform. This
......
arch/arm/mach-imx/Makefile
View file @ 2a85927c
......@@ -4,13 +4,13 @@
# Object file lists.
obj-y := devices.o
obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o
obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o
obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o
......@@ -22,6 +22,10 @@ obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-eukrea_cpuimx25.o
obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o
obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
......
arch/arm/mach-imx/Makefile.boot
View file @ 2a85927c
......@@ -6,6 +6,10 @@ zreladdr-$(CONFIG_MACH_MX21) := 0xC0008000
params_phys-$(CONFIG_MACH_MX21) := 0xC0000100
initrd_phys-$(CONFIG_MACH_MX21) := 0xC0800000
zreladdr-$(CONFIG_ARCH_MX25) := 0x80008000
params_phys-$(CONFIG_ARCH_MX25) := 0x80000100
initrd_phys-$(CONFIG_ARCH_MX25) := 0x80800000
zreladdr-$(CONFIG_MACH_MX27) := 0xA0008000
params_phys-$(CONFIG_MACH_MX27) := 0xA0000100
initrd_phys-$(CONFIG_MACH_MX27) := 0xA0800000
arch/arm/mach-imx/devices-imx21.h
View file @ 2a85927c
......@@ -9,10 +9,26 @@
#include <mach/mx21.h>
#include <mach/devices-common.h>
extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst;
#define imx21_add_imx21_hcd(pdata) \
imx_add_imx21_hcd(&imx21_imx21_hcd_data, pdata)
extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst;
#define imx21_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx21_imx2_wdt_data)
extern const struct imx_imx_fb_data imx21_imx_fb_data __initconst;
#define imx21_add_imx_fb(pdata) \
imx_add_imx_fb(&imx21_imx_fb_data, pdata)
extern const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst;
#define imx21_add_imx_i2c(pdata) \
imx_add_imx_i2c(&imx21_imx_i2c_data, pdata)
extern const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst;
#define imx21_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx21_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst;
#define imx21_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata)
......@@ -25,10 +41,18 @@ extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst;
#define imx21_add_imx_uart2(pdata) imx21_add_imx_uart(2, pdata)
#define imx21_add_imx_uart3(pdata) imx21_add_imx_uart(3, pdata)
extern const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst;
#define imx21_add_mxc_mmc(id, pdata) \
imx_add_mxc_mmc(&imx21_mxc_mmc_data[id], pdata)
extern const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst;
#define imx21_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx21_mxc_nand_data, pdata)
extern const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst;
#define imx21_add_mxc_w1(pdata) \
imx_add_mxc_w1(&imx21_mxc_w1_data)
extern const struct imx_spi_imx_data imx21_cspi_data[] __initconst;
#define imx21_add_cspi(id, pdata) \
imx_add_spi_imx(&imx21_cspi_data[id], pdata)
......
arch/arm/mach-mx25/devices-imx25.h → arch/arm/mach-imx/devices-imx25.h
View file @ 2a85927c
......@@ -13,10 +13,27 @@ extern const struct imx_fec_data imx25_fec_data __initconst;
#define imx25_add_fec(pdata) \
imx_add_fec(&imx25_fec_data, pdata)
#define imx25_add_flexcan0(pdata) \
imx_add_flexcan(0, MX25_CAN1_BASE_ADDR, SZ_16K, MX25_INT_CAN1, pdata)
#define imx25_add_flexcan1(pdata) \
imx_add_flexcan(1, MX25_CAN2_BASE_ADDR, SZ_16K, MX25_INT_CAN2, pdata)
extern const struct imx_flexcan_data imx25_flexcan_data[] __initconst;
#define imx25_add_flexcan(id, pdata) \
imx_add_flexcan(&imx25_flexcan_data[id], pdata)
#define imx25_add_flexcan0(pdata) imx25_add_flexcan(0, pdata)
#define imx25_add_flexcan1(pdata) imx25_add_flexcan(1, pdata)
extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst;
#define imx25_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata)
extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst;
#define imx25_add_imxdi_rtc(pdata) \
imx_add_imxdi_rtc(&imx25_imxdi_rtc_data)
extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst;
#define imx25_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx25_imx2_wdt_data)
extern const struct imx_imx_fb_data imx25_imx_fb_data __initconst;
#define imx25_add_imx_fb(pdata) \
imx_add_imx_fb(&imx25_imx_fb_data, pdata)
extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst;
#define imx25_add_imx_i2c(id, pdata) \
......@@ -25,6 +42,10 @@ extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst;
#define imx25_add_imx_i2c1(pdata) imx25_add_imx_i2c(1, pdata)
#define imx25_add_imx_i2c2(pdata) imx25_add_imx_i2c(2, pdata)
extern const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst;
#define imx25_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx25_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst;
#define imx25_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata)
......@@ -38,17 +59,29 @@ extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst;
#define imx25_add_imx_uart3(pdata) imx25_add_imx_uart(3, pdata)
#define imx25_add_imx_uart4(pdata) imx25_add_imx_uart(4, pdata)
extern const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst;
#define imx25_add_mx2_camera(pdata) \
imx_add_mx2_camera(&imx25_mx2_camera_data, pdata)
extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst;
#define imx25_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx25_mxc_ehci_otg_data, pdata)
extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst;
#define imx25_add_mxc_ehci_hs(pdata) \
imx_add_mxc_ehci(&imx25_mxc_ehci_hs_data, pdata)
extern const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst;
#define imx25_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx25_mxc_nand_data, pdata)
extern const struct imx_sdhci_esdhc_imx_data
imx25_sdhci_esdhc_imx_data[] __initconst;
#define imx25_add_sdhci_esdhc_imx(id, pdata) \
imx_add_sdhci_esdhc_imx(&imx25_sdhci_esdhc_imx_data[id], pdata)
extern const struct imx_spi_imx_data imx25_spi_imx_data[] __initconst;
#define imx25_add_spi_imx(id, pdata) \
imx_add_spi_imx(&imx25_spi_imx_data[id], pdata)
#define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata)
#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata)
#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata)
extern const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst;
#define imx25_add_esdhc(id, pdata) \
imx_add_esdhc(&imx25_esdhc_data[id], pdata)
arch/arm/mach-imx/devices-imx27.h
View file @ 2a85927c
......@@ -13,10 +13,26 @@ extern const struct imx_fec_data imx27_fec_data __initconst;
#define imx27_add_fec(pdata) \
imx_add_fec(&imx27_fec_data, pdata)
extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst;
#define imx27_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata)
extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst;
#define imx27_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx27_imx2_wdt_data)
extern const struct imx_imx_fb_data imx27_imx_fb_data __initconst;
#define imx27_add_imx_fb(pdata) \
imx_add_imx_fb(&imx27_imx_fb_data, pdata)
extern const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst;
#define imx27_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata)
extern const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst;
#define imx27_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx27_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst;
#define imx27_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata)
......@@ -31,10 +47,29 @@ extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst;
#define imx27_add_imx_uart4(pdata) imx27_add_imx_uart(4, pdata)
#define imx27_add_imx_uart5(pdata) imx27_add_imx_uart(5, pdata)
extern const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst;
#define imx27_add_mx2_camera(pdata) \
imx_add_mx2_camera(&imx27_mx2_camera_data, pdata)
extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst;
#define imx27_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx27_mxc_ehci_otg_data, pdata)
extern const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst;
#define imx27_add_mxc_ehci_hs(id, pdata) \
imx_add_mxc_ehci(&imx27_mxc_ehci_hs_data[id - 1], pdata)
extern const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst;
#define imx27_add_mxc_mmc(id, pdata) \
imx_add_mxc_mmc(&imx27_mxc_mmc_data[id], pdata)
extern const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst;
#define imx27_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx27_mxc_nand_data, pdata)
extern const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst;
#define imx27_add_mxc_w1(pdata) \
imx_add_mxc_w1(&imx27_mxc_w1_data)
extern const struct imx_spi_imx_data imx27_cspi_data[] __initconst;
#define imx27_add_cspi(id, pdata) \
imx_add_spi_imx(&imx27_cspi_data[id], pdata)
......
arch/arm/mach-imx/devices.c deleted 100644 → 0
View file @ 3561d43f
/*
* Author: MontaVista Software, Inc.
* <source@mvista.com>
*
* Based on the OMAP devices.c
*
* 2005 (c) MontaVista Software, Inc. This file is licensed under the
* terms of the GNU General Public License version 2. This program is
* licensed "as is" without any warranty of any kind, whether express
* or implied.
*
* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
* Copyright 2008 Sascha Hauer, kernel@pengutronix.de
* Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
* Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/dma-mapping.h>
#include <linux/serial.h>
#include <mach/irqs.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/mmc.h>
#include "devices.h"
#if defined(CONFIG_ARCH_MX1)
static struct resource imx1_camera_resources[] = {
{
.start = 0x00224000,
.end = 0x00224010,
.flags = IORESOURCE_MEM,
}, {
.start = MX1_CSI_INT,
.end = MX1_CSI_INT,
.flags = IORESOURCE_IRQ,
},
};
static u64 imx1_camera_dmamask = DMA_BIT_MASK(32);
struct platform_device imx1_camera_device = {
.name = "mx1-camera",
.id = 0, /* This is used to put cameras on this interface */
.dev = {
.dma_mask = &imx1_camera_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = imx1_camera_resources,
.num_resources = ARRAY_SIZE(imx1_camera_resources),
};
static struct resource imx_rtc_resources[] = {
{
.start = 0x00204000,
.end = 0x00204024,
.flags = IORESOURCE_MEM,
}, {
.start = MX1_RTC_INT,
.end = MX1_RTC_INT,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_RTC_SAMINT,
.end = MX1_RTC_SAMINT,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_rtc_device = {
.name = "rtc-imx",
.id = 0,
.resource = imx_rtc_resources,
.num_resources = ARRAY_SIZE(imx_rtc_resources),
};
static struct resource imx_wdt_resources[] = {
{
.start = 0x00201000,
.end = 0x00201008,
.flags = IORESOURCE_MEM,
}, {
.start = MX1_WDT_INT,
.end = MX1_WDT_INT,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_wdt_device = {
.name = "imx-wdt",
.id = 0,
.resource = imx_wdt_resources,
.num_resources = ARRAY_SIZE(imx_wdt_resources),
};
static struct resource imx_usb_resources[] = {
{
.start = 0x00212000,
.end = 0x00212148,
.flags = IORESOURCE_MEM,
}, {
.start = MX1_USBD_INT0,
.end = MX1_USBD_INT0,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_USBD_INT1,
.end = MX1_USBD_INT1,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_USBD_INT2,
.end = MX1_USBD_INT2,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_USBD_INT3,
.end = MX1_USBD_INT3,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_USBD_INT4,
.end = MX1_USBD_INT4,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_USBD_INT5,
.end = MX1_USBD_INT5,
.flags = IORESOURCE_IRQ,
}, {
.start = MX1_USBD_INT6,
.end = MX1_USBD_INT6,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_usb_device = {
.name = "imx_udc",
.id = 0,
.num_resources = ARRAY_SIZE(imx_usb_resources),
.resource = imx_usb_resources,
};
/* GPIO port description */
static struct mxc_gpio_port imx_gpio_ports[] = {
{
.chip.label = "gpio-0",
.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
.irq = MX1_GPIO_INT_PORTA,
.virtual_irq_start = MXC_GPIO_IRQ_START,
}, {
.chip.label = "gpio-1",
.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100),
.irq = MX1_GPIO_INT_PORTB,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
}, {
.chip.label = "gpio-2",
.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200),
.irq = MX1_GPIO_INT_PORTC,
.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
}, {
.chip.label = "gpio-3",
.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300),
.irq = MX1_GPIO_INT_PORTD,
.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
}
};
int __init imx1_register_gpios(void)
{
return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
}
#endif
#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
#ifdef CONFIG_MACH_MX27
static struct resource mx27_camera_resources[] = {
{
.start = MX27_CSI_BASE_ADDR,
.end = MX27_CSI_BASE_ADDR + 0x1f,
.flags = IORESOURCE_MEM,
}, {
.start = MX27_EMMA_PRP_BASE_ADDR,
.end = MX27_EMMA_PRP_BASE_ADDR + 0x1f,
.flags = IORESOURCE_MEM,
}, {
.start = MX27_INT_CSI,
.end = MX27_INT_CSI,
.flags = IORESOURCE_IRQ,
},{
.start = MX27_INT_EMMAPRP,
.end = MX27_INT_EMMAPRP,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mx27_camera_device = {
.name = "mx2-camera",
.id = 0,
.num_resources = ARRAY_SIZE(mx27_camera_resources),
.resource = mx27_camera_resources,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
#endif
/*
* General Purpose Timer
* - i.MX21: 3 timers
* - i.MX27: 6 timers
*/
#define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
static struct resource timer ## n ##_resources[] = { \
{ \
.start = baseaddr, \
.end = baseaddr + SZ_4K - 1, \
.flags = IORESOURCE_MEM, \
}, { \
.start = irq, \
.end = irq, \
.flags = IORESOURCE_IRQ, \
} \
}; \
\
struct platform_device mxc_gpt ## n = { \
.name = "imx_gpt", \
.id = n, \
.num_resources = ARRAY_SIZE(timer ## n ## _resources), \
.resource = timer ## n ## _resources, \
}
/* We use gpt1 as system timer, so do not add a device for this one */
DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
#ifdef CONFIG_MACH_MX27
DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
#endif
/* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
static struct resource mxc_wdt_resources[] = {
{
.start = MX2x_WDOG_BASE_ADDR,
.end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device mxc_wdt = {
.name = "imx2-wdt",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_wdt_resources),
.resource = mxc_wdt_resources,
};
static struct resource mxc_w1_master_resources[] = {
{
.start = MX2x_OWIRE_BASE_ADDR,
.end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device mxc_w1_master_device = {
.name = "mxc_w1",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
.resource = mxc_w1_master_resources,
};
/*
* lcdc:
* - i.MX1: the basic controller
* - i.MX21: to be checked
* - i.MX27: like i.MX1, with slightly variations
*/
static struct resource mxc_fb[] = {
{
.start = MX2x_LCDC_BASE_ADDR,
.end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = MX2x_INT_LCDC,
.end = MX2x_INT_LCDC,
.flags = IORESOURCE_IRQ,
}
};
/* mxc lcd driver */
struct platform_device mxc_fb_device = {
.name = "imx-fb",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_fb),
.resource = mxc_fb,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct resource mxc_pwm_resources[] = {
{
.start = MX2x_PWM_BASE_ADDR,
.end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = MX2x_INT_PWM,
.end = MX2x_INT_PWM,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_pwm_device = {
.name = "mxc_pwm",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_pwm_resources),
.resource = mxc_pwm_resources,
};
#define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
static struct resource mxc_sdhc_resources ## n[] = { \
{ \
.start = baseaddr, \
.end = baseaddr + SZ_4K - 1, \
.flags = IORESOURCE_MEM, \
}, { \
.start = irq, \
.end = irq, \
.flags = IORESOURCE_IRQ, \
}, { \
.start = dmareq, \
.end = dmareq, \
.flags = IORESOURCE_DMA, \
}, \
}; \
\
static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
\
struct platform_device mxc_sdhc_device ## n = { \
.name = "mxc-mmc", \
.id = n, \
.dev = { \
.dma_mask = &mxc_sdhc ## n ## _dmamask, \
.coherent_dma_mask = DMA_BIT_MASK(32), \
}, \
.num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
.resource = mxc_sdhc_resources ## n, \
}
DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
#ifdef CONFIG_MACH_MX27
static struct resource otg_resources[] = {
{
.start = MX27_USBOTG_BASE_ADDR,
.end = MX27_USBOTG_BASE_ADDR + 0x1ff,
.flags = IORESOURCE_MEM,
}, {
.start = MX27_INT_USB3,
.end = MX27_INT_USB3,
.flags = IORESOURCE_IRQ,
},
};
static u64 otg_dmamask = DMA_BIT_MASK(32);
/* OTG gadget device */
struct platform_device mxc_otg_udc_device = {
.name = "fsl-usb2-udc",
.id = -1,
.dev = {
.dma_mask = &otg_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = otg_resources,
.num_resources = ARRAY_SIZE(otg_resources),
};
/* OTG host */
struct platform_device mxc_otg_host = {
.name = "mxc-ehci",
.id = 0,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
.dma_mask = &otg_dmamask,
},
.resource = otg_resources,
.num_resources = ARRAY_SIZE(otg_resources),
};
/* USB host 1 */
static u64 usbh1_dmamask = DMA_BIT_MASK(32);
static struct resource mxc_usbh1_resources[] = {
{
.start = MX27_USBOTG_BASE_ADDR + 0x200,
.end = MX27_USBOTG_BASE_ADDR + 0x3ff,
.flags = IORESOURCE_MEM,
}, {
.start = MX27_INT_USB1,
.end = MX27_INT_USB1,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_usbh1 = {
.name = "mxc-ehci",
.id = 1,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
.dma_mask = &usbh1_dmamask,
},
.resource = mxc_usbh1_resources,
.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
};
/* USB host 2 */
static u64 usbh2_dmamask = DMA_BIT_MASK(32);
static struct resource mxc_usbh2_resources[] = {
{
.start = MX27_USBOTG_BASE_ADDR + 0x400,
.end = MX27_USBOTG_BASE_ADDR + 0x5ff,
.flags = IORESOURCE_MEM,
}, {
.start = MX27_INT_USB2,
.end = MX27_INT_USB2,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_usbh2 = {
.name = "mxc-ehci",
.id = 2,
.dev = {
.coherent_dma_mask = DMA_BIT_MASK(32),
.dma_mask = &usbh2_dmamask,
},
.resource = mxc_usbh2_resources,
.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
};
#endif
/* GPIO port description */
#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
{ \
.chip.label = "gpio-" #n, \
.irq = _irq, \
.base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
n * 0x100), \
.virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
}
#define DEFINE_MXC_GPIO_PORT(SOC, n) \
{ \
.chip.label = "gpio-" #n, \
.base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
n * 0x100), \
.virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
}
#define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
DEFINE_MXC_GPIO_PORT(SOC, 1), \
DEFINE_MXC_GPIO_PORT(SOC, 2), \
DEFINE_MXC_GPIO_PORT(SOC, 3), \
DEFINE_MXC_GPIO_PORT(SOC, 4), \
DEFINE_MXC_GPIO_PORT(SOC, 5), \
}
#ifdef CONFIG_MACH_MX21
DEFINE_MXC_GPIO_PORTS(MX21, imx21);
int __init imx21_register_gpios(void)
{
return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
}
#endif
#ifdef CONFIG_MACH_MX27
DEFINE_MXC_GPIO_PORTS(MX27, imx27);
int __init imx27_register_gpios(void)
{
return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
}
#endif
#ifdef CONFIG_MACH_MX21
static struct resource mx21_usbhc_resources[] = {
{
.start = MX21_USBOTG_BASE_ADDR,
.end = MX21_USBOTG_BASE_ADDR + SZ_8K - 1,
.flags = IORESOURCE_MEM,
},
{
.start = MX21_INT_USBHOST,
.end = MX21_INT_USBHOST,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mx21_usbhc_device = {
.name = "imx21-hcd",
.id = 0,
.dev = {
.dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(mx21_usbhc_resources),
.resource = mx21_usbhc_resources,
};
#endif
static struct resource imx_kpp_resources[] = {
{
.start = MX2x_KPP_BASE_ADDR,
.end = MX2x_KPP_BASE_ADDR + 0xf,
.flags = IORESOURCE_MEM
}, {
.start = MX2x_INT_KPP,
.end = MX2x_INT_KPP,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_kpp_device = {
.name = "imx-keypad",
.id = -1,
.num_resources = ARRAY_SIZE(imx_kpp_resources),
.resource = imx_kpp_resources,
};
#endif
arch/arm/mach-imx/devices.h deleted 100644 → 0
View file @ 3561d43f
#ifdef CONFIG_ARCH_MX1
extern struct platform_device imx1_camera_device;
extern struct platform_device imx_rtc_device;
extern struct platform_device imx_wdt_device;
extern struct platform_device imx_usb_device;
#endif
#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
extern struct platform_device mxc_gpt1;
extern struct platform_device mxc_gpt2;
#ifdef CONFIG_MACH_MX27
extern struct platform_device mxc_gpt3;
extern struct platform_device mxc_gpt4;
extern struct platform_device mxc_gpt5;
#endif
extern struct platform_device mxc_wdt;
extern struct platform_device mxc_w1_master_device;
extern struct platform_device mxc_fb_device;
extern struct platform_device mxc_pwm_device;
extern struct platform_device mxc_sdhc_device0;
extern struct platform_device mxc_sdhc_device1;
extern struct platform_device mxc_otg_udc_device;
extern struct platform_device mx27_camera_device;
extern struct platform_device mxc_otg_host;
extern struct platform_device mxc_usbh1;
extern struct platform_device mxc_usbh2;
extern struct platform_device mx21_usbhc_device;
extern struct platform_device imx_kpp_device;
#endif
arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
View file @ 2a85927c
......@@ -26,20 +26,16 @@
#include <linux/spi/ads7846.h>
#include <linux/backlight.h>
#include <video/platform_lcd.h>
#include <linux/input/matrix_keypad.h>
#include <asm/mach/arch.h>
#include <mach/common.h>
#include <mach/iomux-mx27.h>
#include <mach/imxfb.h>
#include <mach/hardware.h>
#include <mach/mmc.h>
#include <mach/spi.h>
#include <mach/audmux.h>
#include "devices-imx27.h"
#include "devices.h"
static const int eukrea_mbimx27_pins[] __initconst = {
/* UART2 */
......@@ -111,7 +107,8 @@ static const uint32_t eukrea_mbimx27_keymap[] = {
KEY(1, 1, KEY_LEFT),
};
static struct matrix_keymap_data eukrea_mbimx27_keymap_data = {
static const struct matrix_keymap_data
eukrea_mbimx27_keymap_data __initconst = {
.keymap = eukrea_mbimx27_keymap,
.keymap_size = ARRAY_SIZE(eukrea_mbimx27_keymap),
};
......@@ -196,7 +193,7 @@ static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
},
};
static struct imx_fb_platform_data eukrea_mbimx27_fb_data = {
static const struct imx_fb_platform_data eukrea_mbimx27_fb_data __initconst = {
.mode = eukrea_mbimx27_modes,
.num_modes = ARRAY_SIZE(eukrea_mbimx27_modes),
......@@ -306,7 +303,7 @@ static struct platform_device *platform_devices[] __initdata = {
&leds_gpio,
};
static struct imxmmc_platform_data sdhc_pdata = {
static const struct imxmmc_platform_data sdhc_pdata __initconst = {
.dat3_card_detect = 1,
};
......@@ -351,8 +348,8 @@ void __init eukrea_mbimx27_baseboard_init(void)
imx27_add_imx_uart3(&uart_pdata);
#endif
mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data);
mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata);
imx27_add_imx_fb(&eukrea_mbimx27_fb_data);
imx27_add_mxc_mmc(0, &sdhc_pdata);
i2c_register_board_info(0, eukrea_mbimx27_i2c_devices,
ARRAY_SIZE(eukrea_mbimx27_i2c_devices));
......@@ -386,7 +383,7 @@ void __init eukrea_mbimx27_baseboard_init(void)
gpio_request(GPIO_PORTA | 25, "lcd_enable");
platform_device_register(&eukrea_mbimx27_lcd_powerdev);
mxc_register_device(&imx_kpp_device, &eukrea_mbimx27_keymap_data);
imx27_add_imx_keypad(&eukrea_mbimx27_keymap_data);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
}
arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c → arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
View file @ 2a85927c
......@@ -33,11 +33,9 @@
#include <asm/mach/arch.h>
#include <mach/mx25.h>
#include <mach/imx-uart.h>
#include <mach/imxfb.h>
#include <mach/audmux.h>
#include "devices-imx25.h"
#include "devices.h"
static struct pad_desc eukrea_mbimxsd_pads[] = {
/* LCD */
......@@ -151,7 +149,7 @@ static struct imx_fb_videomode eukrea_mximxsd_modes[] = {
},
};
static struct imx_fb_platform_data eukrea_mximxsd_fb_pdata = {
static const struct imx_fb_platform_data eukrea_mximxsd_fb_pdata __initconst = {
.mode = eukrea_mximxsd_modes,
.num_modes = ARRAY_SIZE(eukrea_mximxsd_modes),
.pwmr = 0x00A903FF,
......@@ -273,11 +271,11 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
#endif
imx25_add_imx_uart1(&uart_pdata);
mxc_register_device(&mx25_fb_device, &eukrea_mximxsd_fb_pdata);
imx25_add_imx_fb(&eukrea_mximxsd_fb_pdata);
imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
imx25_add_flexcan1(NULL);
imx25_add_esdhc(0, NULL);
imx25_add_sdhci_esdhc_imx(0, NULL);
gpio_request(GPIO_LED1, "LED1");
gpio_direction_output(GPIO_LED1, 1);
......
arch/arm/mach-imx/mach-cpuimx27.c
View file @ 2a85927c
......@@ -28,7 +28,6 @@
#include <linux/serial_8250.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/fsl_devices.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
......@@ -40,11 +39,9 @@
#include <mach/hardware.h>
#include <mach/iomux-mx27.h>
#include <mach/mxc_nand.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include "devices-imx27.h"
#include "devices.h"
static const int eukrea_cpuimx27_pins[] __initconst = {
/* UART1 */
......@@ -157,8 +154,6 @@ cpuimx27_nand_board_info __initconst = {
static struct platform_device *platform_devices[] __initdata = {
&eukrea_cpuimx27_nor_mtd_device,
&mxc_wdt,
&mxc_w1_master_device,
};
static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = {
......@@ -215,18 +210,18 @@ static struct platform_device serial_device = {
#endif
#if defined(CONFIG_USB_ULPI)
static struct mxc_usbh_platform_data otg_pdata = {
static struct mxc_usbh_platform_data otg_pdata __initdata = {
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
static struct mxc_usbh_platform_data usbh2_pdata = {
static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
#endif
static struct fsl_usb2_platform_data otg_device_pdata = {
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_ULPI,
};
......@@ -262,10 +257,12 @@ static void __init eukrea_cpuimx27_init(void)
imx27_add_fec(NULL);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
imx27_add_imx2_wdt(NULL);
imx27_add_mxc_w1(NULL);
#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
/* SDHC2 can be used for Wifi */
mxc_register_device(&mxc_sdhc_device1, NULL);
imx27_add_mxc_mmc(1, NULL);
#endif
#if defined(MACH_EUKREA_CPUIMX27_USEUART4)
/* in which case UART4 is also used for Bluetooth */
......@@ -281,16 +278,16 @@ static void __init eukrea_cpuimx27_init(void)
otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_otg_host, &otg_pdata);
imx27_add_mxc_ehci_otg(&otg_pdata);
}
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
#endif
if (!otg_mode_host)
mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
imx27_add_fsl_usb2_udc(&otg_device_pdata);
#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
eukrea_mbimx27_baseboard_init();
......
arch/arm/mach-mx25/mach-cpuimx25.c → arch/arm/mach-imx/mach-eukrea_cpuimx25.c
View file @ 2a85927c
......@@ -26,7 +26,6 @@
#include <linux/platform_device.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/fsl_devices.h>
#include <mach/eukrea-baseboards.h>
#include <mach/hardware.h>
......@@ -39,11 +38,9 @@
#include <mach/mx25.h>
#include <mach/mxc_nand.h>
#include <mach/imxfb.h>
#include <mach/mxc_ehci.h>
#include <mach/iomux-mx25.h>
#include "devices-imx25.h"
#include "devices.h"
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
......@@ -87,18 +84,18 @@ static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = {
},
};
static struct mxc_usbh_platform_data otg_pdata = {
static const struct mxc_usbh_platform_data otg_pdata __initconst = {
.portsc = MXC_EHCI_MODE_UTMI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
static struct mxc_usbh_platform_data usbh2_pdata = {
static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
.portsc = MXC_EHCI_MODE_SERIAL,
.flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
MXC_EHCI_IPPUE_DOWN,
};
static struct fsl_usb2_platform_data otg_device_pdata = {
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_UTMI,
};
......@@ -126,7 +123,7 @@ static void __init eukrea_cpuimx25_init(void)
imx25_add_imx_uart0(&uart_pdata);
imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info);
mxc_register_device(&mx25_rtc_device, NULL);
imx25_add_imxdi_rtc(NULL);
imx25_add_fec(&mx25_fec_pdata);
i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices,
......@@ -134,11 +131,11 @@ static void __init eukrea_cpuimx25_init(void)
imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data);
if (otg_mode_host)
mxc_register_device(&mxc_otg, &otg_pdata);
imx25_add_mxc_ehci_otg(&otg_pdata);
else
mxc_register_device(&otg_udc_device, &otg_device_pdata);
imx25_add_fsl_usb2_udc(&otg_device_pdata);
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
imx25_add_mxc_ehci_hs(&usbh2_pdata);
#ifdef CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD
eukrea_mbimxsd25_baseboard_init();
......
arch/arm/mach-imx/mach-imx27_visstrim_m10.c
View file @ 2a85927c
......@@ -34,12 +34,9 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/common.h>
#include <mach/mmc.h>
#include <mach/iomux.h>
#include <mach/mxc_ehci.h>
#include "devices-imx27.h"
#include "devices.h"
#define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
#define SDHC1_IRQ IRQ_GPIOB(25)
......@@ -156,7 +153,7 @@ static void visstrim_m10_sdhc1_exit(struct device *dev, void *data)
free_irq(SDHC1_IRQ, data);
}
static struct imxmmc_platform_data visstrim_m10_sdhc_pdata = {
static const struct imxmmc_platform_data visstrim_m10_sdhc_pdata __initconst = {
.init = visstrim_m10_sdhc1_init,
.exit = visstrim_m10_sdhc1_exit,
};
......@@ -216,7 +213,8 @@ static int otg_phy_init(struct platform_device *pdev)
return 0;
}
static struct mxc_usbh_platform_data visstrim_m10_usbotg_pdata = {
static const struct mxc_usbh_platform_data
visstrim_m10_usbotg_pdata __initconst = {
.init = otg_phy_init,
.portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
.flags = MXC_EHCI_POWER_PINS_ENABLED,
......@@ -237,8 +235,8 @@ static void __init visstrim_m10_board_init(void)
ARRAY_SIZE(visstrim_m10_i2c_devices));
imx27_add_imx_i2c(0, &visstrim_m10_i2c_data);
imx27_add_imx_i2c(1, &visstrim_m10_i2c_data);
mxc_register_device(&mxc_sdhc_device0, &visstrim_m10_sdhc_pdata);
mxc_register_device(&mxc_otg_host, &visstrim_m10_usbotg_pdata);
imx27_add_mxc_mmc(0, &visstrim_m10_sdhc_pdata);
imx27_add_mxc_ehci_otg(&visstrim_m10_usbotg_pdata);
imx27_add_fec(NULL);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
}
......
arch/arm/mach-imx/mach-imx27lite.c
View file @ 2a85927c
......@@ -25,7 +25,6 @@
#include <mach/iomux-mx27.h>
#include "devices-imx27.h"
#include "devices.h"
static const int mx27lite_pins[] __initconst = {
/* UART1 */
......
arch/arm/mach-imx/mach-mx1ads.c
View file @ 2a85927c
......@@ -30,7 +30,6 @@
#include <mach/irqs.h>
#include "devices-imx1.h"
#include "devices.h"
static const int mx1ads_pins[] __initconst = {
/* UART1 */
......
arch/arm/mach-imx/mach-mx21ads.c
View file @ 2a85927c
......@@ -24,13 +24,10 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <mach/imxfb.h>
#include <mach/iomux-mx21.h>
#include <mach/mxc_nand.h>
#include <mach/mmc.h>
#include "devices-imx21.h"
#include "devices.h"
/*
* Memory-mapped I/O on MX21ADS base board
......@@ -213,7 +210,7 @@ static struct imx_fb_videomode mx21ads_modes[] = {
},
};
static struct imx_fb_platform_data mx21ads_fb_data = {
static const struct imx_fb_platform_data mx21ads_fb_data __initconst = {
.mode = mx21ads_modes,
.num_modes = ARRAY_SIZE(mx21ads_modes),
......@@ -233,15 +230,8 @@ static int mx21ads_sdhc_get_ro(struct device *dev)
static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
void *data)
{
int ret;
ret = request_irq(IRQ_GPIOD(25), detect_irq,
return request_irq(IRQ_GPIOD(25), detect_irq,
IRQF_TRIGGER_FALLING, "mmc-detect", data);
if (ret)
goto out;
return 0;
out:
return ret;
}
static void mx21ads_sdhc_exit(struct device *dev, void *data)
......@@ -249,7 +239,7 @@ static void mx21ads_sdhc_exit(struct device *dev, void *data)
free_irq(IRQ_GPIOD(25), data);
}
static struct imxmmc_platform_data mx21ads_sdhc_pdata = {
static const struct imxmmc_platform_data mx21ads_sdhc_pdata __initconst = {
.ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */
.get_ro = mx21ads_sdhc_get_ro,
.init = mx21ads_sdhc_init,
......@@ -296,8 +286,8 @@ static void __init mx21ads_board_init(void)
imx21_add_imx_uart0(&uart_pdata_rts);
imx21_add_imx_uart2(&uart_pdata_norts);
imx21_add_imx_uart3(&uart_pdata_rts);
mxc_register_device(&mxc_fb_device, &mx21ads_fb_data);
mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata);
imx21_add_imx_fb(&mx21ads_fb_data);
imx21_add_mxc_mmc(0, &mx21ads_sdhc_pdata);
imx21_add_mxc_nand(&mx21ads_nand_board_info);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
......
arch/arm/mach-mx25/mach-mx25_3ds.c → arch/arm/mach-imx/mach-mx25_3ds.c
View file @ 2a85927c
......@@ -39,11 +39,9 @@
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/mx25.h>
#include <mach/imxfb.h>
#include <mach/iomux-mx25.h>
#include "devices-imx25.h"
#include "devices.h"
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
......@@ -107,7 +105,7 @@ static struct pad_desc mx25pdk_pads[] = {
};
static const struct fec_platform_data mx25_fec_pdata __initconst = {
.phy = PHY_INTERFACE_MODE_RMII,
.phy = PHY_INTERFACE_MODE_RMII,
};
#define FEC_ENABLE_GPIO 35
......@@ -154,7 +152,7 @@ static struct imx_fb_videomode mx25pdk_modes[] = {
},
};
static struct imx_fb_platform_data mx25pdk_fb_pdata = {
static const struct imx_fb_platform_data mx25pdk_fb_pdata __initconst = {
.mode = mx25pdk_modes,
.num_modes = ARRAY_SIZE(mx25pdk_modes),
.pwmr = 0x00A903FF,
......@@ -181,7 +179,7 @@ static const uint32_t mx25pdk_keymap[] = {
KEY(3, 3, KEY_POWER),
};
static struct matrix_keymap_data mx25pdk_keymap_data = {
static const struct matrix_keymap_data mx25pdk_keymap_data __initdata = {
.keymap = mx25pdk_keymap,
.keymap_size = ARRAY_SIZE(mx25pdk_keymap),
};
......@@ -192,17 +190,17 @@ static void __init mx25pdk_init(void)
ARRAY_SIZE(mx25pdk_pads));
imx25_add_imx_uart0(&uart_pdata);
mxc_register_device(&mxc_usbh2, NULL);
imx25_add_mxc_ehci_hs(NULL);
imx25_add_mxc_nand(&mx25pdk_nand_board_info);
mxc_register_device(&mx25_rtc_device, NULL);
mxc_register_device(&mx25_fb_device, &mx25pdk_fb_pdata);
mxc_register_device(&mxc_wdt, NULL);
imx25_add_imxdi_rtc(NULL);
imx25_add_imx_fb(&mx25pdk_fb_pdata);
imx25_add_imx2_wdt(NULL);
mx25pdk_fec_reset();
imx25_add_fec(&mx25_fec_pdata);
mxc_register_device(&mx25_kpp_device, &mx25pdk_keymap_data);
imx25_add_imx_keypad(&mx25pdk_keymap_data);
imx25_add_esdhc(0, NULL);
imx25_add_sdhci_esdhc_imx(0, NULL);
}
static void __init mx25pdk_timer_init(void)
......
arch/arm/mach-imx/mach-mx27_3ds.c
View file @ 2a85927c
......@@ -22,7 +22,6 @@
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/input/matrix_keypad.h>
#include <linux/irq.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
......@@ -30,10 +29,8 @@
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/iomux-mx27.h>
#include <mach/mmc.h>
#include "devices-imx27.h"
#include "devices.h"
#define SD1_EN_GPIO (GPIO_PORTB + 25)
......@@ -92,7 +89,7 @@ static const uint32_t mx27_3ds_keymap[] = {
KEY(2, 3, KEY_F10),
};
static struct matrix_keymap_data mx27_3ds_keymap_data = {
static const struct matrix_keymap_data mx27_3ds_keymap_data __initconst = {
.keymap = mx27_3ds_keymap,
.keymap_size = ARRAY_SIZE(mx27_3ds_keymap),
};
......@@ -109,7 +106,7 @@ static void mx27_3ds_sdhc1_exit(struct device *dev, void *data)
free_irq(IRQ_GPIOB(26), data);
}
static struct imxmmc_platform_data sdhc1_pdata = {
static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
.init = mx27_3ds_sdhc1_init,
.exit = mx27_3ds_sdhc1_exit,
};
......@@ -128,8 +125,8 @@ static void __init mx27pdk_init(void)
mx27_3ds_sdhc1_enable_level_translator();
imx27_add_imx_uart0(&uart_pdata);
imx27_add_fec(NULL);
mxc_register_device(&imx_kpp_device, &mx27_3ds_keymap_data);
mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
imx27_add_imx_keypad(&mx27_3ds_keymap_data);
imx27_add_mxc_mmc(0, &sdhc1_pdata);
}
static void __init mx27pdk_timer_init(void)
......
arch/arm/mach-imx/mach-mx27ads.c
View file @ 2a85927c
......@@ -30,11 +30,8 @@
#include <mach/gpio.h>
#include <mach/iomux-mx27.h>
#include <mach/mxc_nand.h>
#include <mach/imxfb.h>
#include <mach/mmc.h>
#include "devices-imx27.h"
#include "devices.h"
/*
* Base address of PBC controller, CS4
......@@ -228,7 +225,7 @@ static struct imx_fb_videomode mx27ads_modes[] = {
},
};
static struct imx_fb_platform_data mx27ads_fb_data = {
static const struct imx_fb_platform_data mx27ads_fb_data __initconst = {
.mode = mx27ads_modes,
.num_modes = ARRAY_SIZE(mx27ads_modes),
......@@ -272,19 +269,18 @@ static void mx27ads_sdhc2_exit(struct device *dev, void *data)
free_irq(IRQ_GPIOB(7), data);
}
static struct imxmmc_platform_data sdhc1_pdata = {
static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
.init = mx27ads_sdhc1_init,
.exit = mx27ads_sdhc1_exit,
};
static struct imxmmc_platform_data sdhc2_pdata = {
static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
.init = mx27ads_sdhc2_init,
.exit = mx27ads_sdhc2_exit,
};
static struct platform_device *platform_devices[] __initdata = {
&mx27ads_nor_mtd_device,
&mxc_w1_master_device,
};
static const struct imxuart_platform_data uart_pdata __initconst = {
......@@ -308,12 +304,13 @@ static void __init mx27ads_board_init(void)
i2c_register_board_info(1, mx27ads_i2c_devices,
ARRAY_SIZE(mx27ads_i2c_devices));
imx27_add_imx_i2c(1, &mx27ads_i2c1_data);
mxc_register_device(&mxc_fb_device, &mx27ads_fb_data);
mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata);
imx27_add_imx_fb(&mx27ads_fb_data);
imx27_add_mxc_mmc(0, &sdhc1_pdata);
imx27_add_mxc_mmc(1, &sdhc2_pdata);
imx27_add_fec(NULL);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
imx27_add_mxc_w1(NULL);
}
static void __init mx27ads_timer_init(void)
......
arch/arm/mach-imx/mach-mxt_td60.c
View file @ 2a85927c
......@@ -31,11 +31,8 @@
#include <mach/iomux-mx27.h>
#include <mach/mxc_nand.h>
#include <linux/i2c/pca953x.h>
#include <mach/imxfb.h>
#include <mach/mmc.h>
#include "devices-imx27.h"
#include "devices.h"
static const int mxt_td60_pins[] __initconst = {
/* UART0 */
......@@ -196,7 +193,7 @@ static struct imx_fb_videomode mxt_td60_modes[] = {
},
};
static struct imx_fb_platform_data mxt_td60_fb_data = {
static const struct imx_fb_platform_data mxt_td60_fb_data __initconst = {
.mode = mxt_td60_modes,
.num_modes = ARRAY_SIZE(mxt_td60_modes),
......@@ -226,7 +223,7 @@ static void mxt_td60_sdhc1_exit(struct device *dev, void *data)
free_irq(IRQ_GPIOF(8), data);
}
static struct imxmmc_platform_data sdhc1_pdata = {
static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
.init = mxt_td60_sdhc1_init,
.exit = mxt_td60_sdhc1_exit,
};
......@@ -253,8 +250,8 @@ static void __init mxt_td60_board_init(void)
imx27_add_imx_i2c(0, &mxt_td60_i2c0_data);
imx27_add_imx_i2c(1, &mxt_td60_i2c1_data);
mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data);
mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
imx27_add_imx_fb(&mxt_td60_fb_data);
imx27_add_mxc_mmc(0, &sdhc1_pdata);
imx27_add_fec(NULL);
}
......
arch/arm/mach-imx/mach-pca100.c
View file @ 2a85927c
......@@ -29,7 +29,6 @@
#include <linux/gpio.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/fsl_devices.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
......@@ -40,13 +39,9 @@
#include <mach/audmux.h>
#include <mach/mxc_nand.h>
#include <mach/irqs.h>
#include <mach/mmc.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include <mach/imxfb.h>
#include "devices-imx27.h"
#include "devices.h"
#define OTG_PHY_CS_GPIO (GPIO_PORTB + 23)
#define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24)
......@@ -171,11 +166,6 @@ pca100_nand_board_info __initconst = {
.hw_ecc = 1,
};
static struct platform_device *platform_devices[] __initdata = {
&mxc_w1_master_device,
&mxc_wdt,
};
static const struct imxi2c_platform_data pca100_i2c1_data __initconst = {
.bitrate = 100000,
};
......@@ -274,7 +264,7 @@ static void pca100_sdhc2_exit(struct device *dev, void *data)
free_irq(IRQ_GPIOC(29), data);
}
static struct imxmmc_platform_data sdhc_pdata = {
static const struct imxmmc_platform_data sdhc_pdata __initconst = {
.init = pca100_sdhc2_init,
.exit = pca100_sdhc2_exit,
};
......@@ -286,7 +276,7 @@ static int otg_phy_init(struct platform_device *pdev)
return 0;
}
static struct mxc_usbh_platform_data otg_pdata = {
static struct mxc_usbh_platform_data otg_pdata __initdata = {
.init = otg_phy_init,
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
......@@ -298,14 +288,14 @@ static int usbh2_phy_init(struct platform_device *pdev)
return 0;
}
static struct mxc_usbh_platform_data usbh2_pdata = {
static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
.init = usbh2_phy_init,
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
#endif
static struct fsl_usb2_platform_data otg_device_pdata = {
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_ULPI,
};
......@@ -355,7 +345,7 @@ static struct imx_fb_videomode pca100_fb_modes[] = {
},
};
static struct imx_fb_platform_data pca100_fb_data = {
static const struct imx_fb_platform_data pca100_fb_data __initconst = {
.mode = pca100_fb_modes,
.num_modes = ARRAY_SIZE(pca100_fb_modes),
......@@ -389,7 +379,7 @@ static void __init pca100_init(void)
imx27_add_imx_uart0(&uart_pdata);
mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
imx27_add_mxc_mmc(1, &sdhc_pdata);
imx27_add_mxc_nand(&pca100_nand_board_info);
......@@ -417,23 +407,24 @@ static void __init pca100_init(void)
otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_otg_host, &otg_pdata);
imx27_add_mxc_ehci_otg(&otg_pdata);
}
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
#endif
if (!otg_mode_host) {
gpio_set_value(OTG_PHY_CS_GPIO, 0);
mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
imx27_add_fsl_usb2_udc(&otg_device_pdata);
}
mxc_register_device(&mxc_fb_device, &pca100_fb_data);
imx27_add_imx_fb(&pca100_fb_data);
imx27_add_fec(NULL);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
imx27_add_imx2_wdt(NULL);
imx27_add_mxc_w1(NULL);
}
static void __init pca100_timer_init(void)
......
arch/arm/mach-imx/mach-pcm038.c
View file @ 2a85927c
......@@ -37,11 +37,9 @@
#include <mach/hardware.h>
#include <mach/iomux-mx27.h>
#include <mach/mxc_nand.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include "devices-imx27.h"
#include "devices.h"
static const int pcm038_pins[] __initconst = {
/* UART1 */
......@@ -172,9 +170,7 @@ pcm038_nand_board_info __initconst = {
static struct platform_device *platform_devices[] __initdata = {
&pcm038_nor_mtd_device,
&mxc_w1_master_device,
&pcm038_sram_mtd_device,
&mxc_wdt,
};
/* On pcm038 there's a sram attached to CS1, we enable the chipselect here and
......@@ -214,7 +210,7 @@ static const struct spi_imx_master pcm038_spi0_data __initconst = {
static struct regulator_consumer_supply sdhc1_consumers[] = {
{
.dev = &mxc_sdhc_device1.dev,
.dev_name = "mxc-mmc.1",
.supply = "sdhc_vcc",
},
};
......@@ -285,7 +281,7 @@ static struct spi_board_info pcm038_spi_board_info[] __initdata = {
}
};
static struct mxc_usbh_platform_data usbh2_pdata = {
static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
};
......@@ -322,10 +318,12 @@ static void __init pcm038_init(void)
spi_register_board_info(pcm038_spi_board_info,
ARRAY_SIZE(pcm038_spi_board_info));
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
imx27_add_fec(NULL);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
imx27_add_imx2_wdt(NULL);
imx27_add_mxc_w1(NULL);
#ifdef CONFIG_MACH_PCM970_BASEBOARD
pcm970_baseboard_init();
......
arch/arm/mach-imx/mach-scb9328.c
View file @ 2a85927c
......@@ -25,7 +25,6 @@
#include <mach/iomux-mx1.h>
#include "devices-imx1.h"
#include "devices.h"
/*
* This scb9328 has a 32MiB flash
......
arch/arm/mach-imx/mm-imx1.c
View file @ 2a85927c
......@@ -25,12 +25,7 @@
#include <mach/hardware.h>
static struct map_desc imx_io_desc[] __initdata = {
{
.virtual = MX1_IO_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX1_IO_BASE_ADDR),
.length = MX1_IO_SIZE,
.type = MT_DEVICE
}
imx_map_entry(MX1, IO, MT_DEVICE),
};
void __init mx1_map_io(void)
......
arch/arm/mach-imx/mm-imx21.c
View file @ 2a85927c
......@@ -35,33 +35,18 @@ static struct map_desc imx21_io_desc[] __initdata = {
* - ROM Patch
* - and some reserved space
*/
{
.virtual = MX21_AIPI_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX21_AIPI_BASE_ADDR),
.length = MX21_AIPI_SIZE,
.type = MT_DEVICE
},
imx_map_entry(MX21, AIPI, MT_DEVICE),
/*
* this fixed mapping covers:
* - CSI
* - ATA
*/
{
.virtual = MX21_SAHB1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX21_SAHB1_BASE_ADDR),
.length = MX21_SAHB1_SIZE,
.type = MT_DEVICE
},
imx_map_entry(MX21, SAHB1, MT_DEVICE),
/*
* this fixed mapping covers:
* - EMI
*/
{
.virtual = MX21_X_MEMC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX21_X_MEMC_BASE_ADDR),
.length = MX21_X_MEMC_SIZE,
.type = MT_DEVICE
},
imx_map_entry(MX21, X_MEMC, MT_DEVICE),
};
/*
......
arch/arm/mach-mx25/mm.c → arch/arm/mach-imx/mm-imx25.c
View file @ 2a85927c
......@@ -30,25 +30,12 @@
/*
* This table defines static virtual address mappings for I/O regions.
* These are the mappings common across all MX3 boards.
* These are the mappings common across all MX25 boards.
*/
static struct map_desc mxc_io_desc[] __initdata = {
{
.virtual = MX25_AVIC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX25_AVIC_BASE_ADDR),
.length = MX25_AVIC_SIZE,
.type = MT_DEVICE_NONSHARED
}, {
.virtual = MX25_AIPS1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX25_AIPS1_BASE_ADDR),
.length = MX25_AIPS1_SIZE,
.type = MT_DEVICE_NONSHARED
}, {
.virtual = MX25_AIPS2_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX25_AIPS2_BASE_ADDR),
.length = MX25_AIPS2_SIZE,
.type = MT_DEVICE_NONSHARED
},
static struct map_desc mx25_io_desc[] __initdata = {
imx_map_entry(MX25, AVIC, MT_DEVICE_NONSHARED),
imx_map_entry(MX25, AIPS1, MT_DEVICE_NONSHARED),
imx_map_entry(MX25, AIPS2, MT_DEVICE_NONSHARED),
};
/*
......@@ -62,14 +49,14 @@ void __init mx25_map_io(void)
mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc));
}
int imx25_register_gpios(void);
void __init mx25_init_irq(void)
{
mxc_init_irq((void __iomem *)MX25_AVIC_BASE_ADDR_VIRT);
mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR));
imx25_register_gpios();
}
arch/arm/mach-imx/mm-imx27.c
View file @ 2a85927c
......@@ -35,33 +35,18 @@ static struct map_desc imx27_io_desc[] __initdata = {
* - ROM Patch
* - and some reserved space
*/
{
.virtual = MX27_AIPI_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX27_AIPI_BASE_ADDR),
.length = MX27_AIPI_SIZE,
.type = MT_DEVICE
},
imx_map_entry(MX27, AIPI, MT_DEVICE),
/*
* this fixed mapping covers:
* - CSI
* - ATA
*/
{
.virtual = MX27_SAHB1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX27_SAHB1_BASE_ADDR),
.length = MX27_SAHB1_SIZE,
.type = MT_DEVICE
},
imx_map_entry(MX27, SAHB1, MT_DEVICE),
/*
* this fixed mapping covers:
* - EMI
*/
{
.virtual = MX27_X_MEMC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX27_X_MEMC_BASE_ADDR),
.length = MX27_X_MEMC_SIZE,
.type = MT_DEVICE
},
imx_map_entry(MX27, X_MEMC, MT_DEVICE),
};
/*
......
arch/arm/mach-imx/pcm970-baseboard.c
View file @ 2a85927c
......@@ -25,11 +25,9 @@
#include <mach/common.h>
#include <mach/iomux-mx27.h>
#include <mach/imxfb.h>
#include <mach/hardware.h>
#include <mach/mmc.h>
#include "devices.h"
#include "devices-imx27.h"
static const int pcm970_pins[] __initconst = {
/* SDHC */
......@@ -119,7 +117,7 @@ static void pcm970_sdhc2_exit(struct device *dev, void *data)
gpio_free(GPIO_PORTC + 28);
}
static struct imxmmc_platform_data sdhc_pdata = {
static const struct imxmmc_platform_data sdhc_pdata __initconst = {
.get_ro = pcm970_sdhc2_get_ro,
.init = pcm970_sdhc2_init,
.exit = pcm970_sdhc2_exit,
......@@ -179,7 +177,7 @@ static struct imx_fb_videomode pcm970_modes[] = {
},
};
static struct imx_fb_platform_data pcm038_fb_data = {
static const struct imx_fb_platform_data pcm038_fb_data __initconst = {
.mode = pcm970_modes,
.num_modes = ARRAY_SIZE(pcm970_modes),
......@@ -226,8 +224,8 @@ void __init pcm970_baseboard_init(void)
mxc_gpio_setup_multiple_pins(pcm970_pins, ARRAY_SIZE(pcm970_pins),
"PCM970");
mxc_register_device(&mxc_fb_device, &pcm038_fb_data);
imx27_add_imx_fb(&pcm038_fb_data);
mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN);
mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
imx27_add_mxc_mmc(1, &sdhc_pdata);
platform_device_register(&pcm970_sja1000);
}
arch/arm/mach-mx25/Kconfig deleted 100644 → 0
View file @ 3561d43f
if ARCH_MX25
comment "MX25 platforms:"
config MACH_MX25_3DS
bool "Support MX25PDK (3DS) Platform"
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_ESDHC
config MACH_EUKREA_CPUIMX25
bool "Support Eukrea CPUIMX25 Platform"
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_ESDHC
select MXC_ULPI if USB_ULPI
choice
prompt "Baseboard"
depends on MACH_EUKREA_CPUIMX25
default MACH_EUKREA_MBIMXSD25_BASEBOARD
config MACH_EUKREA_MBIMXSD25_BASEBOARD
bool "Eukrea MBIMXSD development board"
select IMX_HAVE_PLATFORM_IMX_SSI
help
This adds board specific devices that can be found on Eukrea's
MBIMXSD evaluation board.
endchoice
endif
arch/arm/mach-mx25/Makefile deleted 100644 → 0
View file @ 3561d43f
obj-y := mm.o devices.o
obj-$(CONFIG_ARCH_MX25) += clock.o
obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-cpuimx25.o
obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd-baseboard.o
arch/arm/mach-mx25/Makefile.boot deleted 100644 → 0
View file @ 3561d43f
zreladdr-y := 0x80008000
params_phys-y := 0x80000100
initrd_phys-y := 0x80800000
arch/arm/mach-mx25/devices.c deleted 100644 → 0
View file @ 3561d43f
/*
* Copyright 2009 Sascha Hauer, <kernel@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor,
* Boston, MA 02110-1301, USA.
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/gpio.h>
#include <mach/mx25.h>
#include <mach/irqs.h>
static u64 otg_dmamask = DMA_BIT_MASK(32);
static struct resource mxc_otg_resources[] = {
{
.start = MX25_OTG_BASE_ADDR,
.end = MX25_OTG_BASE_ADDR + 0x1ff,
.flags = IORESOURCE_MEM,
}, {
.start = 37,
.end = 37,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_otg = {
.name = "mxc-ehci",
.id = 0,
.dev = {
.coherent_dma_mask = 0xffffffff,
.dma_mask = &otg_dmamask,
},
.resource = mxc_otg_resources,
.num_resources = ARRAY_SIZE(mxc_otg_resources),
};
/* OTG gadget device */
struct platform_device otg_udc_device = {
.name = "fsl-usb2-udc",
.id = -1,
.dev = {
.dma_mask = &otg_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.resource = mxc_otg_resources,
.num_resources = ARRAY_SIZE(mxc_otg_resources),
};
static u64 usbh2_dmamask = DMA_BIT_MASK(32);
static struct resource mxc_usbh2_resources[] = {
{
.start = MX25_OTG_BASE_ADDR + 0x400,
.end = MX25_OTG_BASE_ADDR + 0x5ff,
.flags = IORESOURCE_MEM,
}, {
.start = 35,
.end = 35,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_usbh2 = {
.name = "mxc-ehci",
.id = 1,
.dev = {
.coherent_dma_mask = 0xffffffff,
.dma_mask = &usbh2_dmamask,
},
.resource = mxc_usbh2_resources,
.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
};
static struct resource mxc_pwm_resources0[] = {
{
.start = 0x53fe0000,
.end = 0x53fe3fff,
.flags = IORESOURCE_MEM,
}, {
.start = 26,
.end = 26,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_pwm_device0 = {
.name = "mxc_pwm",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_pwm_resources0),
.resource = mxc_pwm_resources0,
};
static struct resource mxc_pwm_resources1[] = {
{
.start = 0x53fa0000,
.end = 0x53fa3fff,
.flags = IORESOURCE_MEM,
}, {
.start = 36,
.end = 36,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_pwm_device1 = {
.name = "mxc_pwm",
.id = 1,
.num_resources = ARRAY_SIZE(mxc_pwm_resources1),
.resource = mxc_pwm_resources1,
};
static struct resource mxc_pwm_resources2[] = {
{
.start = 0x53fa8000,
.end = 0x53fabfff,
.flags = IORESOURCE_MEM,
}, {
.start = 41,
.end = 41,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_pwm_device2 = {
.name = "mxc_pwm",
.id = 2,
.num_resources = ARRAY_SIZE(mxc_pwm_resources2),
.resource = mxc_pwm_resources2,
};
static struct resource mxc_keypad_resources[] = {
{
.start = 0x43fa8000,
.end = 0x43fabfff,
.flags = IORESOURCE_MEM,
}, {
.start = 24,
.end = 24,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_keypad_device = {
.name = "mxc-keypad",
.id = -1,
.num_resources = ARRAY_SIZE(mxc_keypad_resources),
.resource = mxc_keypad_resources,
};
static struct resource mxc_pwm_resources3[] = {
{
.start = 0x53fc8000,
.end = 0x53fcbfff,
.flags = IORESOURCE_MEM,
}, {
.start = 42,
.end = 42,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device mxc_pwm_device3 = {
.name = "mxc_pwm",
.id = 3,
.num_resources = ARRAY_SIZE(mxc_pwm_resources3),
.resource = mxc_pwm_resources3,
};
static struct mxc_gpio_port imx_gpio_ports[] = {
{
.chip.label = "gpio-0",
.base = (void __iomem *)MX25_GPIO1_BASE_ADDR_VIRT,
.irq = 52,
.virtual_irq_start = MXC_GPIO_IRQ_START,
}, {
.chip.label = "gpio-1",
.base = (void __iomem *)MX25_GPIO2_BASE_ADDR_VIRT,
.irq = 51,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
}, {
.chip.label = "gpio-2",
.base = (void __iomem *)MX25_GPIO3_BASE_ADDR_VIRT,
.irq = 16,
.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
}, {
.chip.label = "gpio-3",
.base = (void __iomem *)MX25_GPIO4_BASE_ADDR_VIRT,
.irq = 23,
.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
}
};
int __init imx25_register_gpios(void)
{
return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
}
static struct resource mx25_rtc_resources[] = {
{
.start = MX25_DRYICE_BASE_ADDR,
.end = MX25_DRYICE_BASE_ADDR + 0x40,
.flags = IORESOURCE_MEM,
},
{
.start = MX25_INT_DRYICE,
.flags = IORESOURCE_IRQ
},
};
struct platform_device mx25_rtc_device = {
.name = "imxdi_rtc",
.id = 0,
.num_resources = ARRAY_SIZE(mx25_rtc_resources),
.resource = mx25_rtc_resources,
};
static struct resource mx25_fb_resources[] = {
{
.start = MX25_LCDC_BASE_ADDR,
.end = MX25_LCDC_BASE_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
},
{
.start = MX25_INT_LCDC,
.end = MX25_INT_LCDC,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mx25_fb_device = {
.name = "imx-fb",
.id = 0,
.resource = mx25_fb_resources,
.num_resources = ARRAY_SIZE(mx25_fb_resources),
.dev = {
.coherent_dma_mask = 0xFFFFFFFF,
},
};
static struct resource mxc_wdt_resources[] = {
{
.start = MX25_WDOG_BASE_ADDR,
.end = MX25_WDOG_BASE_ADDR + SZ_16K - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device mxc_wdt = {
.name = "imx2-wdt",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_wdt_resources),
.resource = mxc_wdt_resources,
};
static struct resource mx25_kpp_resources[] = {
{
.start = MX25_KPP_BASE_ADDR,
.end = MX25_KPP_BASE_ADDR + 0xf,
.flags = IORESOURCE_MEM,
},
{
.start = MX25_INT_KPP,
.end = MX25_INT_KPP,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mx25_kpp_device = {
.name = "imx-keypad",
.id = -1,
.num_resources = ARRAY_SIZE(mx25_kpp_resources),
.resource = mx25_kpp_resources,
};
static struct resource mx25_csi_resources[] = {
{
.start = MX25_CSI_BASE_ADDR,
.end = MX25_CSI_BASE_ADDR + 0xfff,
.flags = IORESOURCE_MEM,
},
{
.start = MX25_INT_CSI,
.flags = IORESOURCE_IRQ
},
};
struct platform_device mx25_csi_device = {
.name = "mx2-camera",
.id = 0,
.num_resources = ARRAY_SIZE(mx25_csi_resources),
.resource = mx25_csi_resources,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
};
arch/arm/mach-mx25/devices.h deleted 100644 → 0
View file @ 3561d43f
extern struct platform_device mxc_otg;
extern struct platform_device otg_udc_device;
extern struct platform_device mxc_usbh2;
extern struct platform_device mxc_pwm_device0;
extern struct platform_device mxc_pwm_device1;
extern struct platform_device mxc_pwm_device2;
extern struct platform_device mxc_pwm_device3;
extern struct platform_device mxc_keypad_device;
extern struct platform_device mx25_rtc_device;
extern struct platform_device mx25_fb_device;
extern struct platform_device mxc_wdt;
extern struct platform_device mx25_kpp_device;
extern struct platform_device mx25_csi_device;
arch/arm/mach-mx3/Kconfig
View file @ 2a85927c
if ARCH_MX3
# ARCH_MX31 and ARCH_MX35 are left for compatibility
# Some usages assume that having one of them implies not having (e.g.) ARCH_MX2.
# To easily distinguish good and reviewed from unreviewed usages new (and IMHO
# more sensible) names are used: SOC_IMX31 and SOC_IMX35
config ARCH_MX31
select ARCH_HAS_RNGA
select ARCH_MXC_AUDMUX_V2
bool
config ARCH_MX35
bool
config SOC_IMX31
bool
select IMX_HAVE_PLATFORM_MXC_RNGA
select ARCH_MXC_AUDMUX_V2
select ARCH_MX31
config SOC_IMX35
bool
select ARCH_MXC_IOMUX_V3
select ARCH_MXC_AUDMUX_V2
select HAVE_EPIT
select ARCH_MX35
comment "MX3 platforms:"
config MACH_MX31ADS
bool "Support MX31ADS platforms"
select ARCH_MX31
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
......@@ -37,10 +49,15 @@ config MACH_MX31ADS_WM1133_EV1
config MACH_PCM037
bool "Support Phytec pcm037 (i.MX31) platforms"
select ARCH_MX31
select SOC_IMX31
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_W1
select MXC_ULPI if USB_ULPI
help
Include support for Phytec pcm037 platform. This includes
......@@ -57,9 +74,12 @@ config MACH_PCM037_EET
config MACH_MX31LITE
bool "Support MX31 LITEKIT (LogicPD)"
select ARCH_MX31
select SOC_IMX31
select MXC_ULPI if USB_ULPI
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SPI_IMX
help
......@@ -68,8 +88,10 @@ config MACH_MX31LITE
config MACH_MX31_3DS
bool "Support MX31PDK (3DS)"
select ARCH_MX31
select SOC_IMX31
select MXC_DEBUG_BOARD
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX_KEYPAD
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SPI_IMX
......@@ -88,9 +110,12 @@ config MACH_MX31_3DS_MXC_NAND_USE_BBT
config MACH_MX31MOBOARD
bool "Support mx31moboard platforms (EPFL Mobots group)"
select ARCH_MX31
select SOC_IMX31
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
......@@ -99,8 +124,10 @@ config MACH_MX31MOBOARD
config MACH_MX31LILLY
bool "Support MX31 LILLY-1131 platforms (INCO startec)"
select ARCH_MX31
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
help
......@@ -109,7 +136,7 @@ config MACH_MX31LILLY
config MACH_QONG
bool "Support Dave/DENX QongEVB-LITE platform"
select ARCH_MX31
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_UART
help
Include support for Dave/DENX QongEVB-LITE platform. This includes
......@@ -117,13 +144,16 @@ config MACH_QONG
config MACH_PCM043
bool "Support Phytec pcm043 (i.MX35) platforms"
select ARCH_MX35
select SOC_IMX35
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_ESDHC
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select MXC_ULPI if USB_ULPI
help
Include support for Phytec pcm043 platform. This includes
......@@ -131,9 +161,11 @@ config MACH_PCM043
config MACH_ARMADILLO5X0
bool "Support Atmark Armadillo-500 Development Base Board"
select ARCH_MX31
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_MXC_NAND
select MXC_ULPI if USB_ULPI
help
......@@ -142,19 +174,21 @@ config MACH_ARMADILLO5X0
config MACH_MX35_3DS
bool "Support MX35PDK platform"
select ARCH_MX35
select SOC_IMX35
select MXC_DEBUG_BOARD
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_ESDHC
default n
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
help
Include support for MX35PDK platform. This includes specific
configurations for the board and its peripherals.
config MACH_KZM_ARM11_01
bool "Support KZM-ARM11-01(Kyoto Microcomputer)"
select ARCH_MX31
select SOC_IMX31
select IMX_HAVE_PLATFORM_IMX_UART
help
Include support for KZM-ARM11-01. This includes specific
......@@ -162,12 +196,15 @@ config MACH_KZM_ARM11_01
config MACH_EUKREA_CPUIMX35
bool "Support Eukrea CPUIMX35 Platform"
select ARCH_MX35
select IMX_HAVE_PLATFORM_IMX_UART
select SOC_IMX35
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_FLEXCAN
select IMX_HAVE_PLATFORM_ESDHC
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select MXC_ULPI if USB_ULPI
help
Include support for Eukrea CPUIMX35 platform. This includes
......
arch/arm/mach-mx3/Makefile
View file @ 2a85927c
......@@ -5,17 +5,14 @@
# Object file lists.
obj-y := mm.o devices.o cpu.o
CFLAGS_mm.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
obj-$(CONFIG_ARCH_MX31) += clock-imx31.o iomux-imx31.o
obj-$(CONFIG_ARCH_MX35) += clock-imx35.o
obj-$(CONFIG_SOC_IMX31) += clock-imx31.o iomux-imx31.o
obj-$(CONFIG_SOC_IMX35) += clock-imx35.o
obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o
obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o
obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o
obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o
obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o
obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o
CFLAGS_mach-mx31_3ds.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \
mx31moboard-marxbot.o mx31moboard-smartbot.o
obj-$(CONFIG_MACH_QONG) += mach-qong.o
......
arch/arm/mach-mx3/devices-imx31.h
View file @ 2a85927c
......@@ -9,6 +9,14 @@
#include <mach/mx31.h>
#include <mach/devices-common.h>
extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst;
#define imx31_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata)
extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst;
#define imx31_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx31_imx2_wdt_data)
extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst;
#define imx31_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata)
......@@ -16,6 +24,10 @@ extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst;
#define imx31_add_imx_i2c1(pdata) imx31_add_imx_i2c(1, pdata)
#define imx31_add_imx_i2c2(pdata) imx31_add_imx_i2c(2, pdata)
extern const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst;
#define imx31_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx31_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst;
#define imx31_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata)
......@@ -29,10 +41,25 @@ extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst;
#define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata)
#define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata)
extern const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst;
#define imx31_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx31_mxc_ehci_otg_data, pdata)
extern const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst;
#define imx31_add_mxc_ehci_hs(id, pdata) \
imx_add_mxc_ehci(&imx31_mxc_ehci_hs_data[id - 1], pdata)
extern const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst;
#define imx31_add_mxc_mmc(id, pdata) \
imx_add_mxc_mmc(&imx31_mxc_mmc_data[id], pdata)
extern const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst;
#define imx31_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx31_mxc_nand_data, pdata)
extern const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst;
#define imx31_add_mxc_w1(pdata) \
imx_add_mxc_w1(&imx31_mxc_w1_data)
extern const struct imx_spi_imx_data imx31_cspi_data[] __initconst;
#define imx31_add_cspi(id, pdata) \
imx_add_spi_imx(&imx31_cspi_data[id], pdata)
......
arch/arm/mach-mx3/devices-imx35.h
View file @ 2a85927c
......@@ -13,10 +13,19 @@ extern const struct imx_fec_data imx35_fec_data __initconst;
#define imx35_add_fec(pdata) \
imx_add_fec(&imx35_fec_data, pdata)
#define imx35_add_flexcan0(pdata) \
imx_add_flexcan(0, MX35_CAN1_BASE_ADDR, SZ_16K, MX35_INT_CAN1, pdata)
#define imx35_add_flexcan1(pdata) \
imx_add_flexcan(1, MX35_CAN2_BASE_ADDR, SZ_16K, MX35_INT_CAN2, pdata)
extern const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst;
#define imx35_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx35_fsl_usb2_udc_data, pdata)
extern const struct imx_flexcan_data imx35_flexcan_data[] __initconst;
#define imx35_add_flexcan(id, pdata) \
imx_add_flexcan(&imx35_flexcan_data[id], pdata)
#define imx35_add_flexcan0(pdata) imx35_add_flexcan(0, pdata)
#define imx35_add_flexcan1(pdata) imx35_add_flexcan(1, pdata)
extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst;
#define imx35_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx35_imx2_wdt_data)
extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst;
#define imx35_add_imx_i2c(id, pdata) \
......@@ -25,6 +34,10 @@ extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst;
#define imx35_add_imx_i2c1(pdata) imx35_add_imx_i2c(1, pdata)
#define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata)
extern const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst;
#define imx31_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx35_imx_keypad_data, pdata)
extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst;
#define imx35_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata)
......@@ -36,16 +49,28 @@ extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst;
#define imx35_add_imx_uart1(pdata) imx35_add_imx_uart(1, pdata)
#define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata)
extern const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst;
#define imx35_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx35_mxc_ehci_otg_data, pdata)
extern const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst;
#define imx35_add_mxc_ehci_hs(pdata) \
imx_add_mxc_ehci(&imx35_mxc_ehci_hs_data, pdata)
extern const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst;
#define imx35_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx35_mxc_nand_data, pdata)
extern const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst;
#define imx35_add_mxc_w1(pdata) \
imx_add_mxc_w1(&imx35_mxc_w1_data)
extern const struct imx_sdhci_esdhc_imx_data
imx35_sdhci_esdhc_imx_data[] __initconst;
#define imx35_add_sdhci_esdhc_imx(id, pdata) \
imx_add_sdhci_esdhc_imx(&imx35_sdhci_esdhc_imx_data[id], pdata)
extern const struct imx_spi_imx_data imx35_cspi_data[] __initconst;
#define imx35_add_cspi(id, pdata) \
imx_add_spi_imx(&imx35_cspi_data[id], pdata)
#define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata)
#define imx35_add_spi_imx1(pdata) imx35_add_cspi(1, pdata)
extern const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst;
#define imx35_add_esdhc(id, pdata) \
imx_add_esdhc(&imx35_esdhc_data[id], pdata)
arch/arm/mach-mx3/devices.c
View file @ 2a85927c
......@@ -29,120 +29,25 @@
#include "devices.h"
/* GPIO port description */
static struct mxc_gpio_port imx_gpio_ports[] = {
{
.chip.label = "gpio-0",
.base = IO_ADDRESS(GPIO1_BASE_ADDR),
.irq = MXC_INT_GPIO1,
.virtual_irq_start = MXC_GPIO_IRQ_START,
}, {
.chip.label = "gpio-1",
.base = IO_ADDRESS(GPIO2_BASE_ADDR),
.irq = MXC_INT_GPIO2,
.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
}, {
.chip.label = "gpio-2",
.base = IO_ADDRESS(GPIO3_BASE_ADDR),
.irq = MXC_INT_GPIO3,
.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
}
};
int __init imx3x_register_gpios(void)
{
return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
}
static struct resource mxc_w1_master_resources[] = {
{
.start = OWIRE_BASE_ADDR,
.end = OWIRE_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device mxc_w1_master_device = {
.name = "mxc_w1",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
.resource = mxc_w1_master_resources,
};
#ifdef CONFIG_ARCH_MX31
static struct resource mxcsdhc0_resources[] = {
{
.start = MX31_MMC_SDHC1_BASE_ADDR,
.end = MX31_MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = MX31_INT_MMC_SDHC1,
.end = MX31_INT_MMC_SDHC1,
.flags = IORESOURCE_IRQ,
},
};
static struct resource mxcsdhc1_resources[] = {
{
.start = MX31_MMC_SDHC2_BASE_ADDR,
.end = MX31_MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = MX31_INT_MMC_SDHC2,
.end = MX31_INT_MMC_SDHC2,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxcsdhc_device0 = {
.name = "mxc-mmc",
.id = 0,
.num_resources = ARRAY_SIZE(mxcsdhc0_resources),
.resource = mxcsdhc0_resources,
};
struct platform_device mxcsdhc_device1 = {
.name = "mxc-mmc",
.id = 1,
.num_resources = ARRAY_SIZE(mxcsdhc1_resources),
.resource = mxcsdhc1_resources,
};
static struct resource rnga_resources[] = {
{
.start = RNGA_BASE_ADDR,
.end = RNGA_BASE_ADDR + 0x28,
.flags = IORESOURCE_MEM,
},
};
struct platform_device mxc_rnga_device = {
.name = "mxc_rnga",
.id = -1,
.num_resources = 1,
.resource = rnga_resources,
};
#endif /* CONFIG_ARCH_MX31 */
/* i.MX31 Image Processing Unit */
/* The resource order is important! */
static struct resource mx3_ipu_rsrc[] = {
{
.start = IPU_CTRL_BASE_ADDR,
.end = IPU_CTRL_BASE_ADDR + 0x5F,
.start = MX3x_IPU_CTRL_BASE_ADDR,
.end = MX3x_IPU_CTRL_BASE_ADDR + 0x5F,
.flags = IORESOURCE_MEM,
}, {
.start = IPU_CTRL_BASE_ADDR + 0x88,
.end = IPU_CTRL_BASE_ADDR + 0xB3,
.start = MX3x_IPU_CTRL_BASE_ADDR + 0x88,
.end = MX3x_IPU_CTRL_BASE_ADDR + 0xB3,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_IPU_SYN,
.end = MXC_INT_IPU_SYN,
.start = MX3x_INT_IPU_SYN,
.end = MX3x_INT_IPU_SYN,
.flags = IORESOURCE_IRQ,
}, {
.start = MXC_INT_IPU_ERR,
.end = MXC_INT_IPU_ERR,
.start = MX3x_INT_IPU_ERR,
.end = MX3x_INT_IPU_ERR,
.flags = IORESOURCE_IRQ,
},
};
......@@ -156,8 +61,8 @@ struct platform_device mx3_ipu = {
static struct resource fb_resources[] = {
{
.start = IPU_CTRL_BASE_ADDR + 0xB4,
.end = IPU_CTRL_BASE_ADDR + 0x1BF,
.start = MX3x_IPU_CTRL_BASE_ADDR + 0xB4,
.end = MX3x_IPU_CTRL_BASE_ADDR + 0x1BF,
.flags = IORESOURCE_MEM,
},
};
......@@ -174,8 +79,8 @@ struct platform_device mx3_fb = {
static struct resource camera_resources[] = {
{
.start = IPU_CTRL_BASE_ADDR + 0x60,
.end = IPU_CTRL_BASE_ADDR + 0x87,
.start = MX3x_IPU_CTRL_BASE_ADDR + 0x60,
.end = MX3x_IPU_CTRL_BASE_ADDR + 0x87,
.flags = IORESOURCE_MEM,
},
};
......@@ -190,110 +95,6 @@ struct platform_device mx3_camera = {
},
};
static struct resource otg_resources[] = {
{
.start = MX31_OTG_BASE_ADDR,
.end = MX31_OTG_BASE_ADDR + 0x1ff,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_USB3,
.end = MXC_INT_USB3,
.flags = IORESOURCE_IRQ,
},
};
static u64 otg_dmamask = DMA_BIT_MASK(32);
/* OTG gadget device */
struct platform_device mxc_otg_udc_device = {
.name = "fsl-usb2-udc",
.id = -1,
.dev = {
.dma_mask = &otg_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = otg_resources,
.num_resources = ARRAY_SIZE(otg_resources),
};
/* OTG host */
struct platform_device mxc_otg_host = {
.name = "mxc-ehci",
.id = 0,
.dev = {
.coherent_dma_mask = 0xffffffff,
.dma_mask = &otg_dmamask,
},
.resource = otg_resources,
.num_resources = ARRAY_SIZE(otg_resources),
};
/* USB host 1 */
static u64 usbh1_dmamask = ~(u32)0;
static struct resource mxc_usbh1_resources[] = {
{
.start = MX31_OTG_BASE_ADDR + 0x200,
.end = MX31_OTG_BASE_ADDR + 0x3ff,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_USB1,
.end = MXC_INT_USB1,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_usbh1 = {
.name = "mxc-ehci",
.id = 1,
.dev = {
.coherent_dma_mask = 0xffffffff,
.dma_mask = &usbh1_dmamask,
},
.resource = mxc_usbh1_resources,
.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
};
/* USB host 2 */
static u64 usbh2_dmamask = ~(u32)0;
static struct resource mxc_usbh2_resources[] = {
{
.start = MX31_OTG_BASE_ADDR + 0x400,
.end = MX31_OTG_BASE_ADDR + 0x5ff,
.flags = IORESOURCE_MEM,
}, {
.start = MXC_INT_USB2,
.end = MXC_INT_USB2,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_usbh2 = {
.name = "mxc-ehci",
.id = 2,
.dev = {
.coherent_dma_mask = 0xffffffff,
.dma_mask = &usbh2_dmamask,
},
.resource = mxc_usbh2_resources,
.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
};
static struct resource imx_wdt_resources[] = {
{
.flags = IORESOURCE_MEM,
},
};
struct platform_device imx_wdt_device0 = {
.name = "imx2-wdt",
.id = 0,
.num_resources = ARRAY_SIZE(imx_wdt_resources),
.resource = imx_wdt_resources,
};
static struct resource imx_rtc_resources[] = {
{
.start = MX31_RTC_BASE_ADDR,
......@@ -312,51 +113,3 @@ struct platform_device imx_rtc_device0 = {
.num_resources = ARRAY_SIZE(imx_rtc_resources),
.resource = imx_rtc_resources,
};
static struct resource imx_kpp_resources[] = {
{
.start = MX3x_KPP_BASE_ADDR,
.end = MX3x_KPP_BASE_ADDR + 0xf,
.flags = IORESOURCE_MEM
}, {
.start = MX3x_INT_KPP,
.end = MX3x_INT_KPP,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_kpp_device = {
.name = "imx-keypad",
.id = -1,
.num_resources = ARRAY_SIZE(imx_kpp_resources),
.resource = imx_kpp_resources,
};
static int __init mx3_devices_init(void)
{
#if defined(CONFIG_ARCH_MX31)
if (cpu_is_mx31()) {
imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR;
imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff;
mxc_register_device(&mxc_rnga_device, NULL);
}
#endif
#if defined(CONFIG_ARCH_MX35)
if (cpu_is_mx35()) {
otg_resources[0].start = MX35_OTG_BASE_ADDR;
otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
otg_resources[1].start = MXC_INT_USBOTG;
otg_resources[1].end = MXC_INT_USBOTG;
mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400;
mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
mxc_usbh1_resources[1].start = MXC_INT_USBHS;
mxc_usbh1_resources[1].end = MXC_INT_USBHS;
imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
}
#endif
return 0;
}
subsys_initcall(mx3_devices_init);
arch/arm/mach-mx3/devices.h
View file @ 2a85927c
extern struct platform_device mxc_w1_master_device;
extern struct platform_device mx3_ipu;
extern struct platform_device mx3_fb;
extern struct platform_device mx3_camera;
extern struct platform_device mxcsdhc_device0;
extern struct platform_device mxcsdhc_device1;
extern struct platform_device mxc_otg_udc_device;
extern struct platform_device mxc_otg_host;
extern struct platform_device mxc_usbh1;
extern struct platform_device mxc_usbh2;
extern struct platform_device mxc_rnga_device;
extern struct platform_device imx_wdt_device0;
extern struct platform_device imx_rtc_device0;
extern struct platform_device imx_kpp_device;
arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
View file @ 2a85927c
......@@ -289,7 +289,7 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
imx35_add_flexcan1(NULL);
imx35_add_esdhc(0, NULL);
imx35_add_sdhci_esdhc_imx(0, NULL);
gpio_request(GPIO_LED1, "LED1");
gpio_direction_output(GPIO_LED1, 1);
......
arch/arm/mach-mx3/mach-armadillo5x0.c
View file @ 2a85927c
......@@ -49,10 +49,8 @@
#include <mach/common.h>
#include <mach/iomux-mx3.h>
#include <mach/mmc.h>
#include <mach/ipu.h>
#include <mach/mx3fb.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include "devices-imx31.h"
......@@ -245,13 +243,13 @@ static int usbh2_init(struct platform_device *pdev)
return err;
}
static struct mxc_usbh_platform_data usbotg_pdata = {
static struct mxc_usbh_platform_data usbotg_pdata __initdata = {
.init = usbotg_init,
.portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
.flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
};
static struct mxc_usbh_platform_data usbh2_pdata = {
static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
.init = usbh2_init,
.portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
.flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
......@@ -453,7 +451,7 @@ static void armadillo5x0_sdhc1_exit(struct device *dev, void *data)
gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B));
}
static struct imxmmc_platform_data sdhc_pdata = {
static const struct imxmmc_platform_data sdhc_pdata __initconst = {
.get_ro = armadillo5x0_sdhc1_get_ro,
.init = armadillo5x0_sdhc1_init,
.exit = armadillo5x0_sdhc1_exit,
......@@ -520,7 +518,7 @@ static void __init armadillo5x0_init(void)
gpio_direction_input(MX31_PIN_GPIO1_0);
/* Register SDHC */
mxc_register_device(&mxcsdhc_device0, &sdhc_pdata);
imx31_add_mxc_mmc(0, &sdhc_pdata);
/* Register FB */
mxc_register_device(&mx3_ipu, &mx3_ipu_data);
......@@ -555,8 +553,8 @@ static void __init armadillo5x0_init(void)
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_otg_host, &usbotg_pdata);
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
imx31_add_mxc_ehci_otg(&usbotg_pdata);
imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
#endif
}
......
arch/arm/mach-mx3/mach-cpuimx35.c
View file @ 2a85927c
......@@ -30,7 +30,6 @@
#include <linux/i2c/tsc2007.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/fsl_devices.h>
#include <linux/i2c-gpio.h>
#include <asm/mach-types.h>
......@@ -43,7 +42,6 @@
#include <mach/common.h>
#include <mach/iomux-mx35.h>
#include <mach/mxc_nand.h>
#include <mach/mxc_ehci.h>
#include "devices-imx35.h"
#include "devices.h"
......@@ -74,10 +72,6 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
},
};
static struct platform_device *devices[] __initdata = {
&imx_wdt_device0,
};
static struct pad_desc eukrea_cpuimx35_pads[] = {
/* UART1 */
MX35_PAD_CTS1__UART1_CTS,
......@@ -117,18 +111,18 @@ static const struct mxc_nand_platform_data
.flash_bbt = 1,
};
static struct mxc_usbh_platform_data __maybe_unused otg_pdata = {
static const struct mxc_usbh_platform_data otg_pdata __initconst = {
.portsc = MXC_EHCI_MODE_UTMI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
static struct mxc_usbh_platform_data __maybe_unused usbh1_pdata = {
static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
.portsc = MXC_EHCI_MODE_SERIAL,
.flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
MXC_EHCI_IPPUE_DOWN,
};
static struct fsl_usb2_platform_data otg_device_pdata = {
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_UTMI,
.workaround = FLS_USB2_WORKAROUND_ENGCM09152,
......@@ -158,7 +152,7 @@ static void __init mxc_board_init(void)
ARRAY_SIZE(eukrea_cpuimx35_pads));
imx35_add_fec(NULL);
platform_add_devices(devices, ARRAY_SIZE(devices));
imx35_add_imx2_wdt(NULL);
imx35_add_imx_uart0(&uart_pdata);
imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info);
......@@ -168,11 +162,11 @@ static void __init mxc_board_init(void)
imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data);
if (otg_mode_host)
mxc_register_device(&mxc_otg_host, &otg_pdata);
imx35_add_mxc_ehci_otg(&otg_pdata);
else
mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
imx35_add_fsl_usb2_udc(&otg_device_pdata);
mxc_register_device(&mxc_usbh1, &usbh1_pdata);
imx35_add_mxc_ehci_hs(&usbh1_pdata);
#ifdef CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD
eukrea_mbimxsd35_baseboard_init();
......
arch/arm/mach-mx3/mach-kzm_arm11_01.c
View file @ 2a85927c
......@@ -41,9 +41,9 @@
#include "devices-imx31.h"
#include "devices.h"
#define KZM_ARM11_IO_ADDRESS(x) ( \
IMX_IO_ADDRESS(x, MX31_CS4) ?: \
IMX_IO_ADDRESS(x, MX31_CS5) ?: \
#define KZM_ARM11_IO_ADDRESS(x) (IOMEM( \
IMX_IO_P2V_MODULE(x, MX31_CS4) ?: \
IMX_IO_P2V_MODULE(x, MX31_CS5)) ?: \
MX31_IO_ADDRESS(x))
/*
......
arch/arm/mach-mx3/mach-mx31_3ds.c
View file @ 2a85927c
......@@ -22,8 +22,6 @@
#include <linux/mfd/mc13783.h>
#include <linux/spi/spi.h>
#include <linux/regulator/machine.h>
#include <linux/fsl_devices.h>
#include <linux/input/matrix_keypad.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
......@@ -102,7 +100,7 @@ static const uint32_t mx31_3ds_keymap[] = {
KEY(2, 3, KEY_F10),
};
static struct matrix_keymap_data mx31_3ds_keymap_data = {
static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = {
.keymap = mx31_3ds_keymap,
.keymap_size = ARRAY_SIZE(mx31_3ds_keymap),
};
......@@ -214,7 +212,7 @@ static int mx31_3ds_usbotg_init(void)
return err;
}
static struct fsl_usb2_platform_data usbotg_pdata = {
static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_ULPI,
};
......@@ -246,10 +244,10 @@ static void __init mxc_board_init(void)
spi_register_board_info(mx31_3ds_spi_devs,
ARRAY_SIZE(mx31_3ds_spi_devs));
mxc_register_device(&imx_kpp_device, &mx31_3ds_keymap_data);
imx31_add_imx_keypad(&mx31_3ds_keymap_data);
mx31_3ds_usbotg_init();
mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
imx31_add_fsl_usb2_udc(&usbotg_pdata);
if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT))
printk(KERN_WARNING "Init of the debug board failed, all "
......
arch/arm/mach-mx3/mach-mx31lilly.c
View file @ 2a85927c
......@@ -42,7 +42,6 @@
#include <mach/common.h>
#include <mach/iomux-mx3.h>
#include <mach/board-mx31lilly.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include "devices-imx31.h"
......@@ -230,13 +229,13 @@ static struct mxc_usbh_platform_data usbotg_pdata = {
.flags = MXC_EHCI_POWER_PINS_ENABLED,
};
static struct mxc_usbh_platform_data usbh1_pdata = {
static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
.init = usbh1_init,
.portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
.flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
};
static struct mxc_usbh_platform_data usbh2_pdata = {
static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
.init = usbh2_init,
.portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
.flags = MXC_EHCI_POWER_PINS_ENABLED,
......@@ -249,8 +248,8 @@ static void lilly1131_usb_init(void)
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_usbh1, &usbh1_pdata);
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
}
#else
......
arch/arm/mach-mx3/mach-mx31lite.c
View file @ 2a85927c
......@@ -40,7 +40,6 @@
#include <mach/board-mx31lite.h>
#include <mach/iomux-mx3.h>
#include <mach/irqs.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include "devices-imx31.h"
......@@ -171,7 +170,7 @@ static int usbh2_init(struct platform_device *pdev)
return 0;
}
static struct mxc_usbh_platform_data usbh2_pdata = {
static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
.init = usbh2_init,
.portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
.flags = MXC_EHCI_POWER_PINS_ENABLED,
......@@ -258,7 +257,7 @@ static void __init mxc_board_init(void)
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
#endif
/* SMSC9117 IRQ pin */
......
arch/arm/mach-mx3/mach-mx31moboard.c
View file @ 2a85927c
......@@ -40,8 +40,6 @@
#include <mach/hardware.h>
#include <mach/iomux-mx3.h>
#include <mach/ipu.h>
#include <mach/mmc.h>
#include <mach/mxc_ehci.h>
#include <mach/mx3_camera.h>
#include <mach/spi.h>
#include <mach/ulpi.h>
......@@ -170,11 +168,11 @@ static const struct spi_imx_master moboard_spi1_pdata __initconst = {
static struct regulator_consumer_supply sdhc_consumers[] = {
{
.dev = &mxcsdhc_device0.dev,
.dev_name = "mxc-mmc.0",
.supply = "sdhc0_vcc",
},
{
.dev = &mxcsdhc_device1.dev,
.dev_name = "mxc-mmc.1",
.supply = "sdhc1_vcc",
},
};
......@@ -345,7 +343,7 @@ static void moboard_sdhc1_exit(struct device *dev, void *data)
gpio_free(SDHC1_CD);
}
static struct imxmmc_platform_data sdhc1_pdata = {
static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
.get_ro = moboard_sdhc1_get_ro,
.init = moboard_sdhc1_init,
.exit = moboard_sdhc1_exit,
......@@ -404,17 +402,23 @@ static void usb_xcvr_reset(void)
#if defined(CONFIG_USB_ULPI)
static struct mxc_usbh_platform_data usbh2_pdata = {
static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
.portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
.flags = MXC_EHCI_POWER_PINS_ENABLED,
};
static int __init moboard_usbh2_init(void)
{
struct platform_device *pdev;
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
return mxc_register_device(&mxc_usbh2, &usbh2_pdata);
pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
return 0;
}
#else
static inline int moboard_usbh2_init(void) { return 0; }
......@@ -520,7 +524,7 @@ static void __init mxc_board_init(void)
spi_register_board_info(moboard_spi_board_info,
ARRAY_SIZE(moboard_spi_board_info));
mxc_register_device(&mxcsdhc_device0, &sdhc1_pdata);
imx31_add_mxc_mmc(0, &sdhc1_pdata);
mxc_register_device(&mx3_ipu, &mx3_ipu_data);
if (!mx31moboard_cam_alloc_dma(CAMERA_BUF_SIZE))
......
arch/arm/mach-mx3/mach-mx35_3ds.c
View file @ 2a85927c
......@@ -26,7 +26,6 @@
#include <linux/platform_device.h>
#include <linux/memory.h>
#include <linux/gpio.h>
#include <linux/fsl_devices.h>
#include <linux/mtd/physmap.h>
......@@ -40,7 +39,6 @@
#include <mach/iomux-mx35.h>
#include <mach/irqs.h>
#include <mach/3ds_debugboard.h>
#include <mach/mxc_ehci.h>
#include "devices-imx35.h"
#include "devices.h"
......@@ -122,13 +120,13 @@ static struct pad_desc mx35pdk_pads[] = {
};
/* OTG config */
static struct fsl_usb2_platform_data usb_otg_pdata = {
static const struct fsl_usb2_platform_data usb_otg_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_UTMI_WIDE,
};
/* USB HOST config */
static struct mxc_usbh_platform_data usb_host_pdata = {
static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
.portsc = MXC_EHCI_MODE_SERIAL,
.flags = MXC_EHCI_INTERFACE_SINGLE_UNI |
MXC_EHCI_INTERNAL_PHY,
......@@ -142,16 +140,17 @@ static void __init mxc_board_init(void)
mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
imx35_add_fec(NULL);
imx35_add_imx2_wdt(NULL);
platform_add_devices(devices, ARRAY_SIZE(devices));
imx35_add_imx_uart0(&uart_pdata);
mxc_register_device(&mxc_otg_udc_device, &usb_otg_pdata);
imx35_add_fsl_usb2_udc(&usb_otg_pdata);
mxc_register_device(&mxc_usbh1, &usb_host_pdata);
imx35_add_mxc_ehci_hs(&usb_host_pdata);
imx35_add_mxc_nand(&mx35pdk_nand_board_info);
imx35_add_esdhc(0, NULL);
imx35_add_sdhci_esdhc_imx(0, NULL);
if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT))
pr_warn("Init of the debugboard failed, all "
......
arch/arm/mach-mx3/mach-pcm037.c
View file @ 2a85927c
......@@ -27,7 +27,6 @@
#include <linux/delay.h>
#include <linux/spi/spi.h>
#include <linux/irq.h>
#include <linux/fsl_devices.h>
#include <linux/can/platform/sja1000.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
......@@ -43,10 +42,8 @@
#include <mach/hardware.h>
#include <mach/iomux-mx3.h>
#include <mach/ipu.h>
#include <mach/mmc.h>
#include <mach/mx3_camera.h>
#include <mach/mx3fb.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include "devices-imx31.h"
......@@ -399,7 +396,7 @@ static void pcm970_sdhc1_exit(struct device *dev, void *data)
gpio_free(SDHC1_GPIO_WP);
}
static struct imxmmc_platform_data sdhc_pdata = {
static const struct imxmmc_platform_data sdhc_pdata __initconst = {
#ifdef PCM970_SDHC_RW_SWITCH
.get_ro = pcm970_sdhc1_get_ro,
#endif
......@@ -441,7 +438,6 @@ static int __init pcm037_camera_alloc_dma(const size_t buf_size)
static struct platform_device *devices[] __initdata = {
&pcm037_flash,
&pcm037_sram_device,
&imx_wdt_device0,
&pcm037_mt9t031,
&pcm037_mt9v022,
};
......@@ -538,18 +534,18 @@ static struct platform_device pcm970_sja1000 = {
};
#if defined(CONFIG_USB_ULPI)
static struct mxc_usbh_platform_data otg_pdata = {
static struct mxc_usbh_platform_data otg_pdata __initdata = {
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
static struct mxc_usbh_platform_data usbh2_pdata = {
static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
.portsc = MXC_EHCI_MODE_ULPI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
#endif
static struct fsl_usb2_platform_data otg_device_pdata = {
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_ULPI,
};
......@@ -607,12 +603,13 @@ static void __init mxc_board_init(void)
platform_add_devices(devices, ARRAY_SIZE(devices));
imx31_add_imx2_wdt(NULL);
imx31_add_imx_uart0(&uart_pdata);
/* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */
imx31_add_imx_uart1(&uart_pdata);
imx31_add_imx_uart2(&uart_pdata);
mxc_register_device(&mxc_w1_master_device, NULL);
imx31_add_mxc_w1(NULL);
/* LAN9217 IRQ pin */
ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
......@@ -632,7 +629,7 @@ static void __init mxc_board_init(void)
imx31_add_imx_i2c2(&pcm037_i2c2_data);
imx31_add_mxc_nand(&pcm037_nand_board_info);
mxc_register_device(&mxcsdhc_device0, &sdhc_pdata);
imx31_add_mxc_mmc(0, &sdhc_pdata);
mxc_register_device(&mx3_ipu, &mx3_ipu_data);
mxc_register_device(&mx3_fb, &mx3fb_pdata);
......@@ -654,16 +651,16 @@ static void __init mxc_board_init(void)
otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_otg_host, &otg_pdata);
imx31_add_mxc_ehci_otg(&otg_pdata);
}
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
#endif
if (!otg_mode_host)
mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
imx31_add_fsl_usb2_udc(&otg_device_pdata);
}
......
arch/arm/mach-mx3/mach-pcm037_eet.c
View file @ 2a85927c
......@@ -171,7 +171,7 @@ static struct platform_device pcm037_gpio_keys_device = {
},
};
static int eet_init_devices(void)
static int __init eet_init_devices(void)
{
if (!machine_is_pcm037() || pcm037_variant() != PCM037_EET)
return 0;
......
arch/arm/mach-mx3/mach-pcm043.c
View file @ 2a85927c
......@@ -27,7 +27,6 @@
#include <linux/i2c/at24.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/fsl_devices.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
......@@ -39,7 +38,6 @@
#include <mach/iomux-mx35.h>
#include <mach/ipu.h>
#include <mach/mx3fb.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include <mach/audmux.h>
......@@ -140,7 +138,6 @@ static struct i2c_board_info pcm043_i2c_devices[] = {
static struct platform_device *devices[] __initdata = {
&pcm043_flash,
&imx_wdt_device0,
};
static struct pad_desc pcm043_pads[] = {
......@@ -311,19 +308,19 @@ pcm037_nand_board_info __initconst = {
};
#if defined(CONFIG_USB_ULPI)
static struct mxc_usbh_platform_data otg_pdata = {
static struct mxc_usbh_platform_data otg_pdata __initdata = {
.portsc = MXC_EHCI_MODE_UTMI,
.flags = MXC_EHCI_INTERFACE_DIFF_UNI,
};
static struct mxc_usbh_platform_data usbh1_pdata = {
static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
.portsc = MXC_EHCI_MODE_SERIAL,
.flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
MXC_EHCI_IPPUE_DOWN,
};
#endif
static struct fsl_usb2_platform_data otg_device_pdata = {
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_UTMI,
};
......@@ -364,6 +361,7 @@ static void __init mxc_board_init(void)
imx35_add_fec(NULL);
platform_add_devices(devices, ARRAY_SIZE(devices));
imx35_add_imx2_wdt(NULL);
imx35_add_imx_uart0(&uart_pdata);
imx35_add_mxc_nand(&pcm037_nand_board_info);
......@@ -386,16 +384,16 @@ static void __init mxc_board_init(void)
otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
mxc_register_device(&mxc_otg_host, &otg_pdata);
imx35_add_mxc_ehci_otg(&otg_pdata);
}
mxc_register_device(&mxc_usbh1, &usbh1_pdata);
imx35_add_mxc_ehci_hs(&usbh1_pdata);
#endif
if (!otg_mode_host)
mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
imx35_add_fsl_usb2_udc(&otg_device_pdata);
imx35_add_flexcan1(NULL);
imx35_add_esdhc(0, NULL);
imx35_add_sdhci_esdhc_imx(0, NULL);
}
static void __init pcm043_timer_init(void)
......
arch/arm/mach-mx3/mm.c
View file @ 2a85927c
......@@ -36,40 +36,16 @@
* @ingroup Memory
*/
/*!
* This table defines static virtual address mappings for I/O regions.
* These are the mappings common across all MX3 boards.
*/
static struct map_desc mxc_io_desc[] __initdata = {
{
.virtual = X_MEMC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(X_MEMC_BASE_ADDR),
.length = X_MEMC_SIZE,
.type = MT_DEVICE
}, {
.virtual = AVIC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(AVIC_BASE_ADDR),
.length = AVIC_SIZE,
.type = MT_DEVICE_NONSHARED
}, {
.virtual = AIPS1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
.length = AIPS1_SIZE,
.type = MT_DEVICE_NONSHARED
}, {
.virtual = AIPS2_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
.length = AIPS2_SIZE,
.type = MT_DEVICE_NONSHARED
}, {
.virtual = SPBA0_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
.length = SPBA0_SIZE,
.type = MT_DEVICE_NONSHARED
},
#ifdef CONFIG_SOC_IMX31
static struct map_desc mx31_io_desc[] __initdata = {
imx_map_entry(MX31, X_MEMC, MT_DEVICE),
imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
};
/*!
/*
* This function initializes the memory map. It is called during the
* system startup to create static physical to virtual memory mappings
* for the IO modules.
......@@ -77,34 +53,44 @@ static struct map_desc mxc_io_desc[] __initdata = {
void __init mx31_map_io(void)
{
mxc_set_cpu_type(MXC_CPU_MX31);
mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
}
#ifdef CONFIG_ARCH_MX35
void __init mx35_map_io(void)
int imx31_register_gpios(void);
void __init mx31_init_irq(void)
{
mxc_set_cpu_type(MXC_CPU_MX35);
mxc_iomux_v3_init(IO_ADDRESS(IOMUXC_BASE_ADDR));
mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
imx31_register_gpios();
}
#endif
int imx3x_register_gpios(void);
#endif /* ifdef CONFIG_SOC_IMX31 */
#ifdef CONFIG_SOC_IMX35
static struct map_desc mx35_io_desc[] __initdata = {
imx_map_entry(MX35, X_MEMC, MT_DEVICE),
imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
};
void __init mx31_init_irq(void)
void __init mx35_map_io(void)
{
mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
imx3x_register_gpios();
mxc_set_cpu_type(MXC_CPU_MX35);
mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
}
int imx35_register_gpios(void);
void __init mx35_init_irq(void)
{
mx31_init_irq();
mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
imx35_register_gpios();
}
#endif /* ifdef CONFIG_SOC_IMX35 */
#ifdef CONFIG_CACHE_L2X0
static int mxc_init_l2x0(void)
......@@ -129,7 +115,7 @@ static int mxc_init_l2x0(void)
pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
}
l2x0_base = ioremap(L2CC_BASE_ADDR, 4096);
l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
if (IS_ERR(l2x0_base)) {
printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
PTR_ERR(l2x0_base));
......
arch/arm/mach-mx3/mx31lilly-db.c
View file @ 2a85927c
......@@ -34,7 +34,6 @@
#include <mach/common.h>
#include <mach/iomux-mx3.h>
#include <mach/board-mx31lilly.h>
#include <mach/mmc.h>
#include <mach/mx3fb.h>
#include <mach/ipu.h>
......@@ -158,7 +157,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data)
free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data);
}
static struct imxmmc_platform_data mmc_pdata = {
static const struct imxmmc_platform_data mmc_pdata __initconst = {
.get_ro = mxc_mmc1_get_ro,
.init = mxc_mmc1_init,
.exit = mxc_mmc1_exit,
......@@ -216,7 +215,7 @@ void __init mx31lilly_db_init(void)
imx31_add_imx_uart0(&uart_pdata);
imx31_add_imx_uart1(&uart_pdata);
imx31_add_imx_uart2(&uart_pdata);
mxc_register_device(&mxcsdhc_device0, &mmc_pdata);
imx31_add_mxc_mmc(0, &mmc_pdata);
mx31lilly_init_fb();
}
arch/arm/mach-mx3/mx31lite-db.c
View file @ 2a85927c
......@@ -35,7 +35,6 @@
#include <mach/common.h>
#include <mach/iomux-mx3.h>
#include <mach/board-mx31lite.h>
#include <mach/mmc.h>
#include "devices-imx31.h"
#include "devices.h"
......@@ -142,7 +141,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data)
free_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), data);
}
static struct imxmmc_platform_data mmc_pdata = {
static const struct imxmmc_platform_data mmc_pdata __initconst = {
.get_ro = mxc_mmc1_get_ro,
.init = mxc_mmc1_init,
.exit = mxc_mmc1_exit,
......@@ -197,10 +196,9 @@ void __init mx31lite_db_init(void)
ARRAY_SIZE(litekit_db_board_pins),
"development board pins");
imx31_add_imx_uart0(&uart_pdata);
mxc_register_device(&mxcsdhc_device0, &mmc_pdata);
imx31_add_mxc_mmc(0, &mmc_pdata);
imx31_add_spi_imx0(&spi0_pdata);
platform_device_register(&litekit_led_device);
mxc_register_device(&imx_wdt_device0, NULL);
imx31_add_imx2_wdt(NULL);
mxc_register_device(&imx_rtc_device0, NULL);
}
arch/arm/mach-mx3/mx31moboard-devboard.c
View file @ 2a85927c
......@@ -18,15 +18,12 @@
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/fsl_devices.h>
#include <linux/usb/otg.h>
#include <mach/common.h>
#include <mach/iomux-mx3.h>
#include <mach/hardware.h>
#include <mach/mmc.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include "devices-imx31.h"
......@@ -103,7 +100,7 @@ static void devboard_sdhc2_exit(struct device *dev, void *data)
gpio_free(SDHC2_CD);
}
static struct imxmmc_platform_data sdhc2_pdata = {
static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
.get_ro = devboard_sdhc2_get_ro,
.init = devboard_sdhc2_init,
.exit = devboard_sdhc2_exit,
......@@ -187,7 +184,7 @@ static int devboard_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
return 0;
}
static struct mxc_usbh_platform_data usbh1_pdata = {
static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
.init = devboard_usbh1_hw_init,
.portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
.flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
......@@ -196,6 +193,7 @@ static struct mxc_usbh_platform_data usbh1_pdata = {
static int __init devboard_usbh1_init(void)
{
struct otg_transceiver *otg;
struct platform_device *pdev;
otg = kzalloc(sizeof(*otg), GFP_KERNEL);
if (!otg)
......@@ -207,11 +205,15 @@ static int __init devboard_usbh1_init(void)
usbh1_pdata.otg = otg;
return mxc_register_device(&mxc_usbh1, &usbh1_pdata);
pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
return 0;
}
static struct fsl_usb2_platform_data usb_pdata = {
static const struct fsl_usb2_platform_data usb_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_ULPI,
};
......@@ -228,11 +230,11 @@ void __init mx31moboard_devboard_init(void)
imx31_add_imx_uart1(&uart_pdata);
mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
imx31_add_mxc_mmc(1, &sdhc2_pdata);
devboard_init_sel_gpios();
mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
imx31_add_fsl_usb2_udc(&usb_pdata);
devboard_usbh1_init();
}
arch/arm/mach-mx3/mx31moboard-marxbot.c
View file @ 2a85927c
......@@ -21,7 +21,6 @@
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/fsl_devices.h>
#include <linux/usb/otg.h>
......@@ -29,12 +28,11 @@
#include <mach/hardware.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx3.h>
#include <mach/mmc.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include <media/soc_camera.h>
#include "devices-imx31.h"
#include "devices.h"
static unsigned int marxbot_pins[] = {
......@@ -116,7 +114,7 @@ static void marxbot_sdhc2_exit(struct device *dev, void *data)
gpio_free(SDHC2_CD);
}
static struct imxmmc_platform_data sdhc2_pdata = {
static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
.get_ro = marxbot_sdhc2_get_ro,
.init = marxbot_sdhc2_init,
.exit = marxbot_sdhc2_exit,
......@@ -302,7 +300,7 @@ static int marxbot_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
return 0;
}
static struct mxc_usbh_platform_data usbh1_pdata = {
static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
.init = marxbot_usbh1_hw_init,
.portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
.flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
......@@ -311,6 +309,7 @@ static struct mxc_usbh_platform_data usbh1_pdata = {
static int __init marxbot_usbh1_init(void)
{
struct otg_transceiver *otg;
struct platform_device *pdev;
otg = kzalloc(sizeof(*otg), GFP_KERNEL);
if (!otg)
......@@ -322,10 +321,14 @@ static int __init marxbot_usbh1_init(void)
usbh1_pdata.otg = otg;
return mxc_register_device(&mxc_usbh1, &usbh1_pdata);
pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
return 0;
}
static struct fsl_usb2_platform_data usb_pdata = {
static const struct fsl_usb2_platform_data usb_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_ULPI,
};
......@@ -344,7 +347,7 @@ void __init mx31moboard_marxbot_init(void)
dspics_resets_init();
mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
imx31_add_mxc_mmc(1, &sdhc2_pdata);
spi_register_board_info(marxbot_spi_board_info,
ARRAY_SIZE(marxbot_spi_board_info));
......@@ -357,7 +360,7 @@ void __init mx31moboard_marxbot_init(void)
gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0));
gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false);
mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
imx31_add_fsl_usb2_udc(&usb_pdata);
marxbot_usbh1_init();
}
arch/arm/mach-mx3/mx31moboard-smartbot.c
View file @ 2a85927c
......@@ -19,7 +19,6 @@
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/fsl_devices.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
......@@ -28,7 +27,6 @@
#include <mach/hardware.h>
#include <mach/iomux-mx3.h>
#include <mach/board-mx31moboard.h>
#include <mach/mxc_ehci.h>
#include <mach/ulpi.h>
#include <media/soc_camera.h>
......@@ -118,24 +116,30 @@ static int __init smartbot_cam_init(void)
return 0;
}
static struct fsl_usb2_platform_data usb_pdata = {
static const struct fsl_usb2_platform_data usb_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_ULPI,
};
#if defined(CONFIG_USB_ULPI)
static struct mxc_usbh_platform_data otg_host_pdata = {
static struct mxc_usbh_platform_data otg_host_pdata __initdata = {
.portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
.flags = MXC_EHCI_POWER_PINS_ENABLED,
};
static int __init smartbot_otg_host_init(void)
{
struct platform_device *pdev;
otg_host_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
return mxc_register_device(&mxc_otg_host, &otg_host_pdata);
pdev = imx31_add_mxc_ehci_otg(&otg_host_pdata);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
return 0;
}
#else
static inline int smartbot_otg_host_init(void) { return 0; }
......@@ -182,7 +186,7 @@ void __init mx31moboard_smartbot_init(int board)
switch (board) {
case MX31SMARTBOT:
mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
imx31_add_fsl_usb2_udc(&usb_pdata);
break;
case MX31EYEBOT:
smartbot_otg_host_init();
......
arch/arm/mach-mx5/Kconfig
View file @ 2a85927c
......@@ -14,7 +14,7 @@ config MACH_MX51_BABBAGE
bool "Support MX51 BABBAGE platforms"
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_ESDHC
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
help
Include support for MX51 Babbage platform, also known as MX51EVK in
u-boot. This includes specific configurations for the board and its
......@@ -47,7 +47,7 @@ choice
config MACH_EUKREA_MBIMX51_BASEBOARD
prompt "Eukrea MBIMX51 development board"
bool
select IMX_HAVE_PLATFORM_ESDHC
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
help
This adds board specific devices that can be found on Eukrea's
MBIMX51 evaluation board.
......@@ -72,7 +72,7 @@ choice
config MACH_EUKREA_MBIMXSD51_BASEBOARD
prompt "Eukrea MBIMXSD development board"
bool
select IMX_HAVE_PLATFORM_ESDHC
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
help
This adds board specific devices that can be found on Eukrea's
MBIMXSD evaluation board.
......
arch/arm/mach-mx5/board-mx51_babbage.c
View file @ 2a85927c
......@@ -349,8 +349,8 @@ static void __init mxc_board_init(void)
mxc_iomux_v3_setup_pad(&usbh1stp);
babbage_usbhub_reset();
imx51_add_esdhc(0, NULL);
imx51_add_esdhc(1, NULL);
imx51_add_sdhci_esdhc_imx(0, NULL);
imx51_add_sdhci_esdhc_imx(1, NULL);
}
static void __init mx51_babbage_timer_init(void)
......
arch/arm/mach-mx5/devices-imx51.h
View file @ 2a85927c
......@@ -31,6 +31,11 @@ extern const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst;
#define imx51_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx51_mxc_nand_data, pdata)
extern const struct imx_sdhci_esdhc_imx_data
imx51_sdhci_esdhc_imx_data[] __initconst;
#define imx51_add_sdhci_esdhc_imx(id, pdata) \
imx_add_sdhci_esdhc_imx(&imx51_sdhci_esdhc_imx_data[id], pdata)
extern const struct imx_spi_imx_data imx51_cspi_data __initconst;
#define imx51_add_cspi(pdata) \
imx_add_spi_imx(&imx51_cspi_data, pdata)
......@@ -38,7 +43,3 @@ extern const struct imx_spi_imx_data imx51_cspi_data __initconst;
extern const struct imx_spi_imx_data imx51_ecspi_data[] __initconst;
#define imx51_add_ecspi(id, pdata) \
imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
extern const struct imx_esdhc_imx_data imx51_esdhc_data[] __initconst;
#define imx51_add_esdhc(id, pdata) \
imx_add_esdhc(&imx51_esdhc_data[id], pdata)
arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
View file @ 2a85927c
......@@ -217,6 +217,6 @@ void __init eukrea_mbimx51_baseboard_init(void)
i2c_register_board_info(1, mbimx51_i2c_devices,
ARRAY_SIZE(mbimx51_i2c_devices));
imx51_add_esdhc(0, NULL);
imx51_add_esdhc(1, NULL);
imx51_add_sdhci_esdhc_imx(0, NULL);
imx51_add_sdhci_esdhc_imx(1, NULL);
}
arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
View file @ 2a85927c
......@@ -149,7 +149,7 @@ void __init eukrea_mbimxsd51_baseboard_init(void)
imx51_add_imx_uart(1, NULL);
imx51_add_imx_uart(2, &uart_pdata);
imx51_add_esdhc(0, NULL);
imx51_add_sdhci_esdhc_imx(0, NULL);
gpio_request(GPIO_LED1, "LED1");
gpio_direction_output(GPIO_LED1, 1);
......
arch/arm/mach-mx5/mm.c
View file @ 2a85927c
......@@ -23,33 +23,12 @@
/*
* Define the MX51 memory map.
*/
static struct map_desc mxc_io_desc[] __initdata = {
{
.virtual = MX51_IRAM_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX51_IRAM_BASE_ADDR),
.length = MX51_IRAM_SIZE,
.type = MT_DEVICE
}, {
.virtual = MX51_DEBUG_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX51_DEBUG_BASE_ADDR),
.length = MX51_DEBUG_SIZE,
.type = MT_DEVICE
}, {
.virtual = MX51_AIPS1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX51_AIPS1_BASE_ADDR),
.length = MX51_AIPS1_SIZE,
.type = MT_DEVICE
}, {
.virtual = MX51_SPBA0_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX51_SPBA0_BASE_ADDR),
.length = MX51_SPBA0_SIZE,
.type = MT_DEVICE
}, {
.virtual = MX51_AIPS2_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MX51_AIPS2_BASE_ADDR),
.length = MX51_AIPS2_SIZE,
.type = MT_DEVICE
},
static struct map_desc mx51_io_desc[] __initdata = {
imx_map_entry(MX51, IRAM, MT_DEVICE),
imx_map_entry(MX51, DEBUG, MT_DEVICE),
imx_map_entry(MX51, AIPS1, MT_DEVICE),
imx_map_entry(MX51, SPBA0, MT_DEVICE),
imx_map_entry(MX51, AIPS2, MT_DEVICE),
};
/*
......@@ -62,7 +41,7 @@ void __init mx51_map_io(void)
mxc_set_cpu_type(MXC_CPU_MX51);
mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG_BASE_ADDR));
iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
}
int imx51_register_gpios(void);
......
arch/arm/mach-mxc91231/mm.c
View file @ 2a85927c
......@@ -27,48 +27,15 @@
/*
* This structure defines the MXC memory map.
*/
static struct map_desc mxc_io_desc[] __initdata = {
{
.virtual = MXC91231_L2CC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MXC91231_L2CC_BASE_ADDR),
.length = MXC91231_L2CC_SIZE,
.type = MT_DEVICE,
}, {
.virtual = MXC91231_X_MEMC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MXC91231_X_MEMC_BASE_ADDR),
.length = MXC91231_X_MEMC_SIZE,
.type = MT_DEVICE,
}, {
.virtual = MXC91231_ROMP_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MXC91231_ROMP_BASE_ADDR),
.length = MXC91231_ROMP_SIZE,
.type = MT_DEVICE,
}, {
.virtual = MXC91231_AVIC_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MXC91231_AVIC_BASE_ADDR),
.length = MXC91231_AVIC_SIZE,
.type = MT_DEVICE,
}, {
.virtual = MXC91231_AIPS1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MXC91231_AIPS1_BASE_ADDR),
.length = MXC91231_AIPS1_SIZE,
.type = MT_DEVICE,
}, {
.virtual = MXC91231_SPBA0_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MXC91231_SPBA0_BASE_ADDR),
.length = MXC91231_SPBA0_SIZE,
.type = MT_DEVICE,
}, {
.virtual = MXC91231_SPBA1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MXC91231_SPBA1_BASE_ADDR),
.length = MXC91231_SPBA1_SIZE,
.type = MT_DEVICE,
}, {
.virtual = MXC91231_AIPS2_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(MXC91231_AIPS2_BASE_ADDR),
.length = MXC91231_AIPS2_SIZE,
.type = MT_DEVICE,
},
static struct map_desc mxc91231_io_desc[] __initdata = {
imx_map_entry(MXC91231, L2CC, MT_DEVICE),
imx_map_entry(MXC91231, X_MEMC, MT_DEVICE),
imx_map_entry(MXC91231, ROMP, MT_DEVICE),
imx_map_entry(MXC91231, AVIC, MT_DEVICE),
imx_map_entry(MXC91231, AIPS1, MT_DEVICE),
imx_map_entry(MXC91231, SPBA0, MT_DEVICE),
imx_map_entry(MXC91231, SPBA1, MT_DEVICE),
imx_map_entry(MXC91231, AIPS2, MT_DEVICE),
};
/*
......@@ -80,7 +47,7 @@ void __init mxc91231_map_io(void)
{
mxc_set_cpu_type(MXC_CPU_MXC91231);
iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
iotable_init(mxc91231_io_desc, ARRAY_SIZE(mxc91231_io_desc));
}
int mxc91231_register_gpios(void);
......
arch/arm/plat-mxc/Kconfig
View file @ 2a85927c
......@@ -21,10 +21,6 @@ config ARCH_MX2
config ARCH_MX25
bool "MX25-based"
select CPU_ARM926T
select ARCH_MXC_IOMUX_V3
select HAVE_FB_IMX
select ARCH_MXC_AUDMUX_V2
help
This enables support for systems based on the Freescale i.MX25 family
......@@ -51,7 +47,6 @@ endchoice
source "arch/arm/mach-imx/Kconfig"
source "arch/arm/mach-mx3/Kconfig"
source "arch/arm/mach-mx25/Kconfig"
source "arch/arm/mach-mxc91231/Kconfig"
source "arch/arm/mach-mx5/Kconfig"
......
arch/arm/plat-mxc/audmux-v2.c
View file @ 2a85927c
......@@ -209,7 +209,7 @@ static int mxc_audmux_v2_init(void)
audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR);
}
#endif
#if defined(CONFIG_ARCH_MX25)
#if defined(CONFIG_SOC_IMX25)
if (cpu_is_mx25()) {
audmux_clk = clk_get(NULL, "audmux");
if (IS_ERR(audmux_clk)) {
......@@ -220,7 +220,7 @@ static int mxc_audmux_v2_init(void)
}
audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR);
}
#endif
#endif /* if defined(CONFIG_SOC_IMX25) */
audmux_debugfs_init();
return 0;
......
arch/arm/plat-mxc/devices.c
View file @ 2a85927c
......@@ -17,6 +17,7 @@
*/
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/platform_device.h>
......@@ -36,9 +37,10 @@ int __init mxc_register_device(struct platform_device *pdev, void *data)
return ret;
}
struct platform_device *__init imx_add_platform_device(const char *name, int id,
struct platform_device *__init imx_add_platform_device_dmamask(
const char *name, int id,
const struct resource *res, unsigned int num_resources,
const void *data, size_t size_data)
const void *data, size_t size_data, u64 dmamask)
{
int ret = -ENOMEM;
struct platform_device *pdev;
......@@ -47,6 +49,23 @@ struct platform_device *__init imx_add_platform_device(const char *name, int id,
if (!pdev)
goto err;
if (dmamask) {
/*
* This memory isn't freed when the device is put,
* I don't have a nice idea for that though. Conceptually
* dma_mask in struct device should not be a pointer.
* See http://thread.gmane.org/gmane.linux.kernel.pci/9081
*/
pdev->dev.dma_mask =
kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL);
if (!pdev->dev.dma_mask)
/* ret is still -ENOMEM; */
goto err;
*pdev->dev.dma_mask = dmamask;
pdev->dev.coherent_dma_mask = dmamask;
}
if (res) {
ret = platform_device_add_resources(pdev, res, num_resources);
if (ret)
......
arch/arm/plat-mxc/devices/Kconfig
View file @ 2a85927c
config IMX_HAVE_PLATFORM_ESDHC
bool
config IMX_HAVE_PLATFORM_FEC
bool
default y if ARCH_MX25 || SOC_IMX27 || ARCH_MX35 || ARCH_MX51
default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || ARCH_MX51
config IMX_HAVE_PLATFORM_FLEXCAN
select HAVE_CAN_FLEXCAN if CAN
bool
config IMX_HAVE_PLATFORM_FSL_USB2_UDC
bool
config IMX_HAVE_PLATFORM_GPIO_KEYS
bool
default y if ARCH_MX51
config IMX_HAVE_PLATFORM_IMX21_HCD
bool
config IMX_HAVE_PLATFORM_IMX2_WDT
bool
config IMX_HAVE_PLATFORM_IMXDI_RTC
bool
config IMX_HAVE_PLATFORM_IMX_FB
bool
select HAVE_FB_IMX
config IMX_HAVE_PLATFORM_IMX_I2C
bool
config IMX_HAVE_PLATFORM_IMX_KEYPAD
bool
config IMX_HAVE_PLATFORM_IMX_SSI
bool
config IMX_HAVE_PLATFORM_IMX_UART
bool
config IMX_HAVE_PLATFORM_IMX_UDC
bool
config IMX_HAVE_PLATFORM_MX1_CAMERA
bool
config IMX_HAVE_PLATFORM_MX2_CAMERA
bool
config IMX_HAVE_PLATFORM_MXC_EHCI
bool
config IMX_HAVE_PLATFORM_MXC_MMC
bool
config IMX_HAVE_PLATFORM_MXC_NAND
bool
config IMX_HAVE_PLATFORM_MXC_PWM
bool
config IMX_HAVE_PLATFORM_MXC_RNGA
bool
select ARCH_HAS_RNGA
config IMX_HAVE_PLATFORM_MXC_W1
bool
config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
bool
config IMX_HAVE_PLATFORM_SPI_IMX
bool
arch/arm/plat-mxc/devices/Makefile
View file @ 2a85927c
obj-$(CONFIG_IMX_HAVE_PLATFORM_ESDHC) += platform-esdhc.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o
obj-y += platform-imx-dma.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o
arch/arm/plat-mxc/devices/platform-fec.c
View file @ 2a85927c
......@@ -16,17 +16,17 @@
.irq = soc ## _INT_FEC, \
}
#ifdef CONFIG_ARCH_MX25
#ifdef CONFIG_SOC_IMX25
const struct imx_fec_data imx25_fec_data __initconst =
imx_fec_data_entry_single(MX25);
#endif /* ifdef CONFIG_ARCH_MX25 */
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_fec_data imx27_fec_data __initconst =
imx_fec_data_entry_single(MX27);
#endif /* ifdef CONFIG_SOC_IMX27 */
#ifdef CONFIG_ARCH_MX35
#ifdef CONFIG_SOC_IMX35
const struct imx_fec_data imx35_fec_data __initconst =
imx_fec_data_entry_single(MX35);
#endif
......
arch/arm/plat-mxc/devices/platform-flexcan.c
View file @ 2a85927c
......@@ -5,26 +5,54 @@
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <mach/hardware.h>
#include <mach/devices-common.h>
struct platform_device *__init imx_add_flexcan(int id,
resource_size_t iobase, resource_size_t iosize,
resource_size_t irq,
#define imx_flexcan_data_entry_single(soc, _id, _hwid, _size) \
{ \
.id = _id, \
.iobase = soc ## _CAN ## _hwid ## _BASE_ADDR, \
.iosize = _size, \
.irq = soc ## _INT_CAN ## _hwid, \
}
#define imx_flexcan_data_entry(soc, _id, _hwid, _size) \
[_id] = imx_flexcan_data_entry_single(soc, _id, _hwid, _size)
#ifdef CONFIG_SOC_IMX25
const struct imx_flexcan_data imx25_flexcan_data[] __initconst = {
#define imx25_flexcan_data_entry(_id, _hwid) \
imx_flexcan_data_entry(MX25, _id, _hwid, SZ_16K)
imx25_flexcan_data_entry(0, 1),
imx25_flexcan_data_entry(1, 2),
};
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX35
const struct imx_flexcan_data imx35_flexcan_data[] __initconst = {
#define imx35_flexcan_data_entry(_id, _hwid) \
imx_flexcan_data_entry(MX35, _id, _hwid, SZ_16K)
imx35_flexcan_data_entry(0, 1),
imx35_flexcan_data_entry(1, 2),
};
#endif /* ifdef CONFIG_SOC_IMX35 */
struct platform_device *__init imx_add_flexcan(
const struct imx_flexcan_data *data,
const struct flexcan_platform_data *pdata)
{
struct resource res[] = {
{
.start = iobase,
.end = iobase + iosize - 1,
.start = data->iobase,
.end = data->iobase + data->iosize - 1,
.flags = IORESOURCE_MEM,
}, {
.start = irq,
.end = irq,
.start = data->irq,
.end = data->irq,
.flags = IORESOURCE_IRQ,
},
};
return imx_add_platform_device("flexcan", id, res, ARRAY_SIZE(res),
pdata, sizeof(*pdata));
return imx_add_platform_device("flexcan", data->id,
res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
}
arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c 0 → 100644
View file @ 2a85927c
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <mach/hardware.h>
#include <mach/devices-common.h>
#define imx_fsl_usb2_udc_data_entry_single(soc) \
{ \
.iobase = soc ## _USB_OTG_BASE_ADDR, \
.irq = soc ## _INT_USB_OTG, \
}
#ifdef CONFIG_SOC_IMX25
const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst =
imx_fsl_usb2_udc_data_entry_single(MX25);
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst =
imx_fsl_usb2_udc_data_entry_single(MX27);
#endif /* ifdef CONFIG_SOC_IMX27 */
#ifdef CONFIG_SOC_IMX31
const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst =
imx_fsl_usb2_udc_data_entry_single(MX31);
#endif /* ifdef CONFIG_SOC_IMX31 */
#ifdef CONFIG_SOC_IMX35
const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst =
imx_fsl_usb2_udc_data_entry_single(MX35);
#endif /* ifdef CONFIG_SOC_IMX35 */
struct platform_device *__init imx_add_fsl_usb2_udc(
const struct imx_fsl_usb2_udc_data *data,
const struct fsl_usb2_platform_data *pdata)
{
struct resource res[] = {
{
.start = data->iobase,
.end = data->iobase + SZ_512 - 1,
.flags = IORESOURCE_MEM,
}, {
.start = data->irq,
.end = data->irq,
.flags = IORESOURCE_IRQ,
},
};
return imx_add_platform_device_dmamask("fsl-usb2-udc", -1,
res, ARRAY_SIZE(res),
pdata, sizeof(*pdata), DMA_BIT_MASK(32));
}
arch/arm/plat-mxc/devices/platform-imx-dma.c
View file @ 2a85927c
......@@ -39,20 +39,20 @@ struct imx_imx_sdma_data {
}, \
}
#ifdef CONFIG_ARCH_MX25
#ifdef CONFIG_SOC_IMX25
const struct imx_imx_sdma_data imx25_imx_sdma_data __initconst =
imx_imx_sdma_data_entry_single(MX25, 1, "imx25", 0);
#endif /* ifdef CONFIG_ARCH_MX25 */
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_ARCH_MX31
#ifdef CONFIG_SOC_IMX31
struct imx_imx_sdma_data imx31_imx_sdma_data __initdata =
imx_imx_sdma_data_entry_single(MX31, 1, "imx31", 0);
#endif /* ifdef CONFIG_ARCH_MX31 */
#endif /* ifdef CONFIG_SOC_IMX31 */
#ifdef CONFIG_ARCH_MX35
#ifdef CONFIG_SOC_IMX35
struct imx_imx_sdma_data imx35_imx_sdma_data __initdata =
imx_imx_sdma_data_entry_single(MX35, 2, "imx35", 0);
#endif /* ifdef CONFIG_ARCH_MX35 */
#endif /* ifdef CONFIG_SOC_IMX35 */
#ifdef CONFIG_ARCH_MX51
const struct imx_imx_sdma_data imx51_imx_sdma_data __initconst =
......@@ -94,20 +94,20 @@ static int __init imxXX_add_imx_dma(void)
else
#endif
#if defined(CONFIG_ARCH_MX25)
#if defined(CONFIG_SOC_IMX25)
if (cpu_is_mx25())
ret = imx_add_imx_sdma(&imx25_imx_sdma_data);
else
#endif
#if defined(CONFIG_ARCH_MX31)
#if defined(CONFIG_SOC_IMX31)
if (cpu_is_mx31()) {
imx31_imx_sdma_data.pdata.to_version = mx31_revision() >> 4;
ret = imx_add_imx_sdma(&imx31_imx_sdma_data);
} else
#endif
#if defined(CONFIG_ARCH_MX35)
#if defined(CONFIG_SOC_IMX35)
if (cpu_is_mx35()) {
imx35_imx_sdma_data.pdata.to_version = mx35_revision() >> 4;
ret = imx_add_imx_sdma(&imx35_imx_sdma_data);
......
arch/arm/plat-mxc/devices/platform-imx-fb.c 0 → 100644
View file @ 2a85927c
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <mach/hardware.h>
#include <mach/devices-common.h>
#define imx_imx_fb_data_entry_single(soc, _size) \
{ \
.iobase = soc ## _LCDC_BASE_ADDR, \
.iosize = _size, \
.irq = soc ## _INT_LCDC, \
}
#ifdef CONFIG_SOC_IMX21
const struct imx_imx_fb_data imx21_imx_fb_data __initconst =
imx_imx_fb_data_entry_single(MX21, SZ_4K);
#endif /* ifdef CONFIG_SOC_IMX21 */
#ifdef CONFIG_SOC_IMX25
const struct imx_imx_fb_data imx25_imx_fb_data __initconst =
imx_imx_fb_data_entry_single(MX25, SZ_16K);
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_imx_fb_data imx27_imx_fb_data __initconst =
imx_imx_fb_data_entry_single(MX27, SZ_4K);
#endif /* ifdef CONFIG_SOC_IMX27 */
struct platform_device *__init imx_add_imx_fb(
const struct imx_imx_fb_data *data,
const struct imx_fb_platform_data *pdata)
{
struct resource res[] = {
{
.start = data->iobase,
.end = data->iobase + data->iosize - 1,
.flags = IORESOURCE_MEM,
}, {
.start = data->irq,
.end = data->irq,
.flags = IORESOURCE_IRQ,
},
};
return imx_add_platform_device_dmamask("imx-fb", 0,
res, ARRAY_SIZE(res),
pdata, sizeof(*pdata), DMA_BIT_MASK(32));
}
arch/arm/plat-mxc/devices/platform-imx-i2c.c
View file @ 2a85927c
......@@ -30,7 +30,7 @@ const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst =
imx_imx_i2c_data_entry_single(MX21, 0, , SZ_4K);
#endif /* ifdef CONFIG_SOC_IMX21 */
#ifdef CONFIG_ARCH_MX25
#ifdef CONFIG_SOC_IMX25
const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = {
#define imx25_imx_i2c_data_entry(_id, _hwid) \
imx_imx_i2c_data_entry(MX25, _id, _hwid, SZ_16K)
......@@ -38,7 +38,7 @@ const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = {
imx25_imx_i2c_data_entry(1, 2),
imx25_imx_i2c_data_entry(2, 3),
};
#endif /* ifdef CONFIG_ARCH_MX25 */
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = {
......@@ -49,7 +49,7 @@ const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = {
};
#endif /* ifdef CONFIG_SOC_IMX27 */
#ifdef CONFIG_ARCH_MX31
#ifdef CONFIG_SOC_IMX31
const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = {
#define imx31_imx_i2c_data_entry(_id, _hwid) \
imx_imx_i2c_data_entry(MX31, _id, _hwid, SZ_4K)
......@@ -57,9 +57,9 @@ const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = {
imx31_imx_i2c_data_entry(1, 2),
imx31_imx_i2c_data_entry(2, 3),
};
#endif /* ifdef CONFIG_ARCH_MX31 */
#endif /* ifdef CONFIG_SOC_IMX31 */
#ifdef CONFIG_ARCH_MX35
#ifdef CONFIG_SOC_IMX35
const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
#define imx35_imx_i2c_data_entry(_id, _hwid) \
imx_imx_i2c_data_entry(MX35, _id, _hwid, SZ_4K)
......@@ -67,7 +67,7 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
imx35_imx_i2c_data_entry(1, 2),
imx35_imx_i2c_data_entry(2, 3),
};
#endif /* ifdef CONFIG_ARCH_MX35 */
#endif /* ifdef CONFIG_SOC_IMX35 */
#ifdef CONFIG_ARCH_MX51
const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = {
......
arch/arm/plat-mxc/devices/platform-imx-keypad.c 0 → 100644
View file @ 2a85927c
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <mach/hardware.h>
#include <mach/devices-common.h>
#define imx_imx_keypad_data_entry_single(soc, _size) \
{ \
.iobase = soc ## _KPP_BASE_ADDR, \
.iosize = _size, \
.irq = soc ## _INT_KPP, \
}
#ifdef CONFIG_SOC_IMX21
const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst =
imx_imx_keypad_data_entry_single(MX21, SZ_16);
#endif /* ifdef CONFIG_SOC_IMX21 */
#ifdef CONFIG_SOC_IMX25
const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst =
imx_imx_keypad_data_entry_single(MX25, SZ_16K);
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst =
imx_imx_keypad_data_entry_single(MX27, SZ_16);
#endif /* ifdef CONFIG_SOC_IMX27 */
#ifdef CONFIG_SOC_IMX31
const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst =
imx_imx_keypad_data_entry_single(MX31, SZ_16);
#endif /* ifdef CONFIG_SOC_IMX31 */
#ifdef CONFIG_SOC_IMX35
const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst =
imx_imx_keypad_data_entry_single(MX35, SZ_16);
#endif /* ifdef CONFIG_SOC_IMX35 */
struct platform_device *__init imx_add_imx_keypad(
const struct imx_imx_keypad_data *data,
const struct matrix_keymap_data *pdata)
{
struct resource res[] = {
{
.start = data->iobase,
.end = data->iobase + data->iosize - 1,
.flags = IORESOURCE_MEM,
}, {
.start = data->irq,
.end = data->irq,
.flags = IORESOURCE_IRQ,
},
};
return imx_add_platform_device("imx-keypad", -1,
res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
}
arch/arm/plat-mxc/devices/platform-imx-ssi.c
View file @ 2a85927c
......@@ -30,14 +30,14 @@ const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst = {
};
#endif /* ifdef CONFIG_SOC_IMX21 */
#ifdef CONFIG_ARCH_MX25
#ifdef CONFIG_SOC_IMX25
const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = {
#define imx25_imx_ssi_data_entry(_id, _hwid) \
imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K)
imx25_imx_ssi_data_entry(0, 1),
imx25_imx_ssi_data_entry(1, 2),
};
#endif /* ifdef CONFIG_ARCH_MX25 */
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = {
......@@ -48,23 +48,23 @@ const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = {
};
#endif /* ifdef CONFIG_SOC_IMX27 */
#ifdef CONFIG_ARCH_MX31
#ifdef CONFIG_SOC_IMX31
const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst = {
#define imx31_imx_ssi_data_entry(_id, _hwid) \
imx_imx_ssi_data_entry(MX31, _id, _hwid, SZ_4K)
imx31_imx_ssi_data_entry(0, 1),
imx31_imx_ssi_data_entry(1, 2),
};
#endif /* ifdef CONFIG_ARCH_MX31 */
#endif /* ifdef CONFIG_SOC_IMX31 */
#ifdef CONFIG_ARCH_MX35
#ifdef CONFIG_SOC_IMX35
const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = {
#define imx35_imx_ssi_data_entry(_id, _hwid) \
imx_imx_ssi_data_entry(MX35, _id, _hwid, SZ_4K)
imx35_imx_ssi_data_entry(0, 1),
imx35_imx_ssi_data_entry(1, 2),
};
#endif /* ifdef CONFIG_ARCH_MX35 */
#endif /* ifdef CONFIG_SOC_IMX35 */
#ifdef CONFIG_ARCH_MX51
const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = {
......
arch/arm/plat-mxc/devices/platform-imx-uart.c
View file @ 2a85927c
......@@ -47,7 +47,7 @@ const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = {
};
#endif
#ifdef CONFIG_ARCH_MX25
#ifdef CONFIG_SOC_IMX25
const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = {
#define imx25_imx_uart_data_entry(_id, _hwid) \
imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K)
......@@ -57,7 +57,7 @@ const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = {
imx25_imx_uart_data_entry(3, 4),
imx25_imx_uart_data_entry(4, 5),
};
#endif /* ifdef CONFIG_ARCH_MX25 */
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = {
......@@ -72,7 +72,7 @@ const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = {
};
#endif /* ifdef CONFIG_SOC_IMX27 */
#ifdef CONFIG_ARCH_MX31
#ifdef CONFIG_SOC_IMX31
const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = {
#define imx31_imx_uart_data_entry(_id, _hwid) \
imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_4K)
......@@ -82,9 +82,9 @@ const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = {
imx31_imx_uart_data_entry(3, 4),
imx31_imx_uart_data_entry(4, 5),
};
#endif /* ifdef CONFIG_ARCH_MX31 */
#endif /* ifdef CONFIG_SOC_IMX31 */
#ifdef CONFIG_ARCH_MX35
#ifdef CONFIG_SOC_IMX35
const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = {
#define imx35_imx_uart_data_entry(_id, _hwid) \
imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K)
......@@ -92,7 +92,7 @@ const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = {
imx35_imx_uart_data_entry(1, 2),
imx35_imx_uart_data_entry(2, 3),
};
#endif /* ifdef CONFIG_ARCH_MX35 */
#endif /* ifdef CONFIG_SOC_IMX35 */
#ifdef CONFIG_ARCH_MX51
const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = {
......
arch/arm/plat-mxc/devices/platform-imx2-wdt.c 0 → 100644
View file @ 2a85927c
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <asm/sizes.h>
#include <mach/hardware.h>
#include <mach/devices-common.h>
#define imx_imx2_wdt_data_entry_single(soc, _size) \
{ \
.iobase = soc ## _WDOG_BASE_ADDR, \
.iosize = _size, \
}
#ifdef CONFIG_SOC_IMX21
const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst =
imx_imx2_wdt_data_entry_single(MX21, SZ_4K);
#endif /* ifdef CONFIG_SOC_IMX21 */
#ifdef CONFIG_SOC_IMX25
const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst =
imx_imx2_wdt_data_entry_single(MX25, SZ_16K);
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst =
imx_imx2_wdt_data_entry_single(MX27, SZ_4K);
#endif /* ifdef CONFIG_SOC_IMX27 */
#ifdef CONFIG_SOC_IMX31
const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst =
imx_imx2_wdt_data_entry_single(MX31, SZ_16K);
#endif /* ifdef CONFIG_SOC_IMX31 */
#ifdef CONFIG_SOC_IMX35
const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst =
imx_imx2_wdt_data_entry_single(MX35, SZ_16K);
#endif /* ifdef CONFIG_SOC_IMX35 */
struct platform_device *__init imx_add_imx2_wdt(
const struct imx_imx2_wdt_data *data)
{
struct resource res[] = {
{
.start = data->iobase,
.end = data->iobase + data->iosize - 1,
.flags = IORESOURCE_MEM,
},
};
return imx_add_platform_device("imx2-wdt", 0,
res, ARRAY_SIZE(res), NULL, 0);
}
arch/arm/plat-mxc/devices/platform-imx21-hcd.c 0 → 100644
View file @ 2a85927c
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <mach/hardware.h>
#include <mach/devices-common.h>
#define imx_imx21_hcd_data_entry_single(soc) \
{ \
.iobase = soc ## _USBOTG_BASE_ADDR, \
.irq = soc ## _INT_USBHOST, \
}
#ifdef CONFIG_SOC_IMX21
const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst =
imx_imx21_hcd_data_entry_single(MX21);
#endif /* ifdef CONFIG_SOC_IMX21 */
struct platform_device *__init imx_add_imx21_hcd(
const struct imx_imx21_hcd_data *data,
const struct mx21_usbh_platform_data *pdata)
{
struct resource res[] = {
{
.start = data->iobase,
.end = data->iobase + SZ_8K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = data->irq,
.end = data->irq,
.flags = IORESOURCE_IRQ,
},
};
return imx_add_platform_device_dmamask("imx21-hcd", 0,
res, ARRAY_SIZE(res),
pdata, sizeof(*pdata), DMA_BIT_MASK(32));
}
arch/arm/plat-mxc/devices/platform-imx_udc.c 0 → 100644
View file @ 2a85927c
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <mach/hardware.h>
#include <mach/devices-common.h>
#define imx_imx_udc_data_entry_single(soc, _size) \
{ \
.iobase = soc ## _USBD_BASE_ADDR, \
.iosize = _size, \
.irq0 = soc ## _INT_USBD0, \
.irq1 = soc ## _INT_USBD1, \
.irq2 = soc ## _INT_USBD2, \
.irq3 = soc ## _INT_USBD3, \
.irq4 = soc ## _INT_USBD4, \
.irq5 = soc ## _INT_USBD5, \
.irq6 = soc ## _INT_USBD6, \
}
#define imx_imx_udc_data_entry(soc, _size) \
[_id] = imx_imx_udc_data_entry_single(soc, _size)
#ifdef CONFIG_SOC_IMX1
const struct imx_imx_udc_data imx1_imx_udc_data __initconst =
imx_imx_udc_data_entry_single(MX1, SZ_4K);
#endif /* ifdef CONFIG_SOC_IMX1 */
struct platform_device *__init imx_add_imx_udc(
const struct imx_imx_udc_data *data,
const struct imxusb_platform_data *pdata)
{
struct resource res[] = {
{
.start = data->iobase,
.end = data->iobase + data->iosize - 1,
.flags = IORESOURCE_MEM,
}, {
.start = data->irq0,
.end = data->irq0,
.flags = IORESOURCE_IRQ,
}, {
.start = data->irq1,
.end = data->irq1,
.flags = IORESOURCE_IRQ,
}, {
.start = data->irq2,
.end = data->irq2,
.flags = IORESOURCE_IRQ,
}, {
.start = data->irq3,
.end = data->irq3,
.flags = IORESOURCE_IRQ,
}, {
.start = data->irq4,
.end = data->irq4,
.flags = IORESOURCE_IRQ,
}, {
.start = data->irq5,
.end = data->irq5,
.flags = IORESOURCE_IRQ,
}, {
.start = data->irq6,
.end = data->irq6,
.flags = IORESOURCE_IRQ,
},
};
return imx_add_platform_device("imx_udc", 0,
res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
}
arch/arm/plat-mxc/devices/platform-imxdi_rtc.c 0 → 100644
View file @ 2a85927c
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <asm/sizes.h>
#include <mach/hardware.h>
#include <mach/devices-common.h>
#define imx_imxdi_rtc_data_entry_single(soc) \
{ \
.iobase = soc ## _DRYICE_BASE_ADDR, \
.irq = soc ## _INT_DRYICE, \
}
#ifdef CONFIG_SOC_IMX25
const struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst =
imx_imxdi_rtc_data_entry_single(MX25);
#endif /* ifdef CONFIG_SOC_IMX25 */
struct platform_device *__init imx_add_imxdi_rtc(
const struct imx_imxdi_rtc_data *data)
{
struct resource res[] = {
{
.start = data->iobase,
.end = data->iobase + SZ_16K,
.flags = IORESOURCE_MEM,
}, {
.start = data->irq,
.end = data->irq,
.flags = IORESOURCE_IRQ,
},
};
return imx_add_platform_device("imxdi_rtc", 0,
res, ARRAY_SIZE(res), NULL, 0);
}
arch/arm/plat-mxc/devices/platform-mx1-camera.c 0 → 100644
View file @ 2a85927c
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <mach/hardware.h>
#include <mach/devices-common.h>
#define imx_mx1_camera_data_entry_single(soc, _size) \
{ \
.iobase = soc ## _CSI ## _BASE_ADDR, \
.iosize = _size, \
.irq = soc ## _INT_CSI, \
}
#ifdef CONFIG_SOC_IMX1
const struct imx_mx1_camera_data imx1_mx1_camera_data __initconst =
imx_mx1_camera_data_entry_single(MX1, 10);
#endif /* ifdef CONFIG_SOC_IMX1 */
struct platform_device *__init imx_add_mx1_camera(
const struct imx_mx1_camera_data *data,
const struct mx1_camera_pdata *pdata)
{
struct resource res[] = {
{
.start = data->iobase,
.end = data->iobase + data->iosize - 1,
.flags = IORESOURCE_MEM,
}, {
.start = data->irq,
.end = data->irq,
.flags = IORESOURCE_IRQ,
},
};
return imx_add_platform_device_dmamask("mx1-camera", 0,
res, ARRAY_SIZE(res),
pdata, sizeof(*pdata), DMA_BIT_MASK(32));
}
arch/arm/plat-mxc/devices/platform-mx2-camera.c 0 → 100644
View file @ 2a85927c
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <mach/hardware.h>
#include <mach/devices-common.h>
#define imx_mx2_camera_data_entry_single(soc) \
{ \
.iobasecsi = soc ## _CSI_BASE_ADDR, \
.iosizecsi = SZ_4K, \
.irqcsi = soc ## _INT_CSI, \
}
#define imx_mx2_camera_data_entry_single_emma(soc) \
{ \
.iobasecsi = soc ## _CSI_BASE_ADDR, \
.iosizecsi = SZ_32, \
.irqcsi = soc ## _INT_CSI, \
.iobaseemmaprp = soc ## _EMMAPRP_BASE_ADDR, \
.iosizeemmaprp = SZ_32, \
.irqemmaprp = soc ## _INT_EMMAPRP, \
}
#ifdef CONFIG_SOC_IMX25
const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst =
imx_mx2_camera_data_entry_single(MX25);
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst =
imx_mx2_camera_data_entry_single_emma(MX27);
#endif /* ifdef CONFIG_SOC_IMX27 */
struct platform_device *__init imx_add_mx2_camera(
const struct imx_mx2_camera_data *data,
const struct mx2_camera_platform_data *pdata)
{
struct resource res[] = {
{
.start = data->iobasecsi,
.end = data->iobasecsi + data->iosizecsi - 1,
.flags = IORESOURCE_MEM,
}, {
.start = data->irqcsi,
.end = data->irqcsi,
.flags = IORESOURCE_IRQ,
}, {
.start = data->iobaseemmaprp,
.end = data->iobaseemmaprp + data->iosizeemmaprp - 1,
.flags = IORESOURCE_MEM,
}, {
.start = data->irqemmaprp,
.end = data->irqemmaprp,
.flags = IORESOURCE_IRQ,
},
};
return imx_add_platform_device_dmamask("mx2-camera", 0,
res, data->iobaseemmaprp ? 4 : 2,
pdata, sizeof(*pdata), DMA_BIT_MASK(32));
}
arch/arm/plat-mxc/devices/platform-mxc-ehci.c 0 → 100644
View file @ 2a85927c
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <mach/hardware.h>
#include <mach/devices-common.h>
#define imx_mxc_ehci_data_entry_single(soc, _id, hs) \
{ \
.id = _id, \
.iobase = soc ## _USB_ ## hs ## _BASE_ADDR, \
.irq = soc ## _INT_USB_ ## hs, \
}
#ifdef CONFIG_SOC_IMX25
const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst =
imx_mxc_ehci_data_entry_single(MX25, 0, OTG);
const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst =
imx_mxc_ehci_data_entry_single(MX25, 1, HS);
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst =
imx_mxc_ehci_data_entry_single(MX27, 0, OTG);
const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst = {
imx_mxc_ehci_data_entry_single(MX27, 1, HS1),
imx_mxc_ehci_data_entry_single(MX27, 2, HS2),
};
#endif /* ifdef CONFIG_SOC_IMX27 */
#ifdef CONFIG_SOC_IMX31
const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst =
imx_mxc_ehci_data_entry_single(MX31, 0, OTG);
const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst = {
imx_mxc_ehci_data_entry_single(MX31, 1, HS1),
imx_mxc_ehci_data_entry_single(MX31, 2, HS2),
};
#endif /* ifdef CONFIG_SOC_IMX31 */
#ifdef CONFIG_SOC_IMX35
const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst =
imx_mxc_ehci_data_entry_single(MX35, 0, OTG);
const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst =
imx_mxc_ehci_data_entry_single(MX35, 1, HS);
#endif /* ifdef CONFIG_SOC_IMX35 */
struct platform_device *__init imx_add_mxc_ehci(
const struct imx_mxc_ehci_data *data,
const struct mxc_usbh_platform_data *pdata)
{
struct resource res[] = {
{
.start = data->iobase,
.end = data->iobase + SZ_512 - 1,
.flags = IORESOURCE_MEM,
}, {
.start = data->irq,
.end = data->irq,
.flags = IORESOURCE_IRQ,
},
};
return imx_add_platform_device_dmamask("mxc-ehci", data->id,
res, ARRAY_SIZE(res),
pdata, sizeof(*pdata), DMA_BIT_MASK(32));
}
arch/arm/plat-mxc/devices/platform-mxc-mmc.c 0 → 100644
View file @ 2a85927c
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <mach/hardware.h>
#include <mach/devices-common.h>
#define imx_mxc_mmc_data_entry_single(soc, _id, _hwid, _size) \
{ \
.id = _id, \
.iobase = soc ## _SDHC ## _hwid ## _BASE_ADDR, \
.iosize = _size, \
.irq = soc ## _INT_SDHC ## _hwid, \
.dmareq = soc ## _DMA_REQ_SDHC ## _hwid, \
}
#define imx_mxc_mmc_data_entry(soc, _id, _hwid, _size) \
[_id] = imx_mxc_mmc_data_entry_single(soc, _id, _hwid, _size)
#ifdef CONFIG_SOC_IMX21
const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst = {
#define imx21_mxc_mmc_data_entry(_id, _hwid) \
imx_mxc_mmc_data_entry(MX21, _id, _hwid, SZ_4K)
imx21_mxc_mmc_data_entry(0, 1),
imx21_mxc_mmc_data_entry(1, 2),
};
#endif /* ifdef CONFIG_SOC_IMX21 */
#ifdef CONFIG_SOC_IMX27
const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst = {
#define imx27_mxc_mmc_data_entry(_id, _hwid) \
imx_mxc_mmc_data_entry(MX27, _id, _hwid, SZ_4K)
imx27_mxc_mmc_data_entry(0, 1),
imx27_mxc_mmc_data_entry(1, 2),
};
#endif /* ifdef CONFIG_SOC_IMX27 */
#ifdef CONFIG_SOC_IMX31
const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst = {
#define imx31_mxc_mmc_data_entry(_id, _hwid) \
imx_mxc_mmc_data_entry(MX31, _id, _hwid, SZ_16K)
imx31_mxc_mmc_data_entry(0, 1),
imx31_mxc_mmc_data_entry(1, 2),
};
#endif /* ifdef CONFIG_SOC_IMX31 */
struct platform_device *__init imx_add_mxc_mmc(
const struct imx_mxc_mmc_data *data,
const struct imxmmc_platform_data *pdata)
{
struct resource res[] = {
{
.start = data->iobase,
.end = data->iobase + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = data->irq,
.end = data->irq,
.flags = IORESOURCE_IRQ,
}, {
.start = data->dmareq,
.end = data->dmareq,
.flags = IORESOURCE_DMA,
},
};
return imx_add_platform_device_dmamask("mxc-mmc", data->id,
res, ARRAY_SIZE(res),
pdata, sizeof(*pdata), DMA_BIT_MASK(32));
}
arch/arm/plat-mxc/devices/platform-mxc_nand.c
View file @ 2a85927c
......@@ -31,22 +31,22 @@ const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst =
imx_mxc_nand_data_entry_single(MX21, SZ_4K);
#endif /* ifdef CONFIG_SOC_IMX21 */
#ifdef CONFIG_ARCH_MX25
#ifdef CONFIG_SOC_IMX25
const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst =
imx_mxc_nand_data_entry_single(MX25, SZ_8K);
#endif /* ifdef CONFIG_ARCH_MX25 */
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst =
imx_mxc_nand_data_entry_single(MX27, SZ_4K);
#endif /* ifdef CONFIG_SOC_IMX27 */
#ifdef CONFIG_ARCH_MX31
#ifdef CONFIG_SOC_IMX31
const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst =
imx_mxc_nand_data_entry_single(MX31, SZ_4K);
#endif
#ifdef CONFIG_ARCH_MX35
#ifdef CONFIG_SOC_IMX35
const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst =
imx_mxc_nand_data_entry_single(MX35, SZ_8K);
#endif
......
arch/arm/plat-mxc/devices/platform-mxc_pwm.c 0 → 100644
View file @ 2a85927c
/*
* Copyright (C) 2009-2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <mach/hardware.h>
#include <mach/devices-common.h>
#define imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size) \
{ \
.id = _id, \
.iobase = soc ## _PWM ## _hwid ## _BASE_ADDR, \
.iosize = _size, \
.irq = soc ## _INT_PWM ## _hwid, \
}
#define imx_mxc_pwm_data_entry(soc, _id, _hwid, _size) \
[_id] = imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size)
#ifdef CONFIG_SOC_IMX21
const struct imx_mxc_pwm_data imx21_mxc_pwm_data __initconst =
imx_mxc_pwm_data_entry_single(MX21, 0, , SZ_4K);
#endif /* ifdef CONFIG_SOC_IMX21 */
#ifdef CONFIG_SOC_IMX25
const struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst = {
#define imx25_mxc_pwm_data_entry(_id, _hwid) \
imx_mxc_pwm_data_entry(MX25, _id, _hwid, SZ_16K)
imx25_mxc_pwm_data_entry(0, 1),
imx25_mxc_pwm_data_entry(1, 2),
imx25_mxc_pwm_data_entry(2, 3),
imx25_mxc_pwm_data_entry(3, 4),
};
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_mxc_pwm_data imx27_mxc_pwm_data __initconst =
imx_mxc_pwm_data_entry_single(MX27, 0, , SZ_4K);
#endif /* ifdef CONFIG_SOC_IMX27 */
struct platform_device *__init imx_add_mxc_pwm(
const struct imx_mxc_pwm_data *data)
{
struct resource res[] = {
{
.start = data->iobase,
.end = data->iobase + data->iosize - 1,
.flags = IORESOURCE_MEM,
}, {
.start = data->irq,
.end = data->irq,
.flags = IORESOURCE_IRQ,
},
};
return imx_add_platform_device("mxc_pwm", data->id,
res, ARRAY_SIZE(res), NULL, 0);
}
arch/arm/plat-mxc/devices/platform-mxc_rnga.c 0 → 100644
View file @ 2a85927c
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <mach/hardware.h>
#include <mach/devices-common.h>
struct imx_mxc_rnga_data {
resource_size_t iobase;
};
#define imx_mxc_rnga_data_entry_single(soc) \
{ \
.iobase = soc ## _RNGA_BASE_ADDR, \
}
#ifdef CONFIG_SOC_IMX31
static const struct imx_mxc_rnga_data imx31_mxc_rnga_data __initconst =
imx_mxc_rnga_data_entry_single(MX31);
#endif /* ifdef CONFIG_SOC_IMX31 */
static struct platform_device *__init imx_add_mxc_rnga(
const struct imx_mxc_rnga_data *data)
{
struct resource res[] = {
{
.start = data->iobase,
.end = data->iobase + SZ_16K - 1,
.flags = IORESOURCE_MEM,
},
};
return imx_add_platform_device("mxc_rnga", -1,
res, ARRAY_SIZE(res), NULL, 0);
}
static int __init imxXX_add_mxc_rnga(void)
{
struct platform_device *ret;
#if defined(CONFIG_SOC_IMX31)
if (cpu_is_mx31())
ret = imx_add_mxc_rnga(&imx31_mxc_rnga_data);
else
#endif /* if defined(CONFIG_SOC_IMX31) */
ret = ERR_PTR(-ENODEV);
if (IS_ERR(ret))
return PTR_ERR(ret);
return 0;
}
arch_initcall(imxXX_add_mxc_rnga);
arch/arm/plat-mxc/devices/platform-mxc_w1.c 0 → 100644
View file @ 2a85927c
/*
* Copyright (C) 2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <mach/hardware.h>
#include <mach/devices-common.h>
#define imx_mxc_w1_data_entry_single(soc) \
{ \
.iobase = soc ## _OWIRE_BASE_ADDR, \
}
#ifdef CONFIG_SOC_IMX21
const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst =
imx_mxc_w1_data_entry_single(MX21);
#endif /* ifdef CONFIG_SOC_IMX21 */
#ifdef CONFIG_SOC_IMX27
const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst =
imx_mxc_w1_data_entry_single(MX27);
#endif /* ifdef CONFIG_SOC_IMX27 */
#ifdef CONFIG_SOC_IMX31
const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst =
imx_mxc_w1_data_entry_single(MX31);
#endif /* ifdef CONFIG_SOC_IMX31 */
#ifdef CONFIG_SOC_IMX35
const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst =
imx_mxc_w1_data_entry_single(MX35);
#endif /* ifdef CONFIG_SOC_IMX35 */
struct platform_device *__init imx_add_mxc_w1(
const struct imx_mxc_w1_data *data)
{
struct resource res[] = {
{
.start = data->iobase,
.end = data->iobase + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
return imx_add_platform_device("mxc_w1", 0,
res, ARRAY_SIZE(res), NULL, 0);
}
arch/arm/plat-mxc/devices/platform-esdhc.c → arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c
View file @ 2a85927c
......@@ -10,48 +10,51 @@
#include <mach/devices-common.h>
#include <mach/esdhc.h>
#define imx_esdhc_imx_data_entry_single(soc, _id, hwid) \
#define imx_sdhci_esdhc_imx_data_entry_single(soc, _id, hwid) \
{ \
.id = _id, \
.iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR, \
.irq = soc ## _INT_ESDHC ## hwid, \
}
#define imx_esdhc_imx_data_entry(soc, id, hwid) \
[id] = imx_esdhc_imx_data_entry_single(soc, id, hwid)
#define imx_sdhci_esdhc_imx_data_entry(soc, id, hwid) \
[id] = imx_sdhci_esdhc_imx_data_entry_single(soc, id, hwid)
#ifdef CONFIG_ARCH_MX25
const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst = {
#define imx25_esdhc_data_entry(_id, _hwid) \
imx_esdhc_imx_data_entry(MX25, _id, _hwid)
imx25_esdhc_data_entry(0, 1),
imx25_esdhc_data_entry(1, 2),
#ifdef CONFIG_SOC_IMX25
const struct imx_sdhci_esdhc_imx_data
imx25_sdhci_esdhc_imx_data[] __initconst = {
#define imx25_sdhci_esdhc_imx_data_entry(_id, _hwid) \
imx_sdhci_esdhc_imx_data_entry(MX25, _id, _hwid)
imx25_sdhci_esdhc_imx_data_entry(0, 1),
imx25_sdhci_esdhc_imx_data_entry(1, 2),
};
#endif /* ifdef CONFIG_ARCH_MX25 */
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_ARCH_MX35
const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst = {
#define imx35_esdhc_data_entry(_id, _hwid) \
imx_esdhc_imx_data_entry(MX35, _id, _hwid)
imx35_esdhc_data_entry(0, 1),
imx35_esdhc_data_entry(1, 2),
imx35_esdhc_data_entry(2, 3),
#ifdef CONFIG_SOC_IMX35
const struct imx_sdhci_esdhc_imx_data
imx35_sdhci_esdhc_imx_data[] __initconst = {
#define imx35_sdhci_esdhc_imx_data_entry(_id, _hwid) \
imx_sdhci_esdhc_imx_data_entry(MX35, _id, _hwid)
imx35_sdhci_esdhc_imx_data_entry(0, 1),
imx35_sdhci_esdhc_imx_data_entry(1, 2),
imx35_sdhci_esdhc_imx_data_entry(2, 3),
};
#endif /* ifdef CONFIG_ARCH_MX35 */
#endif /* ifdef CONFIG_SOC_IMX35 */
#ifdef CONFIG_ARCH_MX51
const struct imx_esdhc_imx_data imx51_esdhc_data[] __initconst = {
#define imx51_esdhc_data_entry(_id, _hwid) \
imx_esdhc_imx_data_entry(MX51, _id, _hwid)
imx51_esdhc_data_entry(0, 1),
imx51_esdhc_data_entry(1, 2),
imx51_esdhc_data_entry(2, 3),
imx51_esdhc_data_entry(3, 4),
const struct imx_sdhci_esdhc_imx_data
imx51_sdhci_esdhc_imx_data[] __initconst = {
#define imx51_sdhci_esdhc_imx_data_entry(_id, _hwid) \
imx_sdhci_esdhc_imx_data_entry(MX51, _id, _hwid)
imx51_sdhci_esdhc_imx_data_entry(0, 1),
imx51_sdhci_esdhc_imx_data_entry(1, 2),
imx51_sdhci_esdhc_imx_data_entry(2, 3),
imx51_sdhci_esdhc_imx_data_entry(3, 4),
};
#endif /* ifdef CONFIG_ARCH_MX51 */
struct platform_device *__init imx_add_esdhc(
const struct imx_esdhc_imx_data *data,
struct platform_device *__init imx_add_sdhci_esdhc_imx(
const struct imx_sdhci_esdhc_imx_data *data,
const struct esdhc_platform_data *pdata)
{
struct resource res[] = {
......
arch/arm/plat-mxc/devices/platform-spi_imx.c
View file @ 2a85927c
......@@ -29,7 +29,7 @@ const struct imx_spi_imx_data imx21_cspi_data[] __initconst = {
imx21_cspi_data_entry(1, 2),
#endif
#ifdef CONFIG_ARCH_MX25
#ifdef CONFIG_SOC_IMX25
const struct imx_spi_imx_data imx25_cspi_data[] __initconst = {
#define imx25_cspi_data_entry(_id, _hwid) \
imx_spi_imx_data_entry(MX25, CSPI, "imx25-cspi", _id, _hwid, SZ_16K)
......@@ -37,7 +37,7 @@ const struct imx_spi_imx_data imx25_cspi_data[] __initconst = {
imx25_cspi_data_entry(1, 2),
imx25_cspi_data_entry(2, 3),
};
#endif /* ifdef CONFIG_ARCH_MX25 */
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_spi_imx_data imx27_cspi_data[] __initconst = {
......@@ -49,7 +49,7 @@ const struct imx_spi_imx_data imx27_cspi_data[] __initconst = {
};
#endif /* ifdef CONFIG_SOC_IMX27 */
#ifdef CONFIG_ARCH_MX31
#ifdef CONFIG_SOC_IMX31
const struct imx_spi_imx_data imx31_cspi_data[] __initconst = {
#define imx31_cspi_data_entry(_id, _hwid) \
imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K)
......@@ -57,16 +57,16 @@ const struct imx_spi_imx_data imx31_cspi_data[] __initconst = {
imx31_cspi_data_entry(1, 2),
imx31_cspi_data_entry(2, 3),
};
#endif /* ifdef CONFIG_ARCH_MX31 */
#endif /* ifdef CONFIG_SOC_IMX31 */
#ifdef CONFIG_ARCH_MX35
#ifdef CONFIG_SOC_IMX35
const struct imx_spi_imx_data imx35_cspi_data[] __initconst = {
#define imx35_cspi_data_entry(_id, _hwid) \
imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K)
imx35_cspi_data_entry(0, 1),
imx35_cspi_data_entry(1, 2),
};
#endif /* ifdef CONFIG_ARCH_MX35 */
#endif /* ifdef CONFIG_SOC_IMX35 */
#ifdef CONFIG_ARCH_MX51
const struct imx_spi_imx_data imx51_cspi_data __initconst =
......
arch/arm/plat-mxc/ehci.c
View file @ 2a85927c
......@@ -69,9 +69,9 @@
int mxc_initialize_usb_hw(int port, unsigned int flags)
{
unsigned int v;
#if defined(CONFIG_ARCH_MX25)
#if defined(CONFIG_SOC_IMX25)
if (cpu_is_mx25()) {
v = readl(MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR +
v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR +
USBCTRL_OTGBASE_OFFSET));
switch (port) {
......@@ -108,11 +108,11 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
return -EINVAL;
}
writel(v, MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR +
writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR +
USBCTRL_OTGBASE_OFFSET));
return 0;
}
#endif /* CONFIG_ARCH_MX25 */
#endif /* if defined(CONFIG_SOC_IMX25) */
#if defined(CONFIG_ARCH_MX3)
if (cpu_is_mx31()) {
v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +
......
arch/arm/plat-mxc/gpio.c
View file @ 2a85927c
......@@ -175,7 +175,7 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
{
u32 irq_stat;
struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq);
struct mxc_gpio_port *port = get_irq_data(irq);
irq_stat = __raw_readl(port->base + GPIO_ISR) &
__raw_readl(port->base + GPIO_IMR);
......@@ -188,7 +188,7 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
{
int i;
u32 irq_msk, irq_stat;
struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq);
struct mxc_gpio_port *port = get_irq_data(irq);
/* walk through all interrupt status registers */
for (i = 0; i < gpio_table_size; i++) {
......@@ -349,3 +349,96 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
return 0;
}
#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq) \
{ \
.chip.label = "gpio-" #_id, \
.irq = _irq, \
.base = soc ## _IO_ADDRESS( \
soc ## _GPIO ## _hwid ## _BASE_ADDR), \
.virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32, \
}
#define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid) \
DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0)
#define DEFINE_REGISTER_FUNCTION(prefix) \
int __init prefix ## _register_gpios(void) \
{ \
return mxc_gpio_init(prefix ## _gpio_ports, \
ARRAY_SIZE(prefix ## _gpio_ports)); \
}
#if defined(CONFIG_SOC_IMX1)
static struct mxc_gpio_port imx1_gpio_ports[] = {
DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, 1, MX1_GPIO_INT_PORTA),
DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, 2, MX1_GPIO_INT_PORTB),
DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, 3, MX1_GPIO_INT_PORTC),
DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, 4, MX1_GPIO_INT_PORTD),
};
DEFINE_REGISTER_FUNCTION(imx1)
#endif /* if defined(CONFIG_SOC_IMX1) */
#if defined(CONFIG_SOC_IMX21)
static struct mxc_gpio_port imx21_gpio_ports[] = {
DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, 1, MX21_INT_GPIO),
DEFINE_IMX_GPIO_PORT(MX21, 1, 2),
DEFINE_IMX_GPIO_PORT(MX21, 2, 3),
DEFINE_IMX_GPIO_PORT(MX21, 3, 4),
DEFINE_IMX_GPIO_PORT(MX21, 4, 5),
DEFINE_IMX_GPIO_PORT(MX21, 5, 6),
};
DEFINE_REGISTER_FUNCTION(imx21)
#endif /* if defined(CONFIG_SOC_IMX21) */
#if defined(CONFIG_SOC_IMX25)
static struct mxc_gpio_port imx25_gpio_ports[] = {
DEFINE_IMX_GPIO_PORT_IRQ(MX25, 0, 1, MX25_INT_GPIO1),
DEFINE_IMX_GPIO_PORT_IRQ(MX25, 1, 2, MX25_INT_GPIO2),
DEFINE_IMX_GPIO_PORT_IRQ(MX25, 2, 3, MX25_INT_GPIO3),
DEFINE_IMX_GPIO_PORT_IRQ(MX25, 3, 4, MX25_INT_GPIO4),
};
DEFINE_REGISTER_FUNCTION(imx25)
#endif /* if defined(CONFIG_SOC_IMX25) */
#if defined(CONFIG_SOC_IMX27)
static struct mxc_gpio_port imx27_gpio_ports[] = {
DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, 1, MX27_INT_GPIO),
DEFINE_IMX_GPIO_PORT(MX27, 1, 2),
DEFINE_IMX_GPIO_PORT(MX27, 2, 3),
DEFINE_IMX_GPIO_PORT(MX27, 3, 4),
DEFINE_IMX_GPIO_PORT(MX27, 4, 5),
DEFINE_IMX_GPIO_PORT(MX27, 5, 6),
};
DEFINE_REGISTER_FUNCTION(imx27)
#endif /* if defined(CONFIG_SOC_IMX27) */
#if defined(CONFIG_SOC_IMX31)
static struct mxc_gpio_port imx31_gpio_ports[] = {
DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
};
DEFINE_REGISTER_FUNCTION(imx31)
#endif /* if defined(CONFIG_SOC_IMX31) */
#if defined(CONFIG_SOC_IMX35)
static struct mxc_gpio_port imx35_gpio_ports[] = {
DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
};
DEFINE_REGISTER_FUNCTION(imx35)
#endif /* if defined(CONFIG_SOC_IMX35) */
arch/arm/plat-mxc/include/mach/debug-macro.S
View file @ 2a85927c
......@@ -10,58 +10,49 @@
* published by the Free Software Foundation.
*
*/
#define IMX_NEEDS_DEPRECATED_SYMBOLS
#include <mach/hardware.h>
#ifdef CONFIG_ARCH_MX1
#include <mach/mx1.h>
#define UART_PADDR UART1_BASE_ADDR
#define UART_VADDR IO_ADDRESS(UART1_BASE_ADDR)
#define UART_PADDR MX1_UART1_BASE_ADDR
#endif
#ifdef CONFIG_ARCH_MX25
#ifdef UART_PADDR
#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
#endif
#include <mach/mx25.h>
#define UART_PADDR MX25_UART1_BASE_ADDR
#define UART_VADDR MX25_AIPS1_IO_ADDRESS(MX25_UART1_BASE_ADDR)
#endif
#ifdef CONFIG_ARCH_MX2
#ifdef UART_PADDR
#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
#endif
#include <mach/mx2x.h>
#define UART_PADDR UART1_BASE_ADDR
#define UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR)
#define UART_PADDR MX2x_UART1_BASE_ADDR
#endif
#ifdef CONFIG_ARCH_MX3
#ifdef UART_PADDR
#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
#endif
#include <mach/mx3x.h>
#define UART_PADDR UART1_BASE_ADDR
#define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
#define UART_PADDR MX3x_UART1_BASE_ADDR
#endif
#ifdef CONFIG_ARCH_MX5
#ifdef UART_PADDR
#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
#endif
#include <mach/mx51.h>
#define UART_PADDR MX51_UART1_BASE_ADDR
#define UART_VADDR MX51_AIPS1_IO_ADDRESS(MX51_UART1_BASE_ADDR)
#endif
#ifdef CONFIG_ARCH_MXC91231
#ifdef UART_PADDR
#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
#endif
#include <mach/mxc91231.h>
#define UART_PADDR MXC91231_UART2_BASE_ADDR
#define UART_VADDR MXC91231_IO_ADDRESS(MXC91231_UART2_BASE_ADDR)
#endif
#define UART_VADDR IMX_IO_ADDRESS(UART_PADDR)
.macro addruart, rp, rv
ldr \rp, =UART_PADDR @ physical
ldr \rv, =UART_VADDR @ virtual
......
arch/arm/plat-mxc/include/mach/devices-common.h
View file @ 2a85927c
......@@ -10,9 +10,19 @@
#include <linux/platform_device.h>
#include <linux/init.h>
struct platform_device *imx_add_platform_device(const char *name, int id,
struct platform_device *imx_add_platform_device_dmamask(
const char *name, int id,
const struct resource *res, unsigned int num_resources,
const void *data, size_t size_data);
const void *data, size_t size_data, u64 dmamask);
static inline struct platform_device *imx_add_platform_device(
const char *name, int id,
const struct resource *res, unsigned int num_resources,
const void *data, size_t size_data)
{
return imx_add_platform_device_dmamask(
name, id, res, num_resources, data, size_data, 0);
}
#include <linux/fec.h>
struct imx_fec_data {
......@@ -24,15 +34,62 @@ struct platform_device *__init imx_add_fec(
const struct fec_platform_data *pdata);
#include <linux/can/platform/flexcan.h>
struct platform_device *__init imx_add_flexcan(int id,
resource_size_t iobase, resource_size_t iosize,
resource_size_t irq,
struct imx_flexcan_data {
int id;
resource_size_t iobase;
resource_size_t iosize;
resource_size_t irq;
};
struct platform_device *__init imx_add_flexcan(
const struct imx_flexcan_data *data,
const struct flexcan_platform_data *pdata);
#include <linux/fsl_devices.h>
struct imx_fsl_usb2_udc_data {
resource_size_t iobase;
resource_size_t irq;
};
struct platform_device *__init imx_add_fsl_usb2_udc(
const struct imx_fsl_usb2_udc_data *data,
const struct fsl_usb2_platform_data *pdata);
#include <linux/gpio_keys.h>
struct platform_device *__init imx_add_gpio_keys(
const struct gpio_keys_platform_data *pdata);
#include <mach/mx21-usbhost.h>
struct imx_imx21_hcd_data {
resource_size_t iobase;
resource_size_t irq;
};
struct platform_device *__init imx_add_imx21_hcd(
const struct imx_imx21_hcd_data *data,
const struct mx21_usbh_platform_data *pdata);
struct imx_imx2_wdt_data {
resource_size_t iobase;
resource_size_t iosize;
};
struct platform_device *__init imx_add_imx2_wdt(
const struct imx_imx2_wdt_data *data);
struct imx_imxdi_rtc_data {
resource_size_t iobase;
resource_size_t irq;
};
struct platform_device *__init imx_add_imxdi_rtc(
const struct imx_imxdi_rtc_data *data);
#include <mach/imxfb.h>
struct imx_imx_fb_data {
resource_size_t iobase;
resource_size_t iosize;
resource_size_t irq;
};
struct platform_device *__init imx_add_imx_fb(
const struct imx_imx_fb_data *data,
const struct imx_fb_platform_data *pdata);
#include <mach/i2c.h>
struct imx_imx_i2c_data {
int id;
......@@ -44,6 +101,16 @@ struct platform_device *__init imx_add_imx_i2c(
const struct imx_imx_i2c_data *data,
const struct imxi2c_platform_data *pdata);
#include <linux/input/matrix_keypad.h>
struct imx_imx_keypad_data {
resource_size_t iobase;
resource_size_t iosize;
resource_size_t irq;
};
struct platform_device *__init imx_add_imx_keypad(
const struct imx_imx_keypad_data *data,
const struct matrix_keymap_data *pdata);
#include <mach/ssi.h>
struct imx_imx_ssi_data {
int id;
......@@ -82,6 +149,67 @@ struct platform_device *__init imx_add_imx_uart_1irq(
const struct imx_imx_uart_1irq_data *data,
const struct imxuart_platform_data *pdata);
#include <mach/usb.h>
struct imx_imx_udc_data {
resource_size_t iobase;
resource_size_t iosize;
resource_size_t irq0;
resource_size_t irq1;
resource_size_t irq2;
resource_size_t irq3;
resource_size_t irq4;
resource_size_t irq5;
resource_size_t irq6;
};
struct platform_device *__init imx_add_imx_udc(
const struct imx_imx_udc_data *data,
const struct imxusb_platform_data *pdata);
#include <mach/mx1_camera.h>
struct imx_mx1_camera_data {
resource_size_t iobase;
resource_size_t iosize;
resource_size_t irq;
};
struct platform_device *__init imx_add_mx1_camera(
const struct imx_mx1_camera_data *data,
const struct mx1_camera_pdata *pdata);
#include <mach/mx2_cam.h>
struct imx_mx2_camera_data {
resource_size_t iobasecsi;
resource_size_t iosizecsi;
resource_size_t irqcsi;
resource_size_t iobaseemmaprp;
resource_size_t iosizeemmaprp;
resource_size_t irqemmaprp;
};
struct platform_device *__init imx_add_mx2_camera(
const struct imx_mx2_camera_data *data,
const struct mx2_camera_platform_data *pdata);
#include <mach/mxc_ehci.h>
struct imx_mxc_ehci_data {
int id;
resource_size_t iobase;
resource_size_t irq;
};
struct platform_device *__init imx_add_mxc_ehci(
const struct imx_mxc_ehci_data *data,
const struct mxc_usbh_platform_data *pdata);
#include <mach/mmc.h>
struct imx_mxc_mmc_data {
int id;
resource_size_t iobase;
resource_size_t iosize;
resource_size_t irq;
resource_size_t dmareq;
};
struct platform_device *__init imx_add_mxc_mmc(
const struct imx_mxc_mmc_data *data,
const struct imxmmc_platform_data *pdata);
#include <mach/mxc_nand.h>
struct imx_mxc_nand_data {
/*
......@@ -99,24 +227,39 @@ struct platform_device *__init imx_add_mxc_nand(
const struct imx_mxc_nand_data *data,
const struct mxc_nand_platform_data *pdata);
#include <mach/spi.h>
struct imx_spi_imx_data {
const char *devid;
struct imx_mxc_pwm_data {
int id;
resource_size_t iobase;
resource_size_t iosize;
int irq;
resource_size_t irq;
};
struct platform_device *__init imx_add_spi_imx(
const struct imx_spi_imx_data *data,
const struct spi_imx_master *pdata);
struct platform_device *__init imx_add_mxc_pwm(
const struct imx_mxc_pwm_data *data);
struct imx_mxc_w1_data {
resource_size_t iobase;
};
struct platform_device *__init imx_add_mxc_w1(
const struct imx_mxc_w1_data *data);
#include <mach/esdhc.h>
struct imx_esdhc_imx_data {
struct imx_sdhci_esdhc_imx_data {
int id;
resource_size_t iobase;
resource_size_t irq;
};
struct platform_device *__init imx_add_esdhc(
const struct imx_esdhc_imx_data *data,
struct platform_device *__init imx_add_sdhci_esdhc_imx(
const struct imx_sdhci_esdhc_imx_data *data,
const struct esdhc_platform_data *pdata);
#include <mach/spi.h>
struct imx_spi_imx_data {
const char *devid;
int id;
resource_size_t iobase;
resource_size_t iosize;
int irq;
};
struct platform_device *__init imx_add_spi_imx(
const struct imx_spi_imx_data *data,
const struct spi_imx_master *pdata);
arch/arm/plat-mxc/include/mach/hardware.h
View file @ 2a85927c
......@@ -22,10 +22,82 @@
#include <asm/sizes.h>
#define IMX_IO_ADDRESS(addr, module) \
((void __force __iomem *) \
(((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\
(addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0))
#ifdef __ASSEMBLER__
#define IOMEM(addr) (addr)
#else
#define IOMEM(addr) ((void __force __iomem *)(addr))
#endif
#define IMX_IO_P2V_MODULE(addr, module) \
(((addr) - module ## _BASE_ADDR) < module ## _SIZE ? \
(addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
/*
* This is rather complicated for humans and ugly to verify, but for a machine
* it's OK. Still more as it is usually only applied to constants. The upsides
* on using this approach are:
*
* - same mapping on all i.MX machines
* - works for assembler, too
* - no need to nurture #defines for virtual addresses
*
* The downside it, it's hard to verify (but I have a script for that).
*
* Obviously this needs to be injective for each SoC. In general it maps the
* whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff]
* is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there).
*
* It applies the following mappings for the different SoCs:
*
* mx1:
* IO 0x00200000+0x100000 -> 0xf4000000+0x100000
* mx21:
* AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
* SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000
* X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000
* mx25:
* AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
* AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
* AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
* mx27:
* AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
* SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000
* X_MEMC 0xd8000000+0x100000 -> 0xf5c00000+0x100000
* mx31:
* AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
* AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
* AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
* X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000
* SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
* mx35:
* AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
* AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
* AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
* X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000
* SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
* mx51:
* IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000
* DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000
* SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000
* AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000
* AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000
* mxc91231:
* L2CC 0x30000000+0x010000 -> 0xf4400000+0x010000
* X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000
* ROMP 0x60000000+0x010000 -> 0xf5000000+0x010000
* AVIC 0x68000000+0x010000 -> 0xf5800000+0x010000
* AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
* SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
* SPBA1 0x52000000+0x100000 -> 0xf5600000+0x100000
* AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
*/
#define IMX_IO_P2V(x) ( \
0xf4000000 + \
(((x) & 0x50000000) >> 6) + \
(((x) & 0x0b000000) >> 4) + \
(((x) & 0x000fffff)))
#define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x))
#ifdef CONFIG_ARCH_MX5
#include <mach/mx51.h>
......@@ -61,4 +133,11 @@
#include <mach/mxc.h>
#define imx_map_entry(soc, name, _type) { \
.virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
.pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \
.length = soc ## _ ## name ## _SIZE, \
.type = _type, \
}
#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
arch/arm/plat-mxc/include/mach/imxfb.h
View file @ 2a85927c
/*
* This structure describes the machine which we are running on.
*/
#ifndef __MACH_IMXFB_H__
#define __MACH_IMXFB_H__
#include <linux/fb.h>
......@@ -79,3 +81,4 @@ struct imx_fb_platform_data {
};
void set_imx_fb_info(struct imx_fb_platform_data *);
#endif /* ifndef __MACH_IMXFB_H__ */
arch/arm/plat-mxc/include/mach/mx1.h
View file @ 2a85927c
......@@ -19,7 +19,6 @@
*/
#define MX1_IO_BASE_ADDR 0x00200000
#define MX1_IO_SIZE SZ_1M
#define MX1_IO_BASE_ADDR_VIRT VMALLOC_END
#define MX1_CS0_PHYS 0x10000000
#define MX1_CS0_SIZE 0x02000000
......@@ -66,6 +65,10 @@
#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR)
#define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR)
#define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
#define MX1_GPIO1_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
#define MX1_GPIO2_BASE_ADDR (0x1C100 + MX1_IO_BASE_ADDR)
#define MX1_GPIO3_BASE_ADDR (0x1C200 + MX1_IO_BASE_ADDR)
#define MX1_GPIO4_BASE_ADDR (0x1C300 + MX1_IO_BASE_ADDR)
#define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR)
#define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR)
#define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR)
......@@ -73,12 +76,12 @@
#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR)
/* macro to get at IO space when running virtually */
#define MX1_IO_ADDRESS(x) ( \
IMX_IO_ADDRESS(x, MX1_IO))
#define MX1_IO_P2V(x) IMX_IO_P2V(x)
#define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x))
/* fixed interrput numbers */
#define MX1_INT_SOFTINT 0
#define MX1_CSI_INT 6
#define MX1_INT_CSI 6
#define MX1_DSPA_MAC_INT 7
#define MX1_DSPA_INT 8
#define MX1_COMP_INT 9
......@@ -115,13 +118,13 @@
#define MX1_SSI_RX_INT 44
#define MX1_SSI_RX_ERR_INT 45
#define MX1_TOUCH_INT 46
#define MX1_USBD_INT0 47
#define MX1_USBD_INT1 48
#define MX1_USBD_INT2 49
#define MX1_USBD_INT3 50
#define MX1_USBD_INT4 51
#define MX1_USBD_INT5 52
#define MX1_USBD_INT6 53
#define MX1_INT_USBD0 47
#define MX1_INT_USBD1 48
#define MX1_INT_USBD2 49
#define MX1_INT_USBD3 50
#define MX1_INT_USBD4 51
#define MX1_INT_USBD5 52
#define MX1_INT_USBD6 53
#define MX1_BTSYS_INT 55
#define MX1_BTTIM_INT 56
#define MX1_BTWUI_INT 57
......@@ -164,134 +167,6 @@
* to not break drivers/usb/gadget/imx_udc. Should go
* away after this driver uses the new name.
*/
#define USBD_INT0 MX1_USBD_INT0
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
/* these should go away */
#define IMX_IO_PHYS MX1_IO_BASE_ADDR
#define IMX_IO_SIZE MX1_IO_SIZE
#define IMX_IO_BASE MX1_IO_BASE_ADDR_VIRT
#define IMX_CS0_PHYS MX1_CS0_PHYS
#define IMX_CS0_SIZE MX1_CS0_SIZE
#define IMX_CS1_PHYS MX1_CS1_PHYS
#define IMX_CS1_SIZE MX1_CS1_SIZE
#define IMX_CS2_PHYS MX1_CS2_PHYS
#define IMX_CS2_SIZE MX1_CS2_SIZE
#define IMX_CS3_PHYS MX1_CS3_PHYS
#define IMX_CS3_SIZE MX1_CS3_SIZE
#define IMX_CS4_PHYS MX1_CS4_PHYS
#define IMX_CS4_SIZE MX1_CS4_SIZE
#define IMX_CS5_PHYS MX1_CS5_PHYS
#define IMX_CS5_SIZE MX1_CS5_SIZE
#define AIPI1_BASE_ADDR MX1_AIPI1_BASE_ADDR
#define WDT_BASE_ADDR MX1_WDT_BASE_ADDR
#define TIM1_BASE_ADDR MX1_TIM1_BASE_ADDR
#define TIM2_BASE_ADDR MX1_TIM2_BASE_ADDR
#define RTC_BASE_ADDR MX1_RTC_BASE_ADDR
#define LCDC_BASE_ADDR MX1_LCDC_BASE_ADDR
#define UART1_BASE_ADDR MX1_UART1_BASE_ADDR
#define UART2_BASE_ADDR MX1_UART2_BASE_ADDR
#define PWM_BASE_ADDR MX1_PWM_BASE_ADDR
#define DMA_BASE_ADDR MX1_DMA_BASE_ADDR
#define AIPI2_BASE_ADDR MX1_AIPI2_BASE_ADDR
#define SIM_BASE_ADDR MX1_SIM_BASE_ADDR
#define USBD_BASE_ADDR MX1_USBD_BASE_ADDR
#define SPI1_BASE_ADDR MX1_SPI1_BASE_ADDR
#define MMC_BASE_ADDR MX1_MMC_BASE_ADDR
#define ASP_BASE_ADDR MX1_ASP_BASE_ADDR
#define BTA_BASE_ADDR MX1_BTA_BASE_ADDR
#define I2C_BASE_ADDR MX1_I2C_BASE_ADDR
#define SSI_BASE_ADDR MX1_SSI_BASE_ADDR
#define SPI2_BASE_ADDR MX1_SPI2_BASE_ADDR
#define MSHC_BASE_ADDR MX1_MSHC_BASE_ADDR
#define CCM_BASE_ADDR MX1_CCM_BASE_ADDR
#define SCM_BASE_ADDR MX1_SCM_BASE_ADDR
#define GPIO_BASE_ADDR MX1_GPIO_BASE_ADDR
#define EIM_BASE_ADDR MX1_EIM_BASE_ADDR
#define SDRAMC_BASE_ADDR MX1_SDRAMC_BASE_ADDR
#define MMA_BASE_ADDR MX1_MMA_BASE_ADDR
#define AVIC_BASE_ADDR MX1_AVIC_BASE_ADDR
#define CSI_BASE_ADDR MX1_CSI_BASE_ADDR
#define IO_ADDRESS(x) MX1_IO_ADDRESS(x)
#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x)
#define INT_SOFTINT MX1_INT_SOFTINT
#define CSI_INT MX1_CSI_INT
#define DSPA_MAC_INT MX1_DSPA_MAC_INT
#define DSPA_INT MX1_DSPA_INT
#define COMP_INT MX1_COMP_INT
#define MSHC_XINT MX1_MSHC_XINT
#define GPIO_INT_PORTA MX1_GPIO_INT_PORTA
#define GPIO_INT_PORTB MX1_GPIO_INT_PORTB
#define GPIO_INT_PORTC MX1_GPIO_INT_PORTC
#define LCDC_INT MX1_LCDC_INT
#define SIM_INT MX1_SIM_INT
#define SIM_DATA_INT MX1_SIM_DATA_INT
#define RTC_INT MX1_RTC_INT
#define RTC_SAMINT MX1_RTC_SAMINT
#define UART2_MINT_PFERR MX1_UART2_MINT_PFERR
#define UART2_MINT_RTS MX1_UART2_MINT_RTS
#define UART2_MINT_DTR MX1_UART2_MINT_DTR
#define UART2_MINT_UARTC MX1_UART2_MINT_UARTC
#define UART2_MINT_TX MX1_UART2_MINT_TX
#define UART2_MINT_RX MX1_UART2_MINT_RX
#define UART1_MINT_PFERR MX1_UART1_MINT_PFERR
#define UART1_MINT_RTS MX1_UART1_MINT_RTS
#define UART1_MINT_DTR MX1_UART1_MINT_DTR
#define UART1_MINT_UARTC MX1_UART1_MINT_UARTC
#define UART1_MINT_TX MX1_UART1_MINT_TX
#define UART1_MINT_RX MX1_UART1_MINT_RX
#define VOICE_DAC_INT MX1_VOICE_DAC_INT
#define VOICE_ADC_INT MX1_VOICE_ADC_INT
#define PEN_DATA_INT MX1_PEN_DATA_INT
#define PWM_INT MX1_PWM_INT
#define SDHC_INT MX1_SDHC_INT
#define I2C_INT MX1_INT_I2C
#define CSPI_INT MX1_CSPI_INT
#define SSI_TX_INT MX1_SSI_TX_INT
#define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT
#define SSI_RX_INT MX1_SSI_RX_INT
#define SSI_RX_ERR_INT MX1_SSI_RX_ERR_INT
#define TOUCH_INT MX1_TOUCH_INT
#define USBD_INT1 MX1_USBD_INT1
#define USBD_INT2 MX1_USBD_INT2
#define USBD_INT3 MX1_USBD_INT3
#define USBD_INT4 MX1_USBD_INT4
#define USBD_INT5 MX1_USBD_INT5
#define USBD_INT6 MX1_USBD_INT6
#define BTSYS_INT MX1_BTSYS_INT
#define BTTIM_INT MX1_BTTIM_INT
#define BTWUI_INT MX1_BTWUI_INT
#define TIM2_INT MX1_TIM2_INT
#define TIM1_INT MX1_TIM1_INT
#define DMA_ERR MX1_DMA_ERR
#define DMA_INT MX1_DMA_INT
#define GPIO_INT_PORTD MX1_GPIO_INT_PORTD
#define WDT_INT MX1_WDT_INT
#define DMA_REQ_UART3_T MX1_DMA_REQ_UART3_T
#define DMA_REQ_UART3_R MX1_DMA_REQ_UART3_R
#define DMA_REQ_SSI2_T MX1_DMA_REQ_SSI2_T
#define DMA_REQ_SSI2_R MX1_DMA_REQ_SSI2_R
#define DMA_REQ_CSI_STAT MX1_DMA_REQ_CSI_STAT
#define DMA_REQ_CSI_R MX1_DMA_REQ_CSI_R
#define DMA_REQ_MSHC MX1_DMA_REQ_MSHC
#define DMA_REQ_DSPA_DCT_DOUT MX1_DMA_REQ_DSPA_DCT_DOUT
#define DMA_REQ_DSPA_DCT_DIN MX1_DMA_REQ_DSPA_DCT_DIN
#define DMA_REQ_DSPA_MAC MX1_DMA_REQ_DSPA_MAC
#define DMA_REQ_EXT MX1_DMA_REQ_EXT
#define DMA_REQ_SDHC MX1_DMA_REQ_SDHC
#define DMA_REQ_SPI1_R MX1_DMA_REQ_SPI1_R
#define DMA_REQ_SPI1_T MX1_DMA_REQ_SPI1_T
#define DMA_REQ_SSI_T MX1_DMA_REQ_SSI_T
#define DMA_REQ_SSI_R MX1_DMA_REQ_SSI_R
#define DMA_REQ_ASP_DAC MX1_DMA_REQ_ASP_DAC
#define DMA_REQ_ASP_ADC MX1_DMA_REQ_ASP_ADC
#define DMA_REQ_USP_EP(x) MX1_DMA_REQ_USP_EP(x)
#define DMA_REQ_SPI2_R MX1_DMA_REQ_SPI2_R
#define DMA_REQ_SPI2_T MX1_DMA_REQ_SPI2_T
#define DMA_REQ_UART2_T MX1_DMA_REQ_UART2_T
#define DMA_REQ_UART2_R MX1_DMA_REQ_UART2_R
#define DMA_REQ_UART1_T MX1_DMA_REQ_UART1_T
#define DMA_REQ_UART1_R MX1_DMA_REQ_UART1_R
#endif /* ifdef IMX_NEEDS_DEPRECATED_SYMBOLS */
#define USBD_INT0 MX1_INT_USBD0
#endif /* ifndef __MACH_MX1_H__ */
arch/arm/plat-mxc/include/mach/mx21.h
View file @ 2a85927c
......@@ -26,7 +26,6 @@
#define __MACH_MX21_H__
#define MX21_AIPI_BASE_ADDR 0x10000000
#define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000
#define MX21_AIPI_SIZE SZ_1M
#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000)
#define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000)
......@@ -49,6 +48,12 @@
#define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000)
#define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000)
#define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000)
#define MX21_GPIO1_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x000)
#define MX21_GPIO2_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x100)
#define MX21_GPIO3_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x200)
#define MX21_GPIO4_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x300)
#define MX21_GPIO5_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x400)
#define MX21_GPIO6_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x500)
#define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000)
#define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000)
#define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000)
......@@ -64,7 +69,6 @@
#define MX21_AVIC_BASE_ADDR 0x10040000
#define MX21_SAHB1_BASE_ADDR 0x80000000
#define MX21_SAHB1_BASE_ADDR_VIRT 0xf4100000
#define MX21_SAHB1_SIZE SZ_1M
#define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
......@@ -82,7 +86,6 @@
/* NAND, SDRAM, WEIM etc controllers */
#define MX21_X_MEMC_BASE_ADDR 0xdf000000
#define MX21_X_MEMC_BASE_ADDR_VIRT 0xf4200000
#define MX21_X_MEMC_SIZE SZ_256K
#define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000)
......@@ -92,10 +95,8 @@
#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */
#define MX21_IO_ADDRESS(x) ( \
IMX_IO_ADDRESS(x, MX21_AIPI) ?: \
IMX_IO_ADDRESS(x, MX21_SAHB1) ?: \
IMX_IO_ADDRESS(x, MX21_X_MEMC))
#define MX21_IO_P2V(x) IMX_IO_P2V(x)
#define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x))
/* fixed interrupt numbers */
#define MX21_INT_CSPI3 6
......@@ -184,39 +185,4 @@
#define MX21_DMA_REQ_CSI_STAT 30
#define MX21_DMA_REQ_CSI_RX 31
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
/* these should go away */
#define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR
#define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR
#define CS0_BASE_ADDR MX21_CS0_BASE_ADDR
#define CS1_BASE_ADDR MX21_CS1_BASE_ADDR
#define CS2_BASE_ADDR MX21_CS2_BASE_ADDR
#define CS3_BASE_ADDR MX21_CS3_BASE_ADDR
#define CS4_BASE_ADDR MX21_CS4_BASE_ADDR
#define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR
#define CS5_BASE_ADDR MX21_CS5_BASE_ADDR
#define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR
#define X_MEMC_BASE_ADDR_VIRT MX21_X_MEMC_BASE_ADDR_VIRT
#define X_MEMC_SIZE MX21_X_MEMC_SIZE
#define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR
#define EIM_BASE_ADDR MX21_EIM_BASE_ADDR
#define PCMCIA_CTL_BASE_ADDR MX21_PCMCIA_CTL_BASE_ADDR
#define NFC_BASE_ADDR MX21_NFC_BASE_ADDR
#define IRAM_BASE_ADDR MX21_IRAM_BASE_ADDR
#define MXC_INT_FIRI MX21_INT_FIRI
#define MXC_INT_BMI MX21_INT_BMI
#define MXC_INT_EMMAENC MX21_INT_EMMAENC
#define MXC_INT_EMMADEC MX21_INT_EMMADEC
#define MXC_INT_USBWKUP MX21_INT_USBWKUP
#define MXC_INT_USBDMA MX21_INT_USBDMA
#define MXC_INT_USBHOST MX21_INT_USBHOST
#define MXC_INT_USBFUNC MX21_INT_USBFUNC
#define MXC_INT_USBMNP MX21_INT_USBMNP
#define MXC_INT_USBCTRL MX21_INT_USBCTRL
#define MXC_INT_USBCTRL MX21_INT_USBCTRL
#define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX
#define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX
#define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX
#endif
#endif /* ifndef __MACH_MX21_H__ */
arch/arm/plat-mxc/include/mach/mx25.h
View file @ 2a85927c
......@@ -2,13 +2,10 @@
#define __MACH_MX25_H__
#define MX25_AIPS1_BASE_ADDR 0x43f00000
#define MX25_AIPS1_BASE_ADDR_VIRT 0xfc000000
#define MX25_AIPS1_SIZE SZ_1M
#define MX25_AIPS2_BASE_ADDR 0x53f00000
#define MX25_AIPS2_BASE_ADDR_VIRT 0xfc200000
#define MX25_AIPS2_SIZE SZ_1M
#define MX25_AVIC_BASE_ADDR 0x68000000
#define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000
#define MX25_AVIC_SIZE SZ_1M
#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000)
......@@ -21,20 +18,15 @@
#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000)
#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000)
#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000)
#define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000)
#define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000)
#define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000)
#define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000)
#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000)
#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000)
#define MX25_GPIO1_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xcc000)
#define MX25_GPIO2_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xd0000)
#define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000)
#define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000)
#define MX25_IO_ADDRESS(x) ( \
IMX_IO_ADDRESS(x, MX25_AIPS1) ?: \
IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \
IMX_IO_ADDRESS(x, MX25_AVIC))
#define MX25_AIPS1_IO_ADDRESS(x) \
(((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT)
#define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000)
#define MX25_UART1_BASE_ADDR 0x43f90000
#define MX25_UART2_BASE_ADDR 0x43f94000
......@@ -55,9 +47,14 @@
#define MX25_LCDC_BASE_ADDR 0x53fbc000
#define MX25_KPP_BASE_ADDR 0x43fa8000
#define MX25_SDMA_BASE_ADDR 0x53fd4000
#define MX25_OTG_BASE_ADDR 0x53ff4000
#define MX25_USB_BASE_ADDR 0x53ff4000
#define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000)
#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0200)
#define MX25_CSI_BASE_ADDR 0x53ff8000
#define MX25_IO_P2V(x) IMX_IO_P2V(x)
#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x))
#define MX25_INT_CSPI3 0
#define MX25_INT_I2C1 3
#define MX25_INT_I2C2 4
......@@ -69,18 +66,28 @@
#define MX25_INT_SSI1 12
#define MX25_INT_CSPI2 13
#define MX25_INT_CSPI1 14
#define MX25_INT_GPIO3 16
#define MX25_INT_CSI 17
#define MX25_INT_UART3 18
#define MX25_INT_GPIO4 23
#define MX25_INT_KPP 24
#define MX25_INT_DRYICE 25
#define MX25_INT_PWM1 26
#define MX25_INT_UART2 32
#define MX25_INT_NFC 33
#define MX25_INT_SDMA 34
#define MX25_INT_USB_HS 35
#define MX25_INT_PWM2 36
#define MX25_INT_USB_OTG 37
#define MX25_INT_LCDC 39
#define MX25_INT_UART5 40
#define MX25_INT_PWM3 41
#define MX25_INT_PWM4 42
#define MX25_INT_CAN1 43
#define MX25_INT_CAN2 44
#define MX25_INT_UART1 45
#define MX25_INT_GPIO2 51
#define MX25_INT_GPIO1 52
#define MX25_INT_FEC 57
#define MX25_DMA_REQ_SSI2_RX1 22
......
arch/arm/plat-mxc/include/mach/mx27.h
View file @ 2a85927c
......@@ -29,7 +29,6 @@
#endif
#define MX27_AIPI_BASE_ADDR 0x10000000
#define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000
#define MX27_AIPI_SIZE SZ_1M
#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000)
#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000)
......@@ -52,6 +51,12 @@
#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000)
#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000)
#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000)
#define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000)
#define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100)
#define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200)
#define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300)
#define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400)
#define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500)
#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000)
#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000)
#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000)
......@@ -65,11 +70,13 @@
#define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000)
#define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000)
#define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000)
#define MX27_USBOTG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000)
#define MX27_OTG_BASE_ADDR MX27_USBOTG_BASE_ADDR
#define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000)
#define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000)
#define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200)
#define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400)
#define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000)
#define MX27_EMMA_PP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000)
#define MX27_EMMA_PRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400)
#define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000)
#define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400)
#define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000)
#define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800)
#define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000)
......@@ -87,7 +94,6 @@
#define MX27_ROMP_BASE_ADDR 0x10041000
#define MX27_SAHB1_BASE_ADDR 0x80000000
#define MX27_SAHB1_BASE_ADDR_VIRT 0xf4100000
#define MX27_SAHB1_SIZE SZ_1M
#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000)
#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000)
......@@ -105,7 +111,6 @@
/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
#define MX27_X_MEMC_BASE_ADDR 0xd8000000
#define MX27_X_MEMC_BASE_ADDR_VIRT 0xf4200000
#define MX27_X_MEMC_SIZE SZ_1M
#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR)
#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000)
......@@ -123,10 +128,8 @@
/* IRAM */
#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
#define MX27_IO_ADDRESS(x) ( \
IMX_IO_ADDRESS(x, MX27_AIPI) ?: \
IMX_IO_ADDRESS(x, MX27_SAHB1) ?: \
IMX_IO_ADDRESS(x, MX27_X_MEMC))
#define MX27_IO_P2V(x) IMX_IO_P2V(x)
#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x))
#ifndef __ASSEMBLER__
static inline void mx27_setup_weimcs(size_t cs,
......@@ -192,9 +195,9 @@ static inline void mx27_setup_weimcs(size_t cs,
#define MX27_INT_EMMAPRP 51
#define MX27_INT_EMMAPP 52
#define MX27_INT_VPU 53
#define MX27_INT_USB1 54
#define MX27_INT_USB2 55
#define MX27_INT_USB3 56
#define MX27_INT_USB_HS1 54
#define MX27_INT_USB_HS2 55
#define MX27_INT_USB_OTG 56
#define MX27_INT_SCC_SMN 57
#define MX27_INT_SCC_SCM 58
#define MX27_INT_SAHARA 59
......@@ -249,74 +252,4 @@ static inline void mx27_setup_weimcs(size_t cs,
extern int mx27_revision(void);
#endif
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
/* these should go away */
#define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR
#define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR
#define GPT4_BASE_ADDR MX27_GPT4_BASE_ADDR
#define UART5_BASE_ADDR MX27_UART5_BASE_ADDR
#define UART6_BASE_ADDR MX27_UART6_BASE_ADDR
#define I2C2_BASE_ADDR MX27_I2C2_BASE_ADDR
#define SDHC3_BASE_ADDR MX27_SDHC3_BASE_ADDR
#define GPT6_BASE_ADDR MX27_GPT6_BASE_ADDR
#define VPU_BASE_ADDR MX27_VPU_BASE_ADDR
#define OTG_BASE_ADDR MX27_OTG_BASE_ADDR
#define SAHARA_BASE_ADDR MX27_SAHARA_BASE_ADDR
#define IIM_BASE_ADDR MX27_IIM_BASE_ADDR
#define RTIC_BASE_ADDR MX27_RTIC_BASE_ADDR
#define FEC_BASE_ADDR MX27_FEC_BASE_ADDR
#define SCC_BASE_ADDR MX27_SCC_BASE_ADDR
#define ETB_BASE_ADDR MX27_ETB_BASE_ADDR
#define ETB_RAM_BASE_ADDR MX27_ETB_RAM_BASE_ADDR
#define ROMP_BASE_ADDR MX27_ROMP_BASE_ADDR
#define ATA_BASE_ADDR MX27_ATA_BASE_ADDR
#define SDRAM_BASE_ADDR MX27_SDRAM_BASE_ADDR
#define CSD1_BASE_ADDR MX27_CSD1_BASE_ADDR
#define CS0_BASE_ADDR MX27_CS0_BASE_ADDR
#define CS1_BASE_ADDR MX27_CS1_BASE_ADDR
#define CS2_BASE_ADDR MX27_CS2_BASE_ADDR
#define CS3_BASE_ADDR MX27_CS3_BASE_ADDR
#define CS4_BASE_ADDR MX27_CS4_BASE_ADDR
#define CS5_BASE_ADDR MX27_CS5_BASE_ADDR
#define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR
#define X_MEMC_BASE_ADDR_VIRT MX27_X_MEMC_BASE_ADDR_VIRT
#define X_MEMC_SIZE MX27_X_MEMC_SIZE
#define NFC_BASE_ADDR MX27_NFC_BASE_ADDR
#define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR
#define WEIM_BASE_ADDR MX27_WEIM_BASE_ADDR
#define M3IF_BASE_ADDR MX27_M3IF_BASE_ADDR
#define PCMCIA_CTL_BASE_ADDR MX27_PCMCIA_CTL_BASE_ADDR
#define PCMCIA_MEM_BASE_ADDR MX27_PCMCIA_MEM_BASE_ADDR
#define IRAM_BASE_ADDR MX27_IRAM_BASE_ADDR
#define MXC_INT_I2C2 MX27_INT_I2C2
#define MXC_INT_GPT6 MX27_INT_GPT6
#define MXC_INT_GPT5 MX27_INT_GPT5
#define MXC_INT_GPT4 MX27_INT_GPT4
#define MXC_INT_RTIC MX27_INT_RTIC
#define MXC_INT_SDHC MX27_INT_SDHC
#define MXC_INT_SDHC3 MX27_INT_SDHC3
#define MXC_INT_ATA MX27_INT_ATA
#define MXC_INT_UART6 MX27_INT_UART6
#define MXC_INT_UART5 MX27_INT_UART5
#define MXC_INT_FEC MX27_INT_FEC
#define MXC_INT_VPU MX27_INT_VPU
#define MXC_INT_USB1 MX27_INT_USB1
#define MXC_INT_USB2 MX27_INT_USB2
#define MXC_INT_USB3 MX27_INT_USB3
#define MXC_INT_SCC_SMN MX27_INT_SCC_SMN
#define MXC_INT_SCC_SCM MX27_INT_SCC_SCM
#define MXC_INT_SAHARA MX27_INT_SAHARA
#define MXC_INT_IIM MX27_INT_IIM
#define MXC_INT_CCM MX27_INT_CCM
#define DMA_REQ_MSHC MX27_DMA_REQ_MSHC
#define DMA_REQ_ATA_TX MX27_DMA_REQ_ATA_TX
#define DMA_REQ_ATA_RCV MX27_DMA_REQ_ATA_RCV
#define DMA_REQ_UART5_TX MX27_DMA_REQ_UART5_TX
#define DMA_REQ_UART5_RX MX27_DMA_REQ_UART5_RX
#define DMA_REQ_UART6_TX MX27_DMA_REQ_UART6_TX
#define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX
#define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3
#define DMA_REQ_NFC MX27_DMA_REQ_NFC
#endif
#endif /* ifndef __MACH_MX27_H__ */
arch/arm/plat-mxc/include/mach/mx2x.h
View file @ 2a85927c
......@@ -27,7 +27,6 @@
/* Register offsets */
#define MX2x_AIPI_BASE_ADDR 0x10000000
#define MX2x_AIPI_BASE_ADDR_VIRT 0xf4000000
#define MX2x_AIPI_SIZE SZ_1M
#define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
#define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
......@@ -65,43 +64,9 @@
#define MX2x_AVIC_BASE_ADDR 0x10040000
#define MX2x_SAHB1_BASE_ADDR 0x80000000
#define MX2x_SAHB1_BASE_ADDR_VIRT 0xf4100000
#define MX2x_SAHB1_SIZE SZ_1M
#define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
/*
* This macro defines the physical to virtual address mapping for all the
* peripheral modules. It is used by passing in the physical address as x
* and returning the virtual address. If the physical address is not mapped,
* it returns 0xDEADBEEF
*/
#define IO_ADDRESS(x) \
(void __force __iomem *) \
(((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
AIPI_IO_ADDRESS(x) : \
((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
SAHB1_IO_ADDRESS(x) : \
((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \
X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF)
/* define the address mapping macros: in physical address order */
#define AIPI_IO_ADDRESS(x) \
(((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT)
#define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x)
#define SAHB1_IO_ADDRESS(x) \
(((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT)
#define CS4_IO_ADDRESS(x) \
(((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
#define X_MEMC_IO_ADDRESS(x) \
(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
#define PCMCIA_IO_ADDRESS(x) \
(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
/* fixed interrupt numbers */
#define MX2x_INT_CSPI3 6
#define MX2x_INT_GPIO 8
......@@ -176,118 +141,4 @@
#define MX2x_DMA_REQ_CSI_STAT 30
#define MX2x_DMA_REQ_CSI_RX 31
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
/* these should go away */
#define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR
#define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT
#define AIPI_SIZE MX2x_AIPI_SIZE
#define DMA_BASE_ADDR MX2x_DMA_BASE_ADDR
#define WDOG_BASE_ADDR MX2x_WDOG_BASE_ADDR
#define GPT1_BASE_ADDR MX2x_GPT1_BASE_ADDR
#define GPT2_BASE_ADDR MX2x_GPT2_BASE_ADDR
#define GPT3_BASE_ADDR MX2x_GPT3_BASE_ADDR
#define PWM_BASE_ADDR MX2x_PWM_BASE_ADDR
#define RTC_BASE_ADDR MX2x_RTC_BASE_ADDR
#define KPP_BASE_ADDR MX2x_KPP_BASE_ADDR
#define OWIRE_BASE_ADDR MX2x_OWIRE_BASE_ADDR
#define UART1_BASE_ADDR MX2x_UART1_BASE_ADDR
#define UART2_BASE_ADDR MX2x_UART2_BASE_ADDR
#define UART3_BASE_ADDR MX2x_UART3_BASE_ADDR
#define UART4_BASE_ADDR MX2x_UART4_BASE_ADDR
#define CSPI1_BASE_ADDR MX2x_CSPI1_BASE_ADDR
#define CSPI2_BASE_ADDR MX2x_CSPI2_BASE_ADDR
#define SSI1_BASE_ADDR MX2x_SSI1_BASE_ADDR
#define SSI2_BASE_ADDR MX2x_SSI2_BASE_ADDR
#define I2C_BASE_ADDR MX2x_I2C_BASE_ADDR
#define SDHC1_BASE_ADDR MX2x_SDHC1_BASE_ADDR
#define SDHC2_BASE_ADDR MX2x_SDHC2_BASE_ADDR
#define GPIO_BASE_ADDR MX2x_GPIO_BASE_ADDR
#define AUDMUX_BASE_ADDR MX2x_AUDMUX_BASE_ADDR
#define CSPI3_BASE_ADDR MX2x_CSPI3_BASE_ADDR
#define LCDC_BASE_ADDR MX2x_LCDC_BASE_ADDR
#define SLCDC_BASE_ADDR MX2x_SLCDC_BASE_ADDR
#define USBOTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR
#define EMMA_PP_BASE_ADDR MX2x_EMMA_PP_BASE_ADDR
#define EMMA_PRP_BASE_ADDR MX2x_EMMA_PRP_BASE_ADDR
#define CCM_BASE_ADDR MX2x_CCM_BASE_ADDR
#define SYSCTRL_BASE_ADDR MX2x_SYSCTRL_BASE_ADDR
#define JAM_BASE_ADDR MX2x_JAM_BASE_ADDR
#define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR
#define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR
#define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR
#define SAHB1_BASE_ADDR_VIRT MX2x_SAHB1_BASE_ADDR_VIRT
#define SAHB1_SIZE MX2x_SAHB1_SIZE
#define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR
#define MXC_INT_CSPI3 MX2x_INT_CSPI3
#define MXC_INT_GPIO MX2x_INT_GPIO
#define MXC_INT_SDHC2 MX2x_INT_SDHC2
#define MXC_INT_SDHC1 MX2x_INT_SDHC1
#define MXC_INT_I2C MX2x_INT_I2C
#define MXC_INT_SSI2 MX2x_INT_SSI2
#define MXC_INT_SSI1 MX2x_INT_SSI1
#define MXC_INT_CSPI2 MX2x_INT_CSPI2
#define MXC_INT_CSPI1 MX2x_INT_CSPI1
#define MXC_INT_UART4 MX2x_INT_UART4
#define MXC_INT_UART3 MX2x_INT_UART3
#define MXC_INT_UART2 MX2x_INT_UART2
#define MXC_INT_UART1 MX2x_INT_UART1
#define MXC_INT_KPP MX2x_INT_KPP
#define MXC_INT_RTC MX2x_INT_RTC
#define MXC_INT_PWM MX2x_INT_PWM
#define MXC_INT_GPT3 MX2x_INT_GPT3
#define MXC_INT_GPT2 MX2x_INT_GPT2
#define MXC_INT_GPT1 MX2x_INT_GPT1
#define MXC_INT_WDOG MX2x_INT_WDOG
#define MXC_INT_PCMCIA MX2x_INT_PCMCIA
#define MXC_INT_NANDFC MX2x_INT_NANDFC
#define MXC_INT_CSI MX2x_INT_CSI
#define MXC_INT_DMACH0 MX2x_INT_DMACH0
#define MXC_INT_DMACH1 MX2x_INT_DMACH1
#define MXC_INT_DMACH2 MX2x_INT_DMACH2
#define MXC_INT_DMACH3 MX2x_INT_DMACH3
#define MXC_INT_DMACH4 MX2x_INT_DMACH4
#define MXC_INT_DMACH5 MX2x_INT_DMACH5
#define MXC_INT_DMACH6 MX2x_INT_DMACH6
#define MXC_INT_DMACH7 MX2x_INT_DMACH7
#define MXC_INT_DMACH8 MX2x_INT_DMACH8
#define MXC_INT_DMACH9 MX2x_INT_DMACH9
#define MXC_INT_DMACH10 MX2x_INT_DMACH10
#define MXC_INT_DMACH11 MX2x_INT_DMACH11
#define MXC_INT_DMACH12 MX2x_INT_DMACH12
#define MXC_INT_DMACH13 MX2x_INT_DMACH13
#define MXC_INT_DMACH14 MX2x_INT_DMACH14
#define MXC_INT_DMACH15 MX2x_INT_DMACH15
#define MXC_INT_EMMAPRP MX2x_INT_EMMAPRP
#define MXC_INT_EMMAPP MX2x_INT_EMMAPP
#define MXC_INT_SLCDC MX2x_INT_SLCDC
#define MXC_INT_LCDC MX2x_INT_LCDC
#define DMA_REQ_CSPI3_RX MX2x_DMA_REQ_CSPI3_RX
#define DMA_REQ_CSPI3_TX MX2x_DMA_REQ_CSPI3_TX
#define DMA_REQ_EXT MX2x_DMA_REQ_EXT
#define DMA_REQ_SDHC2 MX2x_DMA_REQ_SDHC2
#define DMA_REQ_SDHC1 MX2x_DMA_REQ_SDHC1
#define DMA_REQ_SSI2_RX0 MX2x_DMA_REQ_SSI2_RX0
#define DMA_REQ_SSI2_TX0 MX2x_DMA_REQ_SSI2_TX0
#define DMA_REQ_SSI2_RX1 MX2x_DMA_REQ_SSI2_RX1
#define DMA_REQ_SSI2_TX1 MX2x_DMA_REQ_SSI2_TX1
#define DMA_REQ_SSI1_RX0 MX2x_DMA_REQ_SSI1_RX0
#define DMA_REQ_SSI1_TX0 MX2x_DMA_REQ_SSI1_TX0
#define DMA_REQ_SSI1_RX1 MX2x_DMA_REQ_SSI1_RX1
#define DMA_REQ_SSI1_TX1 MX2x_DMA_REQ_SSI1_TX1
#define DMA_REQ_CSPI2_RX MX2x_DMA_REQ_CSPI2_RX
#define DMA_REQ_CSPI2_TX MX2x_DMA_REQ_CSPI2_TX
#define DMA_REQ_CSPI1_RX MX2x_DMA_REQ_CSPI1_RX
#define DMA_REQ_CSPI1_TX MX2x_DMA_REQ_CSPI1_TX
#define DMA_REQ_UART4_RX MX2x_DMA_REQ_UART4_RX
#define DMA_REQ_UART4_TX MX2x_DMA_REQ_UART4_TX
#define DMA_REQ_UART3_RX MX2x_DMA_REQ_UART3_RX
#define DMA_REQ_UART3_TX MX2x_DMA_REQ_UART3_TX
#define DMA_REQ_UART2_RX MX2x_DMA_REQ_UART2_RX
#define DMA_REQ_UART2_TX MX2x_DMA_REQ_UART2_TX
#define DMA_REQ_UART1_RX MX2x_DMA_REQ_UART1_RX
#define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX
#define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT
#define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX
#endif
#endif /* ifndef __MACH_MX2x_H__ */
arch/arm/plat-mxc/include/mach/mx31.h
View file @ 2a85927c
......@@ -15,7 +15,6 @@
#define MX31_L2CC_SIZE SZ_1M
#define MX31_AIPS1_BASE_ADDR 0x43f00000
#define MX31_AIPS1_BASE_ADDR_VIRT 0xfc000000
#define MX31_AIPS1_SIZE SZ_1M
#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000)
#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000)
......@@ -25,7 +24,10 @@
#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000)
#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000)
#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000)
#define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
#define MX31_USB_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
#define MX31_USB_OTG_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0000)
#define MX31_USB_HS1_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0200)
#define MX31_USB_HS2_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0400)
#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000)
#define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000)
#define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000)
......@@ -41,10 +43,9 @@
#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000)
#define MX31_SPBA0_BASE_ADDR 0x50000000
#define MX31_SPBA0_BASE_ADDR_VIRT 0xfc100000
#define MX31_SPBA0_SIZE SZ_1M
#define MX31_MMC_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000)
#define MX31_MMC_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000)
#define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000)
#define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000)
#define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000)
#define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000)
#define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000)
......@@ -55,7 +56,6 @@
#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000)
#define MX31_AIPS2_BASE_ADDR 0x53f00000
#define MX31_AIPS2_BASE_ADDR_VIRT 0xfc200000
#define MX31_AIPS2_SIZE SZ_1M
#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000)
#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000)
......@@ -84,7 +84,6 @@
#define MX31_ROMP_SIZE SZ_1M
#define MX31_AVIC_BASE_ADDR 0x68000000
#define MX31_AVIC_BASE_ADDR_VIRT 0xfc400000
#define MX31_AVIC_SIZE SZ_1M
#define MX31_IPU_MEM_BASE_ADDR 0x70000000
......@@ -97,15 +96,14 @@
#define MX31_CS3_BASE_ADDR 0xb2000000
#define MX31_CS4_BASE_ADDR 0xb4000000
#define MX31_CS4_BASE_ADDR_VIRT 0xf4000000
#define MX31_CS4_BASE_ADDR_VIRT 0xf6000000
#define MX31_CS4_SIZE SZ_32M
#define MX31_CS5_BASE_ADDR 0xb6000000
#define MX31_CS5_BASE_ADDR_VIRT 0xf6000000
#define MX31_CS5_BASE_ADDR_VIRT 0xf8000000
#define MX31_CS5_SIZE SZ_32M
#define MX31_X_MEMC_BASE_ADDR 0xb8000000
#define MX31_X_MEMC_BASE_ADDR_VIRT 0xfc320000
#define MX31_X_MEMC_SIZE SZ_64K
#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000)
#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000)
......@@ -121,12 +119,8 @@
#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
#define MX31_IO_ADDRESS(x) ( \
IMX_IO_ADDRESS(x, MX31_AIPS1) ?: \
IMX_IO_ADDRESS(x, MX31_AIPS2) ?: \
IMX_IO_ADDRESS(x, MX31_AVIC) ?: \
IMX_IO_ADDRESS(x, MX31_X_MEMC) ?: \
IMX_IO_ADDRESS(x, MX31_SPBA0))
#define MX31_IO_P2V(x) IMX_IO_P2V(x)
#define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x))
#ifndef __ASSEMBLER__
static inline void mx31_setup_weimcs(size_t cs,
......@@ -143,8 +137,8 @@ static inline void mx31_setup_weimcs(size_t cs,
#define MX31_INT_MPEG4_ENCODER 5
#define MX31_INT_RTIC 6
#define MX31_INT_FIRI 7
#define MX31_INT_MMC_SDHC2 8
#define MX31_INT_MMC_SDHC1 9
#define MX31_INT_SDHC2 8
#define MX31_INT_SDHC1 9
#define MX31_INT_I2C1 10
#define MX31_INT_SSI2 11
#define MX31_INT_SSI1 12
......@@ -170,10 +164,9 @@ static inline void mx31_setup_weimcs(size_t cs,
#define MX31_INT_UART2 32
#define MX31_INT_NFC 33
#define MX31_INT_SDMA 34
#define MX31_INT_USB1 35
#define MX31_INT_USB2 36
#define MX31_INT_USB3 37
#define MX31_INT_USB4 38
#define MX31_INT_USB_HS1 35
#define MX31_INT_USB_HS2 36
#define MX31_INT_USB_OTG 37
#define MX31_INT_MSHC1 39
#define MX31_INT_MSHC2 40
#define MX31_INT_IPU_ERR 41
......@@ -197,6 +190,8 @@ static inline void mx31_setup_weimcs(size_t cs,
#define MX31_INT_EXT_WDOG 62
#define MX31_INT_EXT_TV 63
#define MX31_DMA_REQ_SDHC1 20
#define MX31_DMA_REQ_SDHC2 21
#define MX31_DMA_REQ_SSI2_RX1 22
#define MX31_DMA_REQ_SSI2_TX1 23
#define MX31_DMA_REQ_SSI2_RX0 24
......@@ -224,36 +219,4 @@ static inline void mx31_setup_weimcs(size_t cs,
#define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0
#define MX31_SYSTEM_REV_NUM 3
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
/* these should go away */
#define ATA_BASE_ADDR MX31_ATA_BASE_ADDR
#define UART4_BASE_ADDR MX31_UART4_BASE_ADDR
#define UART5_BASE_ADDR MX31_UART5_BASE_ADDR
#define MMC_SDHC1_BASE_ADDR MX31_MMC_SDHC1_BASE_ADDR
#define MMC_SDHC2_BASE_ADDR MX31_MMC_SDHC2_BASE_ADDR
#define SIM1_BASE_ADDR MX31_SIM1_BASE_ADDR
#define IIM_BASE_ADDR MX31_IIM_BASE_ADDR
#define CSPI3_BASE_ADDR MX31_CSPI3_BASE_ADDR
#define FIRI_BASE_ADDR MX31_FIRI_BASE_ADDR
#define SCM_BASE_ADDR MX31_SCM_BASE_ADDR
#define SMN_BASE_ADDR MX31_SMN_BASE_ADDR
#define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR
#define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER
#define MXC_INT_FIRI MX31_INT_FIRI
#define MXC_INT_MBX MX31_INT_MBX
#define MXC_INT_CSPI3 MX31_INT_CSPI3
#define MXC_INT_SIM2 MX31_INT_SIM2
#define MXC_INT_SIM1 MX31_INT_SIM1
#define MXC_INT_CCM_DVFS MX31_INT_CCM_DVFS
#define MXC_INT_USB1 MX31_INT_USB1
#define MXC_INT_USB2 MX31_INT_USB2
#define MXC_INT_USB3 MX31_INT_USB3
#define MXC_INT_USB4 MX31_INT_USB4
#define MXC_INT_MSHC2 MX31_INT_MSHC2
#define MXC_INT_UART4 MX31_INT_UART4
#define MXC_INT_UART5 MX31_INT_UART5
#define MXC_INT_CCM MX31_INT_CCM
#define MXC_INT_PCMCIA MX31_INT_PCMCIA
#endif
#endif /* ifndef __MACH_MX31_H__ */
arch/arm/plat-mxc/include/mach/mx35.h
View file @ 2a85927c
......@@ -11,7 +11,6 @@
#define MX35_L2CC_SIZE SZ_1M
#define MX35_AIPS1_BASE_ADDR 0x43f00000
#define MX35_AIPS1_BASE_ADDR_VIRT 0xfc000000
#define MX35_AIPS1_SIZE SZ_1M
#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000)
#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000)
......@@ -33,7 +32,6 @@
#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000)
#define MX35_SPBA0_BASE_ADDR 0x50000000
#define MX35_SPBA0_BASE_ADDR_VIRT 0xfc100000
#define MX35_SPBA0_SIZE SZ_1M
#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000)
#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000)
......@@ -44,7 +42,6 @@
#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000)
#define MX35_AIPS2_BASE_ADDR 0x53f00000
#define MX35_AIPS2_BASE_ADDR_VIRT 0xfc200000
#define MX35_AIPS2_SIZE SZ_1M
#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000)
#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000)
......@@ -68,15 +65,19 @@
#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000)
#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000)
#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000)
#define MX35_OTG_BASE_ADDR 0x53ff4000
#define MX35_USB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf4000)
#define MX35_USB_OTG_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0000)
/*
* The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for
* HS. When host support was implemented only a preliminary document was
* available, which told 0x400. This works fine.
*/
#define MX35_USB_HS_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0400)
#define MX35_ROMP_BASE_ADDR 0x60000000
#define MX35_ROMP_BASE_ADDR_VIRT 0xfc500000
#define MX35_ROMP_SIZE SZ_1M
#define MX35_AVIC_BASE_ADDR 0x68000000
#define MX35_AVIC_BASE_ADDR_VIRT 0xfc400000
#define MX35_AVIC_SIZE SZ_1M
/*
......@@ -92,18 +93,17 @@
#define MX35_CS3_BASE_ADDR 0xb2000000
#define MX35_CS4_BASE_ADDR 0xb4000000
#define MX35_CS4_BASE_ADDR_VIRT 0xf4000000
#define MX35_CS4_BASE_ADDR_VIRT 0xf6000000
#define MX35_CS4_SIZE SZ_32M
#define MX35_CS5_BASE_ADDR 0xb6000000
#define MX35_CS5_BASE_ADDR_VIRT 0xf6000000
#define MX35_CS5_BASE_ADDR_VIRT 0xf8000000
#define MX35_CS5_SIZE SZ_32M
/*
* NAND, SDRAM, WEIM, M3IF, EMI controllers
*/
#define MX35_X_MEMC_BASE_ADDR 0xb8000000
#define MX35_X_MEMC_BASE_ADDR_VIRT 0xfc320000
#define MX35_X_MEMC_SIZE SZ_64K
#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000)
#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000)
......@@ -114,12 +114,8 @@
#define MX35_NFC_BASE_ADDR 0xbb000000
#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000
#define MX35_IO_ADDRESS(x) ( \
IMX_IO_ADDRESS(x, MX35_AIPS1) ?: \
IMX_IO_ADDRESS(x, MX35_AIPS2) ?: \
IMX_IO_ADDRESS(x, MX35_AVIC) ?: \
IMX_IO_ADDRESS(x, MX35_X_MEMC) ?: \
IMX_IO_ADDRESS(x, MX35_SPBA0))
#define MX35_IO_P2V(x) IMX_IO_P2V(x)
#define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x))
/*
* Interrupt numbers
......@@ -153,8 +149,8 @@
#define MX35_INT_UART2 32
#define MX35_INT_NFC 33
#define MX35_INT_SDMA 34
#define MX35_INT_USBHS 35
#define MX35_INT_USBOTG 37
#define MX35_INT_USB_HS 35
#define MX35_INT_USB_OTG 37
#define MX35_INT_MSHC1 39
#define MX35_INT_ESAI 40
#define MX35_INT_IPU_ERR 41
......@@ -193,20 +189,4 @@
#define MX35_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0
#define MX35_SYSTEM_REV_NUM 3
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
/* these should go away */
#define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR
#define MXC_INT_OWIRE MX35_INT_OWIRE
#define MXC_INT_GPU2D MX35_INT_GPU2D
#define MXC_INT_ASRC MX35_INT_ASRC
#define MXC_INT_USBHS MX35_INT_USBHS
#define MXC_INT_USBOTG MX35_INT_USBOTG
#define MXC_INT_ESAI MX35_INT_ESAI
#define MXC_INT_CAN1 MX35_INT_CAN1
#define MXC_INT_CAN2 MX35_INT_CAN2
#define MXC_INT_MLB MX35_INT_MLB
#define MXC_INT_SPDIF MX35_INT_SPDIF
#define MXC_INT_FEC MX35_INT_FEC
#endif
#endif /* ifndef __MACH_MX35_H__ */
arch/arm/plat-mxc/include/mach/mx3x.h
View file @ 2a85927c
......@@ -44,7 +44,6 @@
* AIPS 1
*/
#define MX3x_AIPS1_BASE_ADDR 0x43f00000
#define MX3x_AIPS1_BASE_ADDR_VIRT 0xfc000000
#define MX3x_AIPS1_SIZE SZ_1M
#define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
#define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
......@@ -69,7 +68,6 @@
* SPBA global module enabled #0
*/
#define MX3x_SPBA0_BASE_ADDR 0x50000000
#define MX3x_SPBA0_BASE_ADDR_VIRT 0xfc100000
#define MX3x_SPBA0_SIZE SZ_1M
#define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000)
#define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000)
......@@ -82,7 +80,6 @@
* AIPS 2
*/
#define MX3x_AIPS2_BASE_ADDR 0x53f00000
#define MX3x_AIPS2_BASE_ADDR_VIRT 0xfc200000
#define MX3x_AIPS2_SIZE SZ_1M
#define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000)
#define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000)
......@@ -105,11 +102,9 @@
* ROMP and AVIC
*/
#define MX3x_ROMP_BASE_ADDR 0x60000000
#define MX3x_ROMP_BASE_ADDR_VIRT 0xfc500000
#define MX3x_ROMP_SIZE SZ_1M
#define MX3x_AVIC_BASE_ADDR 0x68000000
#define MX3x_AVIC_BASE_ADDR_VIRT 0xfc400000
#define MX3x_AVIC_SIZE SZ_1M
/*
......@@ -125,18 +120,17 @@
#define MX3x_CS3_BASE_ADDR 0xb2000000
#define MX3x_CS4_BASE_ADDR 0xb4000000
#define MX3x_CS4_BASE_ADDR_VIRT 0xf4000000
#define MX3x_CS4_BASE_ADDR_VIRT 0xf6000000
#define MX3x_CS4_SIZE SZ_32M
#define MX3x_CS5_BASE_ADDR 0xb6000000
#define MX3x_CS5_BASE_ADDR_VIRT 0xf6000000
#define MX3x_CS5_BASE_ADDR_VIRT 0xf8000000
#define MX3x_CS5_SIZE SZ_32M
/*
* NAND, SDRAM, WEIM, M3IF, EMI controllers
*/
#define MX3x_X_MEMC_BASE_ADDR 0xb8000000
#define MX3x_X_MEMC_BASE_ADDR_VIRT 0xfc320000
#define MX3x_X_MEMC_SIZE SZ_64K
#define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000)
#define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000)
......@@ -146,56 +140,6 @@
#define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000
/*!
* This macro defines the physical to virtual address mapping for all the
* peripheral modules. It is used by passing in the physical address as x
* and returning the virtual address. If the physical address is not mapped,
* it returns 0xDEADBEEF
*/
#define IO_ADDRESS(x) \
(void __force __iomem *) \
(((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
0xDEADBEEF)
/*
* define the address mapping macros: in physical address order
*/
#define L2CC_IO_ADDRESS(x) \
(((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
#define AIPS1_IO_ADDRESS(x) \
(((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
#define SPBA0_IO_ADDRESS(x) \
(((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
#define AIPS2_IO_ADDRESS(x) \
(((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
#define ROMP_IO_ADDRESS(x) \
(((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
#define AVIC_IO_ADDRESS(x) \
(((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
#define CS4_IO_ADDRESS(x) \
(((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
#define CS5_IO_ADDRESS(x) \
(((x) - CS5_BASE_ADDR) + CS5_BASE_ADDR_VIRT)
#define X_MEMC_IO_ADDRESS(x) \
(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
#define PCMCIA_IO_ADDRESS(x) \
(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
/*
* Interrupt numbers
*/
......@@ -277,126 +221,4 @@ static inline int mx35_revision(void)
}
#endif
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
/* these should go away */
#define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR
#define L2CC_SIZE MX3x_L2CC_SIZE
#define AIPS1_BASE_ADDR MX3x_AIPS1_BASE_ADDR
#define AIPS1_BASE_ADDR_VIRT MX3x_AIPS1_BASE_ADDR_VIRT
#define AIPS1_SIZE MX3x_AIPS1_SIZE
#define MAX_BASE_ADDR MX3x_MAX_BASE_ADDR
#define EVTMON_BASE_ADDR MX3x_EVTMON_BASE_ADDR
#define CLKCTL_BASE_ADDR MX3x_CLKCTL_BASE_ADDR
#define ETB_SLOT4_BASE_ADDR MX3x_ETB_SLOT4_BASE_ADDR
#define ETB_SLOT5_BASE_ADDR MX3x_ETB_SLOT5_BASE_ADDR
#define ECT_CTIO_BASE_ADDR MX3x_ECT_CTIO_BASE_ADDR
#define I2C_BASE_ADDR MX3x_I2C_BASE_ADDR
#define I2C3_BASE_ADDR MX3x_I2C3_BASE_ADDR
#define UART1_BASE_ADDR MX3x_UART1_BASE_ADDR
#define UART2_BASE_ADDR MX3x_UART2_BASE_ADDR
#define I2C2_BASE_ADDR MX3x_I2C2_BASE_ADDR
#define OWIRE_BASE_ADDR MX3x_OWIRE_BASE_ADDR
#define SSI1_BASE_ADDR MX3x_SSI1_BASE_ADDR
#define CSPI1_BASE_ADDR MX3x_CSPI1_BASE_ADDR
#define KPP_BASE_ADDR MX3x_KPP_BASE_ADDR
#define IOMUXC_BASE_ADDR MX3x_IOMUXC_BASE_ADDR
#define ECT_IP1_BASE_ADDR MX3x_ECT_IP1_BASE_ADDR
#define ECT_IP2_BASE_ADDR MX3x_ECT_IP2_BASE_ADDR
#define SPBA0_BASE_ADDR MX3x_SPBA0_BASE_ADDR
#define SPBA0_BASE_ADDR_VIRT MX3x_SPBA0_BASE_ADDR_VIRT
#define SPBA0_SIZE MX3x_SPBA0_SIZE
#define UART3_BASE_ADDR MX3x_UART3_BASE_ADDR
#define CSPI2_BASE_ADDR MX3x_CSPI2_BASE_ADDR
#define SSI2_BASE_ADDR MX3x_SSI2_BASE_ADDR
#define ATA_DMA_BASE_ADDR MX3x_ATA_DMA_BASE_ADDR
#define MSHC1_BASE_ADDR MX3x_MSHC1_BASE_ADDR
#define SPBA_CTRL_BASE_ADDR MX3x_SPBA_CTRL_BASE_ADDR
#define AIPS2_BASE_ADDR MX3x_AIPS2_BASE_ADDR
#define AIPS2_BASE_ADDR_VIRT MX3x_AIPS2_BASE_ADDR_VIRT
#define AIPS2_SIZE MX3x_AIPS2_SIZE
#define CCM_BASE_ADDR MX3x_CCM_BASE_ADDR
#define GPT1_BASE_ADDR MX3x_GPT1_BASE_ADDR
#define EPIT1_BASE_ADDR MX3x_EPIT1_BASE_ADDR
#define EPIT2_BASE_ADDR MX3x_EPIT2_BASE_ADDR
#define GPIO3_BASE_ADDR MX3x_GPIO3_BASE_ADDR
#define SCC_BASE_ADDR MX3x_SCC_BASE_ADDR
#define RNGA_BASE_ADDR MX3x_RNGA_BASE_ADDR
#define IPU_CTRL_BASE_ADDR MX3x_IPU_CTRL_BASE_ADDR
#define AUDMUX_BASE_ADDR MX3x_AUDMUX_BASE_ADDR
#define GPIO1_BASE_ADDR MX3x_GPIO1_BASE_ADDR
#define GPIO2_BASE_ADDR MX3x_GPIO2_BASE_ADDR
#define SDMA_BASE_ADDR MX3x_SDMA_BASE_ADDR
#define RTC_BASE_ADDR MX3x_RTC_BASE_ADDR
#define WDOG_BASE_ADDR MX3x_WDOG_BASE_ADDR
#define PWM_BASE_ADDR MX3x_PWM_BASE_ADDR
#define RTIC_BASE_ADDR MX3x_RTIC_BASE_ADDR
#define ROMP_BASE_ADDR MX3x_ROMP_BASE_ADDR
#define ROMP_BASE_ADDR_VIRT MX3x_ROMP_BASE_ADDR_VIRT
#define ROMP_SIZE MX3x_ROMP_SIZE
#define AVIC_BASE_ADDR MX3x_AVIC_BASE_ADDR
#define AVIC_BASE_ADDR_VIRT MX3x_AVIC_BASE_ADDR_VIRT
#define AVIC_SIZE MX3x_AVIC_SIZE
#define IPU_MEM_BASE_ADDR MX3x_IPU_MEM_BASE_ADDR
#define CSD0_BASE_ADDR MX3x_CSD0_BASE_ADDR
#define CSD1_BASE_ADDR MX3x_CSD1_BASE_ADDR
#define CS0_BASE_ADDR MX3x_CS0_BASE_ADDR
#define CS1_BASE_ADDR MX3x_CS1_BASE_ADDR
#define CS2_BASE_ADDR MX3x_CS2_BASE_ADDR
#define CS3_BASE_ADDR MX3x_CS3_BASE_ADDR
#define CS4_BASE_ADDR MX3x_CS4_BASE_ADDR
#define CS4_BASE_ADDR_VIRT MX3x_CS4_BASE_ADDR_VIRT
#define CS4_SIZE MX3x_CS4_SIZE
#define CS5_BASE_ADDR MX3x_CS5_BASE_ADDR
#define CS5_BASE_ADDR_VIRT MX3x_CS5_BASE_ADDR_VIRT
#define CS5_SIZE MX3x_CS5_SIZE
#define X_MEMC_BASE_ADDR MX3x_X_MEMC_BASE_ADDR
#define X_MEMC_BASE_ADDR_VIRT MX3x_X_MEMC_BASE_ADDR_VIRT
#define X_MEMC_SIZE MX3x_X_MEMC_SIZE
#define ESDCTL_BASE_ADDR MX3x_ESDCTL_BASE_ADDR
#define WEIM_BASE_ADDR MX3x_WEIM_BASE_ADDR
#define M3IF_BASE_ADDR MX3x_M3IF_BASE_ADDR
#define EMI_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR
#define PCMCIA_CTL_BASE_ADDR MX3x_PCMCIA_CTL_BASE_ADDR
#define PCMCIA_MEM_BASE_ADDR MX3x_PCMCIA_MEM_BASE_ADDR
#define MXC_INT_I2C3 MX3x_INT_I2C3
#define MXC_INT_I2C2 MX3x_INT_I2C2
#define MXC_INT_RTIC MX3x_INT_RTIC
#define MXC_INT_I2C MX3x_INT_I2C
#define MXC_INT_CSPI2 MX3x_INT_CSPI2
#define MXC_INT_CSPI1 MX3x_INT_CSPI1
#define MXC_INT_ATA MX3x_INT_ATA
#define MXC_INT_UART3 MX3x_INT_UART3
#define MXC_INT_IIM MX3x_INT_IIM
#define MXC_INT_RNGA MX3x_INT_RNGA
#define MXC_INT_EVTMON MX3x_INT_EVTMON
#define MXC_INT_KPP MX3x_INT_KPP
#define MXC_INT_RTC MX3x_INT_RTC
#define MXC_INT_PWM MX3x_INT_PWM
#define MXC_INT_EPIT2 MX3x_INT_EPIT2
#define MXC_INT_EPIT1 MX3x_INT_EPIT1
#define MXC_INT_GPT MX3x_INT_GPT
#define MXC_INT_POWER_FAIL MX3x_INT_POWER_FAIL
#define MXC_INT_UART2 MX3x_INT_UART2
#define MXC_INT_NANDFC MX3x_INT_NANDFC
#define MXC_INT_SDMA MX3x_INT_SDMA
#define MXC_INT_MSHC1 MX3x_INT_MSHC1
#define MXC_INT_IPU_ERR MX3x_INT_IPU_ERR
#define MXC_INT_IPU_SYN MX3x_INT_IPU_SYN
#define MXC_INT_UART1 MX3x_INT_UART1
#define MXC_INT_ECT MX3x_INT_ECT
#define MXC_INT_SCC_SCM MX3x_INT_SCC_SCM
#define MXC_INT_SCC_SMN MX3x_INT_SCC_SMN
#define MXC_INT_GPIO2 MX3x_INT_GPIO2
#define MXC_INT_GPIO1 MX3x_INT_GPIO1
#define MXC_INT_WDOG MX3x_INT_WDOG
#define MXC_INT_GPIO3 MX3x_INT_GPIO3
#define MXC_INT_EXT_POWER MX3x_INT_EXT_POWER
#define MXC_INT_EXT_TEMPER MX3x_INT_EXT_TEMPER
#define MXC_INT_EXT_SENSOR60 MX3x_INT_EXT_SENSOR60
#define MXC_INT_EXT_SENSOR61 MX3x_INT_EXT_SENSOR61
#define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG
#define MXC_INT_EXT_TV MX3x_INT_EXT_TV
#define PROD_SIGNATURE MX3x_PROD_SIGNATURE
#endif
#endif /* ifndef __MACH_MX3x_H__ */
arch/arm/plat-mxc/include/mach/mx51.h
View file @ 2a85927c
#ifndef __MACH_MX51_H__
#define __MACH_MX51_H__
/*
* MX51 memory map:
*
*
* Virt Phys Size What
* ---------------------------------------------------------------------------
* fa3e0000 1ffe0000 128K IRAM (SCCv2 RAM)
* 30000000 256M GPU
* 40000000 512M IPU
* fa200000 60000000 1M DEBUG
* fb100000 70000000 1M SPBA 0
* fb000000 73f00000 1M AIPS 1
* fb200000 83f00000 1M AIPS 2
* 8fffc000 16K TZIC (interrupt controller)
* 90000000 256M CSD0 SDRAM/DDR
* a0000000 256M CSD1 SDRAM/DDR
* b0000000 128M CS0 Flash
* b8000000 128M CS1 Flash
* c0000000 128M CS2 Flash
* c8000000 64M CS3 Flash
* cc000000 32M CS4 SRAM
* ce000000 32M CS5 SRAM
* cfff0000 64K NFC (NAND Flash AXI)
*/
/*
* IROM
*/
......@@ -36,7 +11,6 @@
* IRAM
*/
#define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */
#define MX51_IRAM_BASE_ADDR_VIRT 0xfa3e0000
#define MX51_IRAM_PARTITIONS 16
#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */
......@@ -45,7 +19,6 @@
#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
#define MX51_DEBUG_BASE_ADDR 0x60000000
#define MX51_DEBUG_BASE_ADDR_VIRT 0xfa200000
#define MX51_DEBUG_SIZE SZ_1M
#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000)
......@@ -61,7 +34,6 @@
* SPBA global module enabled #0
*/
#define MX51_SPBA0_BASE_ADDR 0x70000000
#define MX51_SPBA0_BASE_ADDR_VIRT 0xfb100000
#define MX51_SPBA0_SIZE SZ_1M
#define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000)
......@@ -81,7 +53,6 @@
* AIPS 1
*/
#define MX51_AIPS1_BASE_ADDR 0x73f00000
#define MX51_AIPS1_BASE_ADDR_VIRT 0xfb000000
#define MX51_AIPS1_SIZE SZ_1M
#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000)
......@@ -109,7 +80,6 @@
* AIPS 2
*/
#define MX51_AIPS2_BASE_ADDR 0x83f00000
#define MX51_AIPS2_BASE_ADDR_VIRT 0xfb200000
#define MX51_AIPS2_SIZE SZ_1M
#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000)
......@@ -163,16 +133,8 @@
#define MX51_GPU2D_BASE_ADDR 0xd0000000
#define MX51_TZIC_BASE_ADDR 0xe0000000
#define MX51_IO_ADDRESS(x) ( \
IMX_IO_ADDRESS(x, MX51_IRAM) ?: \
IMX_IO_ADDRESS(x, MX51_DEBUG) ?: \
IMX_IO_ADDRESS(x, MX51_SPBA0) ?: \
IMX_IO_ADDRESS(x, MX51_AIPS1) ?: \
IMX_IO_ADDRESS(x, MX51_AIPS2))
/* This is currently used in <mach/debug-macro.S>, but should go away */
#define MX51_AIPS1_IO_ADDRESS(x) \
(((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT)
#define MX51_IO_P2V(x) IMX_IO_P2V(x)
#define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x))
/*
* defines for SPBA modules
......
arch/arm/plat-mxc/include/mach/mxc91231.h
View file @ 2a85927c
......@@ -21,14 +21,12 @@
* L2CC
*/
#define MXC91231_L2CC_BASE_ADDR 0x30000000
#define MXC91231_L2CC_BASE_ADDR_VIRT 0xF9000000
#define MXC91231_L2CC_SIZE SZ_64K
/*
* AIPS 1
*/
#define MXC91231_AIPS1_BASE_ADDR 0x43F00000
#define MXC91231_AIPS1_BASE_ADDR_VIRT 0xFC000000
#define MXC91231_AIPS1_SIZE SZ_1M
#define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR
......@@ -53,7 +51,6 @@
* AIPS 2
*/
#define MXC91231_AIPS2_BASE_ADDR 0x53F00000
#define MXC91231_AIPS2_BASE_ADDR_VIRT 0xFC100000
#define MXC91231_AIPS2_SIZE SZ_1M
#define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000)
......@@ -79,7 +76,6 @@
* SPBA global module 0
*/
#define MXC91231_SPBA0_BASE_ADDR 0x50000000
#define MXC91231_SPBA0_BASE_ADDR_VIRT 0xFC200000
#define MXC91231_SPBA0_SIZE SZ_1M
#define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000)
......@@ -109,7 +105,6 @@
* SPBA global module 1
*/
#define MXC91231_SPBA1_BASE_ADDR 0x52000000
#define MXC91231_SPBA1_BASE_ADDR_VIRT 0xFC300000
#define MXC91231_SPBA1_SIZE SZ_1M
#define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000)
......@@ -144,18 +139,15 @@
* ROMP and AVIC
*/
#define MXC91231_ROMP_BASE_ADDR 0x60000000
#define MXC91231_ROMP_BASE_ADDR_VIRT 0xFC400000
#define MXC91231_ROMP_SIZE SZ_64K
#define MXC91231_AVIC_BASE_ADDR 0x68000000
#define MXC91231_AVIC_BASE_ADDR_VIRT 0xFC410000
#define MXC91231_AVIC_SIZE SZ_64K
/*
* NAND, SDRAM, WEIM, M3IF, EMI controllers
*/
#define MXC91231_X_MEMC_BASE_ADDR 0xB8000000
#define MXC91231_X_MEMC_BASE_ADDR_VIRT 0xFC420000
#define MXC91231_X_MEMC_SIZE SZ_64K
#define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000)
......@@ -183,19 +175,10 @@
/*
* This macro defines the physical to virtual address mapping for all the
* peripheral modules. It is used by passing in the physical address as x
* and returning the virtual address. If the physical address is not mapped,
* it returns 0.
* and returning the virtual address.
*/
#define MXC91231_IO_ADDRESS(x) ( \
IMX_IO_ADDRESS(x, MXC91231_L2CC) ?: \
IMX_IO_ADDRESS(x, MXC91231_X_MEMC) ?: \
IMX_IO_ADDRESS(x, MXC91231_ROMP) ?: \
IMX_IO_ADDRESS(x, MXC91231_AVIC) ?: \
IMX_IO_ADDRESS(x, MXC91231_AIPS1) ?: \
IMX_IO_ADDRESS(x, MXC91231_SPBA0) ?: \
IMX_IO_ADDRESS(x, MXC91231_SPBA1) ?: \
IMX_IO_ADDRESS(x, MXC91231_AIPS2))
#define MXC91231_IO_P2V(x) IMX_IO_P2V(x)
#define MXC91231_IO_ADDRESS(x) IOMEM(MXC91231_IO_P2V(x))
/*
* Interrupt numbers
......
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