Commit 2c50a570 authored by Linus Walleij's avatar Linus Walleij Committed by Russell King

ARM: 9004/1: debug: Split waituart to CTS and TXRDY

This patch was triggered by a remark from Russell that
introducing a call to the waituart (needed to fix debug prints
on the Qualcomm platforms) was dangerous because in some cases
this will involve waiting for a modem CTS (clear to send)
signal, and debug messages would maybe not work on platforms
with no modem connected to the UART port: they will just
hang waiting for the modem to assert CTS and this might never
happen.

Looking through all UART debug drivers implementing the waituart
macro I discovered that all users except two actually use this
macro to check if the UART is ready for TX, let's call this
TXRDY.

Only two debug UART drivers actually check for CTS:
- arch/arm/include/debug/8250.S
- arch/arm/include/debug/tegra.S

The former is very significant since the 8250 is possibly
the most common UART on the planet.

We have the following problem: the semantics of waituart are
ambiguous making it dangerous to introduce the macro to debug
code fixing debug prints for Qualcomm. To start to pry this
problem apart, this patch does the following:

- Convert all debug UART drivers to define two macros:

  - waituartcts with the clear semantic to wait for CTS
    to be asserted

  - waituarttxrdy with the clear semantic to wait for the TX
    capability of the UART to be ready

- When doing this take care to assign the right function to
  each drivers macro, so they now do exactly the above.

- Update the three sites in the kernel invoking the waituart
  macro to call waituartcts/waituarttxrdy in sequence, so that
  the functional impact on the kernel should be zero.

After this we can start to change the code sites using this
code to do the right thing.
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
parent 6428ea27
...@@ -8,7 +8,8 @@ ...@@ -8,7 +8,8 @@
ENTRY(putc) ENTRY(putc)
addruart r1, r2, r3 addruart r1, r2, r3
waituart r3, r1 waituartcts r3, r1
waituarttxrdy r3, r1
senduart r0, r1 senduart r0, r1
busyuart r3, r1 busyuart r3, r1
mov pc, lr mov pc, lr
......
...@@ -45,7 +45,10 @@ ...@@ -45,7 +45,10 @@
bne 1002b bne 1002b
.endm .endm
.macro waituart,rd,rx .macro waituarttxrdy,rd,rx
.endm
.macro waituartcts,rd,rx
#ifdef CONFIG_DEBUG_UART_8250_FLOW_CONTROL #ifdef CONFIG_DEBUG_UART_8250_FLOW_CONTROL
1001: load \rd, [\rx, #UART_MSR << UART_SHIFT] 1001: load \rd, [\rx, #UART_MSR << UART_SHIFT]
tst \rd, #UART_MSR_CTS tst \rd, #UART_MSR_CTS
......
...@@ -11,7 +11,10 @@ ...@@ -11,7 +11,10 @@
ldr \rv, = CONFIG_DEBUG_UART_VIRT ldr \rv, = CONFIG_DEBUG_UART_VIRT
.endm .endm
.macro waituart,rd,rx .macro waituarttxrdy,rd,rx
.endm
.macro waituartcts,rd,rx
.endm .endm
.macro senduart,rd,rx .macro senduart,rd,rx
......
...@@ -19,12 +19,15 @@ ...@@ -19,12 +19,15 @@
strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register
.endm .endm
.macro waituart,rd,rx .macro waituarttxrdy,rd,rx
1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit
beq 1001b beq 1001b
.endm .endm
.macro waituartcts,rd,rx
.endm
.macro busyuart,rd,rx .macro busyuart,rd,rx
1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete
......
...@@ -17,12 +17,15 @@ ...@@ -17,12 +17,15 @@
strb \rd, [\rx, #UART_FIFO_REG] strb \rd, [\rx, #UART_FIFO_REG]
.endm .endm
.macro waituart, rd, rx .macro waituarttxrdy, rd, rx
1001: ldr \rd, [\rx, #UART_IR_REG] 1001: ldr \rd, [\rx, #UART_IR_REG]
tst \rd, #(1 << UART_IR_TXEMPTY) tst \rd, #(1 << UART_IR_TXEMPTY)
beq 1001b beq 1001b
.endm .endm
.macro waituartcts, rd, rx
.endm
.macro busyuart, rd, rx .macro busyuart, rd, rx
1002: ldr \rd, [\rx, #UART_IR_REG] 1002: ldr \rd, [\rx, #UART_IR_REG]
tst \rd, #(1 << UART_IR_TXTRESH) tst \rd, #(1 << UART_IR_TXTRESH)
......
...@@ -142,7 +142,10 @@ ARM_BE8( rev \rd, \rd ) ...@@ -142,7 +142,10 @@ ARM_BE8( rev \rd, \rd )
bne 1002b bne 1002b
.endm .endm
.macro waituart,rd,rx .macro waituarttxrdy,rd,rx
.endm
.macro waituartcts,rd,rx
.endm .endm
/* /*
......
...@@ -20,7 +20,10 @@ ...@@ -20,7 +20,10 @@
ldr \rp, =CLPS711X_UART_PADDR ldr \rp, =CLPS711X_UART_PADDR
.endm .endm
.macro waituart,rd,rx .macro waituartcts,rd,rx
.endm
.macro waituarttxrdy,rd,rx
.endm .endm
.macro senduart,rd,rx .macro senduart,rd,rx
......
...@@ -34,5 +34,8 @@ ...@@ -34,5 +34,8 @@
bne 1001b bne 1001b
.endm .endm
.macro waituart,rd,rx .macro waituartcts,rd,rx
.endm
.macro waituarttxrdy,rd,rx
.endm .endm
...@@ -21,7 +21,10 @@ ...@@ -21,7 +21,10 @@
strb \rd, [\rx, #UA0_EMI_REC] strb \rd, [\rx, #UA0_EMI_REC]
.endm .endm
.macro waituart,rd,rx .macro waituartcts,rd,rx
.endm
.macro waituarttxrdy,rd,rx
.endm .endm
.macro busyuart,rd,rx .macro busyuart,rd,rx
......
...@@ -29,7 +29,10 @@ ...@@ -29,7 +29,10 @@
strb \rd, [\rx, #UARTn_TXDATA] strb \rd, [\rx, #UARTn_TXDATA]
.endm .endm
.macro waituart,rd,rx .macro waituartcts,rd,rx
.endm
.macro waituarttxrdy,rd,rx
1001: ldr \rd, [\rx, #UARTn_STATUS] 1001: ldr \rd, [\rx, #UARTn_STATUS]
tst \rd, #UARTn_STATUS_TXBL tst \rd, #UARTn_STATUS_TXBL
beq 1001b beq 1001b
......
...@@ -23,7 +23,10 @@ ...@@ -23,7 +23,10 @@
beq 1001b beq 1001b
.endm .endm
.macro waituart, rd, rx .macro waituartcts, rd, rx
.endm
.macro waituarttxrdy, rd, rx
mov \rd, #0x2000000 mov \rd, #0x2000000
1001: 1001:
subs \rd, \rd, #1 subs \rd, \rd, #1
...@@ -47,7 +50,10 @@ ...@@ -47,7 +50,10 @@
beq 1001b beq 1001b
.endm .endm
.macro waituart, rd, rx .macro waituartcts, rd, rx
.endm
.macro waituarttxrdy, rd, rx
mov \rd, #0x10000000 mov \rd, #0x10000000
1001: 1001:
subs \rd, \rd, #1 subs \rd, \rd, #1
...@@ -72,7 +78,10 @@ ...@@ -72,7 +78,10 @@
.endm .endm
.macro waituart, rd, rx .macro waituartcts, rd, rx
.endm
.macro waituarttxrdy, rd, rx
mov \rd, #0x2000000 mov \rd, #0x2000000
1001: 1001:
subs \rd, \rd, #1 subs \rd, \rd, #1
......
...@@ -35,7 +35,10 @@ ...@@ -35,7 +35,10 @@
str \rd, [\rx, #0x40] @ TXDATA str \rd, [\rx, #0x40] @ TXDATA
.endm .endm
.macro waituart,rd,rx .macro waituartcts,rd,rx
.endm
.macro waituarttxrdy,rd,rx
.endm .endm
.macro busyuart,rd,rx .macro busyuart,rd,rx
......
...@@ -25,7 +25,10 @@ ...@@ -25,7 +25,10 @@
beq 1002b beq 1002b
.endm .endm
.macro waituart,rd,rx .macro waituartcts,rd,rx
.endm
.macro waituarttxrdy,rd,rx
1001: ldr \rd, [\rx, #MESON_AO_UART_STATUS] 1001: ldr \rd, [\rx, #MESON_AO_UART_STATUS]
tst \rd, #MESON_AO_UART_TX_FIFO_FULL tst \rd, #MESON_AO_UART_TX_FIFO_FULL
bne 1001b bne 1001b
......
...@@ -17,7 +17,10 @@ ARM_BE8(rev \rd, \rd ) ...@@ -17,7 +17,10 @@ ARM_BE8(rev \rd, \rd )
str \rd, [\rx, #0x70] str \rd, [\rx, #0x70]
.endm .endm
.macro waituart, rd, rx .macro waituartcts,rd,rx
.endm
.macro waituarttxrdy, rd, rx
@ check for TX_EMT in UARTDM_SR @ check for TX_EMT in UARTDM_SR
ldr \rd, [\rx, #0x08] ldr \rd, [\rx, #0x08]
ARM_BE8(rev \rd, \rd ) ARM_BE8(rev \rd, \rd )
......
...@@ -75,5 +75,8 @@ omap_uart_lsr: .word 0 ...@@ -75,5 +75,8 @@ omap_uart_lsr: .word 0
bne 1001b bne 1001b
.endm .endm
.macro waituart,rd,rx .macro waituartcts,rd,rx
.endm
.macro waituarttxrdy,rd,rx
.endm .endm
...@@ -26,7 +26,10 @@ ...@@ -26,7 +26,10 @@
strb \rd, [\rx, #UART01x_DR] strb \rd, [\rx, #UART01x_DR]
.endm .endm
.macro waituart,rd,rx .macro waituartcts,rd,rx
.endm
.macro waituarttxrdy,rd,rx
1001: ldr \rd, [\rx, #UART01x_FR] 1001: ldr \rd, [\rx, #UART01x_FR]
ARM_BE8( rev \rd, \rd ) ARM_BE8( rev \rd, \rd )
tst \rd, #UART01x_FR_TXFF tst \rd, #UART01x_FR_TXFF
......
...@@ -33,7 +33,10 @@ ...@@ -33,7 +33,10 @@
ldr \rv, =SCIF_VIRT ldr \rv, =SCIF_VIRT
.endm .endm
.macro waituart, rd, rx .macro waituartcts,rd,rx
.endm
.macro waituarttxrdy, rd, rx
1001: ldrh \rd, [\rx, #FSR] 1001: ldrh \rd, [\rx, #FSR]
tst \rd, #TDFE tst \rd, #TDFE
beq 1001b beq 1001b
......
...@@ -51,7 +51,10 @@ ...@@ -51,7 +51,10 @@
str \rd, [\rx, #UTDR] str \rd, [\rx, #UTDR]
.endm .endm
.macro waituart,rd,rx .macro waituartcts,rd,rx
.endm
.macro waituarttxrdy,rd,rx
1001: ldr \rd, [\rx, #UTSR1] 1001: ldr \rd, [\rx, #UTSR1]
tst \rd, #UTSR1_TNF tst \rd, #UTSR1_TNF
beq 1001b beq 1001b
......
...@@ -69,7 +69,10 @@ ARM_BE8(rev \rd, \rd) ...@@ -69,7 +69,10 @@ ARM_BE8(rev \rd, \rd)
1002: @ exit busyuart 1002: @ exit busyuart
.endm .endm
.macro waituart,rd,rx .macro waituartcts,rd,rx
.endm
.macro waituarttxrdy,rd,rx
ldr \rd, [\rx, # S3C2410_UFCON] ldr \rd, [\rx, # S3C2410_UFCON]
ARM_BE8(rev \rd, \rd) ARM_BE8(rev \rd, \rd)
tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled? tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
......
...@@ -29,7 +29,10 @@ ...@@ -29,7 +29,10 @@
.macro busyuart,rd,rx .macro busyuart,rd,rx
.endm .endm
.macro waituart,rd,rx .macro waituartcts,rd,rx
.endm
.macro waituarttxrdy,rd,rx
1001: ldr \rd, [\rx, #SIRF_LLUART_TXFIFO_STATUS] 1001: ldr \rd, [\rx, #SIRF_LLUART_TXFIFO_STATUS]
tst \rd, #SIRF_LLUART_TXFIFO_EMPTY tst \rd, #SIRF_LLUART_TXFIFO_EMPTY
beq 1001b beq 1001b
......
...@@ -45,7 +45,10 @@ ...@@ -45,7 +45,10 @@
strb \rd, [\rx, #ASC_TX_BUF_OFF] strb \rd, [\rx, #ASC_TX_BUF_OFF]
.endm .endm
.macro waituart,rd,rx .macro waituartcts,rd,rx
.endm
.macro waituarttxrdy,rd,rx
1001: ldr \rd, [\rx, #ASC_STA_OFF] 1001: ldr \rd, [\rx, #ASC_STA_OFF]
tst \rd, #ASC_STA_TX_FULL tst \rd, #ASC_STA_TX_FULL
bne 1001b bne 1001b
......
...@@ -27,7 +27,10 @@ ...@@ -27,7 +27,10 @@
strb \rd, [\rx, #STM32_USART_TDR_OFF] strb \rd, [\rx, #STM32_USART_TDR_OFF]
.endm .endm
.macro waituart,rd,rx .macro waituartcts,rd,rx
.endm
.macro waituarttxrdy,rd,rx
1001: ldr \rd, [\rx, #(STM32_USART_SR_OFF)] @ Read Status Register 1001: ldr \rd, [\rx, #(STM32_USART_SR_OFF)] @ Read Status Register
tst \rd, #STM32_USART_TXE @ TXE = 1 = tx empty tst \rd, #STM32_USART_TXE @ TXE = 1 = tx empty
beq 1001b beq 1001b
......
...@@ -178,7 +178,7 @@ ...@@ -178,7 +178,7 @@
1002: 1002:
.endm .endm
.macro waituart, rd, rx .macro waituartcts, rd, rx
#ifdef FLOW_CONTROL #ifdef FLOW_CONTROL
cmp \rx, #0 cmp \rx, #0
beq 1002f beq 1002f
...@@ -189,6 +189,9 @@ ...@@ -189,6 +189,9 @@
#endif #endif
.endm .endm
.macro waituarttxrdy,rd,rx
.endm
/* /*
* Storage for the state maintained by the macros above. * Storage for the state maintained by the macros above.
* *
......
...@@ -29,5 +29,8 @@ ...@@ -29,5 +29,8 @@
beq 1001b @ wait until transmit done beq 1001b @ wait until transmit done
.endm .endm
.macro waituart,rd,rx .macro waituartcts,rd,rx
.endm
.macro waituarttxrdy,rd,rx
.endm .endm
...@@ -28,7 +28,10 @@ ...@@ -28,7 +28,10 @@
bne 1001b bne 1001b
.endm .endm
.macro waituart,rd,rx .macro waituartcts,rd,rx
.endm
.macro waituarttxrdy,rd,rx
.endm .endm
#endif #endif
...@@ -33,7 +33,10 @@ ...@@ -33,7 +33,10 @@
strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA
.endm .endm
.macro waituart,rd,rx .macro waituartcts,rd,rx
.endm
.macro waituarttxrdy,rd,rx
1001: ldr \rd, [\rx, #UART_SR_OFFSET] 1001: ldr \rd, [\rx, #UART_SR_OFFSET]
ARM_BE8( rev \rd, \rd ) ARM_BE8( rev \rd, \rd )
tst \rd, #UART_SR_TXEMPTY tst \rd, #UART_SR_TXEMPTY
......
...@@ -89,11 +89,13 @@ ENTRY(printascii) ...@@ -89,11 +89,13 @@ ENTRY(printascii)
2: teq r1, #'\n' 2: teq r1, #'\n'
bne 3f bne 3f
mov r1, #'\r' mov r1, #'\r'
waituart r2, r3 waituartcts r2, r3
waituarttxrdy r2, r3
senduart r1, r3 senduart r1, r3
busyuart r2, r3 busyuart r2, r3
mov r1, #'\n' mov r1, #'\n'
3: waituart r2, r3 3: waituartcts r2, r3
waituarttxrdy r2, r3
senduart r1, r3 senduart r1, r3
busyuart r2, r3 busyuart r2, r3
b 1b b 1b
......
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