Commit 2d22c7dd authored by Sujith Manoharan's avatar Sujith Manoharan Committed by John W. Linville

ath9k: Use correct PCIE initvals for AR9485

Currently, the PLL is turned off for AR9485 when
switching to a low power state, but AR9485 has an issue
where the card will become unresponsive if left idle
for a long time without any traffic. To fix this,
force the PLL to always be on using a different initval
array, ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1.

This is done for most of the AR9485 based cards
like HB125, WB225 etc. but certain models require the
feature to be turned off. Identify such cards and use
default values for them.
Signed-off-by: default avatarSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 876efcf0
...@@ -187,17 +187,17 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) ...@@ -187,17 +187,17 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
INIT_INI_ARRAY(&ah->iniCckfirJapan2484, INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
ar9485_1_1_baseband_core_txfir_coeff_japan_2484); ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
/* Load PCIE SERDES settings from INI */ if (ah->config.no_pll_pwrsave) {
/* Awake Setting */
INIT_INI_ARRAY(&ah->iniPcieSerdes, INIT_INI_ARRAY(&ah->iniPcieSerdes,
ar9485_1_1_pcie_phy_clkreq_disable_L1); ar9485_1_1_pcie_phy_clkreq_disable_L1);
/* Sleep Setting */
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
ar9485_1_1_pcie_phy_clkreq_disable_L1); ar9485_1_1_pcie_phy_clkreq_disable_L1);
} else {
INIT_INI_ARRAY(&ah->iniPcieSerdes,
ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
}
} else if (AR_SREV_9462_21(ah)) { } else if (AR_SREV_9462_21(ah)) {
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
ar9462_2p1_mac_core); ar9462_2p1_mac_core);
......
...@@ -32,13 +32,6 @@ static const u32 ar9485_1_1_mac_postamble[][5] = { ...@@ -32,13 +32,6 @@ static const u32 ar9485_1_1_mac_postamble[][5] = {
{0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440}, {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
}; };
static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1[][2] = {
/* Addr allmodes */
{0x00018c00, 0x18012e5e},
{0x00018c04, 0x000801d8},
{0x00018c08, 0x0000080c},
};
static const u32 ar9485Common_wo_xlna_rx_gain_1_1[][2] = { static const u32 ar9485Common_wo_xlna_rx_gain_1_1[][2] = {
/* Addr allmodes */ /* Addr allmodes */
{0x00009e00, 0x037216a0}, {0x00009e00, 0x037216a0},
...@@ -1101,20 +1094,6 @@ static const u32 ar9485_common_rx_gain_1_1[][2] = { ...@@ -1101,20 +1094,6 @@ static const u32 ar9485_common_rx_gain_1_1[][2] = {
{0x0000a1fc, 0x00000296}, {0x0000a1fc, 0x00000296},
}; };
static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_enable_L1[][2] = {
/* Addr allmodes */
{0x00018c00, 0x18052e5e},
{0x00018c04, 0x000801d8},
{0x00018c08, 0x0000080c},
};
static const u32 ar9485_1_1_pcie_phy_clkreq_enable_L1[][2] = {
/* Addr allmodes */
{0x00018c00, 0x18053e5e},
{0x00018c04, 0x000801d8},
{0x00018c08, 0x0000080c},
};
static const u32 ar9485_1_1_soc_preamble[][2] = { static const u32 ar9485_1_1_soc_preamble[][2] = {
/* Addr allmodes */ /* Addr allmodes */
{0x00004014, 0xba280400}, {0x00004014, 0xba280400},
...@@ -1173,13 +1152,6 @@ static const u32 ar9485_1_1_baseband_postamble[][5] = { ...@@ -1173,13 +1152,6 @@ static const u32 ar9485_1_1_baseband_postamble[][5] = {
{0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
}; };
static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
/* Addr allmodes */
{0x00018c00, 0x18013e5e},
{0x00018c04, 0x000801d8},
{0x00018c08, 0x0000080c},
};
static const u32 ar9485_1_1_radio_postamble[][2] = { static const u32 ar9485_1_1_radio_postamble[][2] = {
/* Addr allmodes */ /* Addr allmodes */
{0x0001609c, 0x0b283f31}, {0x0001609c, 0x0b283f31},
...@@ -1358,4 +1330,18 @@ static const u32 ar9485_1_1_baseband_core_txfir_coeff_japan_2484[][2] = { ...@@ -1358,4 +1330,18 @@ static const u32 ar9485_1_1_baseband_core_txfir_coeff_japan_2484[][2] = {
{0x0000a3a0, 0xca9228ee}, {0x0000a3a0, 0xca9228ee},
}; };
static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
/* Addr allmodes */
{0x00018c00, 0x18013e5e},
{0x00018c04, 0x000801d8},
{0x00018c08, 0x0000080c},
};
static const u32 ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1[][2] = {
/* Addr allmodes */
{0x00018c00, 0x1801265e},
{0x00018c04, 0x000801d8},
{0x00018c08, 0x0000080c},
};
#endif /* INITVALS_9485_H */ #endif /* INITVALS_9485_H */
...@@ -641,6 +641,7 @@ void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs); ...@@ -641,6 +641,7 @@ void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs);
#define ATH9K_PCI_D3_L1_WAR 0x0040 #define ATH9K_PCI_D3_L1_WAR 0x0040
#define ATH9K_PCI_AR9565_1ANT 0x0080 #define ATH9K_PCI_AR9565_1ANT 0x0080
#define ATH9K_PCI_AR9565_2ANT 0x0100 #define ATH9K_PCI_AR9565_2ANT 0x0100
#define ATH9K_PCI_NO_PLL_PWRSAVE 0x0200
/* /*
* Default cache line size, in bytes. * Default cache line size, in bytes.
......
...@@ -316,6 +316,7 @@ struct ath9k_ops_config { ...@@ -316,6 +316,7 @@ struct ath9k_ops_config {
u32 ant_ctrl_comm2g_switch_enable; u32 ant_ctrl_comm2g_switch_enable;
bool xatten_margin_cfg; bool xatten_margin_cfg;
bool alt_mingainidx; bool alt_mingainidx;
bool no_pll_pwrsave;
}; };
enum ath9k_int { enum ath9k_int {
......
...@@ -609,6 +609,11 @@ static void ath9k_init_platform(struct ath_softc *sc) ...@@ -609,6 +609,11 @@ static void ath9k_init_platform(struct ath_softc *sc)
ah->config.pcie_waen = 0x0040473b; ah->config.pcie_waen = 0x0040473b;
ath_info(common, "Enable WAR for ASPM D3/L1\n"); ath_info(common, "Enable WAR for ASPM D3/L1\n");
} }
if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) {
ah->config.no_pll_pwrsave = true;
ath_info(common, "Disable PLL PowerSave\n");
}
} }
static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob, static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
......
...@@ -195,6 +195,93 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = { ...@@ -195,6 +195,93 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
0x3219), 0x3219),
.driver_data = ATH9K_PCI_BT_ANT_DIV }, .driver_data = ATH9K_PCI_BT_ANT_DIV },
/* AR9485 cards with PLL power-save disabled by default. */
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0032,
PCI_VENDOR_ID_AZWAVE,
0x2C97),
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0032,
PCI_VENDOR_ID_AZWAVE,
0x2100),
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0032,
0x1C56, /* ASKEY */
0x4001),
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0032,
0x11AD, /* LITEON */
0x6627),
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0032,
0x11AD, /* LITEON */
0x6628),
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0032,
PCI_VENDOR_ID_FOXCONN,
0xE04E),
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0032,
PCI_VENDOR_ID_FOXCONN,
0xE04F),
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0032,
0x144F, /* ASKEY */
0x7197),
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0032,
0x1B9A, /* XAVI */
0x2000),
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0032,
0x1B9A, /* XAVI */
0x2001),
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0032,
PCI_VENDOR_ID_AZWAVE,
0x1186),
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0032,
PCI_VENDOR_ID_AZWAVE,
0x1F86),
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0032,
PCI_VENDOR_ID_AZWAVE,
0x1195),
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0032,
PCI_VENDOR_ID_AZWAVE,
0x1F95),
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0032,
0x1B9A, /* XAVI */
0x1C00),
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0032,
0x1B9A, /* XAVI */
0x1C01),
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
0x0032,
PCI_VENDOR_ID_ASUSTEK,
0x850D),
.driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
{ PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */ { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */
{ PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */ { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */
......
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