Skip to content

L
linux
Commit 2d3c72ed authored by Jason Gunthorpe's avatar Jason Gunthorpe Committed by Doug Ledford
Browse files
Options

rdma: Remove nes 

This driver was first merged over 10 years ago and has not seen major
activity by the authors in the last 7 years. However, in that time it has
been patched 150 times to adapt it to changing kernel APIs.

Further, the hardware has several issues, like not supporting 64 bit DMA,
that make it rather uninteresting for use with modern systems and RDMA.
Signed-off-by: default avatarJason Gunthorpe <jgg@mellanox.com>
Reviewed-by: default avatarLeon Romanovsky <leonro@mellanox.com>
Reviewed-by: default avatarShiraz Saleem <shiraz.saleem@intel.com>
Signed-off-by: default avatarDoug Ledford <dledford@redhat.com>
parent cbdc666f
Show whitespace changes
Inline Side-by-side
Showing with 0 additions and 19700 deletions
Documentation/ABI/stable/sysfs-class-infiniband
View file @ 2d3c72ed
......@@ -423,23 +423,6 @@ Description:
(e.g. driver restart on the VM which owns the VF).
sysfs interface for NetEffect RNIC Low-Level iWARP driver (nes)
---------------------------------------------------------------
What: /sys/class/infiniband/nesX/hw_rev
What: /sys/class/infiniband/nesX/hca_type
What: /sys/class/infiniband/nesX/board_id
Date: Feb, 2008
KernelVersion: v2.6.25
Contact: linux-rdma@vger.kernel.org
Description:
hw_rev: (RO) Hardware revision number
hca_type: (RO) Host Channel Adapter type (NEX020)
board_id: (RO) Manufacturing board id
sysfs interface for Chelsio T4/T5 RDMA driver (cxgb4)
-----------------------------------------------------
......
MAINTAINERS
View file @ 2d3c72ed
......@@ -10830,14 +10830,6 @@ F: driver/net/net_failover.c
F: include/net/net_failover.h
F: Documentation/networking/net_failover.rst
NETEFFECT IWARP RNIC DRIVER (IW_NES)
M: Faisal Latif <faisal.latif@intel.com>
L: linux-rdma@vger.kernel.org
W: http://www.intel.com/Products/Server/Adapters/Server-Cluster/Server-Cluster-overview.htm
S: Supported
F: drivers/infiniband/hw/nes/
F: include/uapi/rdma/nes-abi.h
NETEM NETWORK EMULATOR
M: Stephen Hemminger <stephen@networkplumber.org>
L: netem@lists.linux-foundation.org (moderated for non-subscribers)
......
drivers/infiniband/Kconfig
View file @ 2d3c72ed
......@@ -86,7 +86,6 @@ source "drivers/infiniband/hw/efa/Kconfig"
source "drivers/infiniband/hw/i40iw/Kconfig"
source "drivers/infiniband/hw/mlx4/Kconfig"
source "drivers/infiniband/hw/mlx5/Kconfig"
source "drivers/infiniband/hw/nes/Kconfig"
source "drivers/infiniband/hw/ocrdma/Kconfig"
source "drivers/infiniband/hw/vmw_pvrdma/Kconfig"
source "drivers/infiniband/hw/usnic/Kconfig"
......
drivers/infiniband/hw/Makefile
View file @ 2d3c72ed
......@@ -7,7 +7,6 @@ obj-$(CONFIG_INFINIBAND_EFA) += efa/
obj-$(CONFIG_INFINIBAND_I40IW) += i40iw/
obj-$(CONFIG_MLX4_INFINIBAND) += mlx4/
obj-$(CONFIG_MLX5_INFINIBAND) += mlx5/
obj-$(CONFIG_INFINIBAND_NES) += nes/
obj-$(CONFIG_INFINIBAND_OCRDMA) += ocrdma/
obj-$(CONFIG_INFINIBAND_VMWARE_PVRDMA) += vmw_pvrdma/
obj-$(CONFIG_INFINIBAND_USNIC) += usnic/
......
drivers/infiniband/hw/nes/Kconfig deleted 100644 → 0
View file @ cbdc666f
config INFINIBAND_NES
tristate "NetEffect RNIC Driver"
depends on PCI && INET
select LIBCRC32C
---help---
This is the RDMA Network Interface Card (RNIC) driver for
NetEffect Ethernet Cluster Server Adapters.
config INFINIBAND_NES_DEBUG
bool "Verbose debugging output"
depends on INFINIBAND_NES
default n
---help---
This option enables debug messages from the NetEffect RNIC
driver. Select this if you are diagnosing a problem.
drivers/infiniband/hw/nes/Makefile deleted 100644 → 0
View file @ cbdc666f
obj-$(CONFIG_INFINIBAND_NES) += iw_nes.o
iw_nes-objs := nes.o nes_hw.o nes_nic.o nes_utils.o nes_verbs.o nes_cm.o nes_mgt.o
drivers/infiniband/hw/nes/nes.c deleted 100644 → 0
View file @ cbdc666f
/*
* Copyright (c) 2006 - 2011 Intel Corporation. All rights reserved.
* Copyright (c) 2005 Open Grid Computing, Inc. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/ethtool.h>
#include <linux/mii.h>
#include <linux/if_vlan.h>
#include <linux/crc32.h>
#include <linux/in.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/if_arp.h>
#include <linux/highmem.h>
#include <linux/slab.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/byteorder.h>
#include <rdma/ib_smi.h>
#include <rdma/ib_verbs.h>
#include <rdma/ib_pack.h>
#include <rdma/iw_cm.h>
#include "nes.h"
#include <net/netevent.h>
#include <net/neighbour.h>
#include <linux/route.h>
#include <net/ip_fib.h>
MODULE_AUTHOR("NetEffect");
MODULE_DESCRIPTION("NetEffect RNIC Low-level iWARP Driver");
MODULE_LICENSE("Dual BSD/GPL");
int interrupt_mod_interval = 0;
/* Interoperability */
int mpa_version = 1;
module_param(mpa_version, int, 0644);
MODULE_PARM_DESC(mpa_version, "MPA version to be used int MPA Req/Resp (0 or 1)");
/* Interoperability */
int disable_mpa_crc = 0;
module_param(disable_mpa_crc, int, 0644);
MODULE_PARM_DESC(disable_mpa_crc, "Disable checking of MPA CRC");
unsigned int nes_drv_opt = NES_DRV_OPT_DISABLE_INT_MOD | NES_DRV_OPT_ENABLE_PAU;
module_param(nes_drv_opt, int, 0644);
MODULE_PARM_DESC(nes_drv_opt, "Driver option parameters");
unsigned int nes_debug_level = 0;
module_param_named(debug_level, nes_debug_level, uint, 0644);
MODULE_PARM_DESC(debug_level, "Enable debug output level");
unsigned int wqm_quanta = 0x10000;
module_param(wqm_quanta, int, 0644);
MODULE_PARM_DESC(wqm_quanta, "WQM quanta");
static bool limit_maxrdreqsz;
module_param(limit_maxrdreqsz, bool, 0644);
MODULE_PARM_DESC(limit_maxrdreqsz, "Limit max read request size to 256 Bytes");
LIST_HEAD(nes_adapter_list);
static LIST_HEAD(nes_dev_list);
atomic_t qps_destroyed;
static unsigned int ee_flsh_adapter;
static unsigned int sysfs_nonidx_addr;
static unsigned int sysfs_idx_addr;
static const struct pci_device_id nes_pci_table[] = {
{ PCI_VDEVICE(NETEFFECT, PCI_DEVICE_ID_NETEFFECT_NE020), },
{ PCI_VDEVICE(NETEFFECT, PCI_DEVICE_ID_NETEFFECT_NE020_KR), },
{0}
};
MODULE_DEVICE_TABLE(pci, nes_pci_table);
static int nes_inetaddr_event(struct notifier_block *, unsigned long, void *);
static int nes_net_event(struct notifier_block *, unsigned long, void *);
static int nes_notifiers_registered;
static struct notifier_block nes_inetaddr_notifier = {
.notifier_call = nes_inetaddr_event
};
static struct notifier_block nes_net_notifier = {
.notifier_call = nes_net_event
};
/**
* nes_inetaddr_event
*/
static int nes_inetaddr_event(struct notifier_block *notifier,
unsigned long event, void *ptr)
{
struct in_ifaddr *ifa = ptr;
struct net_device *event_netdev = ifa->ifa_dev->dev;
struct nes_device *nesdev;
struct net_device *netdev;
struct net_device *upper_dev;
struct nes_vnic *nesvnic;
unsigned int is_bonded;
nes_debug(NES_DBG_NETDEV, "nes_inetaddr_event: ip address %pI4, netmask %pI4.\n",
&ifa->ifa_address, &ifa->ifa_mask);
list_for_each_entry(nesdev, &nes_dev_list, list) {
nes_debug(NES_DBG_NETDEV, "Nesdev list entry = 0x%p. (%s)\n",
nesdev, nesdev->netdev[0]->name);
netdev = nesdev->netdev[0];
nesvnic = netdev_priv(netdev);
upper_dev = netdev_master_upper_dev_get(netdev);
is_bonded = netif_is_bond_slave(netdev) &&
(upper_dev == event_netdev);
if ((netdev == event_netdev) || is_bonded) {
if (nesvnic->rdma_enabled == 0) {
nes_debug(NES_DBG_NETDEV, "Returning without processing event for %s since"
" RDMA is not enabled.\n",
netdev->name);
return NOTIFY_OK;
}
/* we have ifa->ifa_address/mask here if we need it */
switch (event) {
case NETDEV_DOWN:
nes_debug(NES_DBG_NETDEV, "event:DOWN\n");
nes_write_indexed(nesdev,
NES_IDX_DST_IP_ADDR+(0x10*PCI_FUNC(nesdev->pcidev->devfn)), 0);
nes_manage_arp_cache(netdev, netdev->dev_addr,
ntohl(nesvnic->local_ipaddr), NES_ARP_DELETE);
nesvnic->local_ipaddr = 0;
if (is_bonded)
continue;
else
return NOTIFY_OK;
break;
case NETDEV_UP:
nes_debug(NES_DBG_NETDEV, "event:UP\n");
if (nesvnic->local_ipaddr != 0) {
nes_debug(NES_DBG_NETDEV, "Interface already has local_ipaddr\n");
return NOTIFY_OK;
}
/* fall through */
case NETDEV_CHANGEADDR:
/* Add the address to the IP table */
if (upper_dev) {
struct in_device *in;
rcu_read_lock();
in = __in_dev_get_rcu(upper_dev);
nesvnic->local_ipaddr = in->ifa_list->ifa_address;
rcu_read_unlock();
} else {
nesvnic->local_ipaddr = ifa->ifa_address;
}
nes_write_indexed(nesdev,
NES_IDX_DST_IP_ADDR+(0x10*PCI_FUNC(nesdev->pcidev->devfn)),
ntohl(nesvnic->local_ipaddr));
nes_manage_arp_cache(netdev, netdev->dev_addr,
ntohl(nesvnic->local_ipaddr), NES_ARP_ADD);
if (is_bonded)
continue;
else
return NOTIFY_OK;
break;
default:
break;
}
}
}
return NOTIFY_DONE;
}
/**
* nes_net_event
*/
static int nes_net_event(struct notifier_block *notifier,
unsigned long event, void *ptr)
{
struct neighbour *neigh = ptr;
struct nes_device *nesdev;
struct net_device *netdev;
struct nes_vnic *nesvnic;
switch (event) {
case NETEVENT_NEIGH_UPDATE:
list_for_each_entry(nesdev, &nes_dev_list, list) {
/* nes_debug(NES_DBG_NETDEV, "Nesdev list entry = 0x%p.\n", nesdev); */
netdev = nesdev->netdev[0];
nesvnic = netdev_priv(netdev);
if (netdev == neigh->dev) {
if (nesvnic->rdma_enabled == 0) {
nes_debug(NES_DBG_NETDEV, "Skipping device %s since no RDMA\n",
netdev->name);
} else {
if (neigh->nud_state & NUD_VALID) {
nes_manage_arp_cache(neigh->dev, neigh->ha,
ntohl(*(__be32 *)neigh->primary_key), NES_ARP_ADD);
} else {
nes_manage_arp_cache(neigh->dev, neigh->ha,
ntohl(*(__be32 *)neigh->primary_key), NES_ARP_DELETE);
}
}
return NOTIFY_OK;
}
}
break;
default:
nes_debug(NES_DBG_NETDEV, "NETEVENT_ %lu undefined\n", event);
break;
}
return NOTIFY_DONE;
}
/**
* nes_add_ref
*/
void nes_add_ref(struct ib_qp *ibqp)
{
struct nes_qp *nesqp;
nesqp = to_nesqp(ibqp);
nes_debug(NES_DBG_QP, "Bumping refcount for QP%u. Pre-inc value = %u\n",
ibqp->qp_num, atomic_read(&nesqp->refcount));
atomic_inc(&nesqp->refcount);
}
static void nes_cqp_rem_ref_callback(struct nes_device *nesdev, struct nes_cqp_request *cqp_request)
{
unsigned long flags;
struct nes_qp *nesqp = cqp_request->cqp_callback_pointer;
struct nes_adapter *nesadapter = nesdev->nesadapter;
atomic_inc(&qps_destroyed);
/* Free the control structures */
if (nesqp->pbl_vbase) {
pci_free_consistent(nesdev->pcidev, nesqp->qp_mem_size,
nesqp->hwqp.q2_vbase, nesqp->hwqp.q2_pbase);
spin_lock_irqsave(&nesadapter->pbl_lock, flags);
nesadapter->free_256pbl++;
spin_unlock_irqrestore(&nesadapter->pbl_lock, flags);
pci_free_consistent(nesdev->pcidev, 256, nesqp->pbl_vbase, nesqp->pbl_pbase);
nesqp->pbl_vbase = NULL;
} else {
pci_free_consistent(nesdev->pcidev, nesqp->qp_mem_size,
nesqp->hwqp.sq_vbase, nesqp->hwqp.sq_pbase);
}
nes_free_resource(nesadapter, nesadapter->allocated_qps, nesqp->hwqp.qp_id);
nesadapter->qp_table[nesqp->hwqp.qp_id-NES_FIRST_QPN] = NULL;
kfree(nesqp->allocated_buffer);
}
/**
* nes_rem_ref
*/
void nes_rem_ref(struct ib_qp *ibqp)
{
u64 u64temp;
struct nes_qp *nesqp;
struct nes_vnic *nesvnic = to_nesvnic(ibqp->device);
struct nes_device *nesdev = nesvnic->nesdev;
struct nes_hw_cqp_wqe *cqp_wqe;
struct nes_cqp_request *cqp_request;
u32 opcode;
nesqp = to_nesqp(ibqp);
if (atomic_read(&nesqp->refcount) == 0) {
printk(KERN_INFO PFX "%s: Reference count already 0 for QP%d, last aeq = 0x%04X.\n",
__func__, ibqp->qp_num, nesqp->last_aeq);
BUG();
}
if (atomic_dec_and_test(&nesqp->refcount)) {
if (nesqp->pau_mode)
nes_destroy_pau_qp(nesdev, nesqp);
/* Destroy the QP */
cqp_request = nes_get_cqp_request(nesdev);
if (cqp_request == NULL) {
nes_debug(NES_DBG_QP, "Failed to get a cqp_request.\n");
return;
}
cqp_request->waiting = 0;
cqp_request->callback = 1;
cqp_request->cqp_callback = nes_cqp_rem_ref_callback;
cqp_request->cqp_callback_pointer = nesqp;
cqp_wqe = &cqp_request->cqp_wqe;
nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
opcode = NES_CQP_DESTROY_QP | NES_CQP_QP_TYPE_IWARP;
if (nesqp->hte_added) {
opcode |= NES_CQP_QP_DEL_HTE;
nesqp->hte_added = 0;
}
set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX, opcode);
set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_ID_IDX, nesqp->hwqp.qp_id);
u64temp = (u64)nesqp->nesqp_context_pbase;
set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_QP_WQE_CONTEXT_LOW_IDX, u64temp);
nes_post_cqp_request(nesdev, cqp_request);
}
}
/**
* nes_get_qp
*/
struct ib_qp *nes_get_qp(struct ib_device *device, int qpn)
{
struct nes_vnic *nesvnic = to_nesvnic(device);
struct nes_device *nesdev = nesvnic->nesdev;
struct nes_adapter *nesadapter = nesdev->nesadapter;
if ((qpn < NES_FIRST_QPN) || (qpn >= (NES_FIRST_QPN + nesadapter->max_qp)))
return NULL;
return &nesadapter->qp_table[qpn - NES_FIRST_QPN]->ibqp;
}
/**
* nes_print_macaddr
*/
static void nes_print_macaddr(struct net_device *netdev)
{
nes_debug(NES_DBG_INIT, "%s: %pM, IRQ %u\n",
netdev->name, netdev->dev_addr, netdev->irq);
}
/**
* nes_interrupt - handle interrupts
*/
static irqreturn_t nes_interrupt(int irq, void *dev_id)
{
struct nes_device *nesdev = (struct nes_device *)dev_id;
int handled = 0;
u32 int_mask;
u32 int_req;
u32 int_stat;
u32 intf_int_stat;
u32 timer_stat;
if (nesdev->msi_enabled) {
/* No need to read the interrupt pending register if msi is enabled */
handled = 1;
} else {
if (unlikely(nesdev->nesadapter->hw_rev == NE020_REV)) {
/* Master interrupt enable provides synchronization for kicking off bottom half
when interrupt sharing is going on */
int_mask = nes_read32(nesdev->regs + NES_INT_MASK);
if (int_mask & 0x80000000) {
/* Check interrupt status to see if this might be ours */
int_stat = nes_read32(nesdev->regs + NES_INT_STAT);
int_req = nesdev->int_req;
if (int_stat&int_req) {
/* if interesting CEQ or AEQ is pending, claim the interrupt */
if ((int_stat&int_req) & (~(NES_INT_TIMER|NES_INT_INTF))) {
handled = 1;
} else {
if (((int_stat & int_req) & NES_INT_TIMER) == NES_INT_TIMER) {
/* Timer might be running but might be for another function */
timer_stat = nes_read32(nesdev->regs + NES_TIMER_STAT);
if ((timer_stat & nesdev->timer_int_req) != 0) {
handled = 1;
}
}
if ((((int_stat & int_req) & NES_INT_INTF) == NES_INT_INTF) &&
(handled == 0)) {
intf_int_stat = nes_read32(nesdev->regs+NES_INTF_INT_STAT);
if ((intf_int_stat & nesdev->intf_int_req) != 0) {
handled = 1;
}
}
}
if (handled) {
nes_write32(nesdev->regs+NES_INT_MASK, int_mask & (~0x80000000));
int_mask = nes_read32(nesdev->regs+NES_INT_MASK);
/* Save off the status to save an additional read */
nesdev->int_stat = int_stat;
nesdev->napi_isr_ran = 1;
}
}
}
} else {
handled = nes_read32(nesdev->regs+NES_INT_PENDING);
}
}
if (handled) {
if (nes_napi_isr(nesdev) == 0) {
tasklet_schedule(&nesdev->dpc_tasklet);
}
return IRQ_HANDLED;
} else {
return IRQ_NONE;
}
}
/**
* nes_probe - Device initialization
*/
static int nes_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
{
struct net_device *netdev = NULL;
struct nes_device *nesdev = NULL;
int ret = 0;
void __iomem *mmio_regs = NULL;
u8 hw_rev;
printk(KERN_INFO PFX "NetEffect RNIC driver v%s loading. (%s)\n",
DRV_VERSION, pci_name(pcidev));
ret = pci_enable_device(pcidev);
if (ret) {
printk(KERN_ERR PFX "Unable to enable PCI device. (%s)\n", pci_name(pcidev));
goto bail0;
}
nes_debug(NES_DBG_INIT, "BAR0 (@0x%08lX) size = 0x%lX bytes\n",
(long unsigned int)pci_resource_start(pcidev, BAR_0),
(long unsigned int)pci_resource_len(pcidev, BAR_0));
nes_debug(NES_DBG_INIT, "BAR1 (@0x%08lX) size = 0x%lX bytes\n",
(long unsigned int)pci_resource_start(pcidev, BAR_1),
(long unsigned int)pci_resource_len(pcidev, BAR_1));
/* Make sure PCI base addr are MMIO */
if (!(pci_resource_flags(pcidev, BAR_0) & IORESOURCE_MEM) ||
!(pci_resource_flags(pcidev, BAR_1) & IORESOURCE_MEM)) {
printk(KERN_ERR PFX "PCI regions not an MMIO resource\n");
ret = -ENODEV;
goto bail1;
}
/* Reserve PCI I/O and memory resources */
ret = pci_request_regions(pcidev, DRV_NAME);
if (ret) {
printk(KERN_ERR PFX "Unable to request regions. (%s)\n", pci_name(pcidev));
goto bail1;
}
if ((sizeof(dma_addr_t) > 4)) {
ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(64));
if (ret < 0) {
printk(KERN_ERR PFX "64b DMA mask configuration failed\n");
goto bail2;
}
ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64));
if (ret) {
printk(KERN_ERR PFX "64b DMA consistent mask configuration failed\n");
goto bail2;
}
} else {
ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
if (ret < 0) {
printk(KERN_ERR PFX "32b DMA mask configuration failed\n");
goto bail2;
}
ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
if (ret) {
printk(KERN_ERR PFX "32b DMA consistent mask configuration failed\n");
goto bail2;
}
}
pci_set_master(pcidev);
/* Allocate hardware structure */
nesdev = kzalloc(sizeof(struct nes_device), GFP_KERNEL);
if (!nesdev) {
ret = -ENOMEM;
goto bail2;
}
nes_debug(NES_DBG_INIT, "Allocated nes device at %p\n", nesdev);
nesdev->pcidev = pcidev;
pci_set_drvdata(pcidev, nesdev);
pci_read_config_byte(pcidev, 0x0008, &hw_rev);
nes_debug(NES_DBG_INIT, "hw_rev=%u\n", hw_rev);
spin_lock_init(&nesdev->indexed_regs_lock);
/* Remap the PCI registers in adapter BAR0 to kernel VA space */
mmio_regs = ioremap_nocache(pci_resource_start(pcidev, BAR_0),
pci_resource_len(pcidev, BAR_0));
if (mmio_regs == NULL) {
printk(KERN_ERR PFX "Unable to remap BAR0\n");
ret = -EIO;
goto bail3;
}
nesdev->regs = mmio_regs;
nesdev->index_reg = 0x50 + (PCI_FUNC(pcidev->devfn)*8) + mmio_regs;
/* Ensure interrupts are disabled */
nes_write32(nesdev->regs+NES_INT_MASK, 0x7fffffff);
if (nes_drv_opt & NES_DRV_OPT_ENABLE_MSI) {
if (!pci_enable_msi(nesdev->pcidev)) {
nesdev->msi_enabled = 1;
nes_debug(NES_DBG_INIT, "MSI is enabled for device %s\n",
pci_name(pcidev));
} else {
nes_debug(NES_DBG_INIT, "MSI is disabled by linux for device %s\n",
pci_name(pcidev));
}
} else {
nes_debug(NES_DBG_INIT, "MSI not requested due to driver options for device %s\n",
pci_name(pcidev));
}
nesdev->csr_start = pci_resource_start(nesdev->pcidev, BAR_0);
nesdev->doorbell_region = pci_resource_start(nesdev->pcidev, BAR_1);
/* Init the adapter */
nesdev->nesadapter = nes_init_adapter(nesdev, hw_rev);
if (!nesdev->nesadapter) {
printk(KERN_ERR PFX "Unable to initialize adapter.\n");
ret = -ENOMEM;
goto bail5;
}
nesdev->nesadapter->et_rx_coalesce_usecs_irq = interrupt_mod_interval;
nesdev->nesadapter->wqm_quanta = wqm_quanta;
/* nesdev->base_doorbell_index =
nesdev->nesadapter->pd_config_base[PCI_FUNC(nesdev->pcidev->devfn)]; */
nesdev->base_doorbell_index = 1;
nesdev->doorbell_start = nesdev->nesadapter->doorbell_start;
if (nesdev->nesadapter->phy_type[0] == NES_PHY_TYPE_PUMA_1G) {
switch (PCI_FUNC(nesdev->pcidev->devfn) %
nesdev->nesadapter->port_count) {
case 1:
nesdev->mac_index = 2;
break;
case 2:
nesdev->mac_index = 1;
break;
case 3:
nesdev->mac_index = 3;
break;
case 0:
default:
nesdev->mac_index = 0;
}
} else {
nesdev->mac_index = PCI_FUNC(nesdev->pcidev->devfn) %
nesdev->nesadapter->port_count;
}
if ((limit_maxrdreqsz ||
((nesdev->nesadapter->phy_type[0] == NES_PHY_TYPE_GLADIUS) &&
(hw_rev == NE020_REV1))) &&
(pcie_get_readrq(pcidev) > 256)) {
if (pcie_set_readrq(pcidev, 256))
printk(KERN_ERR PFX "Unable to set max read request"
" to 256 bytes\n");
else
nes_debug(NES_DBG_INIT, "Max read request size set"
" to 256 bytes\n");
}
tasklet_init(&nesdev->dpc_tasklet, nes_dpc, (unsigned long)nesdev);
/* bring up the Control QP */
if (nes_init_cqp(nesdev)) {
ret = -ENODEV;
goto bail6;
}
/* Arm the CCQ */
nes_write32(nesdev->regs+NES_CQE_ALLOC, NES_CQE_ALLOC_NOTIFY_NEXT |
PCI_FUNC(nesdev->pcidev->devfn));
nes_read32(nesdev->regs+NES_CQE_ALLOC);
/* Enable the interrupts */
nesdev->int_req = (0x101 << PCI_FUNC(nesdev->pcidev->devfn)) |
(1 << (PCI_FUNC(nesdev->pcidev->devfn)+16));
if (PCI_FUNC(nesdev->pcidev->devfn) < 4) {
nesdev->int_req |= (1 << (PCI_FUNC(nesdev->mac_index)+24));
}
/* TODO: This really should be the first driver to load, not function 0 */
if (PCI_FUNC(nesdev->pcidev->devfn) == 0) {
/* pick up PCI and critical errors if the first driver to load */
nesdev->intf_int_req = NES_INTF_INT_PCIERR | NES_INTF_INT_CRITERR;
nesdev->int_req |= NES_INT_INTF;
} else {
nesdev->intf_int_req = 0;
}
nesdev->intf_int_req |= (1 << (PCI_FUNC(nesdev->pcidev->devfn)+16));
nes_write_indexed(nesdev, NES_IDX_DEBUG_ERROR_MASKS0, 0);
nes_write_indexed(nesdev, NES_IDX_DEBUG_ERROR_MASKS1, 0);
nes_write_indexed(nesdev, NES_IDX_DEBUG_ERROR_MASKS2, 0x00001265);
nes_write_indexed(nesdev, NES_IDX_DEBUG_ERROR_MASKS4, 0x18021804);
nes_write_indexed(nesdev, NES_IDX_DEBUG_ERROR_MASKS3, 0x17801790);
/* deal with both periodic and one_shot */
nesdev->timer_int_req = 0x101 << PCI_FUNC(nesdev->pcidev->devfn);
nesdev->nesadapter->timer_int_req |= nesdev->timer_int_req;
nes_debug(NES_DBG_INIT, "setting int_req for function %u, nesdev = 0x%04X, adapter = 0x%04X\n",
PCI_FUNC(nesdev->pcidev->devfn),
nesdev->timer_int_req, nesdev->nesadapter->timer_int_req);
nes_write32(nesdev->regs+NES_INTF_INT_MASK, ~(nesdev->intf_int_req));
list_add_tail(&nesdev->list, &nes_dev_list);
/* Request an interrupt line for the driver */
ret = request_irq(pcidev->irq, nes_interrupt, IRQF_SHARED, DRV_NAME, nesdev);
if (ret) {
printk(KERN_ERR PFX "%s: requested IRQ %u is busy\n",
pci_name(pcidev), pcidev->irq);
goto bail65;
}
nes_write32(nesdev->regs+NES_INT_MASK, ~nesdev->int_req);
if (nes_notifiers_registered == 0) {
register_inetaddr_notifier(&nes_inetaddr_notifier);
register_netevent_notifier(&nes_net_notifier);
}
nes_notifiers_registered++;
INIT_DELAYED_WORK(&nesdev->work, nes_recheck_link_status);
/* Initialize network devices */
netdev = nes_netdev_init(nesdev, mmio_regs);
if (netdev == NULL) {
ret = -ENOMEM;
goto bail7;
}
/* Register network device */
ret = register_netdev(netdev);
if (ret) {
printk(KERN_ERR PFX "Unable to register netdev, ret = %d\n", ret);
nes_netdev_destroy(netdev);
goto bail7;
}
nes_print_macaddr(netdev);
nesdev->netdev_count++;
nesdev->nesadapter->netdev_count++;
printk(KERN_INFO PFX "%s: NetEffect RNIC driver successfully loaded.\n",
pci_name(pcidev));
return 0;
bail7:
printk(KERN_ERR PFX "bail7\n");
while (nesdev->netdev_count > 0) {
nesdev->netdev_count--;
nesdev->nesadapter->netdev_count--;
unregister_netdev(nesdev->netdev[nesdev->netdev_count]);
nes_netdev_destroy(nesdev->netdev[nesdev->netdev_count]);
}
nes_debug(NES_DBG_INIT, "netdev_count=%d, nesadapter->netdev_count=%d\n",
nesdev->netdev_count, nesdev->nesadapter->netdev_count);
nes_notifiers_registered--;
if (nes_notifiers_registered == 0) {
unregister_netevent_notifier(&nes_net_notifier);
unregister_inetaddr_notifier(&nes_inetaddr_notifier);
}
list_del(&nesdev->list);
nes_destroy_cqp(nesdev);
bail65:
printk(KERN_ERR PFX "bail65\n");
free_irq(pcidev->irq, nesdev);
if (nesdev->msi_enabled) {
pci_disable_msi(pcidev);
}
bail6:
printk(KERN_ERR PFX "bail6\n");
tasklet_kill(&nesdev->dpc_tasklet);
/* Deallocate the Adapter Structure */
nes_destroy_adapter(nesdev->nesadapter);
bail5:
printk(KERN_ERR PFX "bail5\n");
iounmap(nesdev->regs);
bail3:
printk(KERN_ERR PFX "bail3\n");
kfree(nesdev);
bail2:
pci_release_regions(pcidev);
bail1:
pci_disable_device(pcidev);
bail0:
return ret;
}
/**
* nes_remove - unload from kernel
*/
static void nes_remove(struct pci_dev *pcidev)
{
struct nes_device *nesdev = pci_get_drvdata(pcidev);
struct net_device *netdev;
int netdev_index = 0;
unsigned long flags;
if (nesdev->netdev_count) {
netdev = nesdev->netdev[netdev_index];
if (netdev) {
netif_stop_queue(netdev);
unregister_netdev(netdev);
nes_netdev_destroy(netdev);
nesdev->netdev[netdev_index] = NULL;
nesdev->netdev_count--;
nesdev->nesadapter->netdev_count--;
}
}
nes_notifiers_registered--;
if (nes_notifiers_registered == 0) {
unregister_netevent_notifier(&nes_net_notifier);
unregister_inetaddr_notifier(&nes_inetaddr_notifier);
}
list_del(&nesdev->list);
nes_destroy_cqp(nesdev);
free_irq(pcidev->irq, nesdev);
tasklet_kill(&nesdev->dpc_tasklet);
spin_lock_irqsave(&nesdev->nesadapter->phy_lock, flags);
if (nesdev->link_recheck) {
spin_unlock_irqrestore(&nesdev->nesadapter->phy_lock, flags);
cancel_delayed_work_sync(&nesdev->work);
} else {
spin_unlock_irqrestore(&nesdev->nesadapter->phy_lock, flags);
}
/* Deallocate the Adapter Structure */
nes_destroy_adapter(nesdev->nesadapter);
if (nesdev->msi_enabled) {
pci_disable_msi(pcidev);
}
iounmap(nesdev->regs);
kfree(nesdev);
/* nes_debug(NES_DBG_SHUTDOWN, "calling pci_release_regions.\n"); */
pci_release_regions(pcidev);
pci_disable_device(pcidev);
pci_set_drvdata(pcidev, NULL);
}
static ssize_t adapter_show(struct device_driver *ddp, char *buf)
{
unsigned int devfn = 0xffffffff;
unsigned char bus_number = 0xff;
unsigned int i = 0;
struct nes_device *nesdev;
list_for_each_entry(nesdev, &nes_dev_list, list) {
if (i == ee_flsh_adapter) {
devfn = nesdev->pcidev->devfn;
bus_number = nesdev->pcidev->bus->number;
break;
}
i++;
}
return snprintf(buf, PAGE_SIZE, "%x:%x\n", bus_number, devfn);
}
static ssize_t adapter_store(struct device_driver *ddp,
const char *buf, size_t count)
{
char *p = (char *)buf;
ee_flsh_adapter = simple_strtoul(p, &p, 10);
return strnlen(buf, count);
}
static ssize_t eeprom_cmd_show(struct device_driver *ddp, char *buf)
{
u32 eeprom_cmd = 0xdead;
u32 i = 0;
struct nes_device *nesdev;
list_for_each_entry(nesdev, &nes_dev_list, list) {
if (i == ee_flsh_adapter) {
eeprom_cmd = nes_read32(nesdev->regs + NES_EEPROM_COMMAND);
break;
}
i++;
}
return snprintf(buf, PAGE_SIZE, "0x%x\n", eeprom_cmd);
}
static ssize_t eeprom_cmd_store(struct device_driver *ddp,
const char *buf, size_t count)
{
char *p = (char *)buf;
u32 val;
u32 i = 0;
struct nes_device *nesdev;
if (p[1] == 'x' || p[1] == 'X' || p[0] == 'x' || p[0] == 'X') {
val = simple_strtoul(p, &p, 16);
list_for_each_entry(nesdev, &nes_dev_list, list) {
if (i == ee_flsh_adapter) {
nes_write32(nesdev->regs + NES_EEPROM_COMMAND, val);
break;
}
i++;
}
}
return strnlen(buf, count);
}
static ssize_t eeprom_data_show(struct device_driver *ddp, char *buf)
{
u32 eeprom_data = 0xdead;
u32 i = 0;
struct nes_device *nesdev;
list_for_each_entry(nesdev, &nes_dev_list, list) {
if (i == ee_flsh_adapter) {
eeprom_data = nes_read32(nesdev->regs + NES_EEPROM_DATA);
break;
}
i++;
}
return snprintf(buf, PAGE_SIZE, "0x%x\n", eeprom_data);
}
static ssize_t eeprom_data_store(struct device_driver *ddp,
const char *buf, size_t count)
{
char *p = (char *)buf;
u32 val;
u32 i = 0;
struct nes_device *nesdev;
if (p[1] == 'x' || p[1] == 'X' || p[0] == 'x' || p[0] == 'X') {
val = simple_strtoul(p, &p, 16);
list_for_each_entry(nesdev, &nes_dev_list, list) {
if (i == ee_flsh_adapter) {
nes_write32(nesdev->regs + NES_EEPROM_DATA, val);
break;
}
i++;
}
}
return strnlen(buf, count);
}
static ssize_t flash_cmd_show(struct device_driver *ddp, char *buf)
{
u32 flash_cmd = 0xdead;
u32 i = 0;
struct nes_device *nesdev;
list_for_each_entry(nesdev, &nes_dev_list, list) {
if (i == ee_flsh_adapter) {
flash_cmd = nes_read32(nesdev->regs + NES_FLASH_COMMAND);
break;
}
i++;
}
return snprintf(buf, PAGE_SIZE, "0x%x\n", flash_cmd);
}
static ssize_t flash_cmd_store(struct device_driver *ddp,
const char *buf, size_t count)
{
char *p = (char *)buf;
u32 val;
u32 i = 0;
struct nes_device *nesdev;
if (p[1] == 'x' || p[1] == 'X' || p[0] == 'x' || p[0] == 'X') {
val = simple_strtoul(p, &p, 16);
list_for_each_entry(nesdev, &nes_dev_list, list) {
if (i == ee_flsh_adapter) {
nes_write32(nesdev->regs + NES_FLASH_COMMAND, val);
break;
}
i++;
}
}
return strnlen(buf, count);
}
static ssize_t flash_data_show(struct device_driver *ddp, char *buf)
{
u32 flash_data = 0xdead;
u32 i = 0;
struct nes_device *nesdev;
list_for_each_entry(nesdev, &nes_dev_list, list) {
if (i == ee_flsh_adapter) {
flash_data = nes_read32(nesdev->regs + NES_FLASH_DATA);
break;
}
i++;
}
return snprintf(buf, PAGE_SIZE, "0x%x\n", flash_data);
}
static ssize_t flash_data_store(struct device_driver *ddp,
const char *buf, size_t count)
{
char *p = (char *)buf;
u32 val;
u32 i = 0;
struct nes_device *nesdev;
if (p[1] == 'x' || p[1] == 'X' || p[0] == 'x' || p[0] == 'X') {
val = simple_strtoul(p, &p, 16);
list_for_each_entry(nesdev, &nes_dev_list, list) {
if (i == ee_flsh_adapter) {
nes_write32(nesdev->regs + NES_FLASH_DATA, val);
break;
}
i++;
}
}
return strnlen(buf, count);
}
static ssize_t nonidx_addr_show(struct device_driver *ddp, char *buf)
{
return snprintf(buf, PAGE_SIZE, "0x%x\n", sysfs_nonidx_addr);
}
static ssize_t nonidx_addr_store(struct device_driver *ddp,
const char *buf, size_t count)
{
char *p = (char *)buf;
if (p[1] == 'x' || p[1] == 'X' || p[0] == 'x' || p[0] == 'X')
sysfs_nonidx_addr = simple_strtoul(p, &p, 16);
return strnlen(buf, count);
}
static ssize_t nonidx_data_show(struct device_driver *ddp, char *buf)
{
u32 nonidx_data = 0xdead;
u32 i = 0;
struct nes_device *nesdev;
list_for_each_entry(nesdev, &nes_dev_list, list) {
if (i == ee_flsh_adapter) {
nonidx_data = nes_read32(nesdev->regs + sysfs_nonidx_addr);
break;
}
i++;
}
return snprintf(buf, PAGE_SIZE, "0x%x\n", nonidx_data);
}
static ssize_t nonidx_data_store(struct device_driver *ddp,
const char *buf, size_t count)
{
char *p = (char *)buf;
u32 val;
u32 i = 0;
struct nes_device *nesdev;
if (p[1] == 'x' || p[1] == 'X' || p[0] == 'x' || p[0] == 'X') {
val = simple_strtoul(p, &p, 16);
list_for_each_entry(nesdev, &nes_dev_list, list) {
if (i == ee_flsh_adapter) {
nes_write32(nesdev->regs + sysfs_nonidx_addr, val);
break;
}
i++;
}
}
return strnlen(buf, count);
}
static ssize_t idx_addr_show(struct device_driver *ddp, char *buf)
{
return snprintf(buf, PAGE_SIZE, "0x%x\n", sysfs_idx_addr);
}
static ssize_t idx_addr_store(struct device_driver *ddp,
const char *buf, size_t count)
{
char *p = (char *)buf;
if (p[1] == 'x' || p[1] == 'X' || p[0] == 'x' || p[0] == 'X')
sysfs_idx_addr = simple_strtoul(p, &p, 16);
return strnlen(buf, count);
}
static ssize_t idx_data_show(struct device_driver *ddp, char *buf)
{
u32 idx_data = 0xdead;
u32 i = 0;
struct nes_device *nesdev;
list_for_each_entry(nesdev, &nes_dev_list, list) {
if (i == ee_flsh_adapter) {
idx_data = nes_read_indexed(nesdev, sysfs_idx_addr);
break;
}
i++;
}
return snprintf(buf, PAGE_SIZE, "0x%x\n", idx_data);
}
static ssize_t idx_data_store(struct device_driver *ddp,
const char *buf, size_t count)
{
char *p = (char *)buf;
u32 val;
u32 i = 0;
struct nes_device *nesdev;
if (p[1] == 'x' || p[1] == 'X' || p[0] == 'x' || p[0] == 'X') {
val = simple_strtoul(p, &p, 16);
list_for_each_entry(nesdev, &nes_dev_list, list) {
if (i == ee_flsh_adapter) {
nes_write_indexed(nesdev, sysfs_idx_addr, val);
break;
}
i++;
}
}
return strnlen(buf, count);
}
static ssize_t wqm_quanta_show(struct device_driver *ddp, char *buf)
{
u32 wqm_quanta_value = 0xdead;
u32 i = 0;
struct nes_device *nesdev;
list_for_each_entry(nesdev, &nes_dev_list, list) {
if (i == ee_flsh_adapter) {
wqm_quanta_value = nesdev->nesadapter->wqm_quanta;
break;
}
i++;
}
return snprintf(buf, PAGE_SIZE, "0x%X\n", wqm_quanta_value);
}
static ssize_t wqm_quanta_store(struct device_driver *ddp, const char *buf,
size_t count)
{
unsigned long wqm_quanta_value;
u32 wqm_config1;
u32 i = 0;
struct nes_device *nesdev;
if (kstrtoul(buf, 0, &wqm_quanta_value) < 0)
return -EINVAL;
list_for_each_entry(nesdev, &nes_dev_list, list) {
if (i == ee_flsh_adapter) {
nesdev->nesadapter->wqm_quanta = wqm_quanta_value;
wqm_config1 = nes_read_indexed(nesdev,
NES_IDX_WQM_CONFIG1);
nes_write_indexed(nesdev, NES_IDX_WQM_CONFIG1,
((wqm_quanta_value << 1) |
(wqm_config1 & 0x00000001)));
break;
}
i++;
}
return strnlen(buf, count);
}
static DRIVER_ATTR_RW(adapter);
static DRIVER_ATTR_RW(eeprom_cmd);
static DRIVER_ATTR_RW(eeprom_data);
static DRIVER_ATTR_RW(flash_cmd);
static DRIVER_ATTR_RW(flash_data);
static DRIVER_ATTR_RW(nonidx_addr);
static DRIVER_ATTR_RW(nonidx_data);
static DRIVER_ATTR_RW(idx_addr);
static DRIVER_ATTR_RW(idx_data);
static DRIVER_ATTR_RW(wqm_quanta);
static struct attribute *nes_attrs[] = {
&driver_attr_adapter.attr,
&driver_attr_eeprom_cmd.attr,
&driver_attr_eeprom_data.attr,
&driver_attr_flash_cmd.attr,
&driver_attr_flash_data.attr,
&driver_attr_nonidx_addr.attr,
&driver_attr_nonidx_data.attr,
&driver_attr_idx_addr.attr,
&driver_attr_idx_data.attr,
&driver_attr_wqm_quanta.attr,
NULL,
};
ATTRIBUTE_GROUPS(nes);
static struct pci_driver nes_pci_driver = {
.name = DRV_NAME,
.id_table = nes_pci_table,
.probe = nes_probe,
.remove = nes_remove,
.groups = nes_groups,
};
/**
* nes_init_module - module initialization entry point
*/
static int __init nes_init_module(void)
{
int retval;
retval = nes_cm_start();
if (retval) {
printk(KERN_ERR PFX "Unable to start NetEffect iWARP CM.\n");
return retval;
}
return pci_register_driver(&nes_pci_driver);
}
/**
* nes_exit_module - module unload entry point
*/
static void __exit nes_exit_module(void)
{
nes_cm_stop();
pci_unregister_driver(&nes_pci_driver);
}
module_init(nes_init_module);
module_exit(nes_exit_module);
drivers/infiniband/hw/nes/nes.h deleted 100644 → 0
View file @ cbdc666f
/*
* Copyright (c) 2006 - 2011 Intel Corporation. All rights reserved.
* Copyright (c) 2005 Open Grid Computing, Inc. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef __NES_H
#define __NES_H
#include <linux/netdevice.h>
#include <linux/inetdevice.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/workqueue.h>
#include <linux/slab.h>
#include <asm/io.h>
#include <linux/crc32c.h>
#include <rdma/ib_smi.h>
#include <rdma/ib_verbs.h>
#include <rdma/ib_pack.h>
#include <rdma/rdma_cm.h>
#include <rdma/iw_cm.h>
#include <rdma/rdma_netlink.h>
#include <rdma/iw_portmap.h>
#define NES_SEND_FIRST_WRITE
#define QUEUE_DISCONNECTS
#define DRV_NAME "iw_nes"
#define DRV_VERSION "1.5.0.1"
#define PFX DRV_NAME ": "
/*
* NetEffect PCI vendor id and NE010 PCI device id.
*/
#ifndef PCI_VENDOR_ID_NETEFFECT /* not in pci.ids yet */
#define PCI_VENDOR_ID_NETEFFECT 0x1678
#define PCI_DEVICE_ID_NETEFFECT_NE020 0x0100
#define PCI_DEVICE_ID_NETEFFECT_NE020_KR 0x0110
#endif
#define NE020_REV 4
#define NE020_REV1 5
#define BAR_0 0
#define BAR_1 2
#define RX_BUF_SIZE (1536 + 8)
#define NES_REG0_SIZE (4 * 1024)
#define NES_TX_TIMEOUT (6*HZ)
#define NES_FIRST_QPN 64
#define NES_SW_CONTEXT_ALIGN 1024
#define NES_MAX_MTU 9000
#define NES_NIC_MAX_NICS 16
#define NES_MAX_ARP_TABLE_SIZE 4096
#define NES_NIC_CEQ_SIZE 8
/* NICs will be on a separate CQ */
#define NES_CCEQ_SIZE ((nesadapter->max_cq / nesadapter->port_count) - 32)
#define NES_MAX_PORT_COUNT 4
#define MAX_DPC_ITERATIONS 128
#define NES_DRV_OPT_ENABLE_MPA_VER_0 0x00000001
#define NES_DRV_OPT_DISABLE_MPA_CRC 0x00000002
#define NES_DRV_OPT_DISABLE_FIRST_WRITE 0x00000004
#define NES_DRV_OPT_DISABLE_INTF 0x00000008
#define NES_DRV_OPT_ENABLE_MSI 0x00000010
#define NES_DRV_OPT_DUAL_LOGICAL_PORT 0x00000020
#define NES_DRV_OPT_SUPRESS_OPTION_BC 0x00000040
#define NES_DRV_OPT_NO_INLINE_DATA 0x00000080
#define NES_DRV_OPT_DISABLE_INT_MOD 0x00000100
#define NES_DRV_OPT_DISABLE_VIRT_WQ 0x00000200
#define NES_DRV_OPT_ENABLE_PAU 0x00000400
#define NES_AEQ_EVENT_TIMEOUT 2500
#define NES_DISCONNECT_EVENT_TIMEOUT 2000
/* debug levels */
/* must match userspace */
#define NES_DBG_HW 0x00000001
#define NES_DBG_INIT 0x00000002
#define NES_DBG_ISR 0x00000004
#define NES_DBG_PHY 0x00000008
#define NES_DBG_NETDEV 0x00000010
#define NES_DBG_CM 0x00000020
#define NES_DBG_CM1 0x00000040
#define NES_DBG_NIC_RX 0x00000080
#define NES_DBG_NIC_TX 0x00000100
#define NES_DBG_CQP 0x00000200
#define NES_DBG_MMAP 0x00000400
#define NES_DBG_MR 0x00000800
#define NES_DBG_PD 0x00001000
#define NES_DBG_CQ 0x00002000
#define NES_DBG_QP 0x00004000
#define NES_DBG_MOD_QP 0x00008000
#define NES_DBG_AEQ 0x00010000
#define NES_DBG_IW_RX 0x00020000
#define NES_DBG_IW_TX 0x00040000
#define NES_DBG_SHUTDOWN 0x00080000
#define NES_DBG_PAU 0x00100000
#define NES_DBG_NLMSG 0x00200000
#define NES_DBG_RSVD1 0x10000000
#define NES_DBG_RSVD2 0x20000000
#define NES_DBG_RSVD3 0x40000000
#define NES_DBG_RSVD4 0x80000000
#define NES_DBG_ALL 0xffffffff
#ifdef CONFIG_INFINIBAND_NES_DEBUG
#define nes_debug(level, fmt, args...) \
do { \
if (level & nes_debug_level) \
printk(KERN_ERR PFX "%s[%u]: " fmt, __func__, __LINE__, ##args); \
} while (0)
#define NES_EVENT_TIMEOUT 1200000
#else
#define nes_debug(level, fmt, args...) no_printk(fmt, ##args)
#define NES_EVENT_TIMEOUT 100000
#endif
#include "nes_hw.h"
#include "nes_verbs.h"
#include "nes_context.h"
#include <rdma/nes-abi.h>
#include "nes_cm.h"
#include "nes_mgt.h"
extern int interrupt_mod_interval;
extern int nes_if_count;
extern int mpa_version;
extern int disable_mpa_crc;
extern unsigned int nes_drv_opt;
extern unsigned int nes_debug_level;
extern unsigned int wqm_quanta;
extern struct list_head nes_adapter_list;
extern atomic_t cm_connects;
extern atomic_t cm_accepts;
extern atomic_t cm_disconnects;
extern atomic_t cm_closes;
extern atomic_t cm_connecteds;
extern atomic_t cm_connect_reqs;
extern atomic_t cm_rejects;
extern atomic_t mod_qp_timouts;
extern atomic_t qps_created;
extern atomic_t qps_destroyed;
extern atomic_t sw_qps_destroyed;
extern u32 mh_detected;
extern u32 mh_pauses_sent;
extern u32 cm_packets_sent;
extern u32 cm_packets_bounced;
extern u32 cm_packets_created;
extern u32 cm_packets_received;
extern u32 cm_packets_dropped;
extern u32 cm_packets_retrans;
extern atomic_t cm_listens_created;
extern atomic_t cm_listens_destroyed;
extern u32 cm_backlog_drops;
extern atomic_t cm_loopbacks;
extern atomic_t cm_nodes_created;
extern atomic_t cm_nodes_destroyed;
extern atomic_t cm_accel_dropped_pkts;
extern atomic_t cm_resets_recvd;
extern atomic_t pau_qps_created;
extern atomic_t pau_qps_destroyed;
extern u32 int_mod_timer_init;
extern u32 int_mod_cq_depth_256;
extern u32 int_mod_cq_depth_128;
extern u32 int_mod_cq_depth_32;
extern u32 int_mod_cq_depth_24;
extern u32 int_mod_cq_depth_16;
extern u32 int_mod_cq_depth_4;
extern u32 int_mod_cq_depth_1;
struct nes_device {
struct nes_adapter *nesadapter;
void __iomem *regs;
void __iomem *index_reg;
struct pci_dev *pcidev;
struct net_device *netdev[NES_NIC_MAX_NICS];
u64 link_status_interrupts;
struct tasklet_struct dpc_tasklet;
spinlock_t indexed_regs_lock;
unsigned long csr_start;
unsigned long doorbell_region;
unsigned long doorbell_start;
unsigned long mac_tx_errors;
unsigned long mac_pause_frames_sent;
unsigned long mac_pause_frames_received;
unsigned long mac_rx_errors;
unsigned long mac_rx_crc_errors;
unsigned long mac_rx_symbol_err_frames;
unsigned long mac_rx_jabber_frames;
unsigned long mac_rx_oversized_frames;
unsigned long mac_rx_short_frames;
unsigned long port_rx_discards;
unsigned long port_tx_discards;
unsigned int mac_index;
unsigned int nes_stack_start;
/* Control Structures */
void *cqp_vbase;
dma_addr_t cqp_pbase;
u32 cqp_mem_size;
u8 ceq_index;
u8 nic_ceq_index;
struct nes_hw_cqp cqp;
struct nes_hw_cq ccq;
struct list_head cqp_avail_reqs;
struct list_head cqp_pending_reqs;
struct nes_cqp_request *nes_cqp_requests;
u32 int_req;
u32 int_stat;
u32 timer_int_req;
u32 timer_only_int_count;
u32 intf_int_req;
u32 last_mac_tx_pauses;
u32 last_used_chunks_tx;
struct list_head list;
u16 base_doorbell_index;
u16 currcq_count;
u16 deepcq_count;
u8 iw_status;
u8 msi_enabled;
u8 netdev_count;
u8 napi_isr_ran;
u8 disable_rx_flow_control;
u8 disable_tx_flow_control;
struct delayed_work work;
u8 link_recheck;
};
/* Receive skb private area - must fit in skb->cb area */
struct nes_rskb_cb {
u64 busaddr;
u32 maplen;
u32 seqnum;
u8 *data_start;
struct nes_qp *nesqp;
};
static inline __le32 get_crc_value(struct nes_v4_quad *nes_quad)
{
u32 crc_value;
crc_value = crc32c(~0, (void *)nes_quad, sizeof (struct nes_v4_quad));
/*
* With commit ef19454b ("[LIB] crc32c: Keep intermediate crc
* state in cpu order"), behavior of crc32c changes on
* big-endian platforms. Our algorithm expects the previous
* behavior; otherwise we have RDMA connection establishment
* issue on big-endian.
*/
return cpu_to_le32(crc_value);
}
static inline void
set_wqe_64bit_value(__le32 *wqe_words, u32 index, u64 value)
{
wqe_words[index] = cpu_to_le32((u32) value);
wqe_words[index + 1] = cpu_to_le32(upper_32_bits(value));
}
static inline void
set_wqe_32bit_value(__le32 *wqe_words, u32 index, u32 value)
{
wqe_words[index] = cpu_to_le32(value);
}
static inline void
nes_fill_init_cqp_wqe(struct nes_hw_cqp_wqe *cqp_wqe, struct nes_device *nesdev)
{
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_LOW_IDX] = 0;
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX] = 0;
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_LOW_IDX] = 0;
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX] = 0;
cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PBL_BLK_COUNT_IDX] = 0;
cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PBL_LEN_IDX] = 0;
cqp_wqe->wqe_words[NES_CQP_STAG_WQE_LEN_LOW_IDX] = 0;
cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PA_LOW_IDX] = 0;
cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PA_HIGH_IDX] = 0;
}
static inline void
nes_fill_init_qp_wqe(struct nes_hw_qp_wqe *wqe, struct nes_qp *nesqp, u32 head)
{
u32 value;
value = ((u32)((unsigned long) nesqp)) | head;
set_wqe_32bit_value(wqe->wqe_words, NES_IWARP_SQ_WQE_COMP_CTX_HIGH_IDX,
(u32)(upper_32_bits((unsigned long)(nesqp))));
set_wqe_32bit_value(wqe->wqe_words, NES_IWARP_SQ_WQE_COMP_CTX_LOW_IDX, value);
}
/* Read from memory-mapped device */
static inline u32 nes_read_indexed(struct nes_device *nesdev, u32 reg_index)
{
unsigned long flags;
void __iomem *addr = nesdev->index_reg;
u32 value;
spin_lock_irqsave(&nesdev->indexed_regs_lock, flags);
writel(reg_index, addr);
value = readl((void __iomem *)addr + 4);
spin_unlock_irqrestore(&nesdev->indexed_regs_lock, flags);
return value;
}
static inline u32 nes_read32(const void __iomem *addr)
{
return readl(addr);
}
static inline u16 nes_read16(const void __iomem *addr)
{
return readw(addr);
}
static inline u8 nes_read8(const void __iomem *addr)
{
return readb(addr);
}
/* Write to memory-mapped device */
static inline void nes_write_indexed(struct nes_device *nesdev, u32 reg_index, u32 val)
{
unsigned long flags;
void __iomem *addr = nesdev->index_reg;
spin_lock_irqsave(&nesdev->indexed_regs_lock, flags);
writel(reg_index, addr);
writel(val, (void __iomem *)addr + 4);
spin_unlock_irqrestore(&nesdev->indexed_regs_lock, flags);
}
static inline void nes_write32(void __iomem *addr, u32 val)
{
writel(val, addr);
}
static inline void nes_write16(void __iomem *addr, u16 val)
{
writew(val, addr);
}
static inline void nes_write8(void __iomem *addr, u8 val)
{
writeb(val, addr);
}
enum nes_resource {
NES_RESOURCE_MW = 1,
NES_RESOURCE_FAST_MR,
NES_RESOURCE_PHYS_MR,
NES_RESOURCE_USER_MR,
NES_RESOURCE_PD,
NES_RESOURCE_QP,
NES_RESOURCE_CQ,
NES_RESOURCE_ARP
};
static inline int nes_alloc_resource(struct nes_adapter *nesadapter,
unsigned long *resource_array, u32 max_resources,
u32 *req_resource_num, u32 *next, enum nes_resource resource_type)
{
unsigned long flags;
u32 resource_num;
spin_lock_irqsave(&nesadapter->resource_lock, flags);
resource_num = find_next_zero_bit(resource_array, max_resources, *next);
if (resource_num >= max_resources) {
resource_num = find_first_zero_bit(resource_array, max_resources);
if (resource_num >= max_resources) {
printk(KERN_ERR PFX "%s: No available resources [type=%u].\n", __func__, resource_type);
spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
return -EMFILE;
}
}
set_bit(resource_num, resource_array);
*next = resource_num+1;
if (*next == max_resources) {
*next = 0;
}
spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
*req_resource_num = resource_num;
return 0;
}
static inline int nes_is_resource_allocated(struct nes_adapter *nesadapter,
unsigned long *resource_array, u32 resource_num)
{
unsigned long flags;
int bit_is_set;
spin_lock_irqsave(&nesadapter->resource_lock, flags);
bit_is_set = test_bit(resource_num, resource_array);
nes_debug(NES_DBG_HW, "resource_num %u is%s allocated.\n",
resource_num, (bit_is_set ? "": " not"));
spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
return bit_is_set;
}
static inline void nes_free_resource(struct nes_adapter *nesadapter,
unsigned long *resource_array, u32 resource_num)
{
unsigned long flags;
spin_lock_irqsave(&nesadapter->resource_lock, flags);
clear_bit(resource_num, resource_array);
spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
}
static inline struct nes_vnic *to_nesvnic(struct ib_device *ibdev)
{
return container_of(ibdev, struct nes_ib_device, ibdev)->nesvnic;
}
static inline struct nes_pd *to_nespd(struct ib_pd *ibpd)
{
return container_of(ibpd, struct nes_pd, ibpd);
}
static inline struct nes_ucontext *to_nesucontext(struct ib_ucontext *ibucontext)
{
return container_of(ibucontext, struct nes_ucontext, ibucontext);
}
static inline struct nes_mr *to_nesmr(struct ib_mr *ibmr)
{
return container_of(ibmr, struct nes_mr, ibmr);
}
static inline struct nes_mr *to_nesmr_from_ibfmr(struct ib_fmr *ibfmr)
{
return container_of(ibfmr, struct nes_mr, ibfmr);
}
static inline struct nes_mr *to_nesmw(struct ib_mw *ibmw)
{
return container_of(ibmw, struct nes_mr, ibmw);
}
static inline struct nes_fmr *to_nesfmr(struct nes_mr *nesmr)
{
return container_of(nesmr, struct nes_fmr, nesmr);
}
static inline struct nes_cq *to_nescq(struct ib_cq *ibcq)
{
return container_of(ibcq, struct nes_cq, ibcq);
}
static inline struct nes_qp *to_nesqp(struct ib_qp *ibqp)
{
return container_of(ibqp, struct nes_qp, ibqp);
}
/* nes.c */
void nes_add_ref(struct ib_qp *);
void nes_rem_ref(struct ib_qp *);
struct ib_qp *nes_get_qp(struct ib_device *, int);
/* nes_hw.c */
struct nes_adapter *nes_init_adapter(struct nes_device *, u8);
void nes_nic_init_timer_defaults(struct nes_device *, u8);
void nes_destroy_adapter(struct nes_adapter *);
int nes_init_cqp(struct nes_device *);
int nes_init_phy(struct nes_device *);
int nes_init_nic_qp(struct nes_device *, struct net_device *);
void nes_destroy_nic_qp(struct nes_vnic *);
int nes_napi_isr(struct nes_device *);
void nes_dpc(unsigned long);
void nes_nic_ce_handler(struct nes_device *, struct nes_hw_nic_cq *);
void nes_iwarp_ce_handler(struct nes_device *, struct nes_hw_cq *);
int nes_destroy_cqp(struct nes_device *);
int nes_nic_cm_xmit(struct sk_buff *, struct net_device *);
void nes_recheck_link_status(struct work_struct *work);
void nes_terminate_timeout(struct timer_list *t);
/* nes_nic.c */
struct net_device *nes_netdev_init(struct nes_device *, void __iomem *);
void nes_netdev_destroy(struct net_device *);
int nes_nic_cm_xmit(struct sk_buff *, struct net_device *);
/* nes_cm.c */
void *nes_cm_create(struct net_device *);
int nes_cm_recv(struct sk_buff *, struct net_device *);
void nes_update_arp(unsigned char *, u32, u32, u16, u16);
void nes_manage_arp_cache(struct net_device *, unsigned char *, u32, u32);
void nes_sock_release(struct nes_qp *, unsigned long *);
void flush_wqes(struct nes_device *nesdev, struct nes_qp *, u32, u32);
int nes_manage_apbvt(struct nes_vnic *, u32, u32, u32);
int nes_cm_disconn(struct nes_qp *);
void nes_cm_disconn_worker(void *);
/* nes_verbs.c */
int nes_hw_modify_qp(struct nes_device *, struct nes_qp *, u32, u32, u32);
int nes_modify_qp(struct ib_qp *, struct ib_qp_attr *, int, struct ib_udata *);
struct nes_ib_device *nes_init_ofa_device(struct net_device *);
void nes_port_ibevent(struct nes_vnic *nesvnic);
void nes_destroy_ofa_device(struct nes_ib_device *);
int nes_register_ofa_device(struct nes_ib_device *);
/* nes_util.c */
int nes_read_eeprom_values(struct nes_device *, struct nes_adapter *);
void nes_write_1G_phy_reg(struct nes_device *, u8, u8, u16);
void nes_read_1G_phy_reg(struct nes_device *, u8, u8, u16 *);
void nes_write_10G_phy_reg(struct nes_device *, u16, u8, u16, u16);
void nes_read_10G_phy_reg(struct nes_device *, u8, u8, u16);
struct nes_cqp_request *nes_get_cqp_request(struct nes_device *);
void nes_free_cqp_request(struct nes_device *nesdev,
struct nes_cqp_request *cqp_request);
void nes_put_cqp_request(struct nes_device *nesdev,
struct nes_cqp_request *cqp_request);
void nes_post_cqp_request(struct nes_device *, struct nes_cqp_request *);
int nes_arp_table(struct nes_device *, u32, u8 *, u32);
void nes_mh_fix(struct timer_list *t);
void nes_clc(struct timer_list *t);
void nes_dump_mem(unsigned int, void *, int);
u32 nes_crc32(u32, u32, u32, u32, u8 *, u32, u32, u32);
#endif /* __NES_H */
drivers/infiniband/hw/nes/nes_cm.c deleted 100644 → 0
View file @ cbdc666f
This source diff could not be displayed because it is too large. You can view the blob instead.
drivers/infiniband/hw/nes/nes_cm.h deleted 100644 → 0
View file @ cbdc666f
/*
* Copyright (c) 2006 - 2014 Intel Corporation. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
*/
#ifndef NES_CM_H
#define NES_CM_H
#define QUEUE_EVENTS
#define NES_MANAGE_APBVT_DEL 0
#define NES_MANAGE_APBVT_ADD 1
#define NES_MPA_REQUEST_ACCEPT 1
#define NES_MPA_REQUEST_REJECT 2
/* IETF MPA -- defines, enums, structs */
#define IEFT_MPA_KEY_REQ "MPA ID Req Frame"
#define IEFT_MPA_KEY_REP "MPA ID Rep Frame"
#define IETF_MPA_KEY_SIZE 16
#define IETF_MPA_VERSION 1
#define IETF_MAX_PRIV_DATA_LEN 512
#define IETF_MPA_FRAME_SIZE 20
#define IETF_RTR_MSG_SIZE 4
#define IETF_MPA_V2_FLAG 0x10
/* IETF RTR MSG Fields */
#define IETF_PEER_TO_PEER 0x8000
#define IETF_FLPDU_ZERO_LEN 0x4000
#define IETF_RDMA0_WRITE 0x8000
#define IETF_RDMA0_READ 0x4000
#define IETF_NO_IRD_ORD 0x3FFF
#define NES_MAX_IRD 0x40
#define NES_MAX_ORD 0x7F
enum ietf_mpa_flags {
IETF_MPA_FLAGS_MARKERS = 0x80, /* receive Markers */
IETF_MPA_FLAGS_CRC = 0x40, /* receive Markers */
IETF_MPA_FLAGS_REJECT = 0x20, /* Reject */
};
struct ietf_mpa_v1 {
u8 key[IETF_MPA_KEY_SIZE];
u8 flags;
u8 rev;
__be16 priv_data_len;
u8 priv_data[0];
};
#define ietf_mpa_req_resp_frame ietf_mpa_frame
struct ietf_rtr_msg {
__be16 ctrl_ird;
__be16 ctrl_ord;
};
struct ietf_mpa_v2 {
u8 key[IETF_MPA_KEY_SIZE];
u8 flags;
u8 rev;
__be16 priv_data_len;
struct ietf_rtr_msg rtr_msg;
u8 priv_data[0];
};
struct nes_v4_quad {
u32 rsvd0;
__le32 DstIpAdrIndex; /* Only most significant 5 bits are valid */
__be32 SrcIpadr;
__be16 TcpPorts[2]; /* src is low, dest is high */
};
struct nes_cm_node;
enum nes_timer_type {
NES_TIMER_TYPE_SEND,
NES_TIMER_TYPE_RECV,
NES_TIMER_NODE_CLEANUP,
NES_TIMER_TYPE_CLOSE,
};
#define NES_PASSIVE_STATE_INDICATED 0
#define NES_DO_NOT_SEND_RESET_EVENT 1
#define NES_SEND_RESET_EVENT 2
#define MAX_NES_IFS 4
#define SET_ACK 1
#define SET_SYN 2
#define SET_FIN 4
#define SET_RST 8
#define TCP_OPTIONS_PADDING 3
struct option_base {
u8 optionnum;
u8 length;
};
enum option_numbers {
OPTION_NUMBER_END,
OPTION_NUMBER_NONE,
OPTION_NUMBER_MSS,
OPTION_NUMBER_WINDOW_SCALE,
OPTION_NUMBER_SACK_PERM,
OPTION_NUMBER_SACK,
OPTION_NUMBER_WRITE0 = 0xbc
};
struct option_mss {
u8 optionnum;
u8 length;
__be16 mss;
};
struct option_windowscale {
u8 optionnum;
u8 length;
u8 shiftcount;
};
union all_known_options {
char as_end;
struct option_base as_base;
struct option_mss as_mss;
struct option_windowscale as_windowscale;
};
struct nes_timer_entry {
struct list_head list;
unsigned long timetosend; /* jiffies */
struct sk_buff *skb;
u32 type;
u32 retrycount;
u32 retranscount;
u32 context;
u32 seq_num;
u32 send_retrans;
int close_when_complete;
struct net_device *netdev;
};
#define NES_DEFAULT_RETRYS 64
#define NES_DEFAULT_RETRANS 8
#ifdef CONFIG_INFINIBAND_NES_DEBUG
#define NES_RETRY_TIMEOUT (1000*HZ/1000)
#else
#define NES_RETRY_TIMEOUT (3000*HZ/1000)
#endif
#define NES_SHORT_TIME (10)
#define NES_LONG_TIME (2000*HZ/1000)
#define NES_MAX_TIMEOUT ((unsigned long) (12*HZ))
#define NES_CM_HASHTABLE_SIZE 1024
#define NES_CM_TCP_TIMER_INTERVAL 3000
#define NES_CM_DEFAULT_MTU 1540
#define NES_CM_DEFAULT_FRAME_CNT 10
#define NES_CM_THREAD_STACK_SIZE 256
#define NES_CM_DEFAULT_RCV_WND 64240 // before we know that window scaling is allowed
#define NES_CM_DEFAULT_RCV_WND_SCALED 256960 // after we know that window scaling is allowed
#define NES_CM_DEFAULT_RCV_WND_SCALE 2
#define NES_CM_DEFAULT_FREE_PKTS 0x000A
#define NES_CM_FREE_PKT_LO_WATERMARK 2
#define NES_CM_DEFAULT_MSS 536
#define NES_CM_DEF_SEQ 0x159bf75f
#define NES_CM_DEF_LOCAL_ID 0x3b47
#define NES_CM_DEF_SEQ2 0x18ed5740
#define NES_CM_DEF_LOCAL_ID2 0xb807
#define MAX_CM_BUFFER (IETF_MPA_FRAME_SIZE + IETF_RTR_MSG_SIZE + IETF_MAX_PRIV_DATA_LEN)
typedef u32 nes_addr_t;
#define nes_cm_tsa_context nes_qp_context
struct nes_qp;
/* cm node transition states */
enum nes_cm_node_state {
NES_CM_STATE_UNKNOWN,
NES_CM_STATE_INITED,
NES_CM_STATE_LISTENING,
NES_CM_STATE_SYN_RCVD,
NES_CM_STATE_SYN_SENT,
NES_CM_STATE_ONE_SIDE_ESTABLISHED,
NES_CM_STATE_ESTABLISHED,
NES_CM_STATE_ACCEPTING,
NES_CM_STATE_MPAREQ_SENT,
NES_CM_STATE_MPAREQ_RCVD,
NES_CM_STATE_MPAREJ_RCVD,
NES_CM_STATE_TSA,
NES_CM_STATE_FIN_WAIT1,
NES_CM_STATE_FIN_WAIT2,
NES_CM_STATE_CLOSE_WAIT,
NES_CM_STATE_TIME_WAIT,
NES_CM_STATE_LAST_ACK,
NES_CM_STATE_CLOSING,
NES_CM_STATE_LISTENER_DESTROYED,
NES_CM_STATE_CLOSED
};
enum mpa_frame_version {
IETF_MPA_V1 = 1,
IETF_MPA_V2 = 2
};
enum mpa_frame_key {
MPA_KEY_REQUEST,
MPA_KEY_REPLY
};
enum send_rdma0 {
SEND_RDMA_READ_ZERO = 1,
SEND_RDMA_WRITE_ZERO = 2
};
enum nes_tcpip_pkt_type {
NES_PKT_TYPE_UNKNOWN,
NES_PKT_TYPE_SYN,
NES_PKT_TYPE_SYNACK,
NES_PKT_TYPE_ACK,
NES_PKT_TYPE_FIN,
NES_PKT_TYPE_RST
};
/* type of nes connection */
enum nes_cm_conn_type {
NES_CM_IWARP_CONN_TYPE,
};
/* CM context params */
struct nes_cm_tcp_context {
u8 client;
u32 loc_seq_num;
u32 loc_ack_num;
u32 rem_ack_num;
u32 rcv_nxt;
u32 loc_id;
u32 rem_id;
u32 snd_wnd;
u32 max_snd_wnd;
u32 rcv_wnd;
u32 mss;
u8 snd_wscale;
u8 rcv_wscale;
struct nes_cm_tsa_context tsa_cntxt;
};
enum nes_cm_listener_state {
NES_CM_LISTENER_PASSIVE_STATE = 1,
NES_CM_LISTENER_ACTIVE_STATE = 2,
NES_CM_LISTENER_EITHER_STATE = 3
};
struct nes_cm_listener {
struct list_head list;
struct nes_cm_core *cm_core;
u8 loc_mac[ETH_ALEN];
nes_addr_t loc_addr;
u16 loc_port;
struct iw_cm_id *cm_id;
enum nes_cm_conn_type conn_type;
atomic_t ref_count;
struct nes_vnic *nesvnic;
atomic_t pend_accepts_cnt;
int backlog;
enum nes_cm_listener_state listener_state;
u32 reused_node;
u8 tos;
};
/* per connection node and node state information */
struct nes_cm_node {
nes_addr_t loc_addr, rem_addr;
u16 loc_port, rem_port;
u8 loc_mac[ETH_ALEN];
u8 rem_mac[ETH_ALEN];
enum nes_cm_node_state state;
struct nes_cm_tcp_context tcp_cntxt;
struct nes_cm_core *cm_core;
struct sk_buff_head resend_list;
atomic_t ref_count;
struct net_device *netdev;
struct nes_cm_node *loopbackpartner;
struct nes_timer_entry *send_entry;
struct nes_timer_entry *recv_entry;
spinlock_t retrans_list_lock;
enum send_rdma0 send_rdma0_op;
union {
struct ietf_mpa_v1 mpa_frame;
struct ietf_mpa_v2 mpa_v2_frame;
u8 mpa_frame_buf[MAX_CM_BUFFER];
};
enum mpa_frame_version mpa_frame_rev;
u16 ird_size;
u16 ord_size;
u16 mpav2_ird_ord;
u16 mpa_frame_size;
struct iw_cm_id *cm_id;
struct list_head list;
bool accelerated;
struct nes_cm_listener *listener;
enum nes_cm_conn_type conn_type;
struct nes_vnic *nesvnic;
int apbvt_set;
int accept_pend;
struct list_head timer_entry;
struct list_head reset_entry;
struct nes_qp *nesqp;
atomic_t passive_state;
u8 tos;
};
/* structure for client or CM to fill when making CM api calls. */
/* - only need to set relevant data, based on op. */
struct nes_cm_info {
union {
struct iw_cm_id *cm_id;
struct net_device *netdev;
};
u16 loc_port;
u16 rem_port;
nes_addr_t loc_addr;
nes_addr_t rem_addr;
enum nes_cm_conn_type conn_type;
int backlog;
};
/* CM event codes */
enum nes_cm_event_type {
NES_CM_EVENT_UNKNOWN,
NES_CM_EVENT_ESTABLISHED,
NES_CM_EVENT_MPA_REQ,
NES_CM_EVENT_MPA_CONNECT,
NES_CM_EVENT_MPA_ACCEPT,
NES_CM_EVENT_MPA_REJECT,
NES_CM_EVENT_MPA_ESTABLISHED,
NES_CM_EVENT_CONNECTED,
NES_CM_EVENT_CLOSED,
NES_CM_EVENT_RESET,
NES_CM_EVENT_DROPPED_PKT,
NES_CM_EVENT_CLOSE_IMMED,
NES_CM_EVENT_CLOSE_HARD,
NES_CM_EVENT_CLOSE_CLEAN,
NES_CM_EVENT_ABORTED,
NES_CM_EVENT_SEND_FIRST
};
/* event to post to CM event handler */
struct nes_cm_event {
enum nes_cm_event_type type;
struct nes_cm_info cm_info;
struct work_struct event_work;
struct nes_cm_node *cm_node;
};
struct nes_cm_core {
enum nes_cm_node_state state;
atomic_t listen_node_cnt;
struct nes_cm_node listen_list;
spinlock_t listen_list_lock;
u32 mtu;
u32 free_tx_pkt_max;
u32 rx_pkt_posted;
atomic_t ht_node_cnt;
struct list_head connected_nodes;
/* struct list_head hashtable[NES_CM_HASHTABLE_SIZE]; */
spinlock_t ht_lock;
struct timer_list tcp_timer;
const struct nes_cm_ops *api;
int (*post_event)(struct nes_cm_event *event);
atomic_t events_posted;
struct workqueue_struct *event_wq;
struct workqueue_struct *disconn_wq;
atomic_t node_cnt;
u64 aborted_connects;
u32 options;
struct nes_cm_node *current_listen_node;
};
#define NES_CM_SET_PKT_SIZE (1 << 1)
#define NES_CM_SET_FREE_PKT_Q_SIZE (1 << 2)
/* CM ops/API for client interface */
struct nes_cm_ops {
int (*accelerated)(struct nes_cm_core *, struct nes_cm_node *);
struct nes_cm_listener * (*listen)(struct nes_cm_core *, struct nes_vnic *,
struct nes_cm_info *);
int (*stop_listener)(struct nes_cm_core *, struct nes_cm_listener *);
struct nes_cm_node * (*connect)(struct nes_cm_core *,
struct nes_vnic *, u16, void *,
struct nes_cm_info *);
int (*close)(struct nes_cm_core *, struct nes_cm_node *);
int (*accept)(struct nes_cm_core *, struct nes_cm_node *);
int (*reject)(struct nes_cm_core *, struct nes_cm_node *);
int (*recv_pkt)(struct nes_cm_core *, struct nes_vnic *,
struct sk_buff *);
int (*destroy_cm_core)(struct nes_cm_core *);
int (*get)(struct nes_cm_core *);
int (*set)(struct nes_cm_core *, u32, u32);
};
int schedule_nes_timer(struct nes_cm_node *, struct sk_buff *,
enum nes_timer_type, int, int);
int nes_accept(struct iw_cm_id *, struct iw_cm_conn_param *);
int nes_reject(struct iw_cm_id *, const void *, u8);
int nes_connect(struct iw_cm_id *, struct iw_cm_conn_param *);
int nes_create_listen(struct iw_cm_id *, int);
int nes_destroy_listen(struct iw_cm_id *);
int nes_cm_recv(struct sk_buff *, struct net_device *);
int nes_cm_start(void);
int nes_cm_stop(void);
int nes_add_ref_cm_node(struct nes_cm_node *cm_node);
int nes_rem_ref_cm_node(struct nes_cm_node *cm_node);
#endif /* NES_CM_H */
drivers/infiniband/hw/nes/nes_context.h deleted 100644 → 0
View file @ cbdc666f
/*
* Copyright (c) 2006 - 2011 Intel Corporation. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef NES_CONTEXT_H
#define NES_CONTEXT_H
struct nes_qp_context {
__le32 misc;
__le32 cqs;
__le32 sq_addr_low;
__le32 sq_addr_high;
__le32 rq_addr_low;
__le32 rq_addr_high;
__le32 misc2;
__le16 tcpPorts[2];
__le32 ip0;
__le32 ip1;
__le32 ip2;
__le32 ip3;
__le32 mss;
__le32 arp_index_vlan;
__le32 tcp_state_flow_label;
__le32 pd_index_wscale;
__le32 keepalive;
u32 ts_recent;
u32 ts_age;
__le32 snd_nxt;
__le32 snd_wnd;
__le32 rcv_nxt;
__le32 rcv_wnd;
__le32 snd_max;
__le32 snd_una;
u32 srtt;
__le32 rttvar;
__le32 ssthresh;
__le32 cwnd;
__le32 snd_wl1;
__le32 snd_wl2;
__le32 max_snd_wnd;
__le32 ts_val_delta;
u32 retransmit;
u32 probe_cnt;
u32 hte_index;
__le32 q2_addr_low;
__le32 q2_addr_high;
__le32 ird_index;
u32 Rsvd3;
__le32 ird_ord_sizes;
u32 mrkr_offset;
__le32 aeq_token_low;
__le32 aeq_token_high;
};
/* QP Context Misc Field */
#define NES_QPCONTEXT_MISC_IWARP_VER_MASK 0x00000003
#define NES_QPCONTEXT_MISC_IWARP_VER_SHIFT 0
#define NES_QPCONTEXT_MISC_EFB_SIZE_MASK 0x000000C0
#define NES_QPCONTEXT_MISC_EFB_SIZE_SHIFT 6
#define NES_QPCONTEXT_MISC_RQ_SIZE_MASK 0x00000300
#define NES_QPCONTEXT_MISC_RQ_SIZE_SHIFT 8
#define NES_QPCONTEXT_MISC_SQ_SIZE_MASK 0x00000c00
#define NES_QPCONTEXT_MISC_SQ_SIZE_SHIFT 10
#define NES_QPCONTEXT_MISC_PCI_FCN_MASK 0x00007000
#define NES_QPCONTEXT_MISC_PCI_FCN_SHIFT 12
#define NES_QPCONTEXT_MISC_DUP_ACKS_MASK 0x00070000
#define NES_QPCONTEXT_MISC_DUP_ACKS_SHIFT 16
enum nes_qp_context_misc_bits {
NES_QPCONTEXT_MISC_RX_WQE_SIZE = 0x00000004,
NES_QPCONTEXT_MISC_IPV4 = 0x00000008,
NES_QPCONTEXT_MISC_DO_NOT_FRAG = 0x00000010,
NES_QPCONTEXT_MISC_INSERT_VLAN = 0x00000020,
NES_QPCONTEXT_MISC_DROS = 0x00008000,
NES_QPCONTEXT_MISC_WSCALE = 0x00080000,
NES_QPCONTEXT_MISC_KEEPALIVE = 0x00100000,
NES_QPCONTEXT_MISC_TIMESTAMP = 0x00200000,
NES_QPCONTEXT_MISC_SACK = 0x00400000,
NES_QPCONTEXT_MISC_RDMA_WRITE_EN = 0x00800000,
NES_QPCONTEXT_MISC_RDMA_READ_EN = 0x01000000,
NES_QPCONTEXT_MISC_WBIND_EN = 0x10000000,
NES_QPCONTEXT_MISC_FAST_REGISTER_EN = 0x20000000,
NES_QPCONTEXT_MISC_PRIV_EN = 0x40000000,
NES_QPCONTEXT_MISC_NO_NAGLE = 0x80000000
};
enum nes_qp_acc_wq_sizes {
HCONTEXT_TSA_WQ_SIZE_4 = 0,
HCONTEXT_TSA_WQ_SIZE_32 = 1,
HCONTEXT_TSA_WQ_SIZE_128 = 2,
HCONTEXT_TSA_WQ_SIZE_512 = 3
};
/* QP Context Misc2 Fields */
#define NES_QPCONTEXT_MISC2_TTL_MASK 0x000000ff
#define NES_QPCONTEXT_MISC2_TTL_SHIFT 0
#define NES_QPCONTEXT_MISC2_HOP_LIMIT_MASK 0x000000ff
#define NES_QPCONTEXT_MISC2_HOP_LIMIT_SHIFT 0
#define NES_QPCONTEXT_MISC2_LIMIT_MASK 0x00000300
#define NES_QPCONTEXT_MISC2_LIMIT_SHIFT 8
#define NES_QPCONTEXT_MISC2_NIC_INDEX_MASK 0x0000fc00
#define NES_QPCONTEXT_MISC2_NIC_INDEX_SHIFT 10
#define NES_QPCONTEXT_MISC2_SRC_IP_MASK 0x001f0000
#define NES_QPCONTEXT_MISC2_SRC_IP_SHIFT 16
#define NES_QPCONTEXT_MISC2_TOS_MASK 0xff000000
#define NES_QPCONTEXT_MISC2_TOS_SHIFT 24
#define NES_QPCONTEXT_MISC2_TRAFFIC_CLASS_MASK 0xff000000
#define NES_QPCONTEXT_MISC2_TRAFFIC_CLASS_SHIFT 24
/* QP Context Tcp State/Flow Label Fields */
#define NES_QPCONTEXT_TCPFLOW_FLOW_LABEL_MASK 0x000fffff
#define NES_QPCONTEXT_TCPFLOW_FLOW_LABEL_SHIFT 0
#define NES_QPCONTEXT_TCPFLOW_TCP_STATE_MASK 0xf0000000
#define NES_QPCONTEXT_TCPFLOW_TCP_STATE_SHIFT 28
enum nes_qp_tcp_state {
NES_QPCONTEXT_TCPSTATE_CLOSED = 1,
NES_QPCONTEXT_TCPSTATE_EST = 5,
NES_QPCONTEXT_TCPSTATE_TIME_WAIT = 11,
};
/* QP Context PD Index/wscale Fields */
#define NES_QPCONTEXT_PDWSCALE_RCV_WSCALE_MASK 0x0000000f
#define NES_QPCONTEXT_PDWSCALE_RCV_WSCALE_SHIFT 0
#define NES_QPCONTEXT_PDWSCALE_SND_WSCALE_MASK 0x00000f00
#define NES_QPCONTEXT_PDWSCALE_SND_WSCALE_SHIFT 8
#define NES_QPCONTEXT_PDWSCALE_PDINDEX_MASK 0xffff0000
#define NES_QPCONTEXT_PDWSCALE_PDINDEX_SHIFT 16
/* QP Context Keepalive Fields */
#define NES_QPCONTEXT_KEEPALIVE_DELTA_MASK 0x0000ffff
#define NES_QPCONTEXT_KEEPALIVE_DELTA_SHIFT 0
#define NES_QPCONTEXT_KEEPALIVE_PROBE_CNT_MASK 0x00ff0000
#define NES_QPCONTEXT_KEEPALIVE_PROBE_CNT_SHIFT 16
#define NES_QPCONTEXT_KEEPALIVE_INTV_MASK 0xff000000
#define NES_QPCONTEXT_KEEPALIVE_INTV_SHIFT 24
/* QP Context ORD/IRD Fields */
#define NES_QPCONTEXT_ORDIRD_ORDSIZE_MASK 0x0000007f
#define NES_QPCONTEXT_ORDIRD_ORDSIZE_SHIFT 0
#define NES_QPCONTEXT_ORDIRD_IRDSIZE_MASK 0x00030000
#define NES_QPCONTEXT_ORDIRD_IRDSIZE_SHIFT 16
#define NES_QPCONTEXT_ORDIRD_IWARP_MODE_MASK 0x30000000
#define NES_QPCONTEXT_ORDIRD_IWARP_MODE_SHIFT 28
enum nes_ord_ird_bits {
NES_QPCONTEXT_ORDIRD_WRPDU = 0x02000000,
NES_QPCONTEXT_ORDIRD_LSMM_PRESENT = 0x04000000,
NES_QPCONTEXT_ORDIRD_ALSMM = 0x08000000,
NES_QPCONTEXT_ORDIRD_AAH = 0x40000000,
NES_QPCONTEXT_ORDIRD_RNMC = 0x80000000
};
enum nes_iwarp_qp_state {
NES_QPCONTEXT_IWARP_STATE_NONEXIST = 0,
NES_QPCONTEXT_IWARP_STATE_IDLE = 1,
NES_QPCONTEXT_IWARP_STATE_RTS = 2,
NES_QPCONTEXT_IWARP_STATE_CLOSING = 3,
NES_QPCONTEXT_IWARP_STATE_TERMINATE = 5,
NES_QPCONTEXT_IWARP_STATE_ERROR = 6
};
#endif /* NES_CONTEXT_H */
drivers/infiniband/hw/nes/nes_hw.c deleted 100644 → 0
View file @ cbdc666f
This source diff could not be displayed because it is too large. You can view the blob instead.
drivers/infiniband/hw/nes/nes_hw.h deleted 100644 → 0
View file @ cbdc666f
/*
* Copyright (c) 2006 - 2011 Intel Corporation. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef __NES_HW_H
#define __NES_HW_H
#define NES_PHY_TYPE_CX4 1
#define NES_PHY_TYPE_1G 2
#define NES_PHY_TYPE_ARGUS 4
#define NES_PHY_TYPE_PUMA_1G 5
#define NES_PHY_TYPE_PUMA_10G 6
#define NES_PHY_TYPE_GLADIUS 7
#define NES_PHY_TYPE_SFP_D 8
#define NES_PHY_TYPE_KR 9
#define NES_MULTICAST_PF_MAX 8
#define NES_A0 3
#define NES_ENABLE_PAU 0x07000001
#define NES_DISABLE_PAU 0x07000000
#define NES_PAU_COUNTER 10
#define NES_CQP_OPCODE_MASK 0x3f
enum pci_regs {
NES_INT_STAT = 0x0000,
NES_INT_MASK = 0x0004,
NES_INT_PENDING = 0x0008,
NES_INTF_INT_STAT = 0x000C,
NES_INTF_INT_MASK = 0x0010,
NES_TIMER_STAT = 0x0014,
NES_PERIODIC_CONTROL = 0x0018,
NES_ONE_SHOT_CONTROL = 0x001C,
NES_EEPROM_COMMAND = 0x0020,
NES_EEPROM_DATA = 0x0024,
NES_FLASH_COMMAND = 0x0028,
NES_FLASH_DATA = 0x002C,
NES_SOFTWARE_RESET = 0x0030,
NES_CQ_ACK = 0x0034,
NES_WQE_ALLOC = 0x0040,
NES_CQE_ALLOC = 0x0044,
NES_AEQ_ALLOC = 0x0048
};
enum indexed_regs {
NES_IDX_CREATE_CQP_LOW = 0x0000,
NES_IDX_CREATE_CQP_HIGH = 0x0004,
NES_IDX_QP_CONTROL = 0x0040,
NES_IDX_FLM_CONTROL = 0x0080,
NES_IDX_INT_CPU_STATUS = 0x00a0,
NES_IDX_GPR_TRIGGER = 0x00bc,
NES_IDX_GPIO_CONTROL = 0x00f0,
NES_IDX_GPIO_DATA = 0x00f4,
NES_IDX_GPR2 = 0x010c,
NES_IDX_TCP_CONFIG0 = 0x01e4,
NES_IDX_TCP_TIMER_CONFIG = 0x01ec,
NES_IDX_TCP_NOW = 0x01f0,
NES_IDX_QP_MAX_CFG_SIZES = 0x0200,
NES_IDX_QP_CTX_SIZE = 0x0218,
NES_IDX_TCP_TIMER_SIZE0 = 0x0238,
NES_IDX_TCP_TIMER_SIZE1 = 0x0240,
NES_IDX_ARP_CACHE_SIZE = 0x0258,
NES_IDX_CQ_CTX_SIZE = 0x0260,
NES_IDX_MRT_SIZE = 0x0278,
NES_IDX_PBL_REGION_SIZE = 0x0280,
NES_IDX_IRRQ_COUNT = 0x02b0,
NES_IDX_RX_WINDOW_BUFFER_PAGE_TABLE_SIZE = 0x02f0,
NES_IDX_RX_WINDOW_BUFFER_SIZE = 0x0300,
NES_IDX_DST_IP_ADDR = 0x0400,
NES_IDX_PCIX_DIAG = 0x08e8,
NES_IDX_MPP_DEBUG = 0x0a00,
NES_IDX_PORT_RX_DISCARDS = 0x0a30,
NES_IDX_PORT_TX_DISCARDS = 0x0a34,
NES_IDX_MPP_LB_DEBUG = 0x0b00,
NES_IDX_DENALI_CTL_22 = 0x1058,
NES_IDX_MAC_TX_CONTROL = 0x2000,
NES_IDX_MAC_TX_CONFIG = 0x2004,
NES_IDX_MAC_TX_PAUSE_QUANTA = 0x2008,
NES_IDX_MAC_RX_CONTROL = 0x200c,
NES_IDX_MAC_RX_CONFIG = 0x2010,
NES_IDX_MAC_EXACT_MATCH_BOTTOM = 0x201c,
NES_IDX_MAC_MDIO_CONTROL = 0x2084,
NES_IDX_MAC_TX_OCTETS_LOW = 0x2100,
NES_IDX_MAC_TX_OCTETS_HIGH = 0x2104,
NES_IDX_MAC_TX_FRAMES_LOW = 0x2108,
NES_IDX_MAC_TX_FRAMES_HIGH = 0x210c,
NES_IDX_MAC_TX_PAUSE_FRAMES = 0x2118,
NES_IDX_MAC_TX_ERRORS = 0x2138,
NES_IDX_MAC_RX_OCTETS_LOW = 0x213c,
NES_IDX_MAC_RX_OCTETS_HIGH = 0x2140,
NES_IDX_MAC_RX_FRAMES_LOW = 0x2144,
NES_IDX_MAC_RX_FRAMES_HIGH = 0x2148,
NES_IDX_MAC_RX_BC_FRAMES_LOW = 0x214c,
NES_IDX_MAC_RX_MC_FRAMES_HIGH = 0x2150,
NES_IDX_MAC_RX_PAUSE_FRAMES = 0x2154,
NES_IDX_MAC_RX_SHORT_FRAMES = 0x2174,
NES_IDX_MAC_RX_OVERSIZED_FRAMES = 0x2178,
NES_IDX_MAC_RX_JABBER_FRAMES = 0x217c,
NES_IDX_MAC_RX_CRC_ERR_FRAMES = 0x2180,
NES_IDX_MAC_RX_LENGTH_ERR_FRAMES = 0x2184,
NES_IDX_MAC_RX_SYMBOL_ERR_FRAMES = 0x2188,
NES_IDX_MAC_INT_STATUS = 0x21f0,
NES_IDX_MAC_INT_MASK = 0x21f4,
NES_IDX_PHY_PCS_CONTROL_STATUS0 = 0x2800,
NES_IDX_PHY_PCS_CONTROL_STATUS1 = 0x2a00,
NES_IDX_ETH_SERDES_COMMON_CONTROL0 = 0x2808,
NES_IDX_ETH_SERDES_COMMON_CONTROL1 = 0x2a08,
NES_IDX_ETH_SERDES_COMMON_STATUS0 = 0x280c,
NES_IDX_ETH_SERDES_COMMON_STATUS1 = 0x2a0c,
NES_IDX_ETH_SERDES_TX_EMP0 = 0x2810,
NES_IDX_ETH_SERDES_TX_EMP1 = 0x2a10,
NES_IDX_ETH_SERDES_TX_DRIVE0 = 0x2814,
NES_IDX_ETH_SERDES_TX_DRIVE1 = 0x2a14,
NES_IDX_ETH_SERDES_RX_MODE0 = 0x2818,
NES_IDX_ETH_SERDES_RX_MODE1 = 0x2a18,
NES_IDX_ETH_SERDES_RX_SIGDET0 = 0x281c,
NES_IDX_ETH_SERDES_RX_SIGDET1 = 0x2a1c,
NES_IDX_ETH_SERDES_BYPASS0 = 0x2820,
NES_IDX_ETH_SERDES_BYPASS1 = 0x2a20,
NES_IDX_ETH_SERDES_LOOPBACK_CONTROL0 = 0x2824,
NES_IDX_ETH_SERDES_LOOPBACK_CONTROL1 = 0x2a24,
NES_IDX_ETH_SERDES_RX_EQ_CONTROL0 = 0x2828,
NES_IDX_ETH_SERDES_RX_EQ_CONTROL1 = 0x2a28,
NES_IDX_ETH_SERDES_RX_EQ_STATUS0 = 0x282c,
NES_IDX_ETH_SERDES_RX_EQ_STATUS1 = 0x2a2c,
NES_IDX_ETH_SERDES_CDR_RESET0 = 0x2830,
NES_IDX_ETH_SERDES_CDR_RESET1 = 0x2a30,
NES_IDX_ETH_SERDES_CDR_CONTROL0 = 0x2834,
NES_IDX_ETH_SERDES_CDR_CONTROL1 = 0x2a34,
NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0 = 0x2838,
NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE1 = 0x2a38,
NES_IDX_ENDNODE0_NSTAT_RX_DISCARD = 0x3080,
NES_IDX_ENDNODE0_NSTAT_RX_OCTETS_LO = 0x3000,
NES_IDX_ENDNODE0_NSTAT_RX_OCTETS_HI = 0x3004,
NES_IDX_ENDNODE0_NSTAT_RX_FRAMES_LO = 0x3008,
NES_IDX_ENDNODE0_NSTAT_RX_FRAMES_HI = 0x300c,
NES_IDX_ENDNODE0_NSTAT_TX_OCTETS_LO = 0x7000,
NES_IDX_ENDNODE0_NSTAT_TX_OCTETS_HI = 0x7004,
NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_LO = 0x7008,
NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_HI = 0x700c,
NES_IDX_WQM_CONFIG0 = 0x5000,
NES_IDX_WQM_CONFIG1 = 0x5004,
NES_IDX_CM_CONFIG = 0x5100,
NES_IDX_NIC_LOGPORT_TO_PHYPORT = 0x6000,
NES_IDX_NIC_PHYPORT_TO_USW = 0x6008,
NES_IDX_NIC_ACTIVE = 0x6010,
NES_IDX_NIC_UNICAST_ALL = 0x6018,
NES_IDX_NIC_MULTICAST_ALL = 0x6020,
NES_IDX_NIC_MULTICAST_ENABLE = 0x6028,
NES_IDX_NIC_BROADCAST_ON = 0x6030,
NES_IDX_USED_CHUNKS_TX = 0x60b0,
NES_IDX_TX_POOL_SIZE = 0x60b8,
NES_IDX_QUAD_HASH_TABLE_SIZE = 0x6148,
NES_IDX_PERFECT_FILTER_LOW = 0x6200,
NES_IDX_PERFECT_FILTER_HIGH = 0x6204,
NES_IDX_IPV4_TCP_REXMITS = 0x7080,
NES_IDX_DEBUG_ERROR_CONTROL_STATUS = 0x913c,
NES_IDX_DEBUG_ERROR_MASKS0 = 0x9140,
NES_IDX_DEBUG_ERROR_MASKS1 = 0x9144,
NES_IDX_DEBUG_ERROR_MASKS2 = 0x9148,
NES_IDX_DEBUG_ERROR_MASKS3 = 0x914c,
NES_IDX_DEBUG_ERROR_MASKS4 = 0x9150,
NES_IDX_DEBUG_ERROR_MASKS5 = 0x9154,
};
#define NES_IDX_MAC_TX_CONFIG_ENABLE_PAUSE 1
#define NES_IDX_MPP_DEBUG_PORT_DISABLE_PAUSE (1 << 17)
enum nes_cqp_opcodes {
NES_CQP_CREATE_QP = 0x00,
NES_CQP_MODIFY_QP = 0x01,
NES_CQP_DESTROY_QP = 0x02,
NES_CQP_CREATE_CQ = 0x03,
NES_CQP_MODIFY_CQ = 0x04,
NES_CQP_DESTROY_CQ = 0x05,
NES_CQP_ALLOCATE_STAG = 0x09,
NES_CQP_REGISTER_STAG = 0x0a,
NES_CQP_QUERY_STAG = 0x0b,
NES_CQP_REGISTER_SHARED_STAG = 0x0c,
NES_CQP_DEALLOCATE_STAG = 0x0d,
NES_CQP_MANAGE_ARP_CACHE = 0x0f,
NES_CQP_DOWNLOAD_SEGMENT = 0x10,
NES_CQP_SUSPEND_QPS = 0x11,
NES_CQP_UPLOAD_CONTEXT = 0x13,
NES_CQP_CREATE_CEQ = 0x16,
NES_CQP_DESTROY_CEQ = 0x18,
NES_CQP_CREATE_AEQ = 0x19,
NES_CQP_DESTROY_AEQ = 0x1b,
NES_CQP_LMI_ACCESS = 0x20,
NES_CQP_FLUSH_WQES = 0x22,
NES_CQP_MANAGE_APBVT = 0x23,
NES_CQP_MANAGE_QUAD_HASH = 0x25
};
enum nes_cqp_wqe_word_idx {
NES_CQP_WQE_OPCODE_IDX = 0,
NES_CQP_WQE_ID_IDX = 1,
NES_CQP_WQE_COMP_CTX_LOW_IDX = 2,
NES_CQP_WQE_COMP_CTX_HIGH_IDX = 3,
NES_CQP_WQE_COMP_SCRATCH_LOW_IDX = 4,
NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX = 5,
};
enum nes_cqp_wqe_word_download_idx { /* format differs from other cqp ops */
NES_CQP_WQE_DL_OPCODE_IDX = 0,
NES_CQP_WQE_DL_COMP_CTX_LOW_IDX = 1,
NES_CQP_WQE_DL_COMP_CTX_HIGH_IDX = 2,
NES_CQP_WQE_DL_LENGTH_0_TOTAL_IDX = 3
/* For index values 4-15 use NES_NIC_SQ_WQE_ values */
};
enum nes_cqp_cq_wqeword_idx {
NES_CQP_CQ_WQE_PBL_LOW_IDX = 6,
NES_CQP_CQ_WQE_PBL_HIGH_IDX = 7,
NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX = 8,
NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX = 9,
NES_CQP_CQ_WQE_DOORBELL_INDEX_HIGH_IDX = 10,
};
enum nes_cqp_stag_wqeword_idx {
NES_CQP_STAG_WQE_PBL_BLK_COUNT_IDX = 1,
NES_CQP_STAG_WQE_LEN_HIGH_PD_IDX = 6,
NES_CQP_STAG_WQE_LEN_LOW_IDX = 7,
NES_CQP_STAG_WQE_STAG_IDX = 8,
NES_CQP_STAG_WQE_VA_LOW_IDX = 10,
NES_CQP_STAG_WQE_VA_HIGH_IDX = 11,
NES_CQP_STAG_WQE_PA_LOW_IDX = 12,
NES_CQP_STAG_WQE_PA_HIGH_IDX = 13,
NES_CQP_STAG_WQE_PBL_LEN_IDX = 14
};
#define NES_CQP_OP_LOGICAL_PORT_SHIFT 26
#define NES_CQP_OP_IWARP_STATE_SHIFT 28
#define NES_CQP_OP_TERMLEN_SHIFT 28
enum nes_cqp_qp_bits {
NES_CQP_QP_ARP_VALID = (1<<8),
NES_CQP_QP_WINBUF_VALID = (1<<9),
NES_CQP_QP_CONTEXT_VALID = (1<<10),
NES_CQP_QP_ORD_VALID = (1<<11),
NES_CQP_QP_WINBUF_DATAIND_EN = (1<<12),
NES_CQP_QP_VIRT_WQS = (1<<13),
NES_CQP_QP_DEL_HTE = (1<<14),
NES_CQP_QP_CQS_VALID = (1<<15),
NES_CQP_QP_TYPE_TSA = 0,
NES_CQP_QP_TYPE_IWARP = (1<<16),
NES_CQP_QP_TYPE_CQP = (4<<16),
NES_CQP_QP_TYPE_NIC = (5<<16),
NES_CQP_QP_MSS_CHG = (1<<20),
NES_CQP_QP_STATIC_RESOURCES = (1<<21),
NES_CQP_QP_IGNORE_MW_BOUND = (1<<22),
NES_CQP_QP_VWQ_USE_LMI = (1<<23),
NES_CQP_QP_IWARP_STATE_IDLE = (1<<NES_CQP_OP_IWARP_STATE_SHIFT),
NES_CQP_QP_IWARP_STATE_RTS = (2<<NES_CQP_OP_IWARP_STATE_SHIFT),
NES_CQP_QP_IWARP_STATE_CLOSING = (3<<NES_CQP_OP_IWARP_STATE_SHIFT),
NES_CQP_QP_IWARP_STATE_TERMINATE = (5<<NES_CQP_OP_IWARP_STATE_SHIFT),
NES_CQP_QP_IWARP_STATE_ERROR = (6<<NES_CQP_OP_IWARP_STATE_SHIFT),
NES_CQP_QP_IWARP_STATE_MASK = (7<<NES_CQP_OP_IWARP_STATE_SHIFT),
NES_CQP_QP_TERM_DONT_SEND_FIN = (1<<24),
NES_CQP_QP_TERM_DONT_SEND_TERM_MSG = (1<<25),
NES_CQP_QP_RESET = (1<<31),
};
enum nes_cqp_qp_wqe_word_idx {
NES_CQP_QP_WQE_CONTEXT_LOW_IDX = 6,
NES_CQP_QP_WQE_CONTEXT_HIGH_IDX = 7,
NES_CQP_QP_WQE_FLUSH_SQ_CODE = 8,
NES_CQP_QP_WQE_FLUSH_RQ_CODE = 9,
NES_CQP_QP_WQE_NEW_MSS_IDX = 15,
};
enum nes_nic_ctx_bits {
NES_NIC_CTX_RQ_SIZE_32 = (3<<8),
NES_NIC_CTX_RQ_SIZE_512 = (3<<8),
NES_NIC_CTX_SQ_SIZE_32 = (1<<10),
NES_NIC_CTX_SQ_SIZE_512 = (3<<10),
};
enum nes_nic_qp_ctx_word_idx {
NES_NIC_CTX_MISC_IDX = 0,
NES_NIC_CTX_SQ_LOW_IDX = 2,
NES_NIC_CTX_SQ_HIGH_IDX = 3,
NES_NIC_CTX_RQ_LOW_IDX = 4,
NES_NIC_CTX_RQ_HIGH_IDX = 5,
};
enum nes_cqp_cq_bits {
NES_CQP_CQ_CEQE_MASK = (1<<9),
NES_CQP_CQ_CEQ_VALID = (1<<10),
NES_CQP_CQ_RESIZE = (1<<11),
NES_CQP_CQ_CHK_OVERFLOW = (1<<12),
NES_CQP_CQ_4KB_CHUNK = (1<<14),
NES_CQP_CQ_VIRT = (1<<15),
};
enum nes_cqp_stag_bits {
NES_CQP_STAG_VA_TO = (1<<9),
NES_CQP_STAG_DEALLOC_PBLS = (1<<10),
NES_CQP_STAG_PBL_BLK_SIZE = (1<<11),
NES_CQP_STAG_MR = (1<<13),
NES_CQP_STAG_RIGHTS_LOCAL_READ = (1<<16),
NES_CQP_STAG_RIGHTS_LOCAL_WRITE = (1<<17),
NES_CQP_STAG_RIGHTS_REMOTE_READ = (1<<18),
NES_CQP_STAG_RIGHTS_REMOTE_WRITE = (1<<19),
NES_CQP_STAG_RIGHTS_WINDOW_BIND = (1<<20),
NES_CQP_STAG_REM_ACC_EN = (1<<21),
NES_CQP_STAG_LEAVE_PENDING = (1<<31),
};
enum nes_cqp_ceq_wqeword_idx {
NES_CQP_CEQ_WQE_ELEMENT_COUNT_IDX = 1,
NES_CQP_CEQ_WQE_PBL_LOW_IDX = 6,
NES_CQP_CEQ_WQE_PBL_HIGH_IDX = 7,
};
enum nes_cqp_ceq_bits {
NES_CQP_CEQ_4KB_CHUNK = (1<<14),
NES_CQP_CEQ_VIRT = (1<<15),
};
enum nes_cqp_aeq_wqeword_idx {
NES_CQP_AEQ_WQE_ELEMENT_COUNT_IDX = 1,
NES_CQP_AEQ_WQE_PBL_LOW_IDX = 6,
NES_CQP_AEQ_WQE_PBL_HIGH_IDX = 7,
};
enum nes_cqp_aeq_bits {
NES_CQP_AEQ_4KB_CHUNK = (1<<14),
NES_CQP_AEQ_VIRT = (1<<15),
};
enum nes_cqp_lmi_wqeword_idx {
NES_CQP_LMI_WQE_LMI_OFFSET_IDX = 1,
NES_CQP_LMI_WQE_FRAG_LOW_IDX = 8,
NES_CQP_LMI_WQE_FRAG_HIGH_IDX = 9,
NES_CQP_LMI_WQE_FRAG_LEN_IDX = 10,
};
enum nes_cqp_arp_wqeword_idx {
NES_CQP_ARP_WQE_MAC_ADDR_LOW_IDX = 6,
NES_CQP_ARP_WQE_MAC_HIGH_IDX = 7,
NES_CQP_ARP_WQE_REACHABILITY_MAX_IDX = 1,
};
enum nes_cqp_upload_wqeword_idx {
NES_CQP_UPLOAD_WQE_CTXT_LOW_IDX = 6,
NES_CQP_UPLOAD_WQE_CTXT_HIGH_IDX = 7,
NES_CQP_UPLOAD_WQE_HTE_IDX = 8,
};
enum nes_cqp_arp_bits {
NES_CQP_ARP_VALID = (1<<8),
NES_CQP_ARP_PERM = (1<<9),
};
enum nes_cqp_flush_bits {
NES_CQP_FLUSH_SQ = (1<<30),
NES_CQP_FLUSH_RQ = (1<<31),
NES_CQP_FLUSH_MAJ_MIN = (1<<28),
};
enum nes_cqe_opcode_bits {
NES_CQE_STAG_VALID = (1<<6),
NES_CQE_ERROR = (1<<7),
NES_CQE_SQ = (1<<8),
NES_CQE_SE = (1<<9),
NES_CQE_PSH = (1<<29),
NES_CQE_FIN = (1<<30),
NES_CQE_VALID = (1<<31),
};
enum nes_cqe_word_idx {
NES_CQE_PAYLOAD_LENGTH_IDX = 0,
NES_CQE_COMP_COMP_CTX_LOW_IDX = 2,
NES_CQE_COMP_COMP_CTX_HIGH_IDX = 3,
NES_CQE_INV_STAG_IDX = 4,
NES_CQE_QP_ID_IDX = 5,
NES_CQE_ERROR_CODE_IDX = 6,
NES_CQE_OPCODE_IDX = 7,
};
enum nes_ceqe_word_idx {
NES_CEQE_CQ_CTX_LOW_IDX = 0,
NES_CEQE_CQ_CTX_HIGH_IDX = 1,
};
enum nes_ceqe_status_bit {
NES_CEQE_VALID = (1<<31),
};
enum nes_int_bits {
NES_INT_CEQ0 = (1<<0),
NES_INT_CEQ1 = (1<<1),
NES_INT_CEQ2 = (1<<2),
NES_INT_CEQ3 = (1<<3),
NES_INT_CEQ4 = (1<<4),
NES_INT_CEQ5 = (1<<5),
NES_INT_CEQ6 = (1<<6),
NES_INT_CEQ7 = (1<<7),
NES_INT_CEQ8 = (1<<8),
NES_INT_CEQ9 = (1<<9),
NES_INT_CEQ10 = (1<<10),
NES_INT_CEQ11 = (1<<11),
NES_INT_CEQ12 = (1<<12),
NES_INT_CEQ13 = (1<<13),
NES_INT_CEQ14 = (1<<14),
NES_INT_CEQ15 = (1<<15),
NES_INT_AEQ0 = (1<<16),
NES_INT_AEQ1 = (1<<17),
NES_INT_AEQ2 = (1<<18),
NES_INT_AEQ3 = (1<<19),
NES_INT_AEQ4 = (1<<20),
NES_INT_AEQ5 = (1<<21),
NES_INT_AEQ6 = (1<<22),
NES_INT_AEQ7 = (1<<23),
NES_INT_MAC0 = (1<<24),
NES_INT_MAC1 = (1<<25),
NES_INT_MAC2 = (1<<26),
NES_INT_MAC3 = (1<<27),
NES_INT_TSW = (1<<28),
NES_INT_TIMER = (1<<29),
NES_INT_INTF = (1<<30),
};
enum nes_intf_int_bits {
NES_INTF_INT_PCIERR = (1<<0),
NES_INTF_PERIODIC_TIMER = (1<<2),
NES_INTF_ONE_SHOT_TIMER = (1<<3),
NES_INTF_INT_CRITERR = (1<<14),
NES_INTF_INT_AEQ0_OFLOW = (1<<16),
NES_INTF_INT_AEQ1_OFLOW = (1<<17),
NES_INTF_INT_AEQ2_OFLOW = (1<<18),
NES_INTF_INT_AEQ3_OFLOW = (1<<19),
NES_INTF_INT_AEQ4_OFLOW = (1<<20),
NES_INTF_INT_AEQ5_OFLOW = (1<<21),
NES_INTF_INT_AEQ6_OFLOW = (1<<22),
NES_INTF_INT_AEQ7_OFLOW = (1<<23),
NES_INTF_INT_AEQ_OFLOW = (0xff<<16),
};
enum nes_mac_int_bits {
NES_MAC_INT_LINK_STAT_CHG = (1<<1),
NES_MAC_INT_XGMII_EXT = (1<<2),
NES_MAC_INT_TX_UNDERFLOW = (1<<6),
NES_MAC_INT_TX_ERROR = (1<<7),
};
enum nes_cqe_allocate_bits {
NES_CQE_ALLOC_INC_SELECT = (1<<28),
NES_CQE_ALLOC_NOTIFY_NEXT = (1<<29),
NES_CQE_ALLOC_NOTIFY_SE = (1<<30),
NES_CQE_ALLOC_RESET = (1<<31),
};
enum nes_nic_rq_wqe_word_idx {
NES_NIC_RQ_WQE_LENGTH_1_0_IDX = 0,
NES_NIC_RQ_WQE_LENGTH_3_2_IDX = 1,
NES_NIC_RQ_WQE_FRAG0_LOW_IDX = 2,
NES_NIC_RQ_WQE_FRAG0_HIGH_IDX = 3,
NES_NIC_RQ_WQE_FRAG1_LOW_IDX = 4,
NES_NIC_RQ_WQE_FRAG1_HIGH_IDX = 5,
NES_NIC_RQ_WQE_FRAG2_LOW_IDX = 6,
NES_NIC_RQ_WQE_FRAG2_HIGH_IDX = 7,
NES_NIC_RQ_WQE_FRAG3_LOW_IDX = 8,
NES_NIC_RQ_WQE_FRAG3_HIGH_IDX = 9,
};
enum nes_nic_sq_wqe_word_idx {
NES_NIC_SQ_WQE_MISC_IDX = 0,
NES_NIC_SQ_WQE_TOTAL_LENGTH_IDX = 1,
NES_NIC_SQ_WQE_LSO_INFO_IDX = 2,
NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX = 3,
NES_NIC_SQ_WQE_LENGTH_2_1_IDX = 4,
NES_NIC_SQ_WQE_LENGTH_4_3_IDX = 5,
NES_NIC_SQ_WQE_FRAG0_LOW_IDX = 6,
NES_NIC_SQ_WQE_FRAG0_HIGH_IDX = 7,
NES_NIC_SQ_WQE_FRAG1_LOW_IDX = 8,
NES_NIC_SQ_WQE_FRAG1_HIGH_IDX = 9,
NES_NIC_SQ_WQE_FRAG2_LOW_IDX = 10,
NES_NIC_SQ_WQE_FRAG2_HIGH_IDX = 11,
NES_NIC_SQ_WQE_FRAG3_LOW_IDX = 12,
NES_NIC_SQ_WQE_FRAG3_HIGH_IDX = 13,
NES_NIC_SQ_WQE_FRAG4_LOW_IDX = 14,
NES_NIC_SQ_WQE_FRAG4_HIGH_IDX = 15,
};
enum nes_iwarp_sq_wqe_word_idx {
NES_IWARP_SQ_WQE_MISC_IDX = 0,
NES_IWARP_SQ_WQE_TOTAL_PAYLOAD_IDX = 1,
NES_IWARP_SQ_WQE_COMP_CTX_LOW_IDX = 2,
NES_IWARP_SQ_WQE_COMP_CTX_HIGH_IDX = 3,
NES_IWARP_SQ_WQE_COMP_SCRATCH_LOW_IDX = 4,
NES_IWARP_SQ_WQE_COMP_SCRATCH_HIGH_IDX = 5,
NES_IWARP_SQ_WQE_INV_STAG_LOW_IDX = 7,
NES_IWARP_SQ_WQE_RDMA_TO_LOW_IDX = 8,
NES_IWARP_SQ_WQE_RDMA_TO_HIGH_IDX = 9,
NES_IWARP_SQ_WQE_RDMA_LENGTH_IDX = 10,
NES_IWARP_SQ_WQE_RDMA_STAG_IDX = 11,
NES_IWARP_SQ_WQE_IMM_DATA_START_IDX = 12,
NES_IWARP_SQ_WQE_FRAG0_LOW_IDX = 16,
NES_IWARP_SQ_WQE_FRAG0_HIGH_IDX = 17,
NES_IWARP_SQ_WQE_LENGTH0_IDX = 18,
NES_IWARP_SQ_WQE_STAG0_IDX = 19,
NES_IWARP_SQ_WQE_FRAG1_LOW_IDX = 20,
NES_IWARP_SQ_WQE_FRAG1_HIGH_IDX = 21,
NES_IWARP_SQ_WQE_LENGTH1_IDX = 22,
NES_IWARP_SQ_WQE_STAG1_IDX = 23,
NES_IWARP_SQ_WQE_FRAG2_LOW_IDX = 24,
NES_IWARP_SQ_WQE_FRAG2_HIGH_IDX = 25,
NES_IWARP_SQ_WQE_LENGTH2_IDX = 26,
NES_IWARP_SQ_WQE_STAG2_IDX = 27,
NES_IWARP_SQ_WQE_FRAG3_LOW_IDX = 28,
NES_IWARP_SQ_WQE_FRAG3_HIGH_IDX = 29,
NES_IWARP_SQ_WQE_LENGTH3_IDX = 30,
NES_IWARP_SQ_WQE_STAG3_IDX = 31,
};
enum nes_iwarp_sq_bind_wqe_word_idx {
NES_IWARP_SQ_BIND_WQE_MR_IDX = 6,
NES_IWARP_SQ_BIND_WQE_MW_IDX = 7,
NES_IWARP_SQ_BIND_WQE_LENGTH_LOW_IDX = 8,
NES_IWARP_SQ_BIND_WQE_LENGTH_HIGH_IDX = 9,
NES_IWARP_SQ_BIND_WQE_VA_FBO_LOW_IDX = 10,
NES_IWARP_SQ_BIND_WQE_VA_FBO_HIGH_IDX = 11,
};
enum nes_iwarp_sq_fmr_wqe_word_idx {
NES_IWARP_SQ_FMR_WQE_MR_STAG_IDX = 7,
NES_IWARP_SQ_FMR_WQE_LENGTH_LOW_IDX = 8,
NES_IWARP_SQ_FMR_WQE_LENGTH_HIGH_IDX = 9,
NES_IWARP_SQ_FMR_WQE_VA_FBO_LOW_IDX = 10,
NES_IWARP_SQ_FMR_WQE_VA_FBO_HIGH_IDX = 11,
NES_IWARP_SQ_FMR_WQE_PBL_ADDR_LOW_IDX = 12,
NES_IWARP_SQ_FMR_WQE_PBL_ADDR_HIGH_IDX = 13,
NES_IWARP_SQ_FMR_WQE_PBL_LENGTH_IDX = 14,
};
enum nes_iwarp_sq_fmr_opcodes {
NES_IWARP_SQ_FMR_WQE_ZERO_BASED = (1<<6),
NES_IWARP_SQ_FMR_WQE_PAGE_SIZE_4K = (0<<7),
NES_IWARP_SQ_FMR_WQE_PAGE_SIZE_2M = (1<<7),
NES_IWARP_SQ_FMR_WQE_RIGHTS_ENABLE_LOCAL_READ = (1<<16),
NES_IWARP_SQ_FMR_WQE_RIGHTS_ENABLE_LOCAL_WRITE = (1<<17),
NES_IWARP_SQ_FMR_WQE_RIGHTS_ENABLE_REMOTE_READ = (1<<18),
NES_IWARP_SQ_FMR_WQE_RIGHTS_ENABLE_REMOTE_WRITE = (1<<19),
NES_IWARP_SQ_FMR_WQE_RIGHTS_ENABLE_WINDOW_BIND = (1<<20),
};
#define NES_IWARP_SQ_FMR_WQE_MR_LENGTH_HIGH_MASK 0xFF;
enum nes_iwarp_sq_locinv_wqe_word_idx {
NES_IWARP_SQ_LOCINV_WQE_INV_STAG_IDX = 6,
};
enum nes_iwarp_rq_wqe_word_idx {
NES_IWARP_RQ_WQE_TOTAL_PAYLOAD_IDX = 1,
NES_IWARP_RQ_WQE_COMP_CTX_LOW_IDX = 2,
NES_IWARP_RQ_WQE_COMP_CTX_HIGH_IDX = 3,
NES_IWARP_RQ_WQE_COMP_SCRATCH_LOW_IDX = 4,
NES_IWARP_RQ_WQE_COMP_SCRATCH_HIGH_IDX = 5,
NES_IWARP_RQ_WQE_FRAG0_LOW_IDX = 8,
NES_IWARP_RQ_WQE_FRAG0_HIGH_IDX = 9,
NES_IWARP_RQ_WQE_LENGTH0_IDX = 10,
NES_IWARP_RQ_WQE_STAG0_IDX = 11,
NES_IWARP_RQ_WQE_FRAG1_LOW_IDX = 12,
NES_IWARP_RQ_WQE_FRAG1_HIGH_IDX = 13,
NES_IWARP_RQ_WQE_LENGTH1_IDX = 14,
NES_IWARP_RQ_WQE_STAG1_IDX = 15,
NES_IWARP_RQ_WQE_FRAG2_LOW_IDX = 16,
NES_IWARP_RQ_WQE_FRAG2_HIGH_IDX = 17,
NES_IWARP_RQ_WQE_LENGTH2_IDX = 18,
NES_IWARP_RQ_WQE_STAG2_IDX = 19,
NES_IWARP_RQ_WQE_FRAG3_LOW_IDX = 20,
NES_IWARP_RQ_WQE_FRAG3_HIGH_IDX = 21,
NES_IWARP_RQ_WQE_LENGTH3_IDX = 22,
NES_IWARP_RQ_WQE_STAG3_IDX = 23,
};
enum nes_nic_sq_wqe_bits {
NES_NIC_SQ_WQE_PHDR_CS_READY = (1<<21),
NES_NIC_SQ_WQE_LSO_ENABLE = (1<<22),
NES_NIC_SQ_WQE_TAGVALUE_ENABLE = (1<<23),
NES_NIC_SQ_WQE_DISABLE_CHKSUM = (1<<30),
NES_NIC_SQ_WQE_COMPLETION = (1<<31),
};
enum nes_nic_cqe_word_idx {
NES_NIC_CQE_ACCQP_ID_IDX = 0,
NES_NIC_CQE_HASH_RCVNXT = 1,
NES_NIC_CQE_TAG_PKT_TYPE_IDX = 2,
NES_NIC_CQE_MISC_IDX = 3,
};
#define NES_PKT_TYPE_APBVT_BITS 0xC112
#define NES_PKT_TYPE_APBVT_MASK 0xff3e
#define NES_PKT_TYPE_PVALID_BITS 0x10000000
#define NES_PKT_TYPE_PVALID_MASK 0x30000000
#define NES_PKT_TYPE_TCPV4_BITS 0x0110
#define NES_PKT_TYPE_TCPV4_MASK 0x3f30
#define NES_PKT_TYPE_UDPV4_BITS 0x0210
#define NES_PKT_TYPE_UDPV4_MASK 0x3f30
#define NES_PKT_TYPE_IPV4_BITS 0x0010
#define NES_PKT_TYPE_IPV4_MASK 0x3f30
#define NES_PKT_TYPE_OTHER_BITS 0x0000
#define NES_PKT_TYPE_OTHER_MASK 0x0030
#define NES_NIC_CQE_ERRV_SHIFT 16
enum nes_nic_ev_bits {
NES_NIC_ERRV_BITS_MODE = (1<<0),
NES_NIC_ERRV_BITS_IPV4_CSUM_ERR = (1<<1),
NES_NIC_ERRV_BITS_TCPUDP_CSUM_ERR = (1<<2),
NES_NIC_ERRV_BITS_WQE_OVERRUN = (1<<3),
NES_NIC_ERRV_BITS_IPH_ERR = (1<<4),
};
enum nes_nic_cqe_bits {
NES_NIC_CQE_ERRV_MASK = (0xff<<NES_NIC_CQE_ERRV_SHIFT),
NES_NIC_CQE_SQ = (1<<24),
NES_NIC_CQE_ACCQP_PORT = (1<<28),
NES_NIC_CQE_ACCQP_VALID = (1<<29),
NES_NIC_CQE_TAG_VALID = (1<<30),
NES_NIC_CQE_VALID = (1<<31),
};
enum nes_aeqe_word_idx {
NES_AEQE_COMP_CTXT_LOW_IDX = 0,
NES_AEQE_COMP_CTXT_HIGH_IDX = 1,
NES_AEQE_COMP_QP_CQ_ID_IDX = 2,
NES_AEQE_MISC_IDX = 3,
};
enum nes_aeqe_bits {
NES_AEQE_QP = (1<<16),
NES_AEQE_CQ = (1<<17),
NES_AEQE_SQ = (1<<18),
NES_AEQE_INBOUND_RDMA = (1<<19),
NES_AEQE_IWARP_STATE_MASK = (7<<20),
NES_AEQE_TCP_STATE_MASK = (0xf<<24),
NES_AEQE_Q2_DATA_WRITTEN = (0x3<<28),
NES_AEQE_VALID = (1<<31),
};
#define NES_AEQE_IWARP_STATE_SHIFT 20
#define NES_AEQE_TCP_STATE_SHIFT 24
#define NES_AEQE_Q2_DATA_ETHERNET (1<<28)
#define NES_AEQE_Q2_DATA_MPA (1<<29)
enum nes_aeqe_iwarp_state {
NES_AEQE_IWARP_STATE_NON_EXISTANT = 0,
NES_AEQE_IWARP_STATE_IDLE = 1,
NES_AEQE_IWARP_STATE_RTS = 2,
NES_AEQE_IWARP_STATE_CLOSING = 3,
NES_AEQE_IWARP_STATE_TERMINATE = 5,
NES_AEQE_IWARP_STATE_ERROR = 6
};
enum nes_aeqe_tcp_state {
NES_AEQE_TCP_STATE_NON_EXISTANT = 0,
NES_AEQE_TCP_STATE_CLOSED = 1,
NES_AEQE_TCP_STATE_LISTEN = 2,
NES_AEQE_TCP_STATE_SYN_SENT = 3,
NES_AEQE_TCP_STATE_SYN_RCVD = 4,
NES_AEQE_TCP_STATE_ESTABLISHED = 5,
NES_AEQE_TCP_STATE_CLOSE_WAIT = 6,
NES_AEQE_TCP_STATE_FIN_WAIT_1 = 7,
NES_AEQE_TCP_STATE_CLOSING = 8,
NES_AEQE_TCP_STATE_LAST_ACK = 9,
NES_AEQE_TCP_STATE_FIN_WAIT_2 = 10,
NES_AEQE_TCP_STATE_TIME_WAIT = 11
};
enum nes_aeqe_aeid {
NES_AEQE_AEID_AMP_UNALLOCATED_STAG = 0x0102,
NES_AEQE_AEID_AMP_INVALID_STAG = 0x0103,
NES_AEQE_AEID_AMP_BAD_QP = 0x0104,
NES_AEQE_AEID_AMP_BAD_PD = 0x0105,
NES_AEQE_AEID_AMP_BAD_STAG_KEY = 0x0106,
NES_AEQE_AEID_AMP_BAD_STAG_INDEX = 0x0107,
NES_AEQE_AEID_AMP_BOUNDS_VIOLATION = 0x0108,
NES_AEQE_AEID_AMP_RIGHTS_VIOLATION = 0x0109,
NES_AEQE_AEID_AMP_TO_WRAP = 0x010a,
NES_AEQE_AEID_AMP_FASTREG_SHARED = 0x010b,
NES_AEQE_AEID_AMP_FASTREG_VALID_STAG = 0x010c,
NES_AEQE_AEID_AMP_FASTREG_MW_STAG = 0x010d,
NES_AEQE_AEID_AMP_FASTREG_INVALID_RIGHTS = 0x010e,
NES_AEQE_AEID_AMP_FASTREG_PBL_TABLE_OVERFLOW = 0x010f,
NES_AEQE_AEID_AMP_FASTREG_INVALID_LENGTH = 0x0110,
NES_AEQE_AEID_AMP_INVALIDATE_SHARED = 0x0111,
NES_AEQE_AEID_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS = 0x0112,
NES_AEQE_AEID_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS = 0x0113,
NES_AEQE_AEID_AMP_MWBIND_VALID_STAG = 0x0114,
NES_AEQE_AEID_AMP_MWBIND_OF_MR_STAG = 0x0115,
NES_AEQE_AEID_AMP_MWBIND_TO_ZERO_BASED_STAG = 0x0116,
NES_AEQE_AEID_AMP_MWBIND_TO_MW_STAG = 0x0117,
NES_AEQE_AEID_AMP_MWBIND_INVALID_RIGHTS = 0x0118,
NES_AEQE_AEID_AMP_MWBIND_INVALID_BOUNDS = 0x0119,
NES_AEQE_AEID_AMP_MWBIND_TO_INVALID_PARENT = 0x011a,
NES_AEQE_AEID_AMP_MWBIND_BIND_DISABLED = 0x011b,
NES_AEQE_AEID_BAD_CLOSE = 0x0201,
NES_AEQE_AEID_RDMAP_ROE_BAD_LLP_CLOSE = 0x0202,
NES_AEQE_AEID_CQ_OPERATION_ERROR = 0x0203,
NES_AEQE_AEID_PRIV_OPERATION_DENIED = 0x0204,
NES_AEQE_AEID_RDMA_READ_WHILE_ORD_ZERO = 0x0205,
NES_AEQE_AEID_STAG_ZERO_INVALID = 0x0206,
NES_AEQE_AEID_DDP_INVALID_MSN_GAP_IN_MSN = 0x0301,
NES_AEQE_AEID_DDP_INVALID_MSN_RANGE_IS_NOT_VALID = 0x0302,
NES_AEQE_AEID_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER = 0x0303,
NES_AEQE_AEID_DDP_UBE_INVALID_DDP_VERSION = 0x0304,
NES_AEQE_AEID_DDP_UBE_INVALID_MO = 0x0305,
NES_AEQE_AEID_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE = 0x0306,
NES_AEQE_AEID_DDP_UBE_INVALID_QN = 0x0307,
NES_AEQE_AEID_DDP_NO_L_BIT = 0x0308,
NES_AEQE_AEID_RDMAP_ROE_INVALID_RDMAP_VERSION = 0x0311,
NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE = 0x0312,
NES_AEQE_AEID_ROE_INVALID_RDMA_READ_REQUEST = 0x0313,
NES_AEQE_AEID_ROE_INVALID_RDMA_WRITE_OR_READ_RESP = 0x0314,
NES_AEQE_AEID_INVALID_ARP_ENTRY = 0x0401,
NES_AEQE_AEID_INVALID_TCP_OPTION_RCVD = 0x0402,
NES_AEQE_AEID_STALE_ARP_ENTRY = 0x0403,
NES_AEQE_AEID_LLP_CLOSE_COMPLETE = 0x0501,
NES_AEQE_AEID_LLP_CONNECTION_RESET = 0x0502,
NES_AEQE_AEID_LLP_FIN_RECEIVED = 0x0503,
NES_AEQE_AEID_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH = 0x0504,
NES_AEQE_AEID_LLP_RECEIVED_MPA_CRC_ERROR = 0x0505,
NES_AEQE_AEID_LLP_SEGMENT_TOO_LARGE = 0x0506,
NES_AEQE_AEID_LLP_SEGMENT_TOO_SMALL = 0x0507,
NES_AEQE_AEID_LLP_SYN_RECEIVED = 0x0508,
NES_AEQE_AEID_LLP_TERMINATE_RECEIVED = 0x0509,
NES_AEQE_AEID_LLP_TOO_MANY_RETRIES = 0x050a,
NES_AEQE_AEID_LLP_TOO_MANY_KEEPALIVE_RETRIES = 0x050b,
NES_AEQE_AEID_RESET_SENT = 0x0601,
NES_AEQE_AEID_TERMINATE_SENT = 0x0602,
NES_AEQE_AEID_DDP_LCE_LOCAL_CATASTROPHIC = 0x0700
};
enum nes_iwarp_sq_opcodes {
NES_IWARP_SQ_WQE_WRPDU = (1<<15),
NES_IWARP_SQ_WQE_PSH = (1<<21),
NES_IWARP_SQ_WQE_STREAMING = (1<<23),
NES_IWARP_SQ_WQE_IMM_DATA = (1<<28),
NES_IWARP_SQ_WQE_READ_FENCE = (1<<29),
NES_IWARP_SQ_WQE_LOCAL_FENCE = (1<<30),
NES_IWARP_SQ_WQE_SIGNALED_COMPL = (1<<31),
};
enum nes_iwarp_sq_wqe_bits {
NES_IWARP_SQ_OP_RDMAW = 0,
NES_IWARP_SQ_OP_RDMAR = 1,
NES_IWARP_SQ_OP_SEND = 3,
NES_IWARP_SQ_OP_SENDINV = 4,
NES_IWARP_SQ_OP_SENDSE = 5,
NES_IWARP_SQ_OP_SENDSEINV = 6,
NES_IWARP_SQ_OP_BIND = 8,
NES_IWARP_SQ_OP_FAST_REG = 9,
NES_IWARP_SQ_OP_LOCINV = 10,
NES_IWARP_SQ_OP_RDMAR_LOCINV = 11,
NES_IWARP_SQ_OP_NOP = 12,
};
enum nes_iwarp_cqe_major_code {
NES_IWARP_CQE_MAJOR_FLUSH = 1,
NES_IWARP_CQE_MAJOR_DRV = 0x8000
};
enum nes_iwarp_cqe_minor_code {
NES_IWARP_CQE_MINOR_FLUSH = 1
};
#define NES_EEPROM_READ_REQUEST (1<<16)
#define NES_MAC_ADDR_VALID (1<<20)
/*
* NES index registers init values.
*/
struct nes_init_values {
u32 index;
u32 data;
u8 wrt;
};
/*
* NES registers in BAR0.
*/
struct nes_pci_regs {
u32 int_status;
u32 int_mask;
u32 int_pending;
u32 intf_int_status;
u32 intf_int_mask;
u32 other_regs[59]; /* pad out to 256 bytes for now */
};
#define NES_CQP_SQ_SIZE 128
#define NES_CCQ_SIZE 128
#define NES_NIC_WQ_SIZE 512
#define NES_NIC_CTX_SIZE ((NES_NIC_CTX_RQ_SIZE_512) | (NES_NIC_CTX_SQ_SIZE_512))
#define NES_NIC_BACK_STORE 0x00038000
struct nes_device;
struct nes_hw_nic_qp_context {
__le32 context_words[6];
};
struct nes_hw_nic_sq_wqe {
__le32 wqe_words[16];
};
struct nes_hw_nic_rq_wqe {
__le32 wqe_words[16];
};
struct nes_hw_nic_cqe {
__le32 cqe_words[4];
};
struct nes_hw_cqp_qp_context {
__le32 context_words[4];
};
struct nes_hw_cqp_wqe {
__le32 wqe_words[16];
};
struct nes_hw_qp_wqe {
__le32 wqe_words[32];
};
struct nes_hw_cqe {
__le32 cqe_words[8];
};
struct nes_hw_ceqe {
__le32 ceqe_words[2];
};
struct nes_hw_aeqe {
__le32 aeqe_words[4];
};
struct nes_cqp_request {
union {
u64 cqp_callback_context;
void *cqp_callback_pointer;
};
wait_queue_head_t waitq;
struct nes_hw_cqp_wqe cqp_wqe;
struct list_head list;
atomic_t refcount;
void (*cqp_callback)(struct nes_device *nesdev, struct nes_cqp_request *cqp_request);
u16 major_code;
u16 minor_code;
u8 waiting;
u8 request_done;
u8 dynamic;
u8 callback;
};
struct nes_hw_cqp {
struct nes_hw_cqp_wqe *sq_vbase;
dma_addr_t sq_pbase;
spinlock_t lock;
wait_queue_head_t waitq;
u16 qp_id;
u16 sq_head;
u16 sq_tail;
u16 sq_size;
};
#define NES_FIRST_FRAG_SIZE 128
struct nes_first_frag {
u8 buffer[NES_FIRST_FRAG_SIZE];
};
struct nes_hw_nic {
struct nes_first_frag *first_frag_vbase; /* virtual address of first frags */
struct nes_hw_nic_sq_wqe *sq_vbase; /* virtual address of sq */
struct nes_hw_nic_rq_wqe *rq_vbase; /* virtual address of rq */
struct sk_buff *tx_skb[NES_NIC_WQ_SIZE];
struct sk_buff *rx_skb[NES_NIC_WQ_SIZE];
dma_addr_t frag_paddr[NES_NIC_WQ_SIZE];
unsigned long first_frag_overflow[BITS_TO_LONGS(NES_NIC_WQ_SIZE)];
dma_addr_t sq_pbase; /* PCI memory for host rings */
dma_addr_t rq_pbase; /* PCI memory for host rings */
u16 qp_id;
u16 sq_head;
u16 sq_tail;
u16 sq_size;
u16 rq_head;
u16 rq_tail;
u16 rq_size;
u8 replenishing_rq;
u8 reserved;
spinlock_t rq_lock;
};
struct nes_hw_nic_cq {
struct nes_hw_nic_cqe volatile *cq_vbase; /* PCI memory for host rings */
void (*ce_handler)(struct nes_device *nesdev, struct nes_hw_nic_cq *cq);
dma_addr_t cq_pbase; /* PCI memory for host rings */
int rx_cqes_completed;
int cqe_allocs_pending;
int rx_pkts_indicated;
u16 cq_head;
u16 cq_size;
u16 cq_number;
u8 cqes_pending;
};
struct nes_hw_qp {
struct nes_hw_qp_wqe *sq_vbase; /* PCI memory for host rings */
struct nes_hw_qp_wqe *rq_vbase; /* PCI memory for host rings */
void *q2_vbase; /* PCI memory for host rings */
dma_addr_t sq_pbase; /* PCI memory for host rings */
dma_addr_t rq_pbase; /* PCI memory for host rings */
dma_addr_t q2_pbase; /* PCI memory for host rings */
u32 qp_id;
u16 sq_head;
u16 sq_tail;
u16 sq_size;
u16 rq_head;
u16 rq_tail;
u16 rq_size;
u8 rq_encoded_size;
u8 sq_encoded_size;
};
struct nes_hw_cq {
struct nes_hw_cqe *cq_vbase; /* PCI memory for host rings */
void (*ce_handler)(struct nes_device *nesdev, struct nes_hw_cq *cq);
dma_addr_t cq_pbase; /* PCI memory for host rings */
u16 cq_head;
u16 cq_size;
u16 cq_number;
};
struct nes_hw_ceq {
struct nes_hw_ceqe volatile *ceq_vbase; /* PCI memory for host rings */
dma_addr_t ceq_pbase; /* PCI memory for host rings */
u16 ceq_head;
u16 ceq_size;
};
struct nes_hw_aeq {
struct nes_hw_aeqe volatile *aeq_vbase; /* PCI memory for host rings */
dma_addr_t aeq_pbase; /* PCI memory for host rings */
u16 aeq_head;
u16 aeq_size;
};
struct nic_qp_map {
u8 qpid;
u8 nic_index;
u8 logical_port;
u8 is_hnic;
};
#define NES_CQP_ARP_AEQ_INDEX_MASK 0x000f0000
#define NES_CQP_ARP_AEQ_INDEX_SHIFT 16
#define NES_CQP_APBVT_ADD 0x00008000
#define NES_CQP_APBVT_NIC_SHIFT 16
#define NES_ARP_ADD 1
#define NES_ARP_DELETE 2
#define NES_ARP_RESOLVE 3
#define NES_MAC_SW_IDLE 0
#define NES_MAC_SW_INTERRUPT 1
#define NES_MAC_SW_MH 2
struct nes_arp_entry {
u32 ip_addr;
u8 mac_addr[ETH_ALEN];
};
#define NES_NIC_FAST_TIMER 96
#define NES_NIC_FAST_TIMER_LOW 40
#define NES_NIC_FAST_TIMER_HIGH 1000
#define DEFAULT_NES_QL_HIGH 256
#define DEFAULT_NES_QL_LOW 16
#define DEFAULT_NES_QL_TARGET 64
#define DEFAULT_JUMBO_NES_QL_LOW 12
#define DEFAULT_JUMBO_NES_QL_TARGET 40
#define DEFAULT_JUMBO_NES_QL_HIGH 128
#define NES_NIC_CQ_DOWNWARD_TREND 16
#define NES_PFT_SIZE 48
#define NES_MGT_WQ_COUNT 32
#define NES_MGT_CTX_SIZE ((NES_NIC_CTX_RQ_SIZE_32) | (NES_NIC_CTX_SQ_SIZE_32))
#define NES_MGT_QP_OFFSET 36
#define NES_MGT_QP_COUNT 4
struct nes_hw_tune_timer {
/* u16 cq_count; */
u16 threshold_low;
u16 threshold_target;
u16 threshold_high;
u16 timer_in_use;
u16 timer_in_use_old;
u16 timer_in_use_min;
u16 timer_in_use_max;
u8 timer_direction_upward;
u8 timer_direction_downward;
u16 cq_count_old;
u8 cq_direction_downward;
};
#define NES_TIMER_INT_LIMIT 2
#define NES_TIMER_INT_LIMIT_DYNAMIC 10
#define NES_TIMER_ENABLE_LIMIT 4
#define NES_MAX_LINK_INTERRUPTS 128
#define NES_MAX_LINK_CHECK 200
struct nes_adapter {
u64 fw_ver;
unsigned long *allocated_qps;
unsigned long *allocated_cqs;
unsigned long *allocated_mrs;
unsigned long *allocated_pds;
unsigned long *allocated_arps;
struct nes_qp **qp_table;
struct workqueue_struct *work_q;
struct list_head list;
struct list_head active_listeners;
/* list of the netdev's associated with each logical port */
struct list_head nesvnic_list[4];
struct timer_list mh_timer;
struct timer_list lc_timer;
struct work_struct work;
spinlock_t resource_lock;
spinlock_t phy_lock;
spinlock_t pbl_lock;
spinlock_t periodic_timer_lock;
struct nes_arp_entry arp_table[NES_MAX_ARP_TABLE_SIZE];
/* Adapter CEQ and AEQs */
struct nes_hw_ceq ceq[16];
struct nes_hw_aeq aeq[8];
struct nes_hw_tune_timer tune_timer;
unsigned long doorbell_start;
u32 hw_rev;
u32 vendor_id;
u32 vendor_part_id;
u32 device_cap_flags;
u32 tick_delta;
u32 timer_int_req;
u32 arp_table_size;
u32 next_arp_index;
u32 max_mr;
u32 max_256pbl;
u32 max_4kpbl;
u32 free_256pbl;
u32 free_4kpbl;
u32 max_mr_size;
u32 max_qp;
u32 next_qp;
u32 max_irrq;
u32 max_qp_wr;
u32 max_sge;
u32 max_cq;
u32 next_cq;
u32 max_cqe;
u32 max_pd;
u32 base_pd;
u32 next_pd;
u32 hte_index_mask;
/* EEPROM information */
u32 rx_pool_size;
u32 tx_pool_size;
u32 rx_threshold;
u32 tcp_timer_core_clk_divisor;
u32 iwarp_config;
u32 cm_config;
u32 sws_timer_config;
u32 tcp_config1;
u32 wqm_wat;
u32 core_clock;
u32 firmware_version;
u32 eeprom_version;
u32 nic_rx_eth_route_err;
u32 et_rx_coalesce_usecs;
u32 et_rx_max_coalesced_frames;
u32 et_rx_coalesce_usecs_irq;
u32 et_rx_max_coalesced_frames_irq;
u32 et_pkt_rate_low;
u32 et_rx_coalesce_usecs_low;
u32 et_rx_max_coalesced_frames_low;
u32 et_pkt_rate_high;
u32 et_rx_coalesce_usecs_high;
u32 et_rx_max_coalesced_frames_high;
u32 et_rate_sample_interval;
u32 timer_int_limit;
u32 wqm_quanta;
u8 allow_unaligned_fpdus;
/* Adapter base MAC address */
u32 mac_addr_low;
u16 mac_addr_high;
u16 firmware_eeprom_offset;
u16 software_eeprom_offset;
u16 max_irrq_wr;
/* pd config for each port */
u16 pd_config_size[4];
u16 pd_config_base[4];
u16 link_interrupt_count[4];
u8 crit_error_count[32];
/* the phy index for each port */
u8 phy_index[4];
u8 mac_sw_state[4];
u8 mac_link_down[4];
u8 phy_type[4];
u8 log_port;
/* PCI information */
struct nes_device *nesdev;
unsigned int devfn;
unsigned char bus_number;
unsigned char OneG_Mode;
unsigned char ref_count;
u8 netdev_count;
u8 netdev_max; /* from host nic address count in EEPROM */
u8 port_count;
u8 virtwq;
u8 send_term_ok;
u8 et_use_adaptive_rx_coalesce;
u8 adapter_fcn_count;
u8 pft_mcast_map[NES_PFT_SIZE];
};
struct nes_pbl {
u64 *pbl_vbase;
dma_addr_t pbl_pbase;
struct page *page;
unsigned long user_base;
u32 pbl_size;
struct list_head list;
/* TODO: need to add list for two level tables */
};
#define NES_4K_PBL_CHUNK_SIZE 4096
struct nes_fast_mr_wqe_pbl {
u64 *kva;
dma_addr_t paddr;
};
struct nes_listener {
struct work_struct work;
struct workqueue_struct *wq;
struct nes_vnic *nesvnic;
struct iw_cm_id *cm_id;
struct list_head list;
unsigned long socket;
u8 accept_failed;
};
struct nes_ib_device;
#define NES_EVENT_DELAY msecs_to_jiffies(100)
struct nes_vnic {
struct nes_ib_device *nesibdev;
u64 sq_full;
u64 tso_requests;
u64 segmented_tso_requests;
u64 linearized_skbs;
u64 tx_sw_dropped;
u64 endnode_nstat_rx_discard;
u64 endnode_nstat_rx_octets;
u64 endnode_nstat_rx_frames;
u64 endnode_nstat_tx_octets;
u64 endnode_nstat_tx_frames;
u64 endnode_ipv4_tcp_retransmits;
/* void *mem; */
struct nes_device *nesdev;
struct net_device *netdev;
atomic_t rx_skbs_needed;
atomic_t rx_skb_timer_running;
int budget;
u32 msg_enable;
/* u32 tx_avail; */
__be32 local_ipaddr;
struct napi_struct napi;
spinlock_t tx_lock; /* could use netdev tx lock? */
struct timer_list rq_wqes_timer;
u32 nic_mem_size;
void *nic_vbase;
dma_addr_t nic_pbase;
struct nes_hw_nic nic;
struct nes_hw_nic_cq nic_cq;
u32 mcrq_qp_id;
struct nes_ucontext *mcrq_ucontext;
struct nes_cqp_request* (*get_cqp_request)(struct nes_device *nesdev);
void (*post_cqp_request)(struct nes_device*, struct nes_cqp_request *);
int (*mcrq_mcast_filter)( struct nes_vnic* nesvnic, __u8* dmi_addr );
struct net_device_stats netstats;
/* used to put the netdev on the adapters logical port list */
struct list_head list;
u16 max_frame_size;
u8 netdev_open;
u8 linkup;
u8 logical_port;
u8 netdev_index; /* might not be needed, indexes nesdev->netdev */
u8 perfect_filter_index;
u8 nic_index;
u8 qp_nic_index[4];
u8 next_qp_nic_index;
u8 of_device_registered;
u8 rdma_enabled;
struct timer_list event_timer;
enum ib_event_type delayed_event;
enum ib_event_type last_dispatched_event;
spinlock_t port_ibevent_lock;
u32 mgt_mem_size;
void *mgt_vbase;
dma_addr_t mgt_pbase;
struct nes_vnic_mgt *mgtvnic[NES_MGT_QP_COUNT];
struct task_struct *mgt_thread;
wait_queue_head_t mgt_wait_queue;
struct sk_buff_head mgt_skb_list;
};
struct nes_ib_device {
struct ib_device ibdev;
struct nes_vnic *nesvnic;
/* Virtual RNIC Limits */
u32 max_mr;
u32 max_qp;
u32 max_cq;
u32 max_pd;
u32 num_mr;
u32 num_qp;
u32 num_cq;
u32 num_pd;
};
enum nes_hdrct_flags {
DDP_LEN_FLAG = 0x80,
DDP_HDR_FLAG = 0x40,
RDMA_HDR_FLAG = 0x20
};
enum nes_term_layers {
LAYER_RDMA = 0,
LAYER_DDP = 1,
LAYER_MPA = 2
};
enum nes_term_error_types {
RDMAP_CATASTROPHIC = 0,
RDMAP_REMOTE_PROT = 1,
RDMAP_REMOTE_OP = 2,
DDP_CATASTROPHIC = 0,
DDP_TAGGED_BUFFER = 1,
DDP_UNTAGGED_BUFFER = 2,
DDP_LLP = 3
};
enum nes_term_rdma_errors {
RDMAP_INV_STAG = 0x00,
RDMAP_INV_BOUNDS = 0x01,
RDMAP_ACCESS = 0x02,
RDMAP_UNASSOC_STAG = 0x03,
RDMAP_TO_WRAP = 0x04,
RDMAP_INV_RDMAP_VER = 0x05,
RDMAP_UNEXPECTED_OP = 0x06,
RDMAP_CATASTROPHIC_LOCAL = 0x07,
RDMAP_CATASTROPHIC_GLOBAL = 0x08,
RDMAP_CANT_INV_STAG = 0x09,
RDMAP_UNSPECIFIED = 0xff
};
enum nes_term_ddp_errors {
DDP_CATASTROPHIC_LOCAL = 0x00,
DDP_TAGGED_INV_STAG = 0x00,
DDP_TAGGED_BOUNDS = 0x01,
DDP_TAGGED_UNASSOC_STAG = 0x02,
DDP_TAGGED_TO_WRAP = 0x03,
DDP_TAGGED_INV_DDP_VER = 0x04,
DDP_UNTAGGED_INV_QN = 0x01,
DDP_UNTAGGED_INV_MSN_NO_BUF = 0x02,
DDP_UNTAGGED_INV_MSN_RANGE = 0x03,
DDP_UNTAGGED_INV_MO = 0x04,
DDP_UNTAGGED_INV_TOO_LONG = 0x05,
DDP_UNTAGGED_INV_DDP_VER = 0x06
};
enum nes_term_mpa_errors {
MPA_CLOSED = 0x01,
MPA_CRC = 0x02,
MPA_MARKER = 0x03,
MPA_REQ_RSP = 0x04,
};
struct nes_terminate_hdr {
u8 layer_etype;
u8 error_code;
u8 hdrct;
u8 rsvd;
};
/* Used to determine how to fill in terminate error codes */
#define IWARP_OPCODE_WRITE 0
#define IWARP_OPCODE_READREQ 1
#define IWARP_OPCODE_READRSP 2
#define IWARP_OPCODE_SEND 3
#define IWARP_OPCODE_SEND_INV 4
#define IWARP_OPCODE_SEND_SE 5
#define IWARP_OPCODE_SEND_SE_INV 6
#define IWARP_OPCODE_TERM 7
/* These values are used only during terminate processing */
#define TERM_DDP_LEN_TAGGED 14
#define TERM_DDP_LEN_UNTAGGED 18
#define TERM_RDMA_LEN 28
#define RDMA_OPCODE_MASK 0x0f
#define RDMA_READ_REQ_OPCODE 1
#define BAD_FRAME_OFFSET 64
#define CQE_MAJOR_DRV 0x8000
/* Used for link status recheck after interrupt processing */
#define NES_LINK_RECHECK_DELAY msecs_to_jiffies(50)
#define NES_LINK_RECHECK_MAX 60
#endif /* __NES_HW_H */
drivers/infiniband/hw/nes/nes_mgt.c deleted 100644 → 0
View file @ cbdc666f
/*
* Copyright (c) 2006 - 2011 Intel-NE, Inc. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
*/
#include <linux/skbuff.h>
#include <linux/etherdevice.h>
#include <linux/kthread.h>
#include <linux/ip.h>
#include <linux/tcp.h>
#include <net/tcp.h>
#include "nes.h"
#include "nes_mgt.h"
atomic_t pau_qps_created;
atomic_t pau_qps_destroyed;
static void nes_replenish_mgt_rq(struct nes_vnic_mgt *mgtvnic)
{
unsigned long flags;
dma_addr_t bus_address;
struct sk_buff *skb;
struct nes_hw_nic_rq_wqe *nic_rqe;
struct nes_hw_mgt *nesmgt;
struct nes_device *nesdev;
struct nes_rskb_cb *cb;
u32 rx_wqes_posted = 0;
nesmgt = &mgtvnic->mgt;
nesdev = mgtvnic->nesvnic->nesdev;
spin_lock_irqsave(&nesmgt->rq_lock, flags);
if (nesmgt->replenishing_rq != 0) {
if (((nesmgt->rq_size - 1) == atomic_read(&mgtvnic->rx_skbs_needed)) &&
(atomic_read(&mgtvnic->rx_skb_timer_running) == 0)) {
atomic_set(&mgtvnic->rx_skb_timer_running, 1);
spin_unlock_irqrestore(&nesmgt->rq_lock, flags);
mgtvnic->rq_wqes_timer.expires = jiffies + (HZ / 2); /* 1/2 second */
add_timer(&mgtvnic->rq_wqes_timer);
} else {
spin_unlock_irqrestore(&nesmgt->rq_lock, flags);
}
return;
}
nesmgt->replenishing_rq = 1;
spin_unlock_irqrestore(&nesmgt->rq_lock, flags);
do {
skb = dev_alloc_skb(mgtvnic->nesvnic->max_frame_size);
if (skb) {
skb->dev = mgtvnic->nesvnic->netdev;
bus_address = pci_map_single(nesdev->pcidev,
skb->data, mgtvnic->nesvnic->max_frame_size, PCI_DMA_FROMDEVICE);
cb = (struct nes_rskb_cb *)&skb->cb[0];
cb->busaddr = bus_address;
cb->maplen = mgtvnic->nesvnic->max_frame_size;
nic_rqe = &nesmgt->rq_vbase[mgtvnic->mgt.rq_head];
nic_rqe->wqe_words[NES_NIC_RQ_WQE_LENGTH_1_0_IDX] =
cpu_to_le32(mgtvnic->nesvnic->max_frame_size);
nic_rqe->wqe_words[NES_NIC_RQ_WQE_LENGTH_3_2_IDX] = 0;
nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_LOW_IDX] =
cpu_to_le32((u32)bus_address);
nic_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_HIGH_IDX] =
cpu_to_le32((u32)((u64)bus_address >> 32));
nesmgt->rx_skb[nesmgt->rq_head] = skb;
nesmgt->rq_head++;
nesmgt->rq_head &= nesmgt->rq_size - 1;
atomic_dec(&mgtvnic->rx_skbs_needed);
barrier();
if (++rx_wqes_posted == 255) {
nes_write32(nesdev->regs + NES_WQE_ALLOC, (rx_wqes_posted << 24) | nesmgt->qp_id);
rx_wqes_posted = 0;
}
} else {
spin_lock_irqsave(&nesmgt->rq_lock, flags);
if (((nesmgt->rq_size - 1) == atomic_read(&mgtvnic->rx_skbs_needed)) &&
(atomic_read(&mgtvnic->rx_skb_timer_running) == 0)) {
atomic_set(&mgtvnic->rx_skb_timer_running, 1);
spin_unlock_irqrestore(&nesmgt->rq_lock, flags);
mgtvnic->rq_wqes_timer.expires = jiffies + (HZ / 2); /* 1/2 second */
add_timer(&mgtvnic->rq_wqes_timer);
} else {
spin_unlock_irqrestore(&nesmgt->rq_lock, flags);
}
break;
}
} while (atomic_read(&mgtvnic->rx_skbs_needed));
barrier();
if (rx_wqes_posted)
nes_write32(nesdev->regs + NES_WQE_ALLOC, (rx_wqes_posted << 24) | nesmgt->qp_id);
nesmgt->replenishing_rq = 0;
}
/**
* nes_mgt_rq_wqes_timeout
*/
static void nes_mgt_rq_wqes_timeout(struct timer_list *t)
{
struct nes_vnic_mgt *mgtvnic = from_timer(mgtvnic, t,
rq_wqes_timer);
atomic_set(&mgtvnic->rx_skb_timer_running, 0);
if (atomic_read(&mgtvnic->rx_skbs_needed))
nes_replenish_mgt_rq(mgtvnic);
}
/**
* nes_mgt_free_skb - unmap and free skb
*/
static void nes_mgt_free_skb(struct nes_device *nesdev, struct sk_buff *skb, u32 dir)
{
struct nes_rskb_cb *cb;
cb = (struct nes_rskb_cb *)&skb->cb[0];
pci_unmap_single(nesdev->pcidev, cb->busaddr, cb->maplen, dir);
cb->busaddr = 0;
dev_kfree_skb_any(skb);
}
/**
* nes_download_callback - handle download completions
*/
static void nes_download_callback(struct nes_device *nesdev, struct nes_cqp_request *cqp_request)
{
struct pau_fpdu_info *fpdu_info = cqp_request->cqp_callback_pointer;
struct nes_qp *nesqp = fpdu_info->nesqp;
struct sk_buff *skb;
int i;
for (i = 0; i < fpdu_info->frag_cnt; i++) {
skb = fpdu_info->frags[i].skb;
if (fpdu_info->frags[i].cmplt) {
nes_mgt_free_skb(nesdev, skb, PCI_DMA_TODEVICE);
nes_rem_ref_cm_node(nesqp->cm_node);
}
}
if (fpdu_info->hdr_vbase)
pci_free_consistent(nesdev->pcidev, fpdu_info->hdr_len,
fpdu_info->hdr_vbase, fpdu_info->hdr_pbase);
kfree(fpdu_info);
}
/**
* nes_get_seq - Get the seq, ack_seq and window from the packet
*/
static u32 nes_get_seq(struct sk_buff *skb, u32 *ack, u16 *wnd, u32 *fin_rcvd, u32 *rst_rcvd)
{
struct nes_rskb_cb *cb = (struct nes_rskb_cb *)&skb->cb[0];
struct iphdr *iph = (struct iphdr *)(cb->data_start + ETH_HLEN);
struct tcphdr *tcph = (struct tcphdr *)(((char *)iph) + (4 * iph->ihl));
*ack = be32_to_cpu(tcph->ack_seq);
*wnd = be16_to_cpu(tcph->window);
*fin_rcvd = tcph->fin;
*rst_rcvd = tcph->rst;
return be32_to_cpu(tcph->seq);
}
/**
* nes_get_next_skb - Get the next skb based on where current skb is in the queue
*/
static struct sk_buff *nes_get_next_skb(struct nes_device *nesdev, struct nes_qp *nesqp,
struct sk_buff *skb, u32 nextseq, u32 *ack,
u16 *wnd, u32 *fin_rcvd, u32 *rst_rcvd)
{
u32 seq;
bool processacks;
struct sk_buff *old_skb;
if (skb) {
/* Continue processing fpdu */
skb = skb_peek_next(skb, &nesqp->pau_list);
if (!skb)
goto out;
processacks = false;
} else {
/* Starting a new one */
if (skb_queue_empty(&nesqp->pau_list))
goto out;
skb = skb_peek(&nesqp->pau_list);
processacks = true;
}
while (1) {
if (skb_queue_empty(&nesqp->pau_list))
goto out;
seq = nes_get_seq(skb, ack, wnd, fin_rcvd, rst_rcvd);
if (seq == nextseq) {
if (skb->len || processacks)
break;
} else if (after(seq, nextseq)) {
goto out;
}
old_skb = skb;
skb = skb_peek_next(skb, &nesqp->pau_list);
skb_unlink(old_skb, &nesqp->pau_list);
nes_mgt_free_skb(nesdev, old_skb, PCI_DMA_TODEVICE);
nes_rem_ref_cm_node(nesqp->cm_node);
if (!skb)
goto out;
}
return skb;
out:
return NULL;
}
/**
* get_fpdu_info - Find the next complete fpdu and return its fragments.
*/
static int get_fpdu_info(struct nes_device *nesdev, struct nes_qp *nesqp,
struct pau_fpdu_info **pau_fpdu_info)
{
struct sk_buff *skb;
struct iphdr *iph;
struct tcphdr *tcph;
struct nes_rskb_cb *cb;
struct pau_fpdu_info *fpdu_info = NULL;
struct pau_fpdu_frag frags[MAX_FPDU_FRAGS];
u32 fpdu_len = 0;
u32 tmp_len;
int frag_cnt = 0;
u32 tot_len;
u32 frag_tot;
u32 ack;
u32 fin_rcvd;
u32 rst_rcvd;
u16 wnd;
int i;
int rc = 0;
*pau_fpdu_info = NULL;
skb = nes_get_next_skb(nesdev, nesqp, NULL, nesqp->pau_rcv_nxt, &ack, &wnd, &fin_rcvd, &rst_rcvd);
if (!skb)
goto out;
cb = (struct nes_rskb_cb *)&skb->cb[0];
if (skb->len) {
fpdu_len = be16_to_cpu(*(__be16 *) skb->data) + MPA_FRAMING;
fpdu_len = (fpdu_len + 3) & 0xfffffffc;
tmp_len = fpdu_len;
/* See if we have all of the fpdu */
frag_tot = 0;
memset(&frags, 0, sizeof frags);
for (i = 0; i < MAX_FPDU_FRAGS; i++) {
frags[i].physaddr = cb->busaddr;
frags[i].physaddr += skb->data - cb->data_start;
frags[i].frag_len = min(tmp_len, skb->len);
frags[i].skb = skb;
frags[i].cmplt = (skb->len == frags[i].frag_len);
frag_tot += frags[i].frag_len;
frag_cnt++;
tmp_len -= frags[i].frag_len;
if (tmp_len == 0)
break;
skb = nes_get_next_skb(nesdev, nesqp, skb,
nesqp->pau_rcv_nxt + frag_tot, &ack, &wnd, &fin_rcvd, &rst_rcvd);
if (!skb)
goto out;
if (rst_rcvd) {
/* rst received in the middle of fpdu */
for (; i >= 0; i--) {
skb_unlink(frags[i].skb, &nesqp->pau_list);
nes_mgt_free_skb(nesdev, frags[i].skb, PCI_DMA_TODEVICE);
}
cb = (struct nes_rskb_cb *)&skb->cb[0];
frags[0].physaddr = cb->busaddr;
frags[0].physaddr += skb->data - cb->data_start;
frags[0].frag_len = skb->len;
frags[0].skb = skb;
frags[0].cmplt = true;
frag_cnt = 1;
break;
}
cb = (struct nes_rskb_cb *)&skb->cb[0];
}
} else {
/* no data */
frags[0].physaddr = cb->busaddr;
frags[0].frag_len = 0;
frags[0].skb = skb;
frags[0].cmplt = true;
frag_cnt = 1;
}
/* Found one */
fpdu_info = kzalloc(sizeof(*fpdu_info), GFP_ATOMIC);
if (!fpdu_info) {
rc = -ENOMEM;
goto out;
}
fpdu_info->cqp_request = nes_get_cqp_request(nesdev);
if (fpdu_info->cqp_request == NULL) {
nes_debug(NES_DBG_PAU, "Failed to get a cqp_request.\n");
rc = -ENOMEM;
goto out;
}
cb = (struct nes_rskb_cb *)&frags[0].skb->cb[0];
iph = (struct iphdr *)(cb->data_start + ETH_HLEN);
tcph = (struct tcphdr *)(((char *)iph) + (4 * iph->ihl));
fpdu_info->hdr_len = (((unsigned char *)tcph) + 4 * (tcph->doff)) - cb->data_start;
fpdu_info->data_len = fpdu_len;
tot_len = fpdu_info->hdr_len + fpdu_len - ETH_HLEN;
if (frags[0].cmplt) {
fpdu_info->hdr_pbase = cb->busaddr;
fpdu_info->hdr_vbase = NULL;
} else {
fpdu_info->hdr_vbase = pci_alloc_consistent(nesdev->pcidev,
fpdu_info->hdr_len, &fpdu_info->hdr_pbase);
if (!fpdu_info->hdr_vbase) {
nes_debug(NES_DBG_PAU, "Unable to allocate memory for pau first frag\n");
rc = -ENOMEM;
goto out;
}
/* Copy hdrs, adjusting len and seqnum */
memcpy(fpdu_info->hdr_vbase, cb->data_start, fpdu_info->hdr_len);
iph = (struct iphdr *)(fpdu_info->hdr_vbase + ETH_HLEN);
tcph = (struct tcphdr *)(((char *)iph) + (4 * iph->ihl));
}
iph->tot_len = cpu_to_be16(tot_len);
iph->saddr = cpu_to_be32(0x7f000001);
tcph->seq = cpu_to_be32(nesqp->pau_rcv_nxt);
tcph->ack_seq = cpu_to_be32(ack);
tcph->window = cpu_to_be16(wnd);
nesqp->pau_rcv_nxt += fpdu_len + fin_rcvd;
memcpy(fpdu_info->frags, frags, sizeof(fpdu_info->frags));
fpdu_info->frag_cnt = frag_cnt;
fpdu_info->nesqp = nesqp;
*pau_fpdu_info = fpdu_info;
/* Update skb's for next pass */
for (i = 0; i < frag_cnt; i++) {
cb = (struct nes_rskb_cb *)&frags[i].skb->cb[0];
skb_pull(frags[i].skb, frags[i].frag_len);
if (frags[i].skb->len == 0) {
/* Pull skb off the list - it will be freed in the callback */
if (!skb_queue_empty(&nesqp->pau_list))
skb_unlink(frags[i].skb, &nesqp->pau_list);
} else {
/* Last skb still has data so update the seq */
iph = (struct iphdr *)(cb->data_start + ETH_HLEN);
tcph = (struct tcphdr *)(((char *)iph) + (4 * iph->ihl));
tcph->seq = cpu_to_be32(nesqp->pau_rcv_nxt);
}
}
out:
if (rc) {
if (fpdu_info) {
if (fpdu_info->cqp_request)
nes_put_cqp_request(nesdev, fpdu_info->cqp_request);
kfree(fpdu_info);
}
}
return rc;
}
/**
* forward_fpdu - send complete fpdus, one at a time
*/
static int forward_fpdus(struct nes_vnic *nesvnic, struct nes_qp *nesqp)
{
struct nes_device *nesdev = nesvnic->nesdev;
struct pau_fpdu_info *fpdu_info;
struct nes_hw_cqp_wqe *cqp_wqe;
struct nes_cqp_request *cqp_request;
unsigned long flags;
u64 u64tmp;
u32 u32tmp;
int rc;
while (1) {
spin_lock_irqsave(&nesqp->pau_lock, flags);
rc = get_fpdu_info(nesdev, nesqp, &fpdu_info);
if (rc || (fpdu_info == NULL)) {
spin_unlock_irqrestore(&nesqp->pau_lock, flags);
return rc;
}
cqp_request = fpdu_info->cqp_request;
cqp_wqe = &cqp_request->cqp_wqe;
nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_DL_OPCODE_IDX,
NES_CQP_DOWNLOAD_SEGMENT |
(((u32)nesvnic->logical_port) << NES_CQP_OP_LOGICAL_PORT_SHIFT));
u32tmp = fpdu_info->hdr_len << 16;
u32tmp |= fpdu_info->hdr_len + (u32)fpdu_info->data_len;
set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_DL_LENGTH_0_TOTAL_IDX,
u32tmp);
u32tmp = (fpdu_info->frags[1].frag_len << 16) | fpdu_info->frags[0].frag_len;
set_wqe_32bit_value(cqp_wqe->wqe_words, NES_NIC_SQ_WQE_LENGTH_2_1_IDX,
u32tmp);
u32tmp = (fpdu_info->frags[3].frag_len << 16) | fpdu_info->frags[2].frag_len;
set_wqe_32bit_value(cqp_wqe->wqe_words, NES_NIC_SQ_WQE_LENGTH_4_3_IDX,
u32tmp);
u64tmp = (u64)fpdu_info->hdr_pbase;
set_wqe_32bit_value(cqp_wqe->wqe_words, NES_NIC_SQ_WQE_FRAG0_LOW_IDX,
lower_32_bits(u64tmp));
set_wqe_32bit_value(cqp_wqe->wqe_words, NES_NIC_SQ_WQE_FRAG0_HIGH_IDX,
upper_32_bits(u64tmp));
set_wqe_32bit_value(cqp_wqe->wqe_words, NES_NIC_SQ_WQE_FRAG1_LOW_IDX,
lower_32_bits(fpdu_info->frags[0].physaddr));
set_wqe_32bit_value(cqp_wqe->wqe_words, NES_NIC_SQ_WQE_FRAG1_HIGH_IDX,
upper_32_bits(fpdu_info->frags[0].physaddr));
set_wqe_32bit_value(cqp_wqe->wqe_words, NES_NIC_SQ_WQE_FRAG2_LOW_IDX,
lower_32_bits(fpdu_info->frags[1].physaddr));
set_wqe_32bit_value(cqp_wqe->wqe_words, NES_NIC_SQ_WQE_FRAG2_HIGH_IDX,
upper_32_bits(fpdu_info->frags[1].physaddr));
set_wqe_32bit_value(cqp_wqe->wqe_words, NES_NIC_SQ_WQE_FRAG3_LOW_IDX,
lower_32_bits(fpdu_info->frags[2].physaddr));
set_wqe_32bit_value(cqp_wqe->wqe_words, NES_NIC_SQ_WQE_FRAG3_HIGH_IDX,
upper_32_bits(fpdu_info->frags[2].physaddr));
set_wqe_32bit_value(cqp_wqe->wqe_words, NES_NIC_SQ_WQE_FRAG4_LOW_IDX,
lower_32_bits(fpdu_info->frags[3].physaddr));
set_wqe_32bit_value(cqp_wqe->wqe_words, NES_NIC_SQ_WQE_FRAG4_HIGH_IDX,
upper_32_bits(fpdu_info->frags[3].physaddr));
cqp_request->cqp_callback_pointer = fpdu_info;
cqp_request->callback = 1;
cqp_request->cqp_callback = nes_download_callback;
atomic_set(&cqp_request->refcount, 1);
nes_post_cqp_request(nesdev, cqp_request);
spin_unlock_irqrestore(&nesqp->pau_lock, flags);
}
return 0;
}
static void process_fpdus(struct nes_vnic *nesvnic, struct nes_qp *nesqp)
{
int again = 1;
unsigned long flags;
do {
/* Ignore rc - if it failed, tcp retries will cause it to try again */
forward_fpdus(nesvnic, nesqp);
spin_lock_irqsave(&nesqp->pau_lock, flags);
if (nesqp->pau_pending) {
nesqp->pau_pending = 0;
} else {
nesqp->pau_busy = 0;
again = 0;
}
spin_unlock_irqrestore(&nesqp->pau_lock, flags);
} while (again);
}
/**
* queue_fpdus - Handle fpdu's that hw passed up to sw
*/
static void queue_fpdus(struct sk_buff *skb, struct nes_vnic *nesvnic, struct nes_qp *nesqp)
{
struct sk_buff *tmpskb;
struct nes_rskb_cb *cb;
struct iphdr *iph;
struct tcphdr *tcph;
unsigned char *tcph_end;
u32 rcv_nxt;
u32 rcv_wnd;
u32 seqnum;
u32 len;
bool process_it = false;
unsigned long flags;
/* Move data ptr to after tcp header */
iph = (struct iphdr *)skb->data;
tcph = (struct tcphdr *)(((char *)iph) + (4 * iph->ihl));
seqnum = be32_to_cpu(tcph->seq);
tcph_end = (((char *)tcph) + (4 * tcph->doff));
len = be16_to_cpu(iph->tot_len);
if (skb->len > len)
skb_trim(skb, len);
skb_pull(skb, tcph_end - skb->data);
/* Initialize tracking values */
cb = (struct nes_rskb_cb *)&skb->cb[0];
cb->seqnum = seqnum;
/* Make sure data is in the receive window */
rcv_nxt = nesqp->pau_rcv_nxt;
rcv_wnd = le32_to_cpu(nesqp->nesqp_context->rcv_wnd);
if (!between(seqnum, rcv_nxt, (rcv_nxt + rcv_wnd))) {
nes_mgt_free_skb(nesvnic->nesdev, skb, PCI_DMA_TODEVICE);
nes_rem_ref_cm_node(nesqp->cm_node);
return;
}
spin_lock_irqsave(&nesqp->pau_lock, flags);
if (nesqp->pau_busy)
nesqp->pau_pending = 1;
else
nesqp->pau_busy = 1;
/* Queue skb by sequence number */
if (skb_queue_len(&nesqp->pau_list) == 0) {
__skb_queue_head(&nesqp->pau_list, skb);
} else {
skb_queue_walk(&nesqp->pau_list, tmpskb) {
cb = (struct nes_rskb_cb *)&tmpskb->cb[0];
if (before(seqnum, cb->seqnum))
break;
}
__skb_insert(skb, tmpskb->prev, tmpskb, &nesqp->pau_list);
}
if (nesqp->pau_state == PAU_READY)
process_it = true;
spin_unlock_irqrestore(&nesqp->pau_lock, flags);
if (process_it)
process_fpdus(nesvnic, nesqp);
return;
}
/**
* mgt_thread - Handle mgt skbs in a safe context
*/
static int mgt_thread(void *context)
{
struct nes_vnic *nesvnic = context;
struct sk_buff *skb;
struct nes_rskb_cb *cb;
while (!kthread_should_stop()) {
wait_event_interruptible(nesvnic->mgt_wait_queue,
skb_queue_len(&nesvnic->mgt_skb_list) || kthread_should_stop());
while ((skb_queue_len(&nesvnic->mgt_skb_list)) && !kthread_should_stop()) {
skb = skb_dequeue(&nesvnic->mgt_skb_list);
cb = (struct nes_rskb_cb *)&skb->cb[0];
cb->data_start = skb->data - ETH_HLEN;
cb->busaddr = pci_map_single(nesvnic->nesdev->pcidev, cb->data_start,
nesvnic->max_frame_size, PCI_DMA_TODEVICE);
queue_fpdus(skb, nesvnic, cb->nesqp);
}
}
/* Closing down so delete any entries on the queue */
while (skb_queue_len(&nesvnic->mgt_skb_list)) {
skb = skb_dequeue(&nesvnic->mgt_skb_list);
cb = (struct nes_rskb_cb *)&skb->cb[0];
nes_rem_ref_cm_node(cb->nesqp->cm_node);
dev_kfree_skb_any(skb);
}
return 0;
}
/**
* nes_queue_skbs - Queue skb so it can be handled in a thread context
*/
void nes_queue_mgt_skbs(struct sk_buff *skb, struct nes_vnic *nesvnic, struct nes_qp *nesqp)
{
struct nes_rskb_cb *cb;
cb = (struct nes_rskb_cb *)&skb->cb[0];
cb->nesqp = nesqp;
skb_queue_tail(&nesvnic->mgt_skb_list, skb);
wake_up_interruptible(&nesvnic->mgt_wait_queue);
}
void nes_destroy_pau_qp(struct nes_device *nesdev, struct nes_qp *nesqp)
{
struct sk_buff *skb;
unsigned long flags;
atomic_inc(&pau_qps_destroyed);
/* Free packets that have not yet been forwarded */
/* Lock is acquired by skb_dequeue when removing the skb */
spin_lock_irqsave(&nesqp->pau_lock, flags);
while (skb_queue_len(&nesqp->pau_list)) {
skb = skb_dequeue(&nesqp->pau_list);
nes_mgt_free_skb(nesdev, skb, PCI_DMA_TODEVICE);
nes_rem_ref_cm_node(nesqp->cm_node);
}
spin_unlock_irqrestore(&nesqp->pau_lock, flags);
}
static void nes_chg_qh_handler(struct nes_device *nesdev, struct nes_cqp_request *cqp_request)
{
struct pau_qh_chg *qh_chg = cqp_request->cqp_callback_pointer;
struct nes_cqp_request *new_request;
struct nes_hw_cqp_wqe *cqp_wqe;
struct nes_adapter *nesadapter;
struct nes_qp *nesqp;
struct nes_v4_quad nes_quad;
u32 crc_value;
u64 u64temp;
nesadapter = nesdev->nesadapter;
nesqp = qh_chg->nesqp;
/* Should we handle the bad completion */
if (cqp_request->major_code)
WARN(1, PFX "Invalid cqp_request major_code=0x%x\n",
cqp_request->major_code);
switch (nesqp->pau_state) {
case PAU_DEL_QH:
/* Old hash code deleted, now set the new one */
nesqp->pau_state = PAU_ADD_LB_QH;
new_request = nes_get_cqp_request(nesdev);
if (new_request == NULL) {
nes_debug(NES_DBG_PAU, "Failed to get a new_request.\n");
WARN_ON(1);
return;
}
memset(&nes_quad, 0, sizeof(nes_quad));
nes_quad.DstIpAdrIndex =
cpu_to_le32((u32)PCI_FUNC(nesdev->pcidev->devfn) << 24);
nes_quad.SrcIpadr = cpu_to_be32(0x7f000001);
nes_quad.TcpPorts[0] = swab16(nesqp->nesqp_context->tcpPorts[1]);
nes_quad.TcpPorts[1] = swab16(nesqp->nesqp_context->tcpPorts[0]);
/* Produce hash key */
crc_value = get_crc_value(&nes_quad);
nesqp->hte_index = cpu_to_be32(crc_value ^ 0xffffffff);
nes_debug(NES_DBG_PAU, "new HTE Index = 0x%08X, CRC = 0x%08X\n",
nesqp->hte_index, nesqp->hte_index & nesadapter->hte_index_mask);
nesqp->hte_index &= nesadapter->hte_index_mask;
nesqp->nesqp_context->hte_index = cpu_to_le32(nesqp->hte_index);
nesqp->nesqp_context->ip0 = cpu_to_le32(0x7f000001);
nesqp->nesqp_context->rcv_nxt = cpu_to_le32(nesqp->pau_rcv_nxt);
cqp_wqe = &new_request->cqp_wqe;
nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
set_wqe_32bit_value(cqp_wqe->wqe_words,
NES_CQP_WQE_OPCODE_IDX, NES_CQP_MANAGE_QUAD_HASH |
NES_CQP_QP_TYPE_IWARP | NES_CQP_QP_CONTEXT_VALID | NES_CQP_QP_IWARP_STATE_RTS);
set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_ID_IDX, nesqp->hwqp.qp_id);
u64temp = (u64)nesqp->nesqp_context_pbase;
set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_QP_WQE_CONTEXT_LOW_IDX, u64temp);
nes_debug(NES_DBG_PAU, "Waiting for CQP completion for adding the quad hash.\n");
new_request->cqp_callback_pointer = qh_chg;
new_request->callback = 1;
new_request->cqp_callback = nes_chg_qh_handler;
atomic_set(&new_request->refcount, 1);
nes_post_cqp_request(nesdev, new_request);
break;
case PAU_ADD_LB_QH:
/* Start processing the queued fpdu's */
nesqp->pau_state = PAU_READY;
process_fpdus(qh_chg->nesvnic, qh_chg->nesqp);
kfree(qh_chg);
break;
}
}
/**
* nes_change_quad_hash
*/
static int nes_change_quad_hash(struct nes_device *nesdev,
struct nes_vnic *nesvnic, struct nes_qp *nesqp)
{
struct nes_cqp_request *cqp_request = NULL;
struct pau_qh_chg *qh_chg = NULL;
u64 u64temp;
struct nes_hw_cqp_wqe *cqp_wqe;
int ret = 0;
cqp_request = nes_get_cqp_request(nesdev);
if (cqp_request == NULL) {
nes_debug(NES_DBG_PAU, "Failed to get a cqp_request.\n");
ret = -ENOMEM;
goto chg_qh_err;
}
qh_chg = kmalloc(sizeof *qh_chg, GFP_ATOMIC);
if (!qh_chg) {
ret = -ENOMEM;
goto chg_qh_err;
}
qh_chg->nesdev = nesdev;
qh_chg->nesvnic = nesvnic;
qh_chg->nesqp = nesqp;
nesqp->pau_state = PAU_DEL_QH;
cqp_wqe = &cqp_request->cqp_wqe;
nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
set_wqe_32bit_value(cqp_wqe->wqe_words,
NES_CQP_WQE_OPCODE_IDX, NES_CQP_MANAGE_QUAD_HASH | NES_CQP_QP_DEL_HTE |
NES_CQP_QP_TYPE_IWARP | NES_CQP_QP_CONTEXT_VALID | NES_CQP_QP_IWARP_STATE_RTS);
set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_ID_IDX, nesqp->hwqp.qp_id);
u64temp = (u64)nesqp->nesqp_context_pbase;
set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_QP_WQE_CONTEXT_LOW_IDX, u64temp);
nes_debug(NES_DBG_PAU, "Waiting for CQP completion for deleting the quad hash.\n");
cqp_request->cqp_callback_pointer = qh_chg;
cqp_request->callback = 1;
cqp_request->cqp_callback = nes_chg_qh_handler;
atomic_set(&cqp_request->refcount, 1);
nes_post_cqp_request(nesdev, cqp_request);
return ret;
chg_qh_err:
kfree(qh_chg);
if (cqp_request)
nes_put_cqp_request(nesdev, cqp_request);
return ret;
}
/**
* nes_mgt_ce_handler
* This management code deals with any packed and unaligned (pau) fpdu's
* that the hardware cannot handle.
*/
static void nes_mgt_ce_handler(struct nes_device *nesdev, struct nes_hw_nic_cq *cq)
{
struct nes_vnic_mgt *mgtvnic = container_of(cq, struct nes_vnic_mgt, mgt_cq);
struct nes_adapter *nesadapter = nesdev->nesadapter;
u32 head;
u32 cq_size;
u32 cqe_count = 0;
u32 cqe_misc;
u32 qp_id = 0;
u32 skbs_needed;
unsigned long context;
struct nes_qp *nesqp;
struct sk_buff *rx_skb;
struct nes_rskb_cb *cb;
head = cq->cq_head;
cq_size = cq->cq_size;
while (1) {
cqe_misc = le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_NIC_CQE_MISC_IDX]);
if (!(cqe_misc & NES_NIC_CQE_VALID))
break;
nesqp = NULL;
if (cqe_misc & NES_NIC_CQE_ACCQP_VALID) {
qp_id = le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_NIC_CQE_ACCQP_ID_IDX]);
qp_id &= 0x001fffff;
if (qp_id < nesadapter->max_qp) {
context = (unsigned long)nesadapter->qp_table[qp_id - NES_FIRST_QPN];
nesqp = (struct nes_qp *)context;
}
}
if (nesqp) {
if (nesqp->pau_mode == false) {
nesqp->pau_mode = true; /* First time for this qp */
nesqp->pau_rcv_nxt = le32_to_cpu(
cq->cq_vbase[head].cqe_words[NES_NIC_CQE_HASH_RCVNXT]);
skb_queue_head_init(&nesqp->pau_list);
spin_lock_init(&nesqp->pau_lock);
atomic_inc(&pau_qps_created);
nes_change_quad_hash(nesdev, mgtvnic->nesvnic, nesqp);
}
rx_skb = mgtvnic->mgt.rx_skb[mgtvnic->mgt.rq_tail];
rx_skb->len = 0;
skb_put(rx_skb, cqe_misc & 0x0000ffff);
rx_skb->protocol = eth_type_trans(rx_skb, mgtvnic->nesvnic->netdev);
cb = (struct nes_rskb_cb *)&rx_skb->cb[0];
pci_unmap_single(nesdev->pcidev, cb->busaddr, cb->maplen, PCI_DMA_FROMDEVICE);
cb->busaddr = 0;
mgtvnic->mgt.rq_tail++;
mgtvnic->mgt.rq_tail &= mgtvnic->mgt.rq_size - 1;
nes_add_ref_cm_node(nesqp->cm_node);
nes_queue_mgt_skbs(rx_skb, mgtvnic->nesvnic, nesqp);
} else {
printk(KERN_ERR PFX "Invalid QP %d for packed/unaligned handling\n", qp_id);
}
cq->cq_vbase[head].cqe_words[NES_NIC_CQE_MISC_IDX] = 0;
cqe_count++;
if (++head >= cq_size)
head = 0;
if (cqe_count == 255) {
/* Replenish mgt CQ */
nes_write32(nesdev->regs + NES_CQE_ALLOC, cq->cq_number | (cqe_count << 16));
nesdev->currcq_count += cqe_count;
cqe_count = 0;
}
skbs_needed = atomic_inc_return(&mgtvnic->rx_skbs_needed);
if (skbs_needed > (mgtvnic->mgt.rq_size >> 1))
nes_replenish_mgt_rq(mgtvnic);
}
cq->cq_head = head;
nes_write32(nesdev->regs + NES_CQE_ALLOC, NES_CQE_ALLOC_NOTIFY_NEXT |
cq->cq_number | (cqe_count << 16));
nes_read32(nesdev->regs + NES_CQE_ALLOC);
nesdev->currcq_count += cqe_count;
}
/**
* nes_init_mgt_qp
*/
int nes_init_mgt_qp(struct nes_device *nesdev, struct net_device *netdev, struct nes_vnic *nesvnic)
{
struct nes_vnic_mgt *mgtvnic;
u32 counter;
void *vmem;
dma_addr_t pmem;
struct nes_hw_cqp_wqe *cqp_wqe;
u32 cqp_head;
unsigned long flags;
struct nes_hw_nic_qp_context *mgt_context;
u64 u64temp;
struct nes_hw_nic_rq_wqe *mgt_rqe;
struct sk_buff *skb;
u32 wqe_count;
struct nes_rskb_cb *cb;
u32 mgt_mem_size;
void *mgt_vbase;
dma_addr_t mgt_pbase;
int i;
int ret;
/* Allocate space the all mgt QPs once */
mgtvnic = kcalloc(NES_MGT_QP_COUNT, sizeof(struct nes_vnic_mgt),
GFP_KERNEL);
if (!mgtvnic)
return -ENOMEM;
/* Allocate fragment, RQ, and CQ; Reuse CEQ based on the PCI function */
/* We are not sending from this NIC so sq is not allocated */
mgt_mem_size = 256 +
(NES_MGT_WQ_COUNT * sizeof(struct nes_hw_nic_rq_wqe)) +
(NES_MGT_WQ_COUNT * sizeof(struct nes_hw_nic_cqe)) +
sizeof(struct nes_hw_nic_qp_context);
mgt_mem_size = (mgt_mem_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
mgt_vbase = pci_alloc_consistent(nesdev->pcidev, NES_MGT_QP_COUNT * mgt_mem_size, &mgt_pbase);
if (!mgt_vbase) {
kfree(mgtvnic);
nes_debug(NES_DBG_INIT, "Unable to allocate memory for mgt host descriptor rings\n");
return -ENOMEM;
}
nesvnic->mgt_mem_size = NES_MGT_QP_COUNT * mgt_mem_size;
nesvnic->mgt_vbase = mgt_vbase;
nesvnic->mgt_pbase = mgt_pbase;
skb_queue_head_init(&nesvnic->mgt_skb_list);
init_waitqueue_head(&nesvnic->mgt_wait_queue);
nesvnic->mgt_thread = kthread_run(mgt_thread, nesvnic, "nes_mgt_thread");
for (i = 0; i < NES_MGT_QP_COUNT; i++) {
mgtvnic->nesvnic = nesvnic;
mgtvnic->mgt.qp_id = nesdev->mac_index + NES_MGT_QP_OFFSET + i;
memset(mgt_vbase, 0, mgt_mem_size);
nes_debug(NES_DBG_INIT, "Allocated mgt QP structures at %p (phys = %016lX), size = %u.\n",
mgt_vbase, (unsigned long)mgt_pbase, mgt_mem_size);
vmem = (void *)(((unsigned long)mgt_vbase + (256 - 1)) &
~(unsigned long)(256 - 1));
pmem = (dma_addr_t)(((unsigned long long)mgt_pbase + (256 - 1)) &
~(unsigned long long)(256 - 1));
spin_lock_init(&mgtvnic->mgt.rq_lock);
/* setup the RQ */
mgtvnic->mgt.rq_vbase = vmem;
mgtvnic->mgt.rq_pbase = pmem;
mgtvnic->mgt.rq_head = 0;
mgtvnic->mgt.rq_tail = 0;
mgtvnic->mgt.rq_size = NES_MGT_WQ_COUNT;
/* setup the CQ */
vmem += (NES_MGT_WQ_COUNT * sizeof(struct nes_hw_nic_rq_wqe));
pmem += (NES_MGT_WQ_COUNT * sizeof(struct nes_hw_nic_rq_wqe));
mgtvnic->mgt_cq.cq_number = mgtvnic->mgt.qp_id;
mgtvnic->mgt_cq.cq_vbase = vmem;
mgtvnic->mgt_cq.cq_pbase = pmem;
mgtvnic->mgt_cq.cq_head = 0;
mgtvnic->mgt_cq.cq_size = NES_MGT_WQ_COUNT;
mgtvnic->mgt_cq.ce_handler = nes_mgt_ce_handler;
/* Send CreateCQ request to CQP */
spin_lock_irqsave(&nesdev->cqp.lock, flags);
cqp_head = nesdev->cqp.sq_head;
cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(
NES_CQP_CREATE_CQ | NES_CQP_CQ_CEQ_VALID |
((u32)mgtvnic->mgt_cq.cq_size << 16));
cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(
mgtvnic->mgt_cq.cq_number | ((u32)nesdev->ceq_index << 16));
u64temp = (u64)mgtvnic->mgt_cq.cq_pbase;
set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_CQ_WQE_PBL_LOW_IDX, u64temp);
cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX] = 0;
u64temp = (unsigned long)&mgtvnic->mgt_cq;
cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX] = cpu_to_le32((u32)(u64temp >> 1));
cqp_wqe->wqe_words[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX] =
cpu_to_le32(((u32)((u64temp) >> 33)) & 0x7FFFFFFF);
cqp_wqe->wqe_words[NES_CQP_CQ_WQE_DOORBELL_INDEX_HIGH_IDX] = 0;
if (++cqp_head >= nesdev->cqp.sq_size)
cqp_head = 0;
cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
/* Send CreateQP request to CQP */
mgt_context = (void *)(&mgtvnic->mgt_cq.cq_vbase[mgtvnic->mgt_cq.cq_size]);
mgt_context->context_words[NES_NIC_CTX_MISC_IDX] =
cpu_to_le32((u32)NES_MGT_CTX_SIZE |
((u32)PCI_FUNC(nesdev->pcidev->devfn) << 12));
nes_debug(NES_DBG_INIT, "RX_WINDOW_BUFFER_PAGE_TABLE_SIZE = 0x%08X, RX_WINDOW_BUFFER_SIZE = 0x%08X\n",
nes_read_indexed(nesdev, NES_IDX_RX_WINDOW_BUFFER_PAGE_TABLE_SIZE),
nes_read_indexed(nesdev, NES_IDX_RX_WINDOW_BUFFER_SIZE));
if (nes_read_indexed(nesdev, NES_IDX_RX_WINDOW_BUFFER_SIZE) != 0)
mgt_context->context_words[NES_NIC_CTX_MISC_IDX] |= cpu_to_le32(NES_NIC_BACK_STORE);
u64temp = (u64)mgtvnic->mgt.rq_pbase;
mgt_context->context_words[NES_NIC_CTX_SQ_LOW_IDX] = cpu_to_le32((u32)u64temp);
mgt_context->context_words[NES_NIC_CTX_SQ_HIGH_IDX] = cpu_to_le32((u32)(u64temp >> 32));
u64temp = (u64)mgtvnic->mgt.rq_pbase;
mgt_context->context_words[NES_NIC_CTX_RQ_LOW_IDX] = cpu_to_le32((u32)u64temp);
mgt_context->context_words[NES_NIC_CTX_RQ_HIGH_IDX] = cpu_to_le32((u32)(u64temp >> 32));
cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX] = cpu_to_le32(NES_CQP_CREATE_QP |
NES_CQP_QP_TYPE_NIC);
cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX] = cpu_to_le32(mgtvnic->mgt.qp_id);
u64temp = (u64)mgtvnic->mgt_cq.cq_pbase +
(mgtvnic->mgt_cq.cq_size * sizeof(struct nes_hw_nic_cqe));
set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_QP_WQE_CONTEXT_LOW_IDX, u64temp);
if (++cqp_head >= nesdev->cqp.sq_size)
cqp_head = 0;
nesdev->cqp.sq_head = cqp_head;
barrier();
/* Ring doorbell (2 WQEs) */
nes_write32(nesdev->regs + NES_WQE_ALLOC, 0x02800000 | nesdev->cqp.qp_id);
spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
nes_debug(NES_DBG_INIT, "Waiting for create MGT QP%u to complete.\n",
mgtvnic->mgt.qp_id);
ret = wait_event_timeout(nesdev->cqp.waitq, (nesdev->cqp.sq_tail == cqp_head),
NES_EVENT_TIMEOUT);
nes_debug(NES_DBG_INIT, "Create MGT QP%u completed, wait_event_timeout ret = %u.\n",
mgtvnic->mgt.qp_id, ret);
if (!ret) {
nes_debug(NES_DBG_INIT, "MGT QP%u create timeout expired\n", mgtvnic->mgt.qp_id);
if (i == 0) {
pci_free_consistent(nesdev->pcidev, nesvnic->mgt_mem_size, nesvnic->mgt_vbase,
nesvnic->mgt_pbase);
kfree(mgtvnic);
} else {
nes_destroy_mgt(nesvnic);
}
return -EIO;
}
/* Populate the RQ */
for (counter = 0; counter < (NES_MGT_WQ_COUNT - 1); counter++) {
skb = dev_alloc_skb(nesvnic->max_frame_size);
if (!skb) {
nes_debug(NES_DBG_INIT, "%s: out of memory for receive skb\n", netdev->name);
return -ENOMEM;
}
skb->dev = netdev;
pmem = pci_map_single(nesdev->pcidev, skb->data,
nesvnic->max_frame_size, PCI_DMA_FROMDEVICE);
cb = (struct nes_rskb_cb *)&skb->cb[0];
cb->busaddr = pmem;
cb->maplen = nesvnic->max_frame_size;
mgt_rqe = &mgtvnic->mgt.rq_vbase[counter];
mgt_rqe->wqe_words[NES_NIC_RQ_WQE_LENGTH_1_0_IDX] = cpu_to_le32((u32)nesvnic->max_frame_size);
mgt_rqe->wqe_words[NES_NIC_RQ_WQE_LENGTH_3_2_IDX] = 0;
mgt_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_LOW_IDX] = cpu_to_le32((u32)pmem);
mgt_rqe->wqe_words[NES_NIC_RQ_WQE_FRAG0_HIGH_IDX] = cpu_to_le32((u32)((u64)pmem >> 32));
mgtvnic->mgt.rx_skb[counter] = skb;
}
timer_setup(&mgtvnic->rq_wqes_timer, nes_mgt_rq_wqes_timeout,
0);
wqe_count = NES_MGT_WQ_COUNT - 1;
mgtvnic->mgt.rq_head = wqe_count;
barrier();
do {
counter = min(wqe_count, ((u32)255));
wqe_count -= counter;
nes_write32(nesdev->regs + NES_WQE_ALLOC, (counter << 24) | mgtvnic->mgt.qp_id);
} while (wqe_count);
nes_write32(nesdev->regs + NES_CQE_ALLOC, NES_CQE_ALLOC_NOTIFY_NEXT |
mgtvnic->mgt_cq.cq_number);
nes_read32(nesdev->regs + NES_CQE_ALLOC);
mgt_vbase += mgt_mem_size;
mgt_pbase += mgt_mem_size;
nesvnic->mgtvnic[i] = mgtvnic++;
}
return 0;
}
void nes_destroy_mgt(struct nes_vnic *nesvnic)
{
struct nes_device *nesdev = nesvnic->nesdev;
struct nes_vnic_mgt *mgtvnic;
struct nes_vnic_mgt *first_mgtvnic;
unsigned long flags;
struct nes_hw_cqp_wqe *cqp_wqe;
u32 cqp_head;
struct sk_buff *rx_skb;
int i;
int ret;
kthread_stop(nesvnic->mgt_thread);
/* Free remaining NIC receive buffers */
first_mgtvnic = nesvnic->mgtvnic[0];
for (i = 0; i < NES_MGT_QP_COUNT; i++) {
mgtvnic = nesvnic->mgtvnic[i];
if (mgtvnic == NULL)
continue;
while (mgtvnic->mgt.rq_head != mgtvnic->mgt.rq_tail) {
rx_skb = mgtvnic->mgt.rx_skb[mgtvnic->mgt.rq_tail];
nes_mgt_free_skb(nesdev, rx_skb, PCI_DMA_FROMDEVICE);
mgtvnic->mgt.rq_tail++;
mgtvnic->mgt.rq_tail &= (mgtvnic->mgt.rq_size - 1);
}
spin_lock_irqsave(&nesdev->cqp.lock, flags);
/* Destroy NIC QP */
cqp_head = nesdev->cqp.sq_head;
cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX,
(NES_CQP_DESTROY_QP | NES_CQP_QP_TYPE_NIC));
set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_ID_IDX,
mgtvnic->mgt.qp_id);
if (++cqp_head >= nesdev->cqp.sq_size)
cqp_head = 0;
cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
/* Destroy NIC CQ */
nes_fill_init_cqp_wqe(cqp_wqe, nesdev);
set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_OPCODE_IDX,
(NES_CQP_DESTROY_CQ | ((u32)mgtvnic->mgt_cq.cq_size << 16)));
set_wqe_32bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_ID_IDX,
(mgtvnic->mgt_cq.cq_number | ((u32)nesdev->ceq_index << 16)));
if (++cqp_head >= nesdev->cqp.sq_size)
cqp_head = 0;
nesdev->cqp.sq_head = cqp_head;
barrier();
/* Ring doorbell (2 WQEs) */
nes_write32(nesdev->regs + NES_WQE_ALLOC, 0x02800000 | nesdev->cqp.qp_id);
spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
nes_debug(NES_DBG_SHUTDOWN, "Waiting for CQP, cqp_head=%u, cqp.sq_head=%u,"
" cqp.sq_tail=%u, cqp.sq_size=%u\n",
cqp_head, nesdev->cqp.sq_head,
nesdev->cqp.sq_tail, nesdev->cqp.sq_size);
ret = wait_event_timeout(nesdev->cqp.waitq, (nesdev->cqp.sq_tail == cqp_head),
NES_EVENT_TIMEOUT);
nes_debug(NES_DBG_SHUTDOWN, "Destroy MGT QP returned, wait_event_timeout ret = %u, cqp_head=%u,"
" cqp.sq_head=%u, cqp.sq_tail=%u\n",
ret, cqp_head, nesdev->cqp.sq_head, nesdev->cqp.sq_tail);
if (!ret)
nes_debug(NES_DBG_SHUTDOWN, "MGT QP%u destroy timeout expired\n",
mgtvnic->mgt.qp_id);
nesvnic->mgtvnic[i] = NULL;
}
if (nesvnic->mgt_vbase) {
pci_free_consistent(nesdev->pcidev, nesvnic->mgt_mem_size, nesvnic->mgt_vbase,
nesvnic->mgt_pbase);
nesvnic->mgt_vbase = NULL;
nesvnic->mgt_pbase = 0;
}
kfree(first_mgtvnic);
}
drivers/infiniband/hw/nes/nes_mgt.h deleted 100644 → 0
View file @ cbdc666f
/*
* Copyright (c) 2006 - 2011 Intel-NE, Inc. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef __NES_MGT_H
#define __NES_MGT_H
#define MPA_FRAMING 6 /* length is 2 bytes, crc is 4 bytes */
int nes_init_mgt_qp(struct nes_device *nesdev, struct net_device *netdev, struct nes_vnic *nesvnic);
void nes_queue_mgt_skbs(struct sk_buff *skb, struct nes_vnic *nesvnic, struct nes_qp *nesqp);
void nes_destroy_mgt(struct nes_vnic *nesvnic);
void nes_destroy_pau_qp(struct nes_device *nesdev, struct nes_qp *nesqp);
struct nes_hw_mgt {
struct nes_hw_nic_rq_wqe *rq_vbase; /* virtual address of rq */
dma_addr_t rq_pbase; /* PCI memory for host rings */
struct sk_buff *rx_skb[NES_NIC_WQ_SIZE];
u16 qp_id;
u16 sq_head;
u16 rq_head;
u16 rq_tail;
u16 rq_size;
u8 replenishing_rq;
u8 reserved;
spinlock_t rq_lock;
};
struct nes_vnic_mgt {
struct nes_vnic *nesvnic;
struct nes_hw_mgt mgt;
struct nes_hw_nic_cq mgt_cq;
atomic_t rx_skbs_needed;
struct timer_list rq_wqes_timer;
atomic_t rx_skb_timer_running;
};
#define MAX_FPDU_FRAGS 4
struct pau_fpdu_frag {
struct sk_buff *skb;
u64 physaddr;
u32 frag_len;
bool cmplt;
};
struct pau_fpdu_info {
struct nes_qp *nesqp;
struct nes_cqp_request *cqp_request;
void *hdr_vbase;
dma_addr_t hdr_pbase;
int hdr_len;
u16 data_len;
u16 frag_cnt;
struct pau_fpdu_frag frags[MAX_FPDU_FRAGS];
};
enum pau_qh_state {
PAU_DEL_QH,
PAU_ADD_LB_QH,
PAU_READY
};
struct pau_qh_chg {
struct nes_device *nesdev;
struct nes_vnic *nesvnic;
struct nes_qp *nesqp;
};
#endif /* __NES_MGT_H */
drivers/infiniband/hw/nes/nes_nic.c deleted 100644 → 0
View file @ cbdc666f
/*
* Copyright (c) 2006 - 2011 Intel Corporation. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/ip.h>
#include <linux/tcp.h>
#include <linux/if_arp.h>
#include <linux/if_vlan.h>
#include <linux/ethtool.h>
#include <linux/slab.h>
#include <net/tcp.h>
#include <net/inet_common.h>
#include <linux/inet.h>
#include "nes.h"
static struct nic_qp_map nic_qp_mapping_0[] = {
{16,0,0,1},{24,4,0,0},{28,8,0,0},{32,12,0,0},
{20,2,2,1},{26,6,2,0},{30,10,2,0},{34,14,2,0},
{18,1,1,1},{25,5,1,0},{29,9,1,0},{33,13,1,0},
{22,3,3,1},{27,7,3,0},{31,11,3,0},{35,15,3,0}
};
static struct nic_qp_map nic_qp_mapping_1[] = {
{18,1,1,1},{25,5,1,0},{29,9,1,0},{33,13,1,0},
{22,3,3,1},{27,7,3,0},{31,11,3,0},{35,15,3,0}
};
static struct nic_qp_map nic_qp_mapping_2[] = {
{20,2,2,1},{26,6,2,0},{30,10,2,0},{34,14,2,0}
};
static struct nic_qp_map nic_qp_mapping_3[] = {
{22,3,3,1},{27,7,3,0},{31,11,3,0},{35,15,3,0}
};
static struct nic_qp_map nic_qp_mapping_4[] = {
{28,8,0,0},{32,12,0,0}
};
static struct nic_qp_map nic_qp_mapping_5[] = {
{29,9,1,0},{33,13,1,0}
};
static struct nic_qp_map nic_qp_mapping_6[] = {
{30,10,2,0},{34,14,2,0}
};
static struct nic_qp_map nic_qp_mapping_7[] = {
{31,11,3,0},{35,15,3,0}
};
static struct nic_qp_map *nic_qp_mapping_per_function[] = {
nic_qp_mapping_0, nic_qp_mapping_1, nic_qp_mapping_2, nic_qp_mapping_3,
nic_qp_mapping_4, nic_qp_mapping_5, nic_qp_mapping_6, nic_qp_mapping_7
};
static const u32 default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
| NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
static int debug = -1;
static int nics_per_function = 1;
/**
* nes_netdev_poll
*/
static int nes_netdev_poll(struct napi_struct *napi, int budget)
{
struct nes_vnic *nesvnic = container_of(napi, struct nes_vnic, napi);
struct nes_device *nesdev = nesvnic->nesdev;
struct nes_hw_nic_cq *nescq = &nesvnic->nic_cq;
nesvnic->budget = budget;
nescq->cqes_pending = 0;
nescq->rx_cqes_completed = 0;
nescq->cqe_allocs_pending = 0;
nescq->rx_pkts_indicated = 0;
nes_nic_ce_handler(nesdev, nescq);
if (nescq->cqes_pending == 0) {
napi_complete(napi);
/* clear out completed cqes and arm */
nes_write32(nesdev->regs+NES_CQE_ALLOC, NES_CQE_ALLOC_NOTIFY_NEXT |
nescq->cq_number | (nescq->cqe_allocs_pending << 16));
nes_read32(nesdev->regs+NES_CQE_ALLOC);
} else {
/* clear out completed cqes but don't arm */
nes_write32(nesdev->regs+NES_CQE_ALLOC,
nescq->cq_number | (nescq->cqe_allocs_pending << 16));
nes_debug(NES_DBG_NETDEV, "%s: exiting with work pending\n",
nesvnic->netdev->name);
}
return nescq->rx_pkts_indicated;
}
/**
* nes_netdev_open - Activate the network interface; ifconfig
* ethx up.
*/
static int nes_netdev_open(struct net_device *netdev)
{
u32 macaddr_low;
u16 macaddr_high;
struct nes_vnic *nesvnic = netdev_priv(netdev);
struct nes_device *nesdev = nesvnic->nesdev;
int ret;
int i;
struct nes_vnic *first_nesvnic = NULL;
u32 nic_active_bit;
u32 nic_active;
struct list_head *list_pos, *list_temp;
unsigned long flags;
if (nesvnic->netdev_open == 1)
return 0;
if (netif_msg_ifup(nesvnic))
printk(KERN_INFO PFX "%s: enabling interface\n", netdev->name);
ret = nes_init_nic_qp(nesdev, netdev);
if (ret) {
return ret;
}
netif_carrier_off(netdev);
netif_stop_queue(netdev);
if ((!nesvnic->of_device_registered) && (nesvnic->rdma_enabled)) {
nesvnic->nesibdev = nes_init_ofa_device(netdev);
if (nesvnic->nesibdev == NULL) {
printk(KERN_ERR PFX "%s: nesvnic->nesibdev alloc failed", netdev->name);
} else {
nesvnic->nesibdev->nesvnic = nesvnic;
ret = nes_register_ofa_device(nesvnic->nesibdev);
if (ret) {
printk(KERN_ERR PFX "%s: Unable to register RDMA device, ret = %d\n",
netdev->name, ret);
}
}
}
/* Set packet filters */
nic_active_bit = 1 << nesvnic->nic_index;
nic_active = nes_read_indexed(nesdev, NES_IDX_NIC_ACTIVE);
nic_active |= nic_active_bit;
nes_write_indexed(nesdev, NES_IDX_NIC_ACTIVE, nic_active);
nic_active = nes_read_indexed(nesdev, NES_IDX_NIC_MULTICAST_ENABLE);
nic_active |= nic_active_bit;
nes_write_indexed(nesdev, NES_IDX_NIC_MULTICAST_ENABLE, nic_active);
nic_active = nes_read_indexed(nesdev, NES_IDX_NIC_BROADCAST_ON);
nic_active |= nic_active_bit;
nes_write_indexed(nesdev, NES_IDX_NIC_BROADCAST_ON, nic_active);
macaddr_high = ((u16)netdev->dev_addr[0]) << 8;
macaddr_high += (u16)netdev->dev_addr[1];
macaddr_low = ((u32)netdev->dev_addr[2]) << 24;
macaddr_low += ((u32)netdev->dev_addr[3]) << 16;
macaddr_low += ((u32)netdev->dev_addr[4]) << 8;
macaddr_low += (u32)netdev->dev_addr[5];
/* Program the various MAC regs */
for (i = 0; i < NES_MAX_PORT_COUNT; i++) {
if (nesvnic->qp_nic_index[i] == 0xf) {
break;
}
nes_debug(NES_DBG_NETDEV, "i=%d, perfect filter table index= %d, PERF FILTER LOW"
" (Addr:%08X) = %08X, HIGH = %08X.\n",
i, nesvnic->qp_nic_index[i],
NES_IDX_PERFECT_FILTER_LOW+
(nesvnic->qp_nic_index[i] * 8),
macaddr_low,
(u32)macaddr_high | NES_MAC_ADDR_VALID |
((((u32)nesvnic->nic_index) << 16)));
nes_write_indexed(nesdev,
NES_IDX_PERFECT_FILTER_LOW + (nesvnic->qp_nic_index[i] * 8),
macaddr_low);
nes_write_indexed(nesdev,
NES_IDX_PERFECT_FILTER_HIGH + (nesvnic->qp_nic_index[i] * 8),
(u32)macaddr_high | NES_MAC_ADDR_VALID |
((((u32)nesvnic->nic_index) << 16)));
}
nes_write32(nesdev->regs+NES_CQE_ALLOC, NES_CQE_ALLOC_NOTIFY_NEXT |
nesvnic->nic_cq.cq_number);
nes_read32(nesdev->regs+NES_CQE_ALLOC);
list_for_each_safe(list_pos, list_temp, &nesdev->nesadapter->nesvnic_list[nesdev->mac_index]) {
first_nesvnic = container_of(list_pos, struct nes_vnic, list);
if (first_nesvnic->netdev_open == 1)
break;
}
if (first_nesvnic->netdev_open == 0) {
nes_debug(NES_DBG_INIT, "Setting up MAC interrupt mask.\n");
nes_write_indexed(nesdev, NES_IDX_MAC_INT_MASK + (0x200 * nesdev->mac_index),
~(NES_MAC_INT_LINK_STAT_CHG | NES_MAC_INT_XGMII_EXT |
NES_MAC_INT_TX_UNDERFLOW | NES_MAC_INT_TX_ERROR));
first_nesvnic = nesvnic;
}
if (first_nesvnic->linkup) {
/* Enable network packets */
nesvnic->linkup = 1;
netif_start_queue(netdev);
netif_carrier_on(netdev);
}
spin_lock_irqsave(&nesdev->nesadapter->phy_lock, flags);
if (nesdev->nesadapter->phy_type[nesdev->mac_index] == NES_PHY_TYPE_SFP_D) {
nesdev->link_recheck = 1;
mod_delayed_work(system_wq, &nesdev->work,
NES_LINK_RECHECK_DELAY);
}
spin_unlock_irqrestore(&nesdev->nesadapter->phy_lock, flags);
spin_lock_irqsave(&nesvnic->port_ibevent_lock, flags);
if (nesvnic->of_device_registered) {
nesdev->nesadapter->send_term_ok = 1;
if (nesvnic->linkup == 1) {
if (nesdev->iw_status == 0) {
nesdev->iw_status = 1;
nes_port_ibevent(nesvnic);
}
} else {
nesdev->iw_status = 0;
}
}
spin_unlock_irqrestore(&nesvnic->port_ibevent_lock, flags);
napi_enable(&nesvnic->napi);
nesvnic->netdev_open = 1;
return 0;
}
/**
* nes_netdev_stop
*/
static int nes_netdev_stop(struct net_device *netdev)
{
struct nes_vnic *nesvnic = netdev_priv(netdev);
struct nes_device *nesdev = nesvnic->nesdev;
u32 nic_active_mask;
u32 nic_active;
struct nes_vnic *first_nesvnic = NULL;
struct list_head *list_pos, *list_temp;
unsigned long flags;
nes_debug(NES_DBG_SHUTDOWN, "nesvnic=%p, nesdev=%p, netdev=%p %s\n",
nesvnic, nesdev, netdev, netdev->name);
if (nesvnic->netdev_open == 0)
return 0;
if (netif_msg_ifdown(nesvnic))
printk(KERN_INFO PFX "%s: disabling interface\n", netdev->name);
netif_carrier_off(netdev);
/* Disable network packets */
napi_disable(&nesvnic->napi);
netif_stop_queue(netdev);
list_for_each_safe(list_pos, list_temp, &nesdev->nesadapter->nesvnic_list[nesdev->mac_index]) {
first_nesvnic = container_of(list_pos, struct nes_vnic, list);
if ((first_nesvnic->netdev_open == 1) && (first_nesvnic != nesvnic))
break;
}
if ((first_nesvnic->netdev_open == 1) && (first_nesvnic != nesvnic) &&
(PCI_FUNC(first_nesvnic->nesdev->pcidev->devfn) !=
PCI_FUNC(nesvnic->nesdev->pcidev->devfn))) {
nes_write_indexed(nesdev, NES_IDX_MAC_INT_MASK+
(0x200*nesdev->mac_index), 0xffffffff);
nes_write_indexed(first_nesvnic->nesdev,
NES_IDX_MAC_INT_MASK+
(0x200*first_nesvnic->nesdev->mac_index),
~(NES_MAC_INT_LINK_STAT_CHG | NES_MAC_INT_XGMII_EXT |
NES_MAC_INT_TX_UNDERFLOW | NES_MAC_INT_TX_ERROR));
} else {
nes_write_indexed(nesdev, NES_IDX_MAC_INT_MASK+(0x200*nesdev->mac_index), 0xffffffff);
}
nic_active_mask = ~((u32)(1 << nesvnic->nic_index));
nes_write_indexed(nesdev, NES_IDX_PERFECT_FILTER_HIGH+
(nesvnic->perfect_filter_index*8), 0);
nic_active = nes_read_indexed(nesdev, NES_IDX_NIC_ACTIVE);
nic_active &= nic_active_mask;
nes_write_indexed(nesdev, NES_IDX_NIC_ACTIVE, nic_active);
nic_active = nes_read_indexed(nesdev, NES_IDX_NIC_MULTICAST_ALL);
nic_active &= nic_active_mask;
nes_write_indexed(nesdev, NES_IDX_NIC_MULTICAST_ALL, nic_active);
nic_active = nes_read_indexed(nesdev, NES_IDX_NIC_MULTICAST_ENABLE);
nic_active &= nic_active_mask;
nes_write_indexed(nesdev, NES_IDX_NIC_MULTICAST_ENABLE, nic_active);
nic_active = nes_read_indexed(nesdev, NES_IDX_NIC_UNICAST_ALL);
nic_active &= nic_active_mask;
nes_write_indexed(nesdev, NES_IDX_NIC_UNICAST_ALL, nic_active);
nic_active = nes_read_indexed(nesdev, NES_IDX_NIC_BROADCAST_ON);
nic_active &= nic_active_mask;
nes_write_indexed(nesdev, NES_IDX_NIC_BROADCAST_ON, nic_active);
spin_lock_irqsave(&nesvnic->port_ibevent_lock, flags);
if (nesvnic->of_device_registered) {
nesdev->nesadapter->send_term_ok = 0;
nesdev->iw_status = 0;
if (nesvnic->linkup == 1)
nes_port_ibevent(nesvnic);
}
del_timer_sync(&nesvnic->event_timer);
nesvnic->event_timer.function = NULL;
spin_unlock_irqrestore(&nesvnic->port_ibevent_lock, flags);
nes_destroy_nic_qp(nesvnic);
nesvnic->netdev_open = 0;
return 0;
}
/**
* nes_nic_send
*/
static bool nes_nic_send(struct sk_buff *skb, struct net_device *netdev)
{
struct nes_vnic *nesvnic = netdev_priv(netdev);
struct nes_device *nesdev = nesvnic->nesdev;
struct nes_hw_nic *nesnic = &nesvnic->nic;
struct nes_hw_nic_sq_wqe *nic_sqe;
struct tcphdr *tcph;
__le16 *wqe_fragment_length;
u32 wqe_misc;
u16 wqe_fragment_index = 1; /* first fragment (0) is used by copy buffer */
u16 skb_fragment_index;
dma_addr_t bus_address;
nic_sqe = &nesnic->sq_vbase[nesnic->sq_head];
wqe_fragment_length = (__le16 *)&nic_sqe->wqe_words[NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX];
/* setup the VLAN tag if present */
if (skb_vlan_tag_present(skb)) {
nes_debug(NES_DBG_NIC_TX, "%s: VLAN packet to send... VLAN = %08X\n",
netdev->name, skb_vlan_tag_get(skb));
wqe_misc = NES_NIC_SQ_WQE_TAGVALUE_ENABLE;
wqe_fragment_length[0] = (__force __le16) skb_vlan_tag_get(skb);
} else
wqe_misc = 0;
/* bump past the vlan tag */
wqe_fragment_length++;
/* wqe_fragment_address = (u64 *)&nic_sqe->wqe_words[NES_NIC_SQ_WQE_FRAG0_LOW_IDX]; */
wqe_misc |= NES_NIC_SQ_WQE_COMPLETION;
if (skb->ip_summed == CHECKSUM_PARTIAL) {
if (skb_is_gso(skb)) {
tcph = tcp_hdr(skb);
/* nes_debug(NES_DBG_NIC_TX, "%s: TSO request... is_gso = %u seg size = %u\n",
netdev->name, skb_is_gso(skb), skb_shinfo(skb)->gso_size); */
wqe_misc |= NES_NIC_SQ_WQE_LSO_ENABLE | (u16)skb_shinfo(skb)->gso_size;
set_wqe_32bit_value(nic_sqe->wqe_words, NES_NIC_SQ_WQE_LSO_INFO_IDX,
((u32)tcph->doff) |
(((u32)(((unsigned char *)tcph) - skb->data)) << 4));
}
} else { /* CHECKSUM_HW */
wqe_misc |= NES_NIC_SQ_WQE_DISABLE_CHKSUM;
}
set_wqe_32bit_value(nic_sqe->wqe_words, NES_NIC_SQ_WQE_TOTAL_LENGTH_IDX,
skb->len);
memcpy(&nesnic->first_frag_vbase[nesnic->sq_head].buffer,
skb->data, min(((unsigned int)NES_FIRST_FRAG_SIZE), skb_headlen(skb)));
wqe_fragment_length[0] = cpu_to_le16(min(((unsigned int)NES_FIRST_FRAG_SIZE),
skb_headlen(skb)));
wqe_fragment_length[1] = 0;
if (skb_headlen(skb) > NES_FIRST_FRAG_SIZE) {
if ((skb_shinfo(skb)->nr_frags + 1) > 4) {
nes_debug(NES_DBG_NIC_TX, "%s: Packet with %u fragments not sent, skb_headlen=%u\n",
netdev->name, skb_shinfo(skb)->nr_frags + 2, skb_headlen(skb));
kfree_skb(skb);
nesvnic->tx_sw_dropped++;
return false;
}
set_bit(nesnic->sq_head, nesnic->first_frag_overflow);
bus_address = pci_map_single(nesdev->pcidev, skb->data + NES_FIRST_FRAG_SIZE,
skb_headlen(skb) - NES_FIRST_FRAG_SIZE, PCI_DMA_TODEVICE);
wqe_fragment_length[wqe_fragment_index++] =
cpu_to_le16(skb_headlen(skb) - NES_FIRST_FRAG_SIZE);
wqe_fragment_length[wqe_fragment_index] = 0;
set_wqe_64bit_value(nic_sqe->wqe_words, NES_NIC_SQ_WQE_FRAG1_LOW_IDX,
((u64)(bus_address)));
nesnic->tx_skb[nesnic->sq_head] = skb;
}
if (skb_headlen(skb) == skb->len) {
if (skb_headlen(skb) <= NES_FIRST_FRAG_SIZE) {
nic_sqe->wqe_words[NES_NIC_SQ_WQE_LENGTH_2_1_IDX] = 0;
nesnic->tx_skb[nesnic->sq_head] = skb;
}
} else {
/* Deal with Fragments */
nesnic->tx_skb[nesnic->sq_head] = skb;
for (skb_fragment_index = 0; skb_fragment_index < skb_shinfo(skb)->nr_frags;
skb_fragment_index++) {
skb_frag_t *frag =
&skb_shinfo(skb)->frags[skb_fragment_index];
bus_address = skb_frag_dma_map(&nesdev->pcidev->dev,
frag, 0, skb_frag_size(frag),
DMA_TO_DEVICE);
wqe_fragment_length[wqe_fragment_index] =
cpu_to_le16(skb_frag_size(&skb_shinfo(skb)->frags[skb_fragment_index]));
set_wqe_64bit_value(nic_sqe->wqe_words, NES_NIC_SQ_WQE_FRAG0_LOW_IDX+(2*wqe_fragment_index),
bus_address);
wqe_fragment_index++;
if (wqe_fragment_index < 5)
wqe_fragment_length[wqe_fragment_index] = 0;
}
}
set_wqe_32bit_value(nic_sqe->wqe_words, NES_NIC_SQ_WQE_MISC_IDX, wqe_misc);
nesnic->sq_head++;
nesnic->sq_head &= nesnic->sq_size - 1;
return true;
}
/**
* nes_netdev_start_xmit
*/
static netdev_tx_t nes_netdev_start_xmit(struct sk_buff *skb, struct net_device *netdev)
{
struct nes_vnic *nesvnic = netdev_priv(netdev);
struct nes_device *nesdev = nesvnic->nesdev;
struct nes_hw_nic *nesnic = &nesvnic->nic;
struct nes_hw_nic_sq_wqe *nic_sqe;
struct tcphdr *tcph;
/* struct udphdr *udph; */
#define NES_MAX_TSO_FRAGS MAX_SKB_FRAGS
/* 64K segment plus overflow on each side */
dma_addr_t tso_bus_address[NES_MAX_TSO_FRAGS];
dma_addr_t bus_address;
u32 tso_frag_index;
u32 tso_frag_count;
u32 tso_wqe_length;
u32 curr_tcp_seq;
u32 wqe_count=1;
struct iphdr *iph;
__le16 *wqe_fragment_length;
u32 nr_frags;
u32 original_first_length;
/* u64 *wqe_fragment_address; */
/* first fragment (0) is used by copy buffer */
u16 wqe_fragment_index=1;
u16 hoffset;
u16 nhoffset;
u16 wqes_needed;
u16 wqes_available;
u32 wqe_misc;
/*
* nes_debug(NES_DBG_NIC_TX, "%s Request to tx NIC packet length %u, headlen %u,"
* " (%u frags), tso_size=%u\n",
* netdev->name, skb->len, skb_headlen(skb),
* skb_shinfo(skb)->nr_frags, skb_is_gso(skb));
*/
if (netif_queue_stopped(netdev))
return NETDEV_TX_BUSY;
/* Check if SQ is full */
if ((((nesnic->sq_tail+(nesnic->sq_size*2))-nesnic->sq_head) & (nesnic->sq_size - 1)) == 1) {
if (!netif_queue_stopped(netdev)) {
netif_stop_queue(netdev);
barrier();
if ((((((volatile u16)nesnic->sq_tail)+(nesnic->sq_size*2))-nesnic->sq_head) & (nesnic->sq_size - 1)) != 1) {
netif_start_queue(netdev);
goto sq_no_longer_full;
}
}
nesvnic->sq_full++;
return NETDEV_TX_BUSY;
}
sq_no_longer_full:
nr_frags = skb_shinfo(skb)->nr_frags;
if (skb_headlen(skb) > NES_FIRST_FRAG_SIZE) {
nr_frags++;
}
/* Check if too many fragments */
if (unlikely((nr_frags > 4))) {
if (skb_is_gso(skb)) {
nesvnic->segmented_tso_requests++;
nesvnic->tso_requests++;
/* Basically 4 fragments available per WQE with extended fragments */
wqes_needed = nr_frags >> 2;
wqes_needed += (nr_frags&3)?1:0;
wqes_available = (((nesnic->sq_tail+nesnic->sq_size)-nesnic->sq_head) - 1) &
(nesnic->sq_size - 1);
if (unlikely(wqes_needed > wqes_available)) {
if (!netif_queue_stopped(netdev)) {
netif_stop_queue(netdev);
barrier();
wqes_available = (((((volatile u16)nesnic->sq_tail)+nesnic->sq_size)-nesnic->sq_head) - 1) &
(nesnic->sq_size - 1);
if (wqes_needed <= wqes_available) {
netif_start_queue(netdev);
goto tso_sq_no_longer_full;
}
}
nesvnic->sq_full++;
nes_debug(NES_DBG_NIC_TX, "%s: HNIC SQ full- TSO request has too many frags!\n",
netdev->name);
return NETDEV_TX_BUSY;
}
tso_sq_no_longer_full:
/* Map all the buffers */
for (tso_frag_count=0; tso_frag_count < skb_shinfo(skb)->nr_frags;
tso_frag_count++) {
skb_frag_t *frag =
&skb_shinfo(skb)->frags[tso_frag_count];
tso_bus_address[tso_frag_count] =
skb_frag_dma_map(&nesdev->pcidev->dev,
frag, 0, skb_frag_size(frag),
DMA_TO_DEVICE);
}
tso_frag_index = 0;
curr_tcp_seq = ntohl(tcp_hdr(skb)->seq);
hoffset = skb_transport_header(skb) - skb->data;
nhoffset = skb_network_header(skb) - skb->data;
original_first_length = hoffset + ((((struct tcphdr *)skb_transport_header(skb))->doff)<<2);
for (wqe_count=0; wqe_count<((u32)wqes_needed); wqe_count++) {
tso_wqe_length = 0;
nic_sqe = &nesnic->sq_vbase[nesnic->sq_head];
wqe_fragment_length =
(__le16 *)&nic_sqe->wqe_words[NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX];
/* setup the VLAN tag if present */
if (skb_vlan_tag_present(skb)) {
nes_debug(NES_DBG_NIC_TX, "%s: VLAN packet to send... VLAN = %08X\n",
netdev->name,
skb_vlan_tag_get(skb));
wqe_misc = NES_NIC_SQ_WQE_TAGVALUE_ENABLE;
wqe_fragment_length[0] = (__force __le16) skb_vlan_tag_get(skb);
} else
wqe_misc = 0;
/* bump past the vlan tag */
wqe_fragment_length++;
/* Assumes header totally fits in allocated buffer and is in first fragment */
if (original_first_length > NES_FIRST_FRAG_SIZE) {
nes_debug(NES_DBG_NIC_TX, "ERROR: SKB header too big, headlen=%u, FIRST_FRAG_SIZE=%u\n",
original_first_length, NES_FIRST_FRAG_SIZE);
nes_debug(NES_DBG_NIC_TX, "%s Request to tx NIC packet length %u, headlen %u,"
" (%u frags), is_gso = %u tso_size=%u\n",
netdev->name,
skb->len, skb_headlen(skb),
skb_shinfo(skb)->nr_frags, skb_is_gso(skb), skb_shinfo(skb)->gso_size);
}
memcpy(&nesnic->first_frag_vbase[nesnic->sq_head].buffer,
skb->data, min(((unsigned int)NES_FIRST_FRAG_SIZE),
original_first_length));
iph = (struct iphdr *)
(&nesnic->first_frag_vbase[nesnic->sq_head].buffer[nhoffset]);
tcph = (struct tcphdr *)
(&nesnic->first_frag_vbase[nesnic->sq_head].buffer[hoffset]);
if ((wqe_count+1)!=(u32)wqes_needed) {
tcph->fin = 0;
tcph->psh = 0;
tcph->rst = 0;
tcph->urg = 0;
}
if (wqe_count) {
tcph->syn = 0;
}
tcph->seq = htonl(curr_tcp_seq);
wqe_fragment_length[0] = cpu_to_le16(min(((unsigned int)NES_FIRST_FRAG_SIZE),
original_first_length));
wqe_fragment_index = 1;
if ((wqe_count==0) && (skb_headlen(skb) > original_first_length)) {
set_bit(nesnic->sq_head, nesnic->first_frag_overflow);
bus_address = pci_map_single(nesdev->pcidev, skb->data + original_first_length,
skb_headlen(skb) - original_first_length, PCI_DMA_TODEVICE);
wqe_fragment_length[wqe_fragment_index++] =
cpu_to_le16(skb_headlen(skb) - original_first_length);
wqe_fragment_length[wqe_fragment_index] = 0;
set_wqe_64bit_value(nic_sqe->wqe_words, NES_NIC_SQ_WQE_FRAG1_LOW_IDX,
bus_address);
tso_wqe_length += skb_headlen(skb) -
original_first_length;
}
while (wqe_fragment_index < 5) {
wqe_fragment_length[wqe_fragment_index] =
cpu_to_le16(skb_frag_size(&skb_shinfo(skb)->frags[tso_frag_index]));
set_wqe_64bit_value(nic_sqe->wqe_words, NES_NIC_SQ_WQE_FRAG0_LOW_IDX+(2*wqe_fragment_index),
(u64)tso_bus_address[tso_frag_index]);
wqe_fragment_index++;
tso_wqe_length += skb_frag_size(&skb_shinfo(skb)->frags[tso_frag_index++]);
if (wqe_fragment_index < 5)
wqe_fragment_length[wqe_fragment_index] = 0;
if (tso_frag_index == tso_frag_count)
break;
}
if ((wqe_count+1) == (u32)wqes_needed) {
nesnic->tx_skb[nesnic->sq_head] = skb;
} else {
nesnic->tx_skb[nesnic->sq_head] = NULL;
}
wqe_misc |= NES_NIC_SQ_WQE_COMPLETION | (u16)skb_shinfo(skb)->gso_size;
if ((tso_wqe_length + original_first_length) > skb_shinfo(skb)->gso_size) {
wqe_misc |= NES_NIC_SQ_WQE_LSO_ENABLE;
} else {
iph->tot_len = htons(tso_wqe_length + original_first_length - nhoffset);
}
set_wqe_32bit_value(nic_sqe->wqe_words, NES_NIC_SQ_WQE_MISC_IDX,
wqe_misc);
set_wqe_32bit_value(nic_sqe->wqe_words, NES_NIC_SQ_WQE_LSO_INFO_IDX,
((u32)tcph->doff) | (((u32)hoffset) << 4));
set_wqe_32bit_value(nic_sqe->wqe_words, NES_NIC_SQ_WQE_TOTAL_LENGTH_IDX,
tso_wqe_length + original_first_length);
curr_tcp_seq += tso_wqe_length;
nesnic->sq_head++;
nesnic->sq_head &= nesnic->sq_size-1;
}
} else {
hoffset = skb_transport_header(skb) - skb->data;
nhoffset = skb_network_header(skb) - skb->data;
if (skb_linearize(skb)) {
nesvnic->tx_sw_dropped++;
kfree_skb(skb);
return NETDEV_TX_OK;
}
nesvnic->linearized_skbs++;
skb_set_transport_header(skb, hoffset);
skb_set_network_header(skb, nhoffset);
if (!nes_nic_send(skb, netdev))
return NETDEV_TX_OK;
}
} else {
if (!nes_nic_send(skb, netdev))
return NETDEV_TX_OK;
}
barrier();
if (wqe_count)
nes_write32(nesdev->regs+NES_WQE_ALLOC,
(wqe_count << 24) | (1 << 23) | nesvnic->nic.qp_id);
netif_trans_update(netdev);
return NETDEV_TX_OK;
}
/**
* nes_netdev_get_stats
*/
static struct net_device_stats *nes_netdev_get_stats(struct net_device *netdev)
{
struct nes_vnic *nesvnic = netdev_priv(netdev);
struct nes_device *nesdev = nesvnic->nesdev;
u64 u64temp;
u32 u32temp;
u32temp = nes_read_indexed(nesdev,
NES_IDX_ENDNODE0_NSTAT_RX_DISCARD + (nesvnic->nic_index*0x200));
nesvnic->netstats.rx_dropped += u32temp;
nesvnic->endnode_nstat_rx_discard += u32temp;
u64temp = (u64)nes_read_indexed(nesdev,
NES_IDX_ENDNODE0_NSTAT_RX_OCTETS_LO + (nesvnic->nic_index*0x200));
u64temp += ((u64)nes_read_indexed(nesdev,
NES_IDX_ENDNODE0_NSTAT_RX_OCTETS_HI + (nesvnic->nic_index*0x200))) << 32;
nesvnic->endnode_nstat_rx_octets += u64temp;
nesvnic->netstats.rx_bytes += u64temp;
u64temp = (u64)nes_read_indexed(nesdev,
NES_IDX_ENDNODE0_NSTAT_RX_FRAMES_LO + (nesvnic->nic_index*0x200));
u64temp += ((u64)nes_read_indexed(nesdev,
NES_IDX_ENDNODE0_NSTAT_RX_FRAMES_HI + (nesvnic->nic_index*0x200))) << 32;
nesvnic->endnode_nstat_rx_frames += u64temp;
nesvnic->netstats.rx_packets += u64temp;
u64temp = (u64)nes_read_indexed(nesdev,
NES_IDX_ENDNODE0_NSTAT_TX_OCTETS_LO + (nesvnic->nic_index*0x200));
u64temp += ((u64)nes_read_indexed(nesdev,
NES_IDX_ENDNODE0_NSTAT_TX_OCTETS_HI + (nesvnic->nic_index*0x200))) << 32;
nesvnic->endnode_nstat_tx_octets += u64temp;
nesvnic->netstats.tx_bytes += u64temp;
u64temp = (u64)nes_read_indexed(nesdev,
NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_LO + (nesvnic->nic_index*0x200));
u64temp += ((u64)nes_read_indexed(nesdev,
NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_HI + (nesvnic->nic_index*0x200))) << 32;
nesvnic->endnode_nstat_tx_frames += u64temp;
nesvnic->netstats.tx_packets += u64temp;
u32temp = nes_read_indexed(nesdev,
NES_IDX_MAC_RX_SHORT_FRAMES + (nesvnic->nesdev->mac_index*0x200));
nesvnic->netstats.rx_dropped += u32temp;
nesvnic->nesdev->mac_rx_errors += u32temp;
nesvnic->nesdev->mac_rx_short_frames += u32temp;
u32temp = nes_read_indexed(nesdev,
NES_IDX_MAC_RX_OVERSIZED_FRAMES + (nesvnic->nesdev->mac_index*0x200));
nesvnic->netstats.rx_dropped += u32temp;
nesvnic->nesdev->mac_rx_errors += u32temp;
nesvnic->nesdev->mac_rx_oversized_frames += u32temp;
u32temp = nes_read_indexed(nesdev,
NES_IDX_MAC_RX_JABBER_FRAMES + (nesvnic->nesdev->mac_index*0x200));
nesvnic->netstats.rx_dropped += u32temp;
nesvnic->nesdev->mac_rx_errors += u32temp;
nesvnic->nesdev->mac_rx_jabber_frames += u32temp;
u32temp = nes_read_indexed(nesdev,
NES_IDX_MAC_RX_SYMBOL_ERR_FRAMES + (nesvnic->nesdev->mac_index*0x200));
nesvnic->netstats.rx_dropped += u32temp;
nesvnic->nesdev->mac_rx_errors += u32temp;
nesvnic->nesdev->mac_rx_symbol_err_frames += u32temp;
u32temp = nes_read_indexed(nesdev,
NES_IDX_MAC_RX_LENGTH_ERR_FRAMES + (nesvnic->nesdev->mac_index*0x200));
nesvnic->netstats.rx_length_errors += u32temp;
nesvnic->nesdev->mac_rx_errors += u32temp;
u32temp = nes_read_indexed(nesdev,
NES_IDX_MAC_RX_CRC_ERR_FRAMES + (nesvnic->nesdev->mac_index*0x200));
nesvnic->nesdev->mac_rx_errors += u32temp;
nesvnic->nesdev->mac_rx_crc_errors += u32temp;
nesvnic->netstats.rx_crc_errors += u32temp;
u32temp = nes_read_indexed(nesdev,
NES_IDX_MAC_TX_ERRORS + (nesvnic->nesdev->mac_index*0x200));
nesvnic->nesdev->mac_tx_errors += u32temp;
nesvnic->netstats.tx_errors += u32temp;
return &nesvnic->netstats;
}
/**
* nes_netdev_tx_timeout
*/
static void nes_netdev_tx_timeout(struct net_device *netdev)
{
struct nes_vnic *nesvnic = netdev_priv(netdev);
if (netif_msg_timer(nesvnic))
nes_debug(NES_DBG_NIC_TX, "%s: tx timeout\n", netdev->name);
}
/**
* nes_netdev_set_mac_address
*/
static int nes_netdev_set_mac_address(struct net_device *netdev, void *p)
{
struct nes_vnic *nesvnic = netdev_priv(netdev);
struct nes_device *nesdev = nesvnic->nesdev;
struct sockaddr *mac_addr = p;
int i;
u32 macaddr_low;
u16 macaddr_high;
if (!is_valid_ether_addr(mac_addr->sa_data))
return -EADDRNOTAVAIL;
memcpy(netdev->dev_addr, mac_addr->sa_data, netdev->addr_len);
printk(PFX "%s: Address length = %d, Address = %pM\n",
__func__, netdev->addr_len, mac_addr->sa_data);
macaddr_high = ((u16)netdev->dev_addr[0]) << 8;
macaddr_high += (u16)netdev->dev_addr[1];
macaddr_low = ((u32)netdev->dev_addr[2]) << 24;
macaddr_low += ((u32)netdev->dev_addr[3]) << 16;
macaddr_low += ((u32)netdev->dev_addr[4]) << 8;
macaddr_low += (u32)netdev->dev_addr[5];
for (i = 0; i < NES_MAX_PORT_COUNT; i++) {
if (nesvnic->qp_nic_index[i] == 0xf) {
break;
}
nes_write_indexed(nesdev,
NES_IDX_PERFECT_FILTER_LOW + (nesvnic->qp_nic_index[i] * 8),
macaddr_low);
nes_write_indexed(nesdev,
NES_IDX_PERFECT_FILTER_HIGH + (nesvnic->qp_nic_index[i] * 8),
(u32)macaddr_high | NES_MAC_ADDR_VALID |
((((u32)nesvnic->nic_index) << 16)));
}
return 0;
}
static void set_allmulti(struct nes_device *nesdev, u32 nic_active_bit)
{
u32 nic_active;
nic_active = nes_read_indexed(nesdev, NES_IDX_NIC_MULTICAST_ALL);
nic_active |= nic_active_bit;
nes_write_indexed(nesdev, NES_IDX_NIC_MULTICAST_ALL, nic_active);
nic_active = nes_read_indexed(nesdev, NES_IDX_NIC_UNICAST_ALL);
nic_active &= ~nic_active_bit;
nes_write_indexed(nesdev, NES_IDX_NIC_UNICAST_ALL, nic_active);
}
#define get_addr(addrs, index) ((addrs) + (index) * ETH_ALEN)
/**
* nes_netdev_set_multicast_list
*/
static void nes_netdev_set_multicast_list(struct net_device *netdev)
{
struct nes_vnic *nesvnic = netdev_priv(netdev);
struct nes_device *nesdev = nesvnic->nesdev;
struct nes_adapter *nesadapter = nesvnic->nesdev->nesadapter;
u32 nic_active_bit;
u32 nic_active;
u32 perfect_filter_register_address;
u32 macaddr_low;
u16 macaddr_high;
u8 mc_all_on = 0;
u8 mc_index;
int mc_nic_index = -1;
u8 pft_entries_preallocated = max(nesadapter->adapter_fcn_count *
nics_per_function, 4);
u8 max_pft_entries_avaiable = NES_PFT_SIZE - pft_entries_preallocated;
unsigned long flags;
int mc_count = netdev_mc_count(netdev);
spin_lock_irqsave(&nesadapter->resource_lock, flags);
nic_active_bit = 1 << nesvnic->nic_index;
if (netdev->flags & IFF_PROMISC) {
nic_active = nes_read_indexed(nesdev, NES_IDX_NIC_MULTICAST_ALL);
nic_active |= nic_active_bit;
nes_write_indexed(nesdev, NES_IDX_NIC_MULTICAST_ALL, nic_active);
nic_active = nes_read_indexed(nesdev, NES_IDX_NIC_UNICAST_ALL);
nic_active |= nic_active_bit;
nes_write_indexed(nesdev, NES_IDX_NIC_UNICAST_ALL, nic_active);
mc_all_on = 1;
} else if ((netdev->flags & IFF_ALLMULTI) ||
(nesvnic->nic_index > 3)) {
set_allmulti(nesdev, nic_active_bit);
mc_all_on = 1;
} else {
nic_active = nes_read_indexed(nesdev, NES_IDX_NIC_MULTICAST_ALL);
nic_active &= ~nic_active_bit;
nes_write_indexed(nesdev, NES_IDX_NIC_MULTICAST_ALL, nic_active);
nic_active = nes_read_indexed(nesdev, NES_IDX_NIC_UNICAST_ALL);
nic_active &= ~nic_active_bit;
nes_write_indexed(nesdev, NES_IDX_NIC_UNICAST_ALL, nic_active);
}
nes_debug(NES_DBG_NIC_RX, "Number of MC entries = %d, Promiscuous = %d, All Multicast = %d.\n",
mc_count, !!(netdev->flags & IFF_PROMISC),
!!(netdev->flags & IFF_ALLMULTI));
if (!mc_all_on) {
char *addrs;
int i;
struct netdev_hw_addr *ha;
addrs = kmalloc_array(mc_count, ETH_ALEN, GFP_ATOMIC);
if (!addrs) {
set_allmulti(nesdev, nic_active_bit);
goto unlock;
}
i = 0;
netdev_for_each_mc_addr(ha, netdev)
memcpy(get_addr(addrs, i++), ha->addr, ETH_ALEN);
perfect_filter_register_address = NES_IDX_PERFECT_FILTER_LOW +
pft_entries_preallocated * 0x8;
for (i = 0, mc_index = 0; mc_index < max_pft_entries_avaiable;
mc_index++) {
while (i < mc_count && nesvnic->mcrq_mcast_filter &&
((mc_nic_index = nesvnic->mcrq_mcast_filter(nesvnic,
get_addr(addrs, i++))) == 0));
if (mc_nic_index < 0)
mc_nic_index = nesvnic->nic_index;
while (nesadapter->pft_mcast_map[mc_index] < 16 &&
nesadapter->pft_mcast_map[mc_index] !=
nesvnic->nic_index &&
mc_index < max_pft_entries_avaiable) {
nes_debug(NES_DBG_NIC_RX,
"mc_index=%d skipping nic_index=%d, used for=%d\n",
mc_index, nesvnic->nic_index,
nesadapter->pft_mcast_map[mc_index]);
mc_index++;
}
if (mc_index >= max_pft_entries_avaiable)
break;
if (i < mc_count) {
char *addr = get_addr(addrs, i++);
nes_debug(NES_DBG_NIC_RX, "Assigning MC Address %pM to register 0x%04X nic_idx=%d\n",
addr,
perfect_filter_register_address+(mc_index * 8),
mc_nic_index);
macaddr_high = ((u8) addr[0]) << 8;
macaddr_high += (u8) addr[1];
macaddr_low = ((u8) addr[2]) << 24;
macaddr_low += ((u8) addr[3]) << 16;
macaddr_low += ((u8) addr[4]) << 8;
macaddr_low += (u8) addr[5];
nes_write_indexed(nesdev,
perfect_filter_register_address+(mc_index * 8),
macaddr_low);
nes_write_indexed(nesdev,
perfect_filter_register_address+4+(mc_index * 8),
(u32)macaddr_high | NES_MAC_ADDR_VALID |
((((u32)(1<<mc_nic_index)) << 16)));
nesadapter->pft_mcast_map[mc_index] =
nesvnic->nic_index;
} else {
nes_debug(NES_DBG_NIC_RX, "Clearing MC Address at register 0x%04X\n",
perfect_filter_register_address+(mc_index * 8));
nes_write_indexed(nesdev,
perfect_filter_register_address+4+(mc_index * 8),
0);
nesadapter->pft_mcast_map[mc_index] = 255;
}
}
kfree(addrs);
/* PFT is not large enough */
if (i < mc_count)
set_allmulti(nesdev, nic_active_bit);
}
unlock:
spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
}
/**
* nes_netdev_change_mtu
*/
static int nes_netdev_change_mtu(struct net_device *netdev, int new_mtu)
{
struct nes_vnic *nesvnic = netdev_priv(netdev);
struct nes_device *nesdev = nesvnic->nesdev;
u8 jumbomode = 0;
u32 nic_active;
u32 nic_active_bit;
u32 uc_all_active;
u32 mc_all_active;
netdev->mtu = new_mtu;
nesvnic->max_frame_size = new_mtu + VLAN_ETH_HLEN;
if (netdev->mtu > ETH_DATA_LEN) {
jumbomode=1;
}
nes_nic_init_timer_defaults(nesdev, jumbomode);
if (netif_running(netdev)) {
nic_active_bit = 1 << nesvnic->nic_index;
mc_all_active = nes_read_indexed(nesdev,
NES_IDX_NIC_MULTICAST_ALL) & nic_active_bit;
uc_all_active = nes_read_indexed(nesdev,
NES_IDX_NIC_UNICAST_ALL) & nic_active_bit;
nes_netdev_stop(netdev);
nes_netdev_open(netdev);
nic_active = nes_read_indexed(nesdev,
NES_IDX_NIC_MULTICAST_ALL);
nic_active |= mc_all_active;
nes_write_indexed(nesdev, NES_IDX_NIC_MULTICAST_ALL,
nic_active);
nic_active = nes_read_indexed(nesdev, NES_IDX_NIC_UNICAST_ALL);
nic_active |= uc_all_active;
nes_write_indexed(nesdev, NES_IDX_NIC_UNICAST_ALL, nic_active);
}
return 0;
}
static const char nes_ethtool_stringset[][ETH_GSTRING_LEN] = {
"Link Change Interrupts",
"Linearized SKBs",
"T/GSO Requests",
"Pause Frames Sent",
"Pause Frames Received",
"Internal Routing Errors",
"SQ SW Dropped SKBs",
"SQ Full",
"Segmented TSO Requests",
"Rx Symbol Errors",
"Rx Jabber Errors",
"Rx Oversized Frames",
"Rx Short Frames",
"Rx Length Errors",
"Rx CRC Errors",
"Rx Port Discard",
"Endnode Rx Discards",
"Endnode Rx Octets",
"Endnode Rx Frames",
"Endnode Tx Octets",
"Endnode Tx Frames",
"Tx Errors",
"mh detected",
"mh pauses",
"Retransmission Count",
"CM Connects",
"CM Accepts",
"Disconnects",
"Connected Events",
"Connect Requests",
"CM Rejects",
"ModifyQP Timeouts",
"CreateQPs",
"SW DestroyQPs",
"DestroyQPs",
"CM Closes",
"CM Packets Sent",
"CM Packets Bounced",
"CM Packets Created",
"CM Packets Rcvd",
"CM Packets Dropped",
"CM Packets Retrans",
"CM Listens Created",
"CM Listens Destroyed",
"CM Backlog Drops",
"CM Loopbacks",
"CM Nodes Created",
"CM Nodes Destroyed",
"CM Accel Drops",
"CM Resets Received",
"Free 4Kpbls",
"Free 256pbls",
"Timer Inits",
"PAU CreateQPs",
"PAU DestroyQPs",
};
#define NES_ETHTOOL_STAT_COUNT ARRAY_SIZE(nes_ethtool_stringset)
/**
* nes_netdev_get_sset_count
*/
static int nes_netdev_get_sset_count(struct net_device *netdev, int stringset)
{
if (stringset == ETH_SS_STATS)
return NES_ETHTOOL_STAT_COUNT;
else
return -EINVAL;
}
/**
* nes_netdev_get_strings
*/
static void nes_netdev_get_strings(struct net_device *netdev, u32 stringset,
u8 *ethtool_strings)
{
if (stringset == ETH_SS_STATS)
memcpy(ethtool_strings,
&nes_ethtool_stringset,
sizeof(nes_ethtool_stringset));
}
/**
* nes_netdev_get_ethtool_stats
*/
static void nes_netdev_get_ethtool_stats(struct net_device *netdev,
struct ethtool_stats *target_ethtool_stats, u64 *target_stat_values)
{
u64 u64temp;
struct nes_vnic *nesvnic = netdev_priv(netdev);
struct nes_device *nesdev = nesvnic->nesdev;
struct nes_adapter *nesadapter = nesdev->nesadapter;
u32 nic_count;
u32 u32temp;
u32 index = 0;
target_ethtool_stats->n_stats = NES_ETHTOOL_STAT_COUNT;
target_stat_values[index] = nesvnic->nesdev->link_status_interrupts;
target_stat_values[++index] = nesvnic->linearized_skbs;
target_stat_values[++index] = nesvnic->tso_requests;
u32temp = nes_read_indexed(nesdev,
NES_IDX_MAC_TX_PAUSE_FRAMES + (nesvnic->nesdev->mac_index*0x200));
nesvnic->nesdev->mac_pause_frames_sent += u32temp;
target_stat_values[++index] = nesvnic->nesdev->mac_pause_frames_sent;
u32temp = nes_read_indexed(nesdev,
NES_IDX_MAC_RX_PAUSE_FRAMES + (nesvnic->nesdev->mac_index*0x200));
nesvnic->nesdev->mac_pause_frames_received += u32temp;
u32temp = nes_read_indexed(nesdev,
NES_IDX_PORT_RX_DISCARDS + (nesvnic->nesdev->mac_index*0x40));
nesvnic->nesdev->port_rx_discards += u32temp;
nesvnic->netstats.rx_dropped += u32temp;
u32temp = nes_read_indexed(nesdev,
NES_IDX_PORT_TX_DISCARDS + (nesvnic->nesdev->mac_index*0x40));
nesvnic->nesdev->port_tx_discards += u32temp;
nesvnic->netstats.tx_dropped += u32temp;
u32temp = nes_read_indexed(nesdev,
NES_IDX_MAC_RX_SHORT_FRAMES + (nesvnic->nesdev->mac_index*0x200));
nesvnic->netstats.rx_dropped += u32temp;
nesvnic->nesdev->mac_rx_errors += u32temp;
nesvnic->nesdev->mac_rx_short_frames += u32temp;
u32temp = nes_read_indexed(nesdev,
NES_IDX_MAC_RX_OVERSIZED_FRAMES + (nesvnic->nesdev->mac_index*0x200));
nesvnic->netstats.rx_dropped += u32temp;
nesvnic->nesdev->mac_rx_errors += u32temp;
nesvnic->nesdev->mac_rx_oversized_frames += u32temp;
u32temp = nes_read_indexed(nesdev,
NES_IDX_MAC_RX_JABBER_FRAMES + (nesvnic->nesdev->mac_index*0x200));
nesvnic->netstats.rx_dropped += u32temp;
nesvnic->nesdev->mac_rx_errors += u32temp;
nesvnic->nesdev->mac_rx_jabber_frames += u32temp;
u32temp = nes_read_indexed(nesdev,
NES_IDX_MAC_RX_SYMBOL_ERR_FRAMES + (nesvnic->nesdev->mac_index*0x200));
nesvnic->netstats.rx_dropped += u32temp;
nesvnic->nesdev->mac_rx_errors += u32temp;
nesvnic->nesdev->mac_rx_symbol_err_frames += u32temp;
u32temp = nes_read_indexed(nesdev,
NES_IDX_MAC_RX_LENGTH_ERR_FRAMES + (nesvnic->nesdev->mac_index*0x200));
nesvnic->netstats.rx_length_errors += u32temp;
nesvnic->nesdev->mac_rx_errors += u32temp;
u32temp = nes_read_indexed(nesdev,
NES_IDX_MAC_RX_CRC_ERR_FRAMES + (nesvnic->nesdev->mac_index*0x200));
nesvnic->nesdev->mac_rx_errors += u32temp;
nesvnic->nesdev->mac_rx_crc_errors += u32temp;
nesvnic->netstats.rx_crc_errors += u32temp;
u32temp = nes_read_indexed(nesdev,
NES_IDX_MAC_TX_ERRORS + (nesvnic->nesdev->mac_index*0x200));
nesvnic->nesdev->mac_tx_errors += u32temp;
nesvnic->netstats.tx_errors += u32temp;
for (nic_count = 0; nic_count < NES_MAX_PORT_COUNT; nic_count++) {
if (nesvnic->qp_nic_index[nic_count] == 0xf)
break;
u32temp = nes_read_indexed(nesdev,
NES_IDX_ENDNODE0_NSTAT_RX_DISCARD +
(nesvnic->qp_nic_index[nic_count]*0x200));
nesvnic->netstats.rx_dropped += u32temp;
nesvnic->endnode_nstat_rx_discard += u32temp;
u64temp = (u64)nes_read_indexed(nesdev,
NES_IDX_ENDNODE0_NSTAT_RX_OCTETS_LO +
(nesvnic->qp_nic_index[nic_count]*0x200));
u64temp += ((u64)nes_read_indexed(nesdev,
NES_IDX_ENDNODE0_NSTAT_RX_OCTETS_HI +
(nesvnic->qp_nic_index[nic_count]*0x200))) << 32;
nesvnic->endnode_nstat_rx_octets += u64temp;
nesvnic->netstats.rx_bytes += u64temp;
u64temp = (u64)nes_read_indexed(nesdev,
NES_IDX_ENDNODE0_NSTAT_RX_FRAMES_LO +
(nesvnic->qp_nic_index[nic_count]*0x200));
u64temp += ((u64)nes_read_indexed(nesdev,
NES_IDX_ENDNODE0_NSTAT_RX_FRAMES_HI +
(nesvnic->qp_nic_index[nic_count]*0x200))) << 32;
nesvnic->endnode_nstat_rx_frames += u64temp;
nesvnic->netstats.rx_packets += u64temp;
u64temp = (u64)nes_read_indexed(nesdev,
NES_IDX_ENDNODE0_NSTAT_TX_OCTETS_LO +
(nesvnic->qp_nic_index[nic_count]*0x200));
u64temp += ((u64)nes_read_indexed(nesdev,
NES_IDX_ENDNODE0_NSTAT_TX_OCTETS_HI +
(nesvnic->qp_nic_index[nic_count]*0x200))) << 32;
nesvnic->endnode_nstat_tx_octets += u64temp;
nesvnic->netstats.tx_bytes += u64temp;
u64temp = (u64)nes_read_indexed(nesdev,
NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_LO +
(nesvnic->qp_nic_index[nic_count]*0x200));
u64temp += ((u64)nes_read_indexed(nesdev,
NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_HI +
(nesvnic->qp_nic_index[nic_count]*0x200))) << 32;
nesvnic->endnode_nstat_tx_frames += u64temp;
nesvnic->netstats.tx_packets += u64temp;
u32temp = nes_read_indexed(nesdev,
NES_IDX_IPV4_TCP_REXMITS + (nesvnic->qp_nic_index[nic_count]*0x200));
nesvnic->endnode_ipv4_tcp_retransmits += u32temp;
}
target_stat_values[++index] = nesvnic->nesdev->mac_pause_frames_received;
target_stat_values[++index] = nesdev->nesadapter->nic_rx_eth_route_err;
target_stat_values[++index] = nesvnic->tx_sw_dropped;
target_stat_values[++index] = nesvnic->sq_full;
target_stat_values[++index] = nesvnic->segmented_tso_requests;
target_stat_values[++index] = nesvnic->nesdev->mac_rx_symbol_err_frames;
target_stat_values[++index] = nesvnic->nesdev->mac_rx_jabber_frames;
target_stat_values[++index] = nesvnic->nesdev->mac_rx_oversized_frames;
target_stat_values[++index] = nesvnic->nesdev->mac_rx_short_frames;
target_stat_values[++index] = nesvnic->netstats.rx_length_errors;
target_stat_values[++index] = nesvnic->nesdev->mac_rx_crc_errors;
target_stat_values[++index] = nesvnic->nesdev->port_rx_discards;
target_stat_values[++index] = nesvnic->endnode_nstat_rx_discard;
target_stat_values[++index] = nesvnic->endnode_nstat_rx_octets;
target_stat_values[++index] = nesvnic->endnode_nstat_rx_frames;
target_stat_values[++index] = nesvnic->endnode_nstat_tx_octets;
target_stat_values[++index] = nesvnic->endnode_nstat_tx_frames;
target_stat_values[++index] = nesvnic->nesdev->mac_tx_errors;
target_stat_values[++index] = mh_detected;
target_stat_values[++index] = mh_pauses_sent;
target_stat_values[++index] = nesvnic->endnode_ipv4_tcp_retransmits;
target_stat_values[++index] = atomic_read(&cm_connects);
target_stat_values[++index] = atomic_read(&cm_accepts);
target_stat_values[++index] = atomic_read(&cm_disconnects);
target_stat_values[++index] = atomic_read(&cm_connecteds);
target_stat_values[++index] = atomic_read(&cm_connect_reqs);
target_stat_values[++index] = atomic_read(&cm_rejects);
target_stat_values[++index] = atomic_read(&mod_qp_timouts);
target_stat_values[++index] = atomic_read(&qps_created);
target_stat_values[++index] = atomic_read(&sw_qps_destroyed);
target_stat_values[++index] = atomic_read(&qps_destroyed);
target_stat_values[++index] = atomic_read(&cm_closes);
target_stat_values[++index] = cm_packets_sent;
target_stat_values[++index] = cm_packets_bounced;
target_stat_values[++index] = cm_packets_created;
target_stat_values[++index] = cm_packets_received;
target_stat_values[++index] = cm_packets_dropped;
target_stat_values[++index] = cm_packets_retrans;
target_stat_values[++index] = atomic_read(&cm_listens_created);
target_stat_values[++index] = atomic_read(&cm_listens_destroyed);
target_stat_values[++index] = cm_backlog_drops;
target_stat_values[++index] = atomic_read(&cm_loopbacks);
target_stat_values[++index] = atomic_read(&cm_nodes_created);
target_stat_values[++index] = atomic_read(&cm_nodes_destroyed);
target_stat_values[++index] = atomic_read(&cm_accel_dropped_pkts);
target_stat_values[++index] = atomic_read(&cm_resets_recvd);
target_stat_values[++index] = nesadapter->free_4kpbl;
target_stat_values[++index] = nesadapter->free_256pbl;
target_stat_values[++index] = int_mod_timer_init;
target_stat_values[++index] = atomic_read(&pau_qps_created);
target_stat_values[++index] = atomic_read(&pau_qps_destroyed);
}
/**
* nes_netdev_get_drvinfo
*/
static void nes_netdev_get_drvinfo(struct net_device *netdev,
struct ethtool_drvinfo *drvinfo)
{
struct nes_vnic *nesvnic = netdev_priv(netdev);
struct nes_adapter *nesadapter = nesvnic->nesdev->nesadapter;
strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
strlcpy(drvinfo->bus_info, pci_name(nesvnic->nesdev->pcidev),
sizeof(drvinfo->bus_info));
snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
"%u.%u", nesadapter->firmware_version >> 16,
nesadapter->firmware_version & 0x000000ff);
strlcpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version));
}
/**
* nes_netdev_set_coalesce
*/
static int nes_netdev_set_coalesce(struct net_device *netdev,
struct ethtool_coalesce *et_coalesce)
{
struct nes_vnic *nesvnic = netdev_priv(netdev);
struct nes_device *nesdev = nesvnic->nesdev;
struct nes_adapter *nesadapter = nesdev->nesadapter;
struct nes_hw_tune_timer *shared_timer = &nesadapter->tune_timer;
unsigned long flags;
spin_lock_irqsave(&nesadapter->periodic_timer_lock, flags);
if (et_coalesce->rx_max_coalesced_frames_low) {
shared_timer->threshold_low = et_coalesce->rx_max_coalesced_frames_low;
}
if (et_coalesce->rx_max_coalesced_frames_irq) {
shared_timer->threshold_target = et_coalesce->rx_max_coalesced_frames_irq;
}
if (et_coalesce->rx_max_coalesced_frames_high) {
shared_timer->threshold_high = et_coalesce->rx_max_coalesced_frames_high;
}
if (et_coalesce->rx_coalesce_usecs_low) {
shared_timer->timer_in_use_min = et_coalesce->rx_coalesce_usecs_low;
}
if (et_coalesce->rx_coalesce_usecs_high) {
shared_timer->timer_in_use_max = et_coalesce->rx_coalesce_usecs_high;
}
spin_unlock_irqrestore(&nesadapter->periodic_timer_lock, flags);
/* using this to drive total interrupt moderation */
nesadapter->et_rx_coalesce_usecs_irq = et_coalesce->rx_coalesce_usecs_irq;
if (et_coalesce->use_adaptive_rx_coalesce) {
nesadapter->et_use_adaptive_rx_coalesce = 1;
nesadapter->timer_int_limit = NES_TIMER_INT_LIMIT_DYNAMIC;
nesadapter->et_rx_coalesce_usecs_irq = 0;
if (et_coalesce->pkt_rate_low) {
nesadapter->et_pkt_rate_low = et_coalesce->pkt_rate_low;
}
} else {
nesadapter->et_use_adaptive_rx_coalesce = 0;
nesadapter->timer_int_limit = NES_TIMER_INT_LIMIT;
if (nesadapter->et_rx_coalesce_usecs_irq) {
nes_write32(nesdev->regs+NES_PERIODIC_CONTROL,
0x80000000 | ((u32)(nesadapter->et_rx_coalesce_usecs_irq*8)));
}
}
return 0;
}
/**
* nes_netdev_get_coalesce
*/
static int nes_netdev_get_coalesce(struct net_device *netdev,
struct ethtool_coalesce *et_coalesce)
{
struct nes_vnic *nesvnic = netdev_priv(netdev);
struct nes_device *nesdev = nesvnic->nesdev;
struct nes_adapter *nesadapter = nesdev->nesadapter;
struct ethtool_coalesce temp_et_coalesce;
struct nes_hw_tune_timer *shared_timer = &nesadapter->tune_timer;
unsigned long flags;
memset(&temp_et_coalesce, 0, sizeof(temp_et_coalesce));
temp_et_coalesce.rx_coalesce_usecs_irq = nesadapter->et_rx_coalesce_usecs_irq;
temp_et_coalesce.use_adaptive_rx_coalesce = nesadapter->et_use_adaptive_rx_coalesce;
temp_et_coalesce.rate_sample_interval = nesadapter->et_rate_sample_interval;
temp_et_coalesce.pkt_rate_low = nesadapter->et_pkt_rate_low;
spin_lock_irqsave(&nesadapter->periodic_timer_lock, flags);
temp_et_coalesce.rx_max_coalesced_frames_low = shared_timer->threshold_low;
temp_et_coalesce.rx_max_coalesced_frames_irq = shared_timer->threshold_target;
temp_et_coalesce.rx_max_coalesced_frames_high = shared_timer->threshold_high;
temp_et_coalesce.rx_coalesce_usecs_low = shared_timer->timer_in_use_min;
temp_et_coalesce.rx_coalesce_usecs_high = shared_timer->timer_in_use_max;
if (nesadapter->et_use_adaptive_rx_coalesce) {
temp_et_coalesce.rx_coalesce_usecs_irq = shared_timer->timer_in_use;
}
spin_unlock_irqrestore(&nesadapter->periodic_timer_lock, flags);
memcpy(et_coalesce, &temp_et_coalesce, sizeof(*et_coalesce));
return 0;
}
/**
* nes_netdev_get_pauseparam
*/
static void nes_netdev_get_pauseparam(struct net_device *netdev,
struct ethtool_pauseparam *et_pauseparam)
{
struct nes_vnic *nesvnic = netdev_priv(netdev);
et_pauseparam->autoneg = 0;
et_pauseparam->rx_pause = (nesvnic->nesdev->disable_rx_flow_control == 0) ? 1:0;
et_pauseparam->tx_pause = (nesvnic->nesdev->disable_tx_flow_control == 0) ? 1:0;
}
/**
* nes_netdev_set_pauseparam
*/
static int nes_netdev_set_pauseparam(struct net_device *netdev,
struct ethtool_pauseparam *et_pauseparam)
{
struct nes_vnic *nesvnic = netdev_priv(netdev);
struct nes_device *nesdev = nesvnic->nesdev;
u32 u32temp;
if (et_pauseparam->autoneg) {
/* TODO: should return unsupported */
return 0;
}
if ((et_pauseparam->tx_pause == 1) && (nesdev->disable_tx_flow_control == 1)) {
u32temp = nes_read_indexed(nesdev,
NES_IDX_MAC_TX_CONFIG + (nesdev->mac_index*0x200));
u32temp |= NES_IDX_MAC_TX_CONFIG_ENABLE_PAUSE;
nes_write_indexed(nesdev,
NES_IDX_MAC_TX_CONFIG + (nesdev->mac_index*0x200), u32temp);
nesdev->disable_tx_flow_control = 0;
} else if ((et_pauseparam->tx_pause == 0) && (nesdev->disable_tx_flow_control == 0)) {
u32temp = nes_read_indexed(nesdev,
NES_IDX_MAC_TX_CONFIG + (nesdev->mac_index*0x200));
u32temp &= ~NES_IDX_MAC_TX_CONFIG_ENABLE_PAUSE;
nes_write_indexed(nesdev,
NES_IDX_MAC_TX_CONFIG + (nesdev->mac_index*0x200), u32temp);
nesdev->disable_tx_flow_control = 1;
}
if ((et_pauseparam->rx_pause == 1) && (nesdev->disable_rx_flow_control == 1)) {
u32temp = nes_read_indexed(nesdev,
NES_IDX_MPP_DEBUG + (nesdev->mac_index*0x40));
u32temp &= ~NES_IDX_MPP_DEBUG_PORT_DISABLE_PAUSE;
nes_write_indexed(nesdev,
NES_IDX_MPP_DEBUG + (nesdev->mac_index*0x40), u32temp);
nesdev->disable_rx_flow_control = 0;
} else if ((et_pauseparam->rx_pause == 0) && (nesdev->disable_rx_flow_control == 0)) {
u32temp = nes_read_indexed(nesdev,
NES_IDX_MPP_DEBUG + (nesdev->mac_index*0x40));
u32temp |= NES_IDX_MPP_DEBUG_PORT_DISABLE_PAUSE;
nes_write_indexed(nesdev,
NES_IDX_MPP_DEBUG + (nesdev->mac_index*0x40), u32temp);
nesdev->disable_rx_flow_control = 1;
}
return 0;
}
/**
* nes_netdev_get_settings
*/
static int nes_netdev_get_link_ksettings(struct net_device *netdev,
struct ethtool_link_ksettings *cmd)
{
struct nes_vnic *nesvnic = netdev_priv(netdev);
struct nes_device *nesdev = nesvnic->nesdev;
struct nes_adapter *nesadapter = nesdev->nesadapter;
u32 mac_index = nesdev->mac_index;
u8 phy_type = nesadapter->phy_type[mac_index];
u8 phy_index = nesadapter->phy_index[mac_index];
u16 phy_data;
u32 supported, advertising;
cmd->base.duplex = DUPLEX_FULL;
cmd->base.port = PORT_MII;
if (nesadapter->OneG_Mode) {
cmd->base.speed = SPEED_1000;
if (phy_type == NES_PHY_TYPE_PUMA_1G) {
supported = SUPPORTED_1000baseT_Full;
advertising = ADVERTISED_1000baseT_Full;
cmd->base.autoneg = AUTONEG_DISABLE;
cmd->base.phy_address = mac_index;
} else {
unsigned long flags;
supported = SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg;
advertising = ADVERTISED_1000baseT_Full
| ADVERTISED_Autoneg;
spin_lock_irqsave(&nesadapter->phy_lock, flags);
nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data);
spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
if (phy_data & 0x1000)
cmd->base.autoneg = AUTONEG_ENABLE;
else
cmd->base.autoneg = AUTONEG_DISABLE;
cmd->base.phy_address = phy_index;
}
ethtool_convert_legacy_u32_to_link_mode(
cmd->link_modes.supported, supported);
ethtool_convert_legacy_u32_to_link_mode(
cmd->link_modes.advertising, advertising);
return 0;
}
if ((phy_type == NES_PHY_TYPE_ARGUS) ||
(phy_type == NES_PHY_TYPE_SFP_D) ||
(phy_type == NES_PHY_TYPE_KR)) {
cmd->base.port = PORT_FIBRE;
supported = SUPPORTED_FIBRE;
advertising = ADVERTISED_FIBRE;
cmd->base.phy_address = phy_index;
} else {
supported = SUPPORTED_10000baseT_Full;
advertising = ADVERTISED_10000baseT_Full;
cmd->base.phy_address = mac_index;
}
cmd->base.speed = SPEED_10000;
cmd->base.autoneg = AUTONEG_DISABLE;
ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
supported);
ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
advertising);
return 0;
}
/**
* nes_netdev_set_settings
*/
static int
nes_netdev_set_link_ksettings(struct net_device *netdev,
const struct ethtool_link_ksettings *cmd)
{
struct nes_vnic *nesvnic = netdev_priv(netdev);
struct nes_device *nesdev = nesvnic->nesdev;
struct nes_adapter *nesadapter = nesdev->nesadapter;
if ((nesadapter->OneG_Mode) &&
(nesadapter->phy_type[nesdev->mac_index] != NES_PHY_TYPE_PUMA_1G)) {
unsigned long flags;
u16 phy_data;
u8 phy_index = nesadapter->phy_index[nesdev->mac_index];
spin_lock_irqsave(&nesadapter->phy_lock, flags);
nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data);
if (cmd->base.autoneg) {
/* Turn on Full duplex, Autoneg, and restart autonegotiation */
phy_data |= 0x1300;
} else {
/* Turn off autoneg */
phy_data &= ~0x1000;
}
nes_write_1G_phy_reg(nesdev, 0, phy_index, phy_data);
spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
}
return 0;
}
static const struct ethtool_ops nes_ethtool_ops = {
.get_link = ethtool_op_get_link,
.get_strings = nes_netdev_get_strings,
.get_sset_count = nes_netdev_get_sset_count,
.get_ethtool_stats = nes_netdev_get_ethtool_stats,
.get_drvinfo = nes_netdev_get_drvinfo,
.get_coalesce = nes_netdev_get_coalesce,
.set_coalesce = nes_netdev_set_coalesce,
.get_pauseparam = nes_netdev_get_pauseparam,
.set_pauseparam = nes_netdev_set_pauseparam,
.get_link_ksettings = nes_netdev_get_link_ksettings,
.set_link_ksettings = nes_netdev_set_link_ksettings,
};
static void nes_vlan_mode(struct net_device *netdev, struct nes_device *nesdev, netdev_features_t features)
{
struct nes_adapter *nesadapter = nesdev->nesadapter;
u32 u32temp;
unsigned long flags;
spin_lock_irqsave(&nesadapter->phy_lock, flags);
nes_debug(NES_DBG_NETDEV, "%s: %s\n", __func__, netdev->name);
/* Enable/Disable VLAN Stripping */
u32temp = nes_read_indexed(nesdev, NES_IDX_PCIX_DIAG);
if (features & NETIF_F_HW_VLAN_CTAG_RX)
u32temp &= 0xfdffffff;
else
u32temp |= 0x02000000;
nes_write_indexed(nesdev, NES_IDX_PCIX_DIAG, u32temp);
spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
}
static netdev_features_t nes_fix_features(struct net_device *netdev, netdev_features_t features)
{
/*
* Since there is no support for separate rx/tx vlan accel
* enable/disable make sure tx flag is always in same state as rx.
*/
if (features & NETIF_F_HW_VLAN_CTAG_RX)
features |= NETIF_F_HW_VLAN_CTAG_TX;
else
features &= ~NETIF_F_HW_VLAN_CTAG_TX;
return features;
}
static int nes_set_features(struct net_device *netdev, netdev_features_t features)
{
struct nes_vnic *nesvnic = netdev_priv(netdev);
struct nes_device *nesdev = nesvnic->nesdev;
u32 changed = netdev->features ^ features;
if (changed & NETIF_F_HW_VLAN_CTAG_RX)
nes_vlan_mode(netdev, nesdev, features);
return 0;
}
static const struct net_device_ops nes_netdev_ops = {
.ndo_open = nes_netdev_open,
.ndo_stop = nes_netdev_stop,
.ndo_start_xmit = nes_netdev_start_xmit,
.ndo_get_stats = nes_netdev_get_stats,
.ndo_tx_timeout = nes_netdev_tx_timeout,
.ndo_set_mac_address = nes_netdev_set_mac_address,
.ndo_set_rx_mode = nes_netdev_set_multicast_list,
.ndo_change_mtu = nes_netdev_change_mtu,
.ndo_validate_addr = eth_validate_addr,
.ndo_fix_features = nes_fix_features,
.ndo_set_features = nes_set_features,
};
/**
* nes_netdev_init - initialize network device
*/
struct net_device *nes_netdev_init(struct nes_device *nesdev,
void __iomem *mmio_addr)
{
u64 u64temp;
struct nes_vnic *nesvnic;
struct net_device *netdev;
struct nic_qp_map *curr_qp_map;
u8 phy_type = nesdev->nesadapter->phy_type[nesdev->mac_index];
netdev = alloc_etherdev(sizeof(struct nes_vnic));
if (!netdev) {
printk(KERN_ERR PFX "nesvnic etherdev alloc failed");
return NULL;
}
nesvnic = netdev_priv(netdev);
nes_debug(NES_DBG_INIT, "netdev = %p, %s\n", netdev, netdev->name);
SET_NETDEV_DEV(netdev, &nesdev->pcidev->dev);
netdev->watchdog_timeo = NES_TX_TIMEOUT;
netdev->irq = nesdev->pcidev->irq;
netdev->max_mtu = NES_MAX_MTU;
netdev->hard_header_len = ETH_HLEN;
netdev->addr_len = ETH_ALEN;
netdev->type = ARPHRD_ETHER;
netdev->netdev_ops = &nes_netdev_ops;
netdev->ethtool_ops = &nes_ethtool_ops;
netif_napi_add(netdev, &nesvnic->napi, nes_netdev_poll, 128);
nes_debug(NES_DBG_INIT, "Enabling VLAN Insert/Delete.\n");
/* Fill in the port structure */
nesvnic->netdev = netdev;
nesvnic->nesdev = nesdev;
nesvnic->msg_enable = netif_msg_init(debug, default_msg);
nesvnic->netdev_index = nesdev->netdev_count;
nesvnic->perfect_filter_index = nesdev->nesadapter->netdev_count;
nesvnic->max_frame_size = netdev->mtu + netdev->hard_header_len + VLAN_HLEN;
curr_qp_map = nic_qp_mapping_per_function[PCI_FUNC(nesdev->pcidev->devfn)];
nesvnic->nic.qp_id = curr_qp_map[nesdev->netdev_count].qpid;
nesvnic->nic_index = curr_qp_map[nesdev->netdev_count].nic_index;
nesvnic->logical_port = curr_qp_map[nesdev->netdev_count].logical_port;
/* Setup the burned in MAC address */
u64temp = (u64)nesdev->nesadapter->mac_addr_low;
u64temp += ((u64)nesdev->nesadapter->mac_addr_high) << 32;
u64temp += nesvnic->nic_index;
netdev->dev_addr[0] = (u8)(u64temp>>40);
netdev->dev_addr[1] = (u8)(u64temp>>32);
netdev->dev_addr[2] = (u8)(u64temp>>24);
netdev->dev_addr[3] = (u8)(u64temp>>16);
netdev->dev_addr[4] = (u8)(u64temp>>8);
netdev->dev_addr[5] = (u8)u64temp;
netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
if ((nesvnic->logical_port < 2) || (nesdev->nesadapter->hw_rev != NE020_REV))
netdev->hw_features |= NETIF_F_TSO;
netdev->features = netdev->hw_features | NETIF_F_HIGHDMA | NETIF_F_HW_VLAN_CTAG_TX;
nes_debug(NES_DBG_INIT, "nesvnic = %p, reported features = 0x%lX, QPid = %d,"
" nic_index = %d, logical_port = %d, mac_index = %d.\n",
nesvnic, (unsigned long)netdev->features, nesvnic->nic.qp_id,
nesvnic->nic_index, nesvnic->logical_port, nesdev->mac_index);
if (nesvnic->nesdev->nesadapter->port_count == 1 &&
nesvnic->nesdev->nesadapter->adapter_fcn_count == 1) {
nesvnic->qp_nic_index[0] = nesvnic->nic_index;
nesvnic->qp_nic_index[1] = nesvnic->nic_index + 1;
if (nes_drv_opt & NES_DRV_OPT_DUAL_LOGICAL_PORT) {
nesvnic->qp_nic_index[2] = 0xf;
nesvnic->qp_nic_index[3] = 0xf;
} else {
nesvnic->qp_nic_index[2] = nesvnic->nic_index + 2;
nesvnic->qp_nic_index[3] = nesvnic->nic_index + 3;
}
} else {
if (nesvnic->nesdev->nesadapter->port_count == 2 ||
(nesvnic->nesdev->nesadapter->port_count == 1 &&
nesvnic->nesdev->nesadapter->adapter_fcn_count == 2)) {
nesvnic->qp_nic_index[0] = nesvnic->nic_index;
nesvnic->qp_nic_index[1] = nesvnic->nic_index
+ 2;
nesvnic->qp_nic_index[2] = 0xf;
nesvnic->qp_nic_index[3] = 0xf;
} else {
nesvnic->qp_nic_index[0] = nesvnic->nic_index;
nesvnic->qp_nic_index[1] = 0xf;
nesvnic->qp_nic_index[2] = 0xf;
nesvnic->qp_nic_index[3] = 0xf;
}
}
nesvnic->next_qp_nic_index = 0;
if (nesdev->netdev_count == 0) {
nesvnic->rdma_enabled = 1;
} else {
nesvnic->rdma_enabled = 0;
}
nesvnic->nic_cq.cq_number = nesvnic->nic.qp_id;
timer_setup(&nesvnic->event_timer, NULL, 0);
spin_lock_init(&nesvnic->tx_lock);
spin_lock_init(&nesvnic->port_ibevent_lock);
nesdev->netdev[nesdev->netdev_count] = netdev;
nes_debug(NES_DBG_INIT, "Adding nesvnic (%p) to the adapters nesvnic_list for MAC%d.\n",
nesvnic, nesdev->mac_index);
list_add_tail(&nesvnic->list, &nesdev->nesadapter->nesvnic_list[nesdev->mac_index]);
if ((nesdev->netdev_count == 0) &&
((PCI_FUNC(nesdev->pcidev->devfn) == nesdev->mac_index) ||
((phy_type == NES_PHY_TYPE_PUMA_1G) &&
(((PCI_FUNC(nesdev->pcidev->devfn) == 1) && (nesdev->mac_index == 2)) ||
((PCI_FUNC(nesdev->pcidev->devfn) == 2) && (nesdev->mac_index == 1)))))) {
u32 u32temp;
u32 link_mask = 0;
u32 link_val = 0;
u16 temp_phy_data;
u16 phy_data = 0;
unsigned long flags;
u32temp = nes_read_indexed(nesdev, NES_IDX_PHY_PCS_CONTROL_STATUS0 +
(0x200 * (nesdev->mac_index & 1)));
if (phy_type != NES_PHY_TYPE_PUMA_1G) {
u32temp |= 0x00200000;
nes_write_indexed(nesdev, NES_IDX_PHY_PCS_CONTROL_STATUS0 +
(0x200 * (nesdev->mac_index & 1)), u32temp);
}
/* Check and set linkup here. This is for back to back */
/* configuration where second port won't get link interrupt */
switch (phy_type) {
case NES_PHY_TYPE_PUMA_1G:
if (nesdev->mac_index < 2) {
link_mask = 0x01010000;
link_val = 0x01010000;
} else {
link_mask = 0x02020000;
link_val = 0x02020000;
}
break;
case NES_PHY_TYPE_SFP_D:
spin_lock_irqsave(&nesdev->nesadapter->phy_lock, flags);
nes_read_10G_phy_reg(nesdev,
nesdev->nesadapter->phy_index[nesdev->mac_index],
1, 0x9003);
temp_phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
nes_read_10G_phy_reg(nesdev,
nesdev->nesadapter->phy_index[nesdev->mac_index],
3, 0x0021);
nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
nes_read_10G_phy_reg(nesdev,
nesdev->nesadapter->phy_index[nesdev->mac_index],
3, 0x0021);
phy_data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
spin_unlock_irqrestore(&nesdev->nesadapter->phy_lock, flags);
phy_data = (!temp_phy_data && (phy_data == 0x8000)) ? 0x4 : 0x0;
break;
default:
link_mask = 0x0f1f0000;
link_val = 0x0f0f0000;
break;
}
u32temp = nes_read_indexed(nesdev,
NES_IDX_PHY_PCS_CONTROL_STATUS0 +
(0x200 * (nesdev->mac_index & 1)));
if (phy_type == NES_PHY_TYPE_SFP_D) {
if (phy_data & 0x0004)
nesvnic->linkup = 1;
} else {
if ((u32temp & link_mask) == link_val)
nesvnic->linkup = 1;
}
/* clear the MAC interrupt status, assumes direct logical to physical mapping */
u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS + (0x200 * nesdev->mac_index));
nes_debug(NES_DBG_INIT, "Phy interrupt status = 0x%X.\n", u32temp);
nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS + (0x200 * nesdev->mac_index), u32temp);
nes_init_phy(nesdev);
}
nes_vlan_mode(netdev, nesdev, netdev->features);
return netdev;
}
/**
* nes_netdev_destroy - destroy network device structure
*/
void nes_netdev_destroy(struct net_device *netdev)
{
struct nes_vnic *nesvnic = netdev_priv(netdev);
/* make sure 'stop' method is called by Linux stack */
/* nes_netdev_stop(netdev); */
list_del(&nesvnic->list);
if (nesvnic->of_device_registered) {
nes_destroy_ofa_device(nesvnic->nesibdev);
}
free_netdev(netdev);
}
/**
* nes_nic_cm_xmit -- CM calls this to send out pkts
*/
int nes_nic_cm_xmit(struct sk_buff *skb, struct net_device *netdev)
{
int ret;
skb->dev = netdev;
ret = dev_queue_xmit(skb);
if (ret) {
nes_debug(NES_DBG_CM, "Bad return code from dev_queue_xmit %d\n", ret);
}
return ret;
}
drivers/infiniband/hw/nes/nes_utils.c deleted 100644 → 0
View file @ cbdc666f
/*
* Copyright (c) 2006 - 2011 Intel Corporation. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/ethtool.h>
#include <linux/mii.h>
#include <linux/if_vlan.h>
#include <linux/slab.h>
#include <linux/crc32.h>
#include <linux/in.h>
#include <linux/ip.h>
#include <linux/tcp.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/byteorder.h>
#include "nes.h"
static u16 nes_read16_eeprom(void __iomem *addr, u16 offset);
u32 mh_detected;
u32 mh_pauses_sent;
static u32 nes_set_pau(struct nes_device *nesdev)
{
u32 ret = 0;
u32 counter;
nes_write_indexed(nesdev, NES_IDX_GPR2, NES_ENABLE_PAU);
nes_write_indexed(nesdev, NES_IDX_GPR_TRIGGER, 1);
for (counter = 0; counter < NES_PAU_COUNTER; counter++) {
udelay(30);
if (!nes_read_indexed(nesdev, NES_IDX_GPR2)) {
printk(KERN_INFO PFX "PAU is supported.\n");
break;
}
nes_write_indexed(nesdev, NES_IDX_GPR_TRIGGER, 1);
}
if (counter == NES_PAU_COUNTER) {
printk(KERN_INFO PFX "PAU is not supported.\n");
return -EPERM;
}
return ret;
}
/**
* nes_read_eeprom_values -
*/
int nes_read_eeprom_values(struct nes_device *nesdev, struct nes_adapter *nesadapter)
{
u32 mac_addr_low;
u16 mac_addr_high;
u16 eeprom_data;
u16 eeprom_offset;
u16 next_section_address;
u16 sw_section_ver;
u8 major_ver = 0;
u8 minor_ver = 0;
/* TODO: deal with EEPROM endian issues */
if (nesadapter->firmware_eeprom_offset == 0) {
/* Read the EEPROM Parameters */
eeprom_data = nes_read16_eeprom(nesdev->regs, 0);
nes_debug(NES_DBG_HW, "EEPROM Offset 0 = 0x%04X\n", eeprom_data);
eeprom_offset = 2 + (((eeprom_data & 0x007f) << 3) <<
((eeprom_data & 0x0080) >> 7));
nes_debug(NES_DBG_HW, "Firmware Offset = 0x%04X\n", eeprom_offset);
nesadapter->firmware_eeprom_offset = eeprom_offset;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 4);
if (eeprom_data != 0x5746) {
nes_debug(NES_DBG_HW, "Not a valid Firmware Image = 0x%04X\n", eeprom_data);
return -1;
}
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
nes_debug(NES_DBG_HW, "EEPROM Offset %u = 0x%04X\n",
eeprom_offset + 2, eeprom_data);
eeprom_offset += ((eeprom_data & 0x00ff) << 3) << ((eeprom_data & 0x0100) >> 8);
nes_debug(NES_DBG_HW, "Software Offset = 0x%04X\n", eeprom_offset);
nesadapter->software_eeprom_offset = eeprom_offset;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 4);
if (eeprom_data != 0x5753) {
printk("Not a valid Software Image = 0x%04X\n", eeprom_data);
return -1;
}
sw_section_ver = nes_read16_eeprom(nesdev->regs, nesadapter->software_eeprom_offset + 6);
nes_debug(NES_DBG_HW, "Software section version number = 0x%04X\n",
sw_section_ver);
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
eeprom_offset + 2, eeprom_data);
next_section_address = eeprom_offset + (((eeprom_data & 0x00ff) << 3) <<
((eeprom_data & 0x0100) >> 8));
eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
if (eeprom_data != 0x414d) {
nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x414d but was 0x%04X\n",
eeprom_data);
goto no_fw_rev;
}
eeprom_offset = next_section_address;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
eeprom_offset + 2, eeprom_data);
next_section_address = eeprom_offset + (((eeprom_data & 0x00ff) << 3) <<
((eeprom_data & 0x0100) >> 8));
eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
if (eeprom_data != 0x4f52) {
nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x4f52 but was 0x%04X\n",
eeprom_data);
goto no_fw_rev;
}
eeprom_offset = next_section_address;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
eeprom_offset + 2, eeprom_data);
next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
if (eeprom_data != 0x5746) {
nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x5746 but was 0x%04X\n",
eeprom_data);
goto no_fw_rev;
}
eeprom_offset = next_section_address;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
eeprom_offset + 2, eeprom_data);
next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
if (eeprom_data != 0x5753) {
nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x5753 but was 0x%04X\n",
eeprom_data);
goto no_fw_rev;
}
eeprom_offset = next_section_address;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
eeprom_offset + 2, eeprom_data);
next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
if (eeprom_data != 0x414d) {
nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x414d but was 0x%04X\n",
eeprom_data);
goto no_fw_rev;
}
eeprom_offset = next_section_address;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
eeprom_offset + 2, eeprom_data);
next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
if (eeprom_data != 0x464e) {
nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x464e but was 0x%04X\n",
eeprom_data);
goto no_fw_rev;
}
eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 8);
printk(PFX "Firmware version %u.%u\n", (u8)(eeprom_data>>8), (u8)eeprom_data);
major_ver = (u8)(eeprom_data >> 8);
minor_ver = (u8)(eeprom_data);
if (nes_drv_opt & NES_DRV_OPT_DISABLE_VIRT_WQ) {
nes_debug(NES_DBG_HW, "Virtual WQs have been disabled\n");
} else if (((major_ver == 2) && (minor_ver > 21)) || ((major_ver > 2) && (major_ver != 255))) {
nesadapter->virtwq = 1;
}
if (((major_ver == 3) && (minor_ver >= 16)) || (major_ver > 3))
nesadapter->send_term_ok = 1;
if (nes_drv_opt & NES_DRV_OPT_ENABLE_PAU) {
if (!nes_set_pau(nesdev))
nesadapter->allow_unaligned_fpdus = 1;
}
nesadapter->firmware_version = (((u32)(u8)(eeprom_data>>8)) << 16) +
(u32)((u8)eeprom_data);
eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 10);
printk(PFX "EEPROM version %u.%u\n", (u8)(eeprom_data>>8), (u8)eeprom_data);
nesadapter->eeprom_version = (((u32)(u8)(eeprom_data>>8)) << 16) +
(u32)((u8)eeprom_data);
no_fw_rev:
/* eeprom is valid */
eeprom_offset = nesadapter->software_eeprom_offset;
eeprom_offset += 8;
nesadapter->netdev_max = (u8)nes_read16_eeprom(nesdev->regs, eeprom_offset);
eeprom_offset += 2;
mac_addr_high = nes_read16_eeprom(nesdev->regs, eeprom_offset);
eeprom_offset += 2;
mac_addr_low = (u32)nes_read16_eeprom(nesdev->regs, eeprom_offset);
eeprom_offset += 2;
mac_addr_low <<= 16;
mac_addr_low += (u32)nes_read16_eeprom(nesdev->regs, eeprom_offset);
nes_debug(NES_DBG_HW, "Base MAC Address = 0x%04X%08X\n",
mac_addr_high, mac_addr_low);
nes_debug(NES_DBG_HW, "MAC Address count = %u\n", nesadapter->netdev_max);
nesadapter->mac_addr_low = mac_addr_low;
nesadapter->mac_addr_high = mac_addr_high;
/* Read the Phy Type array */
eeprom_offset += 10;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
nesadapter->phy_type[0] = (u8)(eeprom_data >> 8);
nesadapter->phy_type[1] = (u8)eeprom_data;
/* Read the port array */
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
nesadapter->phy_type[2] = (u8)(eeprom_data >> 8);
nesadapter->phy_type[3] = (u8)eeprom_data;
/* port_count is set by soft reset reg */
nes_debug(NES_DBG_HW, "port_count = %u, port 0 -> %u, port 1 -> %u,"
" port 2 -> %u, port 3 -> %u\n",
nesadapter->port_count,
nesadapter->phy_type[0], nesadapter->phy_type[1],
nesadapter->phy_type[2], nesadapter->phy_type[3]);
/* Read PD config array */
eeprom_offset += 10;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
nesadapter->pd_config_size[0] = eeprom_data;
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
nesadapter->pd_config_base[0] = eeprom_data;
nes_debug(NES_DBG_HW, "PD0 config, size=0x%04x, base=0x%04x\n",
nesadapter->pd_config_size[0], nesadapter->pd_config_base[0]);
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
nesadapter->pd_config_size[1] = eeprom_data;
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
nesadapter->pd_config_base[1] = eeprom_data;
nes_debug(NES_DBG_HW, "PD1 config, size=0x%04x, base=0x%04x\n",
nesadapter->pd_config_size[1], nesadapter->pd_config_base[1]);
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
nesadapter->pd_config_size[2] = eeprom_data;
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
nesadapter->pd_config_base[2] = eeprom_data;
nes_debug(NES_DBG_HW, "PD2 config, size=0x%04x, base=0x%04x\n",
nesadapter->pd_config_size[2], nesadapter->pd_config_base[2]);
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
nesadapter->pd_config_size[3] = eeprom_data;
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
nesadapter->pd_config_base[3] = eeprom_data;
nes_debug(NES_DBG_HW, "PD3 config, size=0x%04x, base=0x%04x\n",
nesadapter->pd_config_size[3], nesadapter->pd_config_base[3]);
/* Read Rx Pool Size */
eeprom_offset += 22; /* 46 */
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
eeprom_offset += 2;
nesadapter->rx_pool_size = (((u32)eeprom_data) << 16) +
nes_read16_eeprom(nesdev->regs, eeprom_offset);
nes_debug(NES_DBG_HW, "rx_pool_size = 0x%08X\n", nesadapter->rx_pool_size);
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
eeprom_offset += 2;
nesadapter->tx_pool_size = (((u32)eeprom_data) << 16) +
nes_read16_eeprom(nesdev->regs, eeprom_offset);
nes_debug(NES_DBG_HW, "tx_pool_size = 0x%08X\n", nesadapter->tx_pool_size);
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
eeprom_offset += 2;
nesadapter->rx_threshold = (((u32)eeprom_data) << 16) +
nes_read16_eeprom(nesdev->regs, eeprom_offset);
nes_debug(NES_DBG_HW, "rx_threshold = 0x%08X\n", nesadapter->rx_threshold);
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
eeprom_offset += 2;
nesadapter->tcp_timer_core_clk_divisor = (((u32)eeprom_data) << 16) +
nes_read16_eeprom(nesdev->regs, eeprom_offset);
nes_debug(NES_DBG_HW, "tcp_timer_core_clk_divisor = 0x%08X\n",
nesadapter->tcp_timer_core_clk_divisor);
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
eeprom_offset += 2;
nesadapter->iwarp_config = (((u32)eeprom_data) << 16) +
nes_read16_eeprom(nesdev->regs, eeprom_offset);
nes_debug(NES_DBG_HW, "iwarp_config = 0x%08X\n", nesadapter->iwarp_config);
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
eeprom_offset += 2;
nesadapter->cm_config = (((u32)eeprom_data) << 16) +
nes_read16_eeprom(nesdev->regs, eeprom_offset);
nes_debug(NES_DBG_HW, "cm_config = 0x%08X\n", nesadapter->cm_config);
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
eeprom_offset += 2;
nesadapter->sws_timer_config = (((u32)eeprom_data) << 16) +
nes_read16_eeprom(nesdev->regs, eeprom_offset);
nes_debug(NES_DBG_HW, "sws_timer_config = 0x%08X\n", nesadapter->sws_timer_config);
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
eeprom_offset += 2;
nesadapter->tcp_config1 = (((u32)eeprom_data) << 16) +
nes_read16_eeprom(nesdev->regs, eeprom_offset);
nes_debug(NES_DBG_HW, "tcp_config1 = 0x%08X\n", nesadapter->tcp_config1);
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
eeprom_offset += 2;
nesadapter->wqm_wat = (((u32)eeprom_data) << 16) +
nes_read16_eeprom(nesdev->regs, eeprom_offset);
nes_debug(NES_DBG_HW, "wqm_wat = 0x%08X\n", nesadapter->wqm_wat);
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
eeprom_offset += 2;
nesadapter->core_clock = (((u32)eeprom_data) << 16) +
nes_read16_eeprom(nesdev->regs, eeprom_offset);
nes_debug(NES_DBG_HW, "core_clock = 0x%08X\n", nesadapter->core_clock);
if ((sw_section_ver) && (nesadapter->hw_rev != NE020_REV)) {
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
nesadapter->phy_index[0] = (eeprom_data & 0xff00)>>8;
nesadapter->phy_index[1] = eeprom_data & 0x00ff;
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
nesadapter->phy_index[2] = (eeprom_data & 0xff00)>>8;
nesadapter->phy_index[3] = eeprom_data & 0x00ff;
} else {
nesadapter->phy_index[0] = 4;
nesadapter->phy_index[1] = 5;
nesadapter->phy_index[2] = 6;
nesadapter->phy_index[3] = 7;
}
nes_debug(NES_DBG_HW, "Phy address map = 0 > %u, 1 > %u, 2 > %u, 3 > %u\n",
nesadapter->phy_index[0],nesadapter->phy_index[1],
nesadapter->phy_index[2],nesadapter->phy_index[3]);
}
return 0;
}
/**
* nes_read16_eeprom
*/
static u16 nes_read16_eeprom(void __iomem *addr, u16 offset)
{
writel(NES_EEPROM_READ_REQUEST + (offset >> 1),
(void __iomem *)addr + NES_EEPROM_COMMAND);
do {
} while (readl((void __iomem *)addr + NES_EEPROM_COMMAND) &
NES_EEPROM_READ_REQUEST);
return readw((void __iomem *)addr + NES_EEPROM_DATA);
}
/**
* nes_write_1G_phy_reg
*/
void nes_write_1G_phy_reg(struct nes_device *nesdev, u8 phy_reg, u8 phy_addr, u16 data)
{
u32 u32temp;
u32 counter;
nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
0x50020000 | data | ((u32)phy_reg << 18) | ((u32)phy_addr << 23));
for (counter = 0; counter < 100 ; counter++) {
udelay(30);
u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
if (u32temp & 1) {
/* nes_debug(NES_DBG_PHY, "Phy interrupt status = 0x%X.\n", u32temp); */
nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
break;
}
}
if (!(u32temp & 1))
nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
u32temp);
}
/**
* nes_read_1G_phy_reg
* This routine only issues the read, the data must be read
* separately.
*/
void nes_read_1G_phy_reg(struct nes_device *nesdev, u8 phy_reg, u8 phy_addr, u16 *data)
{
u32 u32temp;
u32 counter;
/* nes_debug(NES_DBG_PHY, "phy addr = %d, mac_index = %d\n",
phy_addr, nesdev->mac_index); */
nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
0x60020000 | ((u32)phy_reg << 18) | ((u32)phy_addr << 23));
for (counter = 0; counter < 100 ; counter++) {
udelay(30);
u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
if (u32temp & 1) {
/* nes_debug(NES_DBG_PHY, "Phy interrupt status = 0x%X.\n", u32temp); */
nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
break;
}
}
if (!(u32temp & 1)) {
nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
u32temp);
*data = 0xffff;
} else {
*data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
}
}
/**
* nes_write_10G_phy_reg
*/
void nes_write_10G_phy_reg(struct nes_device *nesdev, u16 phy_addr, u8 dev_addr, u16 phy_reg,
u16 data)
{
u32 port_addr;
u32 u32temp;
u32 counter;
port_addr = phy_addr;
/* set address */
nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
0x00020000 | (u32)phy_reg | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
for (counter = 0; counter < 100 ; counter++) {
udelay(30);
u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
if (u32temp & 1) {
nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
break;
}
}
if (!(u32temp & 1))
nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
u32temp);
/* set data */
nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
0x10020000 | (u32)data | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
for (counter = 0; counter < 100 ; counter++) {
udelay(30);
u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
if (u32temp & 1) {
nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
break;
}
}
if (!(u32temp & 1))
nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
u32temp);
}
/**
* nes_read_10G_phy_reg
* This routine only issues the read, the data must be read
* separately.
*/
void nes_read_10G_phy_reg(struct nes_device *nesdev, u8 phy_addr, u8 dev_addr, u16 phy_reg)
{
u32 port_addr;
u32 u32temp;
u32 counter;
port_addr = phy_addr;
/* set address */
nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
0x00020000 | (u32)phy_reg | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
for (counter = 0; counter < 100 ; counter++) {
udelay(30);
u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
if (u32temp & 1) {
nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
break;
}
}
if (!(u32temp & 1))
nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
u32temp);
/* issue read */
nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
0x30020000 | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
for (counter = 0; counter < 100 ; counter++) {
udelay(30);
u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
if (u32temp & 1) {
nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
break;
}
}
if (!(u32temp & 1))
nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
u32temp);
}
/**
* nes_get_cqp_request
*/
struct nes_cqp_request *nes_get_cqp_request(struct nes_device *nesdev)
{
unsigned long flags;
struct nes_cqp_request *cqp_request = NULL;
if (!list_empty(&nesdev->cqp_avail_reqs)) {
spin_lock_irqsave(&nesdev->cqp.lock, flags);
if (!list_empty(&nesdev->cqp_avail_reqs)) {
cqp_request = list_entry(nesdev->cqp_avail_reqs.next,
struct nes_cqp_request, list);
list_del_init(&cqp_request->list);
}
spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
}
if (cqp_request == NULL) {
cqp_request = kzalloc(sizeof(struct nes_cqp_request), GFP_ATOMIC);
if (cqp_request) {
cqp_request->dynamic = 1;
INIT_LIST_HEAD(&cqp_request->list);
}
}
if (cqp_request) {
init_waitqueue_head(&cqp_request->waitq);
cqp_request->waiting = 0;
cqp_request->request_done = 0;
cqp_request->callback = 0;
nes_debug(NES_DBG_CQP, "Got cqp request %p from the available list \n",
cqp_request);
}
return cqp_request;
}
void nes_free_cqp_request(struct nes_device *nesdev,
struct nes_cqp_request *cqp_request)
{
unsigned long flags;
nes_debug(NES_DBG_CQP, "CQP request %p (opcode 0x%02X) freed.\n",
cqp_request,
le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_OPCODE_IDX]) & 0x3f);
if (cqp_request->dynamic) {
kfree(cqp_request);
} else {
spin_lock_irqsave(&nesdev->cqp.lock, flags);
list_add_tail(&cqp_request->list, &nesdev->cqp_avail_reqs);
spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
}
}
void nes_put_cqp_request(struct nes_device *nesdev,
struct nes_cqp_request *cqp_request)
{
if (atomic_dec_and_test(&cqp_request->refcount))
nes_free_cqp_request(nesdev, cqp_request);
}
/**
* nes_post_cqp_request
*/
void nes_post_cqp_request(struct nes_device *nesdev,
struct nes_cqp_request *cqp_request)
{
struct nes_hw_cqp_wqe *cqp_wqe;
unsigned long flags;
u32 cqp_head;
u64 u64temp;
u32 opcode;
int ctx_index = NES_CQP_WQE_COMP_CTX_LOW_IDX;
spin_lock_irqsave(&nesdev->cqp.lock, flags);
if (((((nesdev->cqp.sq_tail+(nesdev->cqp.sq_size*2))-nesdev->cqp.sq_head) &
(nesdev->cqp.sq_size - 1)) != 1)
&& (list_empty(&nesdev->cqp_pending_reqs))) {
cqp_head = nesdev->cqp.sq_head++;
nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
memcpy(cqp_wqe, &cqp_request->cqp_wqe, sizeof(*cqp_wqe));
opcode = le32_to_cpu(cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX]);
if ((opcode & NES_CQP_OPCODE_MASK) == NES_CQP_DOWNLOAD_SEGMENT)
ctx_index = NES_CQP_WQE_DL_COMP_CTX_LOW_IDX;
barrier();
u64temp = (unsigned long)cqp_request;
set_wqe_64bit_value(cqp_wqe->wqe_words, ctx_index, u64temp);
nes_debug(NES_DBG_CQP, "CQP request (opcode 0x%02X), line 1 = 0x%08X put on CQPs SQ,"
" request = %p, cqp_head = %u, cqp_tail = %u, cqp_size = %u,"
" waiting = %d, refcount = %d.\n",
opcode & NES_CQP_OPCODE_MASK,
le32_to_cpu(cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX]), cqp_request,
nesdev->cqp.sq_head, nesdev->cqp.sq_tail, nesdev->cqp.sq_size,
cqp_request->waiting, atomic_read(&cqp_request->refcount));
barrier();
/* Ring doorbell (1 WQEs) */
nes_write32(nesdev->regs+NES_WQE_ALLOC, 0x01800000 | nesdev->cqp.qp_id);
barrier();
} else {
nes_debug(NES_DBG_CQP, "CQP request %p (opcode 0x%02X), line 1 = 0x%08X"
" put on the pending queue.\n",
cqp_request,
le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_OPCODE_IDX])&0x3f,
le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_ID_IDX]));
list_add_tail(&cqp_request->list, &nesdev->cqp_pending_reqs);
}
spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
return;
}
/**
* nes_arp_table
*/
int nes_arp_table(struct nes_device *nesdev, u32 ip_addr, u8 *mac_addr, u32 action)
{
struct nes_adapter *nesadapter = nesdev->nesadapter;
int arp_index;
int err = 0;
__be32 tmp_addr;
for (arp_index = 0; (u32) arp_index < nesadapter->arp_table_size; arp_index++) {
if (nesadapter->arp_table[arp_index].ip_addr == ip_addr)
break;
}
if (action == NES_ARP_ADD) {
if (arp_index != nesadapter->arp_table_size) {
return -1;
}
arp_index = 0;
err = nes_alloc_resource(nesadapter, nesadapter->allocated_arps,
nesadapter->arp_table_size, (u32 *)&arp_index, &nesadapter->next_arp_index, NES_RESOURCE_ARP);
if (err) {
nes_debug(NES_DBG_NETDEV, "nes_alloc_resource returned error = %u\n", err);
return err;
}
nes_debug(NES_DBG_NETDEV, "ADD, arp_index=%d\n", arp_index);
nesadapter->arp_table[arp_index].ip_addr = ip_addr;
memcpy(nesadapter->arp_table[arp_index].mac_addr, mac_addr, ETH_ALEN);
return arp_index;
}
/* DELETE or RESOLVE */
if (arp_index == nesadapter->arp_table_size) {
tmp_addr = cpu_to_be32(ip_addr);
nes_debug(NES_DBG_NETDEV, "MAC for %pI4 not in ARP table - cannot %s\n",
&tmp_addr, action == NES_ARP_RESOLVE ? "resolve" : "delete");
return -1;
}
if (action == NES_ARP_RESOLVE) {
nes_debug(NES_DBG_NETDEV, "RESOLVE, arp_index=%d\n", arp_index);
return arp_index;
}
if (action == NES_ARP_DELETE) {
nes_debug(NES_DBG_NETDEV, "DELETE, arp_index=%d\n", arp_index);
nesadapter->arp_table[arp_index].ip_addr = 0;
eth_zero_addr(nesadapter->arp_table[arp_index].mac_addr);
nes_free_resource(nesadapter, nesadapter->allocated_arps, arp_index);
return arp_index;
}
return -1;
}
/**
* nes_mh_fix
*/
void nes_mh_fix(struct timer_list *t)
{
struct nes_adapter *nesadapter = from_timer(nesadapter, t, mh_timer);
struct nes_device *nesdev = nesadapter->nesdev;
unsigned long flags;
struct nes_vnic *nesvnic;
u32 used_chunks_tx;
u32 temp_used_chunks_tx;
u32 temp_last_used_chunks_tx;
u32 used_chunks_mask;
u32 mac_tx_frames_low;
u32 mac_tx_frames_high;
u32 mac_tx_pauses;
u32 reset_value;
u32 tx_control;
u32 tx_config;
u32 tx_pause_quanta;
u32 rx_control;
u32 rx_config;
u32 mac_exact_match;
u32 mpp_debug;
u32 i=0;
u32 chunks_tx_progress = 0;
spin_lock_irqsave(&nesadapter->phy_lock, flags);
if ((nesadapter->mac_sw_state[0] != NES_MAC_SW_IDLE) || (nesadapter->mac_link_down[0])) {
spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
goto no_mh_work;
}
nesadapter->mac_sw_state[0] = NES_MAC_SW_MH;
spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
do {
mac_tx_frames_low = nes_read_indexed(nesdev, NES_IDX_MAC_TX_FRAMES_LOW);
mac_tx_frames_high = nes_read_indexed(nesdev, NES_IDX_MAC_TX_FRAMES_HIGH);
mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
used_chunks_tx = nes_read_indexed(nesdev, NES_IDX_USED_CHUNKS_TX);
nesdev->mac_pause_frames_sent += mac_tx_pauses;
used_chunks_mask = 0;
temp_used_chunks_tx = used_chunks_tx;
temp_last_used_chunks_tx = nesdev->last_used_chunks_tx;
if (nesdev->netdev[0]) {
nesvnic = netdev_priv(nesdev->netdev[0]);
} else {
break;
}
for (i=0; i<4; i++) {
used_chunks_mask <<= 8;
if (nesvnic->qp_nic_index[i] != 0xff) {
used_chunks_mask |= 0xff;
if ((temp_used_chunks_tx&0xff)<(temp_last_used_chunks_tx&0xff)) {
chunks_tx_progress = 1;
}
}
temp_used_chunks_tx >>= 8;
temp_last_used_chunks_tx >>= 8;
}
if ((mac_tx_frames_low) || (mac_tx_frames_high) ||
(!(used_chunks_tx&used_chunks_mask)) ||
(!(nesdev->last_used_chunks_tx&used_chunks_mask)) ||
(chunks_tx_progress) ) {
nesdev->last_used_chunks_tx = used_chunks_tx;
break;
}
nesdev->last_used_chunks_tx = used_chunks_tx;
barrier();
nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, 0x00000005);
mh_pauses_sent++;
mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
if (mac_tx_pauses) {
nesdev->mac_pause_frames_sent += mac_tx_pauses;
break;
}
tx_control = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONTROL);
tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
tx_pause_quanta = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_QUANTA);
rx_control = nes_read_indexed(nesdev, NES_IDX_MAC_RX_CONTROL);
rx_config = nes_read_indexed(nesdev, NES_IDX_MAC_RX_CONFIG);
mac_exact_match = nes_read_indexed(nesdev, NES_IDX_MAC_EXACT_MATCH_BOTTOM);
mpp_debug = nes_read_indexed(nesdev, NES_IDX_MPP_DEBUG);
/* one last ditch effort to avoid a false positive */
mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
if (mac_tx_pauses) {
nesdev->last_mac_tx_pauses = nesdev->mac_pause_frames_sent;
nes_debug(NES_DBG_HW, "failsafe caught slow outbound pause\n");
break;
}
mh_detected++;
nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, 0x00000000);
nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, 0x00000000);
reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
nes_write32(nesdev->regs+NES_SOFTWARE_RESET, reset_value | 0x0000001d);
while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET)
& 0x00000040) != 0x00000040) && (i++ < 5000)) {
/* mdelay(1); */
}
nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, 0x00000008);
nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0);
nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x000bdef7);
nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_DRIVE0, 0x9ce73000);
nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_MODE0, 0x0ff00000);
nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_SIGDET0, 0x00000000);
nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_BYPASS0, 0x00000000);
nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_LOOPBACK_CONTROL0, 0x00000000);
if (nesadapter->OneG_Mode) {
nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0182222);
} else {
nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0042222);
}
nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_STATUS0);
nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000ff);
nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, tx_control);
nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
nes_write_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_QUANTA, tx_pause_quanta);
nes_write_indexed(nesdev, NES_IDX_MAC_RX_CONTROL, rx_control);
nes_write_indexed(nesdev, NES_IDX_MAC_RX_CONFIG, rx_config);
nes_write_indexed(nesdev, NES_IDX_MAC_EXACT_MATCH_BOTTOM, mac_exact_match);
nes_write_indexed(nesdev, NES_IDX_MPP_DEBUG, mpp_debug);
} while (0);
nesadapter->mac_sw_state[0] = NES_MAC_SW_IDLE;
no_mh_work:
nesdev->nesadapter->mh_timer.expires = jiffies + (HZ/5);
add_timer(&nesdev->nesadapter->mh_timer);
}
/**
* nes_clc
*/
void nes_clc(struct timer_list *t)
{
struct nes_adapter *nesadapter = from_timer(nesadapter, t, lc_timer);
unsigned long flags;
spin_lock_irqsave(&nesadapter->phy_lock, flags);
nesadapter->link_interrupt_count[0] = 0;
nesadapter->link_interrupt_count[1] = 0;
nesadapter->link_interrupt_count[2] = 0;
nesadapter->link_interrupt_count[3] = 0;
spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
nesadapter->lc_timer.expires = jiffies + 3600 * HZ; /* 1 hour */
add_timer(&nesadapter->lc_timer);
}
/**
* nes_dump_mem
*/
void nes_dump_mem(unsigned int dump_debug_level, void *addr, int length)
{
if (!(nes_debug_level & dump_debug_level)) {
return;
}
if (length > 0x100) {
nes_debug(dump_debug_level, "Length truncated from %x to %x\n", length, 0x100);
length = 0x100;
}
nes_debug(dump_debug_level, "Address=0x%p, length=0x%x (%d)\n", addr, length, length);
print_hex_dump(KERN_ERR, PFX, DUMP_PREFIX_NONE, 16, 1, addr, length, true);
}
drivers/infiniband/hw/nes/nes_verbs.c deleted 100644 → 0
View file @ cbdc666f
This source diff could not be displayed because it is too large. You can view the blob instead.
drivers/infiniband/hw/nes/nes_verbs.h deleted 100644 → 0
View file @ cbdc666f
/*
* Copyright (c) 2006 - 2011 Intel Corporation. All rights reserved.
* Copyright (c) 2005 Open Grid Computing, Inc. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
*/
#ifndef NES_VERBS_H
#define NES_VERBS_H
struct nes_device;
#define NES_MAX_USER_DB_REGIONS 4096
#define NES_MAX_USER_WQ_REGIONS 4096
#define NES_TERM_SENT 0x01
#define NES_TERM_RCVD 0x02
#define NES_TERM_DONE 0x04
struct nes_ucontext {
struct ib_ucontext ibucontext;
struct nes_device *nesdev;
unsigned long mmap_wq_offset;
unsigned long mmap_cq_offset; /* to be removed */
int index; /* rnic index (minor) */
unsigned long allocated_doorbells[BITS_TO_LONGS(NES_MAX_USER_DB_REGIONS)];
u16 mmap_db_index[NES_MAX_USER_DB_REGIONS];
u16 first_free_db;
unsigned long allocated_wqs[BITS_TO_LONGS(NES_MAX_USER_WQ_REGIONS)];
struct nes_qp *mmap_nesqp[NES_MAX_USER_WQ_REGIONS];
u16 first_free_wq;
struct list_head cq_reg_mem_list;
struct list_head qp_reg_mem_list;
u32 mcrqf;
};
struct nes_pd {
struct ib_pd ibpd;
u16 pd_id;
atomic_t sqp_count;
u16 mmap_db_index;
};
struct nes_mr {
union {
struct ib_mr ibmr;
struct ib_mw ibmw;
struct ib_fmr ibfmr;
};
struct ib_umem *region;
u16 pbls_used;
u8 mode;
u8 pbl_4k;
__le64 *pages;
dma_addr_t paddr;
u32 max_pages;
u32 npages;
};
struct nes_hw_pb {
__le32 pa_low;
__le32 pa_high;
};
struct nes_vpbl {
dma_addr_t pbl_pbase;
struct nes_hw_pb *pbl_vbase;
};
struct nes_root_vpbl {
dma_addr_t pbl_pbase;
struct nes_hw_pb *pbl_vbase;
struct nes_vpbl *leaf_vpbl;
};
struct nes_fmr {
struct nes_mr nesmr;
u32 leaf_pbl_cnt;
struct nes_root_vpbl root_vpbl;
struct ib_qp *ib_qp;
int access_rights;
struct ib_fmr_attr attr;
};
struct nes_av;
struct nes_cq {
struct ib_cq ibcq;
struct nes_hw_cq hw_cq;
u32 polled_completions;
u32 cq_mem_size;
spinlock_t lock;
u8 virtual_cq;
u8 pad[3];
u32 mcrqf;
};
struct nes_wq {
spinlock_t lock;
};
struct disconn_work {
struct work_struct work;
struct nes_qp *nesqp;
};
struct iw_cm_id;
struct ietf_mpa_frame;
struct nes_qp {
struct ib_qp ibqp;
void *allocated_buffer;
struct iw_cm_id *cm_id;
struct nes_cq *nesscq;
struct nes_cq *nesrcq;
struct nes_pd *nespd;
void *cm_node; /* handle of the node this QP is associated with */
void *ietf_frame;
u8 ietf_frame_size;
dma_addr_t ietf_frame_pbase;
struct ib_mr *lsmm_mr;
struct nes_hw_qp hwqp;
struct work_struct work;
enum ib_qp_state ibqp_state;
u32 iwarp_state;
u32 hte_index;
u32 last_aeq;
u32 qp_mem_size;
atomic_t refcount;
atomic_t close_timer_started;
u32 mmap_sq_db_index;
u32 mmap_rq_db_index;
spinlock_t lock;
spinlock_t pau_lock;
struct nes_qp_context *nesqp_context;
dma_addr_t nesqp_context_pbase;
void *pbl_vbase;
dma_addr_t pbl_pbase;
struct page *page;
struct timer_list terminate_timer;
enum ib_event_type terminate_eventtype;
struct sk_buff_head pau_list;
u32 pau_rcv_nxt;
u16 active_conn:1;
u16 skip_lsmm:1;
u16 user_mode:1;
u16 hte_added:1;
u16 flush_issued:1;
u16 destroyed:1;
u16 sig_all:1;
u16 pau_mode:1;
u16 rsvd:8;
u16 private_data_len;
u16 term_sq_flush_code;
u16 term_rq_flush_code;
u8 hw_iwarp_state;
u8 hw_tcp_state;
u8 term_flags;
u8 sq_kmapped;
u8 pau_busy;
u8 pau_pending;
u8 pau_state;
__u64 nesuqp_addr;
struct completion sq_drained;
struct completion rq_drained;
};
struct ib_mr *nes_reg_phys_mr(struct ib_pd *ib_pd,
u64 addr, u64 size, int acc, u64 *iova_start);
#endif /* NES_VERBS_H */
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7