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Commit 30eb7369 authored by Vasanthakumar Thiagarajan's avatar Vasanthakumar Thiagarajan Committed by Greg Kroah-Hartman
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ath6kl: Remove somemore unused header files from hw4.0/hw/ 

Signed-off-by: default avatarVasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 053db306
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drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/efuse_reg.h deleted 100644 → 0
View file @ 053db306
// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifndef _EFUSE_REG_REG_H_
#define _EFUSE_REG_REG_H_
#define EFUSE_WR_ENABLE_REG_ADDRESS 0x00000000
#define EFUSE_WR_ENABLE_REG_OFFSET 0x00000000
#define EFUSE_WR_ENABLE_REG_V_MSB 0
#define EFUSE_WR_ENABLE_REG_V_LSB 0
#define EFUSE_WR_ENABLE_REG_V_MASK 0x00000001
#define EFUSE_WR_ENABLE_REG_V_GET(x) (((x) & EFUSE_WR_ENABLE_REG_V_MASK) >> EFUSE_WR_ENABLE_REG_V_LSB)
#define EFUSE_WR_ENABLE_REG_V_SET(x) (((x) << EFUSE_WR_ENABLE_REG_V_LSB) & EFUSE_WR_ENABLE_REG_V_MASK)
#define EFUSE_INT_ENABLE_REG_ADDRESS 0x00000004
#define EFUSE_INT_ENABLE_REG_OFFSET 0x00000004
#define EFUSE_INT_ENABLE_REG_V_MSB 0
#define EFUSE_INT_ENABLE_REG_V_LSB 0
#define EFUSE_INT_ENABLE_REG_V_MASK 0x00000001
#define EFUSE_INT_ENABLE_REG_V_GET(x) (((x) & EFUSE_INT_ENABLE_REG_V_MASK) >> EFUSE_INT_ENABLE_REG_V_LSB)
#define EFUSE_INT_ENABLE_REG_V_SET(x) (((x) << EFUSE_INT_ENABLE_REG_V_LSB) & EFUSE_INT_ENABLE_REG_V_MASK)
#define EFUSE_INT_STATUS_REG_ADDRESS 0x00000008
#define EFUSE_INT_STATUS_REG_OFFSET 0x00000008
#define EFUSE_INT_STATUS_REG_V_MSB 0
#define EFUSE_INT_STATUS_REG_V_LSB 0
#define EFUSE_INT_STATUS_REG_V_MASK 0x00000001
#define EFUSE_INT_STATUS_REG_V_GET(x) (((x) & EFUSE_INT_STATUS_REG_V_MASK) >> EFUSE_INT_STATUS_REG_V_LSB)
#define EFUSE_INT_STATUS_REG_V_SET(x) (((x) << EFUSE_INT_STATUS_REG_V_LSB) & EFUSE_INT_STATUS_REG_V_MASK)
#define BITMASK_WR_REG_ADDRESS 0x0000000c
#define BITMASK_WR_REG_OFFSET 0x0000000c
#define BITMASK_WR_REG_V_MSB 31
#define BITMASK_WR_REG_V_LSB 0
#define BITMASK_WR_REG_V_MASK 0xffffffff
#define BITMASK_WR_REG_V_GET(x) (((x) & BITMASK_WR_REG_V_MASK) >> BITMASK_WR_REG_V_LSB)
#define BITMASK_WR_REG_V_SET(x) (((x) << BITMASK_WR_REG_V_LSB) & BITMASK_WR_REG_V_MASK)
#define VDDQ_SETTLE_TIME_REG_ADDRESS 0x00000010
#define VDDQ_SETTLE_TIME_REG_OFFSET 0x00000010
#define VDDQ_SETTLE_TIME_REG_V_MSB 31
#define VDDQ_SETTLE_TIME_REG_V_LSB 0
#define VDDQ_SETTLE_TIME_REG_V_MASK 0xffffffff
#define VDDQ_SETTLE_TIME_REG_V_GET(x) (((x) & VDDQ_SETTLE_TIME_REG_V_MASK) >> VDDQ_SETTLE_TIME_REG_V_LSB)
#define VDDQ_SETTLE_TIME_REG_V_SET(x) (((x) << VDDQ_SETTLE_TIME_REG_V_LSB) & VDDQ_SETTLE_TIME_REG_V_MASK)
#define RD_STROBE_PW_REG_ADDRESS 0x00000014
#define RD_STROBE_PW_REG_OFFSET 0x00000014
#define RD_STROBE_PW_REG_V_MSB 31
#define RD_STROBE_PW_REG_V_LSB 0
#define RD_STROBE_PW_REG_V_MASK 0xffffffff
#define RD_STROBE_PW_REG_V_GET(x) (((x) & RD_STROBE_PW_REG_V_MASK) >> RD_STROBE_PW_REG_V_LSB)
#define RD_STROBE_PW_REG_V_SET(x) (((x) << RD_STROBE_PW_REG_V_LSB) & RD_STROBE_PW_REG_V_MASK)
#define PG_STROBE_PW_REG_ADDRESS 0x00000018
#define PG_STROBE_PW_REG_OFFSET 0x00000018
#define PG_STROBE_PW_REG_V_MSB 31
#define PG_STROBE_PW_REG_V_LSB 0
#define PG_STROBE_PW_REG_V_MASK 0xffffffff
#define PG_STROBE_PW_REG_V_GET(x) (((x) & PG_STROBE_PW_REG_V_MASK) >> PG_STROBE_PW_REG_V_LSB)
#define PG_STROBE_PW_REG_V_SET(x) (((x) << PG_STROBE_PW_REG_V_LSB) & PG_STROBE_PW_REG_V_MASK)
#define EFUSE_INTF_ADDRESS 0x00000800
#define EFUSE_INTF_OFFSET 0x00000800
#define EFUSE_INTF_R_MSB 31
#define EFUSE_INTF_R_LSB 0
#define EFUSE_INTF_R_MASK 0xffffffff
#define EFUSE_INTF_R_GET(x) (((x) & EFUSE_INTF_R_MASK) >> EFUSE_INTF_R_LSB)
#define EFUSE_INTF_R_SET(x) (((x) << EFUSE_INTF_R_LSB) & EFUSE_INTF_R_MASK)
#ifndef __ASSEMBLER__
typedef struct efuse_reg_reg_s {
volatile unsigned int efuse_wr_enable_reg;
volatile unsigned int efuse_int_enable_reg;
volatile unsigned int efuse_int_status_reg;
volatile unsigned int bitmask_wr_reg;
volatile unsigned int vddq_settle_time_reg;
volatile unsigned int rd_strobe_pw_reg;
volatile unsigned int pg_strobe_pw_reg;
unsigned char pad0[2020]; /* pad to 0x800 */
volatile unsigned int efuse_intf[512];
} efuse_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _EFUSE_REG_H_ */
drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_dma_reg.h deleted 100644 → 0
View file @ 053db306
// ------------------------------------------------------------------
// Copyright (c) 2002-2010 Atheros Communications Inc.
// All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
/*****************************************************************************/
/* AR6003 WLAN MAC DMA register definitions */
/*****************************************************************************/
#ifndef _AR6000_DMAREG_H_
#define _AR6000_DMAREG_H_
/*
* Definitions for the Atheros AR6003 chipset.
*/
/* DMA Control and Interrupt Registers */
#define MAC_DMA_CR_ADDRESS 0x00000008 /* MAC control register */
#define MAC_DMA_CR_RXE_MASK 0x00000004 /* Receive enable */
#define MAC_DMA_CR_RXD_MASK 0x00000020 /* Receive disable */
#define MAC_DMA_CR_SWI_MASK 0x00000040 /* One-shot software interrupt */
#define MAC_DMA_RXDP_ADDRESS 0x0000000C /* MAC receive queue descriptor pointer */
#define MAC_DMA_CFG_ADDRESS 0x00000014 /* MAC configuration and status register */
#define MAC_DMA_CFG_SWTD_MASK 0x00000001 /* byteswap tx descriptor words */
#define MAC_DMA_CFG_SWTB_MASK 0x00000002 /* byteswap tx data buffer words */
#define MAC_DMA_CFG_SWRD_MASK 0x00000004 /* byteswap rx descriptor words */
#define MAC_DMA_CFG_SWRB_MASK 0x00000008 /* byteswap rx data buffer words */
#define MAC_DMA_CFG_SWRG_MASK 0x00000010 /* byteswap register access data words */
#define MAC_DMA_CFG_AP_ADHOC_INDICATION_MASK 0x00000020 /* AP/adhoc indication (0-AP, 1-Adhoc) */
#define MAC_DMA_CFG_PHOK_MASK 0x00000100 /* PHY OK status */
#define MAC_DMA_CFG_CLK_GATE_DIS_MASK 0x00000400 /* Clock gating disable */
#define MAC_DMA_MIRT_ADDRESS 0x00000020 /* Maximum rate threshold register */
#define MAC_DMA_MIRT_THRESH_MASK 0x0000FFFF
#define MAC_DMA_IER_ADDRESS 0x00000024 /* MAC Interrupt enable register */
#define MAC_DMA_IER_ENABLE_MASK 0x00000001 /* Global interrupt enable */
#define MAC_DMA_IER_DISABLE_MASK 0x00000000 /* Global interrupt disable */
#define MAC_DMA_TIMT_ADDRESS 0x00000028 /* Transmit Interrupt Mitigation Threshold */
#define MAC_DMA_TIMT_LAST_PACKER_THRESH_MASK 0x0000FFFF /* Last packet threshold mask */
#define MAC_DMA_TIMT_FIRST_PACKER_THRESH_MASK 0xFFFF0000 /* First packet threshold mask */
#define MAC_DMA_RIMT_ADDRESS 0x0000002C /* Receive Interrupt Mitigation Threshold */
#define MAC_DMA_RIMT_LAST_PACKER_THRESH_MASK 0x0000FFFF /* Last packet threshold mask */
#define MAC_DMA_RIMT_FIRST_PACKER_THRESH_MASK 0xFFFF0000 /* First packet threshold mask */
#define MAC_DMA_TXCFG_ADDRESS 0x00000030 /* MAC tx DMA size config register */
#define MAC_DMA_FTRIG_MASK 0x000003F0 /* Mask for Frame trigger level */
#define MAC_DMA_FTRIG_LSB 4 /* Shift for Frame trigger level */
#define MAC_DMA_FTRIG_IMMED 0x00000000 /* bytes in PCU TX FIFO before air */
#define MAC_DMA_FTRIG_64B 0x00000010 /* default */
#define MAC_DMA_FTRIG_128B 0x00000020
#define MAC_DMA_FTRIG_192B 0x00000030
#define MAC_DMA_FTRIG_256B 0x00000040 /* 5 bits total */
#define MAC_DMA_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY_MASK 0x00000800
#define MAC_DMA_RXCFG_ADDRESS 0x00000034 /* MAC rx DMA size config register */
#define MAC_DMA_RXCFG_ZLFDMA_MASK 0x00000010 /* Enable DMA of zero-length frame */
#define MAC_DMA_RXCFG_DMASIZE_4B 0x00000000 /* DMA size 4 bytes (TXCFG + RXCFG) */
#define MAC_DMA_RXCFG_DMASIZE_8B 0x00000001 /* DMA size 8 bytes */
#define MAC_DMA_RXCFG_DMASIZE_16B 0x00000002 /* DMA size 16 bytes */
#define MAC_DMA_RXCFG_DMASIZE_32B 0x00000003 /* DMA size 32 bytes */
#define MAC_DMA_RXCFG_DMASIZE_64B 0x00000004 /* DMA size 64 bytes */
#define MAC_DMA_RXCFG_DMASIZE_128B 0x00000005 /* DMA size 128 bytes */
#define MAC_DMA_RXCFG_DMASIZE_256B 0x00000006 /* DMA size 256 bytes */
#define MAC_DMA_RXCFG_DMASIZE_512B 0x00000007 /* DMA size 512 bytes */
#define MAC_DMA_MIBC_ADDRESS 0x00000040 /* MAC MIB control register */
#define MAC_DMA_MIBC_COW_MASK 0x00000001 /* counter overflow warning */
#define MAC_DMA_MIBC_FMC_MASK 0x00000002 /* freeze MIB counters */
#define MAC_DMA_MIBC_CMC_MASK 0x00000004 /* clear MIB counters */
#define MAC_DMA_MIBC_MCS_MASK 0x00000008 /* MIB counter strobe, increment all */
#define MAC_DMA_TOPS_ADDRESS 0x00000044 /* MAC timeout prescale count */
#define MAC_DMA_TOPS_MASK 0x0000FFFF /* Mask for timeout prescale */
#define MAC_DMA_RXNPTO_ADDRESS 0x00000048 /* MAC no frame received timeout */
#define MAC_DMA_RXNPTO_MASK 0x000003FF /* Mask for no frame received timeout */
#define MAC_DMA_TXNPTO_ADDRESS 0x0000004C /* MAC no frame trasmitted timeout */
#define MAC_DMA_TXNPTO_MASK 0x000003FF /* Mask for no frame transmitted timeout */
#define MAC_DMA_TXNPTO_QCU_MASK 0x000FFC00 /* Mask indicating the set of QCUs */
/* for which frame completions will cause */
/* a reset of the no frame xmit'd timeout */
#define MAC_DMA_RPGTO_ADDRESS 0x00000050 /* MAC receive frame gap timeout */
#define MAC_DMA_RPGTO_MASK 0x000003FF /* Mask for receive frame gap timeout */
#define MAC_DMA_RPCNT_ADDRESS 0x00000054 /* MAC receive frame count limit */
#define MAC_DMA_RPCNT_MASK 0x0000001F /* Mask for receive frame count limit */
#define MAC_DMA_MACMISC_ADDRESS 0x00000058 /* MAC miscellaneous control/status register */
#define MAC_DMA_MACMISC_DMA_OBS_MASK 0x000001E0 /* Mask for DMA observation bus mux select */
#define MAC_DMA_MACMISC_DMA_OBS_LSB 5 /* Shift for DMA observation bus mux select */
#define MAC_DMA_MACMISC_MISC_OBS 0x00000E00 /* Mask for MISC observation bus mux select */
#define MAC_DMA_MACMISC_MISC_OBS_LSB 9 /* Shift for MISC observation bus mux select */
#define MAC_DMA_MACMISC_MAC_OBS_BUS_LSB 0x00007000 /* Mask for MAC observation bus mux select (lsb) */
#define MAC_DMA_MACMISC_MAC_OBS_BUS_LSB_LSB 12 /* Shift for MAC observation bus mux select (lsb) */
#define MAC_DMA_MACMISC_MAC_OBS_BUS_MSB 0x00038000 /* Mask for MAC observation bus mux select (msb) */
#define MAC_DMA_MACMISC_MAC_OBS_BUS_MSB_LSB 15 /* Shift for MAC observation bus mux select (msb) */
#define MAC_DMA_ISR_ADDRESS 0x00000080 /* MAC Primary interrupt status register */
/*
* Interrupt Status Registers
*
* Only the bits in the ISR_P register and the IMR_P registers
* control whether the MAC's INTA# output is asserted. The bits in
* the secondary interrupt status/mask registers control what bits
* are set in the primary interrupt status register; however the
* IMR_S* registers DO NOT determine whether INTA# is asserted.
* That is INTA# is asserted only when the logical AND of ISR_P
* and IMR_P is non-zero. The secondary interrupt mask/status
* registers affect what bits are set in ISR_P but they do not
* directly affect whether INTA# is asserted.
*/
#define MAC_DMA_ISR_RXOK_MASK 0x00000001 /* At least one frame received sans errors */
#define MAC_DMA_ISR_RXDESC_MASK 0x00000002 /* Receive interrupt request */
#define MAC_DMA_ISR_RXERR_MASK 0x00000004 /* Receive error interrupt */
#define MAC_DMA_ISR_RXNOPKT_MASK 0x00000008 /* No frame received within timeout clock */
#define MAC_DMA_ISR_RXEOL_MASK 0x00000010 /* Received descriptor empty interrupt */
#define MAC_DMA_ISR_RXORN_MASK 0x00000020 /* Receive FIFO overrun interrupt */
#define MAC_DMA_ISR_TXOK_MASK 0x00000040 /* Transmit okay interrupt */
#define MAC_DMA_ISR_TXDESC_MASK 0x00000080 /* Transmit interrupt request */
#define MAC_DMA_ISR_TXERR_MASK 0x00000100 /* Transmit error interrupt */
#define MAC_DMA_ISR_TXNOPKT_MASK 0x00000200 /* No frame transmitted interrupt */
#define MAC_DMA_ISR_TXEOL_MASK 0x00000400 /* Transmit descriptor empty interrupt */
#define MAC_DMA_ISR_TXURN_MASK 0x00000800 /* Transmit FIFO underrun interrupt */
#define MAC_DMA_ISR_MIB_MASK 0x00001000 /* MIB interrupt - see MIBC */
#define MAC_DMA_ISR_SWI_MASK 0x00002000 /* Software interrupt */
#define MAC_DMA_ISR_RXPHY_MASK 0x00004000 /* PHY receive error interrupt */
#define MAC_DMA_ISR_RXKCM_MASK 0x00008000 /* Key-cache miss interrupt */
#define MAC_DMA_ISR_BRSSI_HI_MASK 0x00010000 /* Beacon rssi high threshold interrupt */
#define MAC_DMA_ISR_BRSSI_LO_MASK 0x00020000 /* Beacon threshold interrupt */
#define MAC_DMA_ISR_BMISS_MASK 0x00040000 /* Beacon missed interrupt */
#define MAC_DMA_ISR_TXMINTR_MASK 0x00080000 /* Maximum transmit interrupt rate */
#define MAC_DMA_ISR_BNR_MASK 0x00100000 /* Beacon not ready interrupt */
#define MAC_DMA_ISR_HIUERR_MASK 0x00200000 /* An unexpected bus error has occurred */
#define MAC_DMA_ISR_BCNMISC_MASK 0x00800000 /* 'or' of TIM, CABEND, DTIMSYNC, BCNTO */
#define MAC_DMA_ISR_RXMINTR_MASK 0x01000000 /* Maximum receive interrupt rate */
#define MAC_DMA_ISR_QCBROVF_MASK 0x02000000 /* QCU CBR overflow interrupt */
#define MAC_DMA_ISR_QCBRURN_MASK 0x04000000 /* QCU CBR underrun interrupt */
#define MAC_DMA_ISR_QTRIG_MASK 0x08000000 /* QCU scheduling trigger interrupt */
#define MAC_DMA_ISR_TIMER_MASK 0x10000000 /* GENTMR interrupt */
#define MAC_DMA_ISR_HCFTO_MASK 0x20000000 /* HCFTO interrupt */
#define MAC_DMA_ISR_TXINTM_MASK 0x40000000 /* Transmit completion mitigation interrupt */
#define MAC_DMA_ISR_RXINTM_MASK 0x80000000 /* Receive completion mitigation interrupt */
#define MAC_DMA_ISR_S0_ADDRESS 0x00000084 /* MAC Secondary interrupt status register 0 */
#define MAC_DMA_ISR_S0_QCU_TXOK_MASK 0x000003FF /* Mask for TXOK (QCU 0-9) */
#define MAC_DMA_ISR_S0_QCU_TXOK_LSB 0
#define MAC_DMA_ISR_S0_QCU_TXDESC_MASK 0x03FF0000 /* Mask for TXDESC (QCU 0-9) */
#define MAC_DMA_ISR_S0_QCU_TXDESC_LSB 16
#define MAC_DMA_ISR_S1_ADDRESS 0x00000088 /* MAC Secondary interrupt status register 1 */
#define MAC_DMA_ISR_S1_QCU_TXERR_MASK 0x000003FF /* Mask for TXERR (QCU 0-9) */
#define MAC_DMA_ISR_S1_QCU_TXERR_LSB 0
#define MAC_DMA_ISR_S1_QCU_TXEOL_MASK 0x03FF0000 /* Mask for TXEOL (QCU 0-9) */
#define MAC_DMA_ISR_S1_QCU_TXEOL_LSB 16
#define MAC_DMA_ISR_S2_ADDRESS 0x0000008c /* MAC Secondary interrupt status register 2 */
#define MAC_DMA_ISR_S2_QCU_TXURN_MASK 0x000003FF /* Mask for TXURN (QCU 0-9) */
#define MAC_DMA_ISR_S2_QCU_TXURN_LSB 0 /* Shift for TXURN (QCU 0-9) */
#define MAC_DMA_ISR_S2_RX_INT_MASK 0x00000800
#define MAC_DMA_ISR_S2_WL_STOMPED_MASK 0x00001000
#define MAC_DMA_ISR_S2_RX_PTR_BAD_MASK 0x00002000
#define MAC_DMA_ISR_S2_BT_LOW_PRIORITY_RISING_MASK 0x00004000
#define MAC_DMA_ISR_S2_BT_LOW_PRIORITY_FALLING_MASK 0x00008000
#define MAC_DMA_ISR_S2_BB_PANIC_IRQ_MASK 0x00010000
#define MAC_DMA_ISR_S2_BT_STOMPED_MASK 0x00020000
#define MAC_DMA_ISR_S2_BT_ACTIVE_RISING_MASK 0x00040000
#define MAC_DMA_ISR_S2_BT_ACTIVE_FALLING_MASK 0x00080000
#define MAC_DMA_ISR_S2_BT_PRIORITY_RISING_MASK 0x00100000
#define MAC_DMA_ISR_S2_BT_PRIORITY_FALLING_MASK 0x00200000
#define MAC_DMA_ISR_S2_CST_MASK 0x00400000
#define MAC_DMA_ISR_S2_GTT_MASK 0x00800000
#define MAC_DMA_ISR_S2_TIM_MASK 0x01000000 /* TIM */
#define MAC_DMA_ISR_S2_CABEND_MASK 0x02000000 /* CABEND */
#define MAC_DMA_ISR_S2_DTIMSYNC_MASK 0x04000000 /* DTIMSYNC */
#define MAC_DMA_ISR_S2_BCNTO_MASK 0x08000000 /* BCNTO */
#define MAC_DMA_ISR_S2_CABTO_MASK 0x10000000 /* CABTO */
#define MAC_DMA_ISR_S2_DTIM_MASK 0x20000000 /* DTIM */
#define MAC_DMA_ISR_S2_TSFOOR_MASK 0x40000000 /* TSFOOR */
#define MAC_DMA_ISR_S3_ADDRESS 0x00000090 /* MAC Secondary interrupt status register 3 */
#define MAC_DMA_ISR_S3_QCU_QCBROVF_MASK 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
#define MAC_DMA_ISR_S3_QCU_QCBRURN_MASK 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
#define MAC_DMA_ISR_S4_ADDRESS 0x00000094 /* MAC Secondary interrupt status register 4 */
#define MAC_DMA_ISR_S4_QCU_QTRIG_MASK 0x000003FF /* Mask for QTRIG (QCU 0-9) */
#define MAC_DMA_ISR_S5_ADDRESS 0x00000098 /* MAC Secondary interrupt status register 5 */
#define MAC_DMA_ISR_S5_TBTT_TIMER_TRIGGER_MASK 0x00000001
#define MAC_DMA_ISR_S5_DBA_TIMER_TRIGGER_MASK 0x00000002
#define MAC_DMA_ISR_S5_SBA_TIMER_TRIGGER_MASK 0x00000004
#define MAC_DMA_ISR_S5_HCF_TIMER_TRIGGER_MASK 0x00000008
#define MAC_DMA_ISR_S5_TIM_TIMER_TRIGGER_MASK 0x00000010
#define MAC_DMA_ISR_S5_DTIM_TIMER_TRIGGER_MASK 0x00000020
#define MAC_DMA_ISR_S5_QUIET_TIMER_TRIGGER_MASK 0x00000040
#define MAC_DMA_ISR_S5_NDP_TIMER_TRIGGER_MASK 0x00000080
#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER_MASK 0x0000FF00
#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER_LSB 8
#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER(_i) (0x00000100 << (_i))
#define MAC_DMA_ISR_S5_TIMER_OVERFLOW_MASK 0x00010000
#define MAC_DMA_ISR_S5_DBA_TIMER_THRESHOLD_MASK 0x00020000
#define MAC_DMA_ISR_S5_SBA_TIMER_THRESHOLD_MASK 0x00040000
#define MAC_DMA_ISR_S5_HCF_TIMER_THRESHOLD_MASK 0x00080000
#define MAC_DMA_ISR_S5_TIM_TIMER_THRESHOLD_MASK 0x00100000
#define MAC_DMA_ISR_S5_DTIM_TIMER_THRESHOLD_MASK 0x00200000
#define MAC_DMA_ISR_S5_QUIET_TIMER_THRESHOLD_MASK 0x00400000
#define MAC_DMA_ISR_S5_NDP_TIMER_THRESHOLD_MASK 0x00800000
#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_MASK 0xFF000000
#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_LSB 24
#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD(_i) (0x01000000 << (_i))
#define MAC_DMA_IMR_ADDRESS 0x000000A0 /* MAC Primary interrupt mask register */
/*
* Interrupt Mask Registers
*
* Only the bits in the IMR control whether the MAC's INTA#
* output will be asserted. The bits in the secondary interrupt
* mask registers control what bits get set in the primary
* interrupt status register; however the IMR_S* registers
* DO NOT determine whether INTA# is asserted.
*/
#define MAC_DMA_IMR_RXOK_MASK 0x00000001 /* At least one frame received sans errors */
#define MAC_DMA_IMR_RXDESC_MASK 0x00000002 /* Receive interrupt request */
#define MAC_DMA_IMR_RXERR_MASK 0x00000004 /* Receive error interrupt */
#define MAC_DMA_IMR_RXNOPKT_MASK 0x00000008 /* No frame received within timeout clock */
#define MAC_DMA_IMR_RXEOL_MASK 0x00000010 /* Received descriptor empty interrupt */
#define MAC_DMA_IMR_RXORN_MASK 0x00000020 /* Receive FIFO overrun interrupt */
#define MAC_DMA_IMR_TXOK_MASK 0x00000040 /* Transmit okay interrupt */
#define MAC_DMA_IMR_TXDESC_MASK 0x00000080 /* Transmit interrupt request */
#define MAC_DMA_IMR_TXERR_MASK 0x00000100 /* Transmit error interrupt */
#define MAC_DMA_IMR_TXNOPKT_MASK 0x00000200 /* No frame transmitted interrupt */
#define MAC_DMA_IMR_TXEOL_MASK 0x00000400 /* Transmit descriptor empty interrupt */
#define MAC_DMA_IMR_TXURN_MASK 0x00000800 /* Transmit FIFO underrun interrupt */
#define MAC_DMA_IMR_MIB_MASK 0x00001000 /* MIB interrupt - see MIBC */
#define MAC_DMA_IMR_SWI_MASK 0x00002000 /* Software interrupt */
#define MAC_DMA_IMR_RXPHY_MASK 0x00004000 /* PHY receive error interrupt */
#define MAC_DMA_IMR_RXKCM_MASK 0x00008000 /* Key-cache miss interrupt */
#define MAC_DMA_IMR_BRSSI_HI_MASK 0x00010000 /* Beacon rssi hi threshold interrupt */
#define MAC_DMA_IMR_BRSSI_LO_MASK 0x00020000 /* Beacon rssi lo threshold interrupt */
#define MAC_DMA_IMR_BMISS_MASK 0x00040000 /* Beacon missed interrupt */
#define MAC_DMA_IMR_TXMINTR_MASK 0x00080000 /* Maximum transmit interrupt rate */
#define MAC_DMA_IMR_BNR_MASK 0x00100000 /* BNR interrupt */
#define MAC_DMA_IMR_HIUERR_MASK 0x00200000 /* An unexpected bus error has occurred */
#define MAC_DMA_IMR_BCNMISC_MASK 0x00800000 /* Beacon Misc */
#define MAC_DMA_IMR_RXMINTR_MASK 0x01000000 /* Maximum receive interrupt rate */
#define MAC_DMA_IMR_QCBROVF_MASK 0x02000000 /* QCU CBR overflow interrupt */
#define MAC_DMA_IMR_QCBRURN_MASK 0x04000000 /* QCU CBR underrun interrupt */
#define MAC_DMA_IMR_QTRIG_MASK 0x08000000 /* QCU scheduling trigger interrupt */
#define MAC_DMA_IMR_TIMER_MASK 0x10000000 /* GENTMR interrupt */
#define MAC_DMA_IMR_HCFTO_MASK 0x20000000 /* HCFTO interrupt*/
#define MAC_DMA_IMR_TXINTM_MASK 0x40000000 /* Transmit completion mitigation interrupt */
#define MAC_DMA_IMR_RXINTM_MASK 0x80000000 /* Receive completion mitigation interrupt */
#define MAC_DMA_IMR_S0_ADDRESS 0x000000A4 /* MAC Secondary interrupt mask register 0 */
#define MAC_DMA_IMR_S0_QCU_TXOK_MASK 0x000003FF /* TXOK (QCU 0-9) */
#define MAC_DMA_IMR_S0_QCU_TXOK_LSB 0
#define MAC_DMA_IMR_S0_QCU_TXDESC_MASK 0x03FF0000 /* TXDESC (QCU 0-9) */
#define MAC_DMA_IMR_S0_QCU_TXDESC_LSB 16
#define MAC_DMA_IMR_S1_ADDRESS 0x000000A8 /* MAC Secondary interrupt mask register 1 */
#define MAC_DMA_IMR_S1_QCU_TXERR_MASK 0x000003FF /* TXERR (QCU 0-9) */
#define MAC_DMA_IMR_S1_QCU_TXERR_LSB 0
#define MAC_DMA_IMR_S1_QCU_TXEOL_MASK 0x03FF0000 /* TXEOL (QCU 0-9) */
#define MAC_DMA_IMR_S1_QCU_TXEOL_LSB 16
#define MAC_DMA_IMR_S2_ADDRESS 0x000000AC /* MAC Secondary interrupt mask register 2 */
#define MAC_DMA_IMR_S2_QCU_TXURN_MASK 0x000003FF /* Mask for TXURN (QCU 0-9) */
#define MAC_DMA_IMR_S2_QCU_TXURN_LSB 0
#define MAC_DMA_IMR_S2_RX_INT_MASK 0x00000800
#define MAC_DMA_IMR_S2_WL_STOMPED_MASK 0x00001000
#define MAC_DMA_IMR_S2_RX_PTR_BAD_MASK 0x00002000
#define MAC_DMA_IMR_S2_BT_LOW_PRIORITY_RISING_MASK 0x00004000
#define MAC_DMA_IMR_S2_BT_LOW_PRIORITY_FALLING_MASK 0x00008000
#define MAC_DMA_IMR_S2_BB_PANIC_IRQ_MASK 0x00010000
#define MAC_DMA_IMR_S2_BT_STOMPED_MASK 0x00020000
#define MAC_DMA_IMR_S2_BT_ACTIVE_RISING_MASK 0x00040000
#define MAC_DMA_IMR_S2_BT_ACTIVE_FALLING_MASK 0x00080000
#define MAC_DMA_IMR_S2_BT_PRIORITY_RISING_MASK 0x00100000
#define MAC_DMA_IMR_S2_BT_PRIORITY_FALLING_MASK 0x00200000
#define MAC_DMA_IMR_S2_CST_MASK 0x00400000
#define MAC_DMA_IMR_S2_GTT_MASK 0x00800000
#define MAC_DMA_IMR_S2_TIM_MASK 0x01000000 /* TIM */
#define MAC_DMA_IMR_S2_CABEND_MASK 0x02000000 /* CABEND */
#define MAC_DMA_IMR_S2_DTIMSYNC_MASK 0x04000000 /* DTIMSYNC */
#define MAC_DMA_IMR_S2_BCNTO_MASK 0x08000000 /* BCNTO */
#define MAC_DMA_IMR_S2_CABTO_MASK 0x10000000 /* CABTO */
#define MAC_DMA_IMR_S2_DTIM_MASK 0x20000000 /* DTIM */
#define MAC_DMA_IMR_S2_TSFOOR_MASK 0x40000000 /* TSFOOR */
#define MAC_DMA_IMR_S3_ADDRESS 0x000000B0 /* MAC Secondary interrupt mask register 3 */
#define MAC_DMA_IMR_S3_QCU_QCBROVF_MASK 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
#define MAC_DMA_IMR_S3_QCU_QCBRURN_MASK 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
#define MAC_DMA_IMR_S3_QCU_QCBRURN_LSB 16
#define MAC_DMA_IMR_S4_ADDRESS 0x000000B4 /* MAC Secondary interrupt mask register 4 */
#define MAC_DMA_IMR_S4_QCU_QTRIG_MASK 0x000003FF /* Mask for QTRIG (QCU 0-9) */
#define MAC_DMA_IMR_S5_ADDRESS 0x000000B8 /* MAC Secondary interrupt mask register 5 */
#define MAC_DMA_IMR_S5_TBTT_TIMER_TRIGGER_MASK 0x00000001
#define MAC_DMA_IMR_S5_DBA_TIMER_TRIGGER_MASK 0x00000002
#define MAC_DMA_IMR_S5_SBA_TIMER_TRIGGER_MASK 0x00000004
#define MAC_DMA_IMR_S5_HCF_TIMER_TRIGGER_MASK 0x00000008
#define MAC_DMA_IMR_S5_TIM_TIMER_TRIGGER_MASK 0x00000010
#define MAC_DMA_IMR_S5_DTIM_TIMER_TRIGGER_MASK 0x00000020
#define MAC_DMA_IMR_S5_QUIET_TIMER_TRIGGER_MASK 0x00000040
#define MAC_DMA_IMR_S5_NDP_TIMER_TRIGGER_MASK 0x00000080
#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER_MASK 0x0000FF00
#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER_LSB 8
#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER(_i) (0x100 << (_i))
#define MAC_DMA_IMR_S5_TIMER_OVERFLOW_MASK 0x00010000
#define MAC_DMA_IMR_S5_DBA_TIMER_THRESHOLD_MASK 0x00020000
#define MAC_DMA_IMR_S5_SBA_TIMER_THRESHOLD_MASK 0x00040000
#define MAC_DMA_IMR_S5_HCF_TIMER_THRESHOLD_MASK 0x00080000
#define MAC_DMA_IMR_S5_TIM_TIMER_THRESHOLD_MASK 0x00100000
#define MAC_DMA_IMR_S5_DTIM_TIMER_THRESHOLD_MASK 0x00200000
#define MAC_DMA_IMR_S5_QUIET_TIMER_THRESHOLD_MASK 0000400000
#define MAC_DMA_IMR_S5_NDP_TIMER_THRESHOLD_MASK 0x00800000
#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_MASK 0xFF000000
#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_LSB 24
#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD(_i) (0x01000000 << (_i))
#define MAC_DMA_ISR_RAC_ADDRESS 0x000000C0 /* ISR read-and-clear access */
/* Shadow copies with read-and-clear access */
#define MAC_DMA_ISR_S0_S_ADDRESS 0x000000C4 /* ISR_S0 shadow copy */
#define MAC_DMA_ISR_S1_S_ADDRESS 0x000000C8 /* ISR_S1 shadow copy */
#define MAC_DMA_ISR_S2_S_ADDRESS 0x000000Cc /* ISR_S2 shadow copy */
#define MAC_DMA_ISR_S3_S_ADDRESS 0x000000D0 /* ISR_S3 shadow copy */
#define MAC_DMA_ISR_S4_S_ADDRESS 0x000000D4 /* ISR_S4 shadow copy */
#define MAC_DMA_ISR_S5_S_ADDRESS 0x000000D8 /* ISR_S5 shadow copy */
#define MAC_DMA_Q0_TXDP_ADDRESS 0x00000800 /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_Q1_TXDP_ADDRESS 0x00000804 /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_Q2_TXDP_ADDRESS 0x00000808 /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_Q3_TXDP_ADDRESS 0x0000080C /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_Q4_TXDP_ADDRESS 0x00000810 /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_Q5_TXDP_ADDRESS 0x00000814 /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_Q6_TXDP_ADDRESS 0x00000818 /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_Q7_TXDP_ADDRESS 0x0000081C /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_Q8_TXDP_ADDRESS 0x00000820 /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_Q9_TXDP_ADDRESS 0x00000824 /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_QTXDP_ADDRESS(_i) (MAC_DMA_Q0_TXDP_ADDRESS + ((_i)<<2))
#define MAC_DMA_Q_TXE_ADDRESS 0x00000840 /* MAC Transmit Queue enable */
#define MAC_DMA_Q_TXD_ADDRESS 0x00000880 /* MAC Transmit Queue disable */
/* QCU registers */
#define MAC_DMA_Q0_CBRCFG_ADDRESS 0x000008C0 /* MAC CBR configuration */
#define MAC_DMA_Q1_CBRCFG_ADDRESS 0x000008C4 /* MAC CBR configuration */
#define MAC_DMA_Q2_CBRCFG_ADDRESS 0x000008C8 /* MAC CBR configuration */
#define MAC_DMA_Q3_CBRCFG_ADDRESS 0x000008CC /* MAC CBR configuration */
#define MAC_DMA_Q4_CBRCFG_ADDRESS 0x000008D0 /* MAC CBR configuration */
#define MAC_DMA_Q5_CBRCFG_ADDRESS 0x000008D4 /* MAC CBR configuration */
#define MAC_DMA_Q6_CBRCFG_ADDRESS 0x000008D8 /* MAC CBR configuration */
#define MAC_DMA_Q7_CBRCFG_ADDRESS 0x000008DC /* MAC CBR configuration */
#define MAC_DMA_Q8_CBRCFG_ADDRESS 0x000008E0 /* MAC CBR configuration */
#define MAC_DMA_Q9_CBRCFG_ADDRESS 0x000008E4 /* MAC CBR configuration */
#define MAC_DMA_QCBRCFG_ADDRESS(_i) (MAC_DMA_Q0_CBRCFG_ADDRESS + ((_i)<<2))
#define MAC_DMA_Q_CBRCFG_CBR_INTERVAL_MASK 0x00FFFFFF /* Mask for CBR interval (us) */
#define MAC_DMA_Q_CBRCFG_CBR_INTERVAL_LSB 0 /* Shift for CBR interval */
#define MAC_DMA_Q_CBRCFG_CBR_OVF_THRESH_MASK 0xFF000000 /* Mask for CBR overflow threshold */
#define MAC_DMA_Q_CBRCFG_CBR_OVF_THRESH_LSB 24 /* Shift for CBR overflow thresh */
#define MAC_DMA_Q0_RDYTIMECFG_ADDRESS 0x00000900 /* MAC ReadyTime configuration */
#define MAC_DMA_Q1_RDYTIMECFG_ADDRESS 0x00000904 /* MAC ReadyTime configuration */
#define MAC_DMA_Q2_RDYTIMECFG_ADDRESS 0x00000908 /* MAC ReadyTime configuration */
#define MAC_DMA_Q3_RDYTIMECFG_ADDRESS 0x0000090C /* MAC ReadyTime configuration */
#define MAC_DMA_Q4_RDYTIMECFG_ADDRESS 0x00000910 /* MAC ReadyTime configuration */
#define MAC_DMA_Q5_RDYTIMECFG_ADDRESS 0x00000914 /* MAC ReadyTime configuration */
#define MAC_DMA_Q6_RDYTIMECFG_ADDRESS 0x00000918 /* MAC ReadyTime configuration */
#define MAC_DMA_Q7_RDYTIMECFG_ADDRESS 0x0000091C /* MAC ReadyTime configuration */
#define MAC_DMA_Q8_RDYTIMECFG_ADDRESS 0x00000920 /* MAC ReadyTime configuration */
#define MAC_DMA_Q9_RDYTIMECFG_ADDRESS 0x00000924 /* MAC ReadyTime configuration */
#define MAC_DMA_QRDYTIMECFG_ADDRESS(_i) (MAC_DMA_Q0_RDYTIMECFG_ADDRESS + ((_i)<<2))
#define MAC_DMA_Q_RDYTIMECFG_INT_MASK 0x00FFFFFF /* CBR interval (us) */
#define MAC_DMA_Q_RDYTIMECFG_INT_LSB 0 /* Shift for ReadyTime Interval (us) */
#define MAC_DMA_Q_RDYTIMECFG_ENA_MASK 0x01000000 /* CBR enable */
#define MAC_DMA_Q_ONESHOTMAC_DMAM_SC_ADDRESS 0x00000940 /* MAC OneShotArm set control */
#define MAC_DMA_Q_ONESHOTMAC_DMAM_CC_ADDRESS 0x00000980 /* MAC OneShotArm clear control */
#define MAC_DMA_Q0_MISC_ADDRESS 0x000009C0 /* MAC Miscellaneous QCU settings */
#define MAC_DMA_Q1_MISC_ADDRESS 0x000009C4 /* MAC Miscellaneous QCU settings */
#define MAC_DMA_Q2_MISC_ADDRESS 0x000009C8 /* MAC Miscellaneous QCU settings */
#define MAC_DMA_Q3_MISC_ADDRESS 0x000009CC /* MAC Miscellaneous QCU settings */
#define MAC_DMA_Q4_MISC_ADDRESS 0x000009D0 /* MAC Miscellaneous QCU settings */
#define MAC_DMA_Q5_MISC_ADDRESS 0x000009D4 /* MAC Miscellaneous QCU settings */
#define MAC_DMA_Q6_MISC_ADDRESS 0x000009D8 /* MAC Miscellaneous QCU settings */
#define MAC_DMA_Q7_MISC_ADDRESS 0x000009DC /* MAC Miscellaneous QCU settings */
#define MAC_DMA_Q8_MISC_ADDRESS 0x000009E0 /* MAC Miscellaneous QCU settings */
#define MAC_DMA_Q9_MISC_ADDRESS 0x000009E4 /* MAC Miscellaneous QCU settings */
#define MAC_DMA_QMISC_ADDRESS(_i) (MAC_DMA_Q0_MISC_ADDRESS + ((_i)<<2))
#define MAC_DMA_Q_MISC_FSP_MASK 0x0000000F /* Frame Scheduling Policy mask */
#define MAC_DMA_Q_MISC_FSP_ASAP 0 /* ASAP */
#define MAC_DMA_Q_MISC_FSP_CBR 1 /* CBR */
#define MAC_DMA_Q_MISC_FSP_DBA_GATED 2 /* DMA Beacon Alert gated */
#define MAC_DMA_Q_MISC_FSP_TIM_GATED 3 /* TIM gated */
#define MAC_DMA_Q_MISC_FSP_BEACON_SENT_GATED 4 /* Beacon-sent-gated */
#define MAC_DMA_Q_MISC_ONE_SHOT_EN_MASK 0x00000010 /* OneShot enable */
#define MAC_DMA_Q_MISC_CBR_INCR_DIS1_MASK 0x00000020 /* Disable CBR expired counter incr
(empty q) */
#define MAC_DMA_Q_MISC_CBR_INCR_DIS0_MASK 0x00000040 /* Disable CBR expired counter incr
(empty beacon q) */
#define MAC_DMA_Q_MISC_BEACON_USE_MASK 0x00000080 /* Beacon use indication */
#define MAC_DMA_Q_MISC_CBR_EXP_CNTR_LIMIT_MASK 0x00000100 /* CBR expired counter limit enable */
#define MAC_DMA_Q_MISC_RDYTIME_EXP_POLICY_MASK 0x00000200 /* Enable TXE cleared on ReadyTime expired or VEOL */
#define MAC_DMA_Q_MISC_RESET_CBR_EXP_CTR_MASK 0x00000400 /* Reset CBR expired counter */
#define MAC_DMA_Q_MISC_DCU_EARLY_TERM_REQ_MASK 0x00000800 /* DCU frame early termination request control */
#define MAC_DMA_Q0_STS_ADDRESS 0x00000A00 /* MAC Miscellaneous QCU status */
#define MAC_DMA_Q1_STS_ADDRESS 0x00000A04 /* MAC Miscellaneous QCU status */
#define MAC_DMA_Q2_STS_ADDRESS 0x00000A08 /* MAC Miscellaneous QCU status */
#define MAC_DMA_Q3_STS_ADDRESS 0x00000A0C /* MAC Miscellaneous QCU status */
#define MAC_DMA_Q4_STS_ADDRESS 0x00000A10 /* MAC Miscellaneous QCU status */
#define MAC_DMA_Q5_STS_ADDRESS 0x00000A14 /* MAC Miscellaneous QCU status */
#define MAC_DMA_Q6_STS_ADDRESS 0x00000A18 /* MAC Miscellaneous QCU status */
#define MAC_DMA_Q7_STS_ADDRESS 0x00000A1C /* MAC Miscellaneous QCU status */
#define MAC_DMA_Q8_STS_ADDRESS 0x00000A20 /* MAC Miscellaneous QCU status */
#define MAC_DMA_Q9_STS_ADDRESS 0x00000A24 /* MAC Miscellaneous QCU status */
#define MAC_DMA_QSTS_ADDRESS(_i) (MAC_DMA_Q0_STS_ADDRESS + ((_i)<<2))
#define MAC_DMA_Q_STS_PEND_FR_CNT_MASK 0x00000003 /* Mask for Pending Frame Count */
#define MAC_DMA_Q_STS_CBR_EXP_CNT_MASK 0x0000FF00 /* Mask for CBR expired counter */
#define MAC_DMA_Q_RDYTIMESHDN_ADDRESS 0x00000A40 /* MAC ReadyTimeShutdown status */
/* DCU registers */
#define MAC_DMA_D0_QCUMASK_ADDRESS 0x00001000 /* MAC QCU Mask */
#define MAC_DMA_D1_QCUMASK_ADDRESS 0x00001004 /* MAC QCU Mask */
#define MAC_DMA_D2_QCUMASK_ADDRESS 0x00001008 /* MAC QCU Mask */
#define MAC_DMA_D3_QCUMASK_ADDRESS 0x0000100C /* MAC QCU Mask */
#define MAC_DMA_D4_QCUMASK_ADDRESS 0x00001010 /* MAC QCU Mask */
#define MAC_DMA_D5_QCUMASK_ADDRESS 0x00001014 /* MAC QCU Mask */
#define MAC_DMA_D6_QCUMASK_ADDRESS 0x00001018 /* MAC QCU Mask */
#define MAC_DMA_D7_QCUMASK_ADDRESS 0x0000101C /* MAC QCU Mask */
#define MAC_DMA_D8_QCUMASK_ADDRESS 0x00001020 /* MAC QCU Mask */
#define MAC_DMA_D9_QCUMASK_ADDRESS 0x00001024 /* MAC QCU Mask */
#define MAC_DMA_DQCUMASK_ADDRESS(_i) (MAC_DMA_D0_QCUMASK_ADDRESS + ((_i)<<2))
#define MAC_DMA_D_QCUMASK_MASK 0x000003FF /* Mask for QCU Mask (QCU 0-9) */
#define MAC_DMA_D_GBL_IFS_SIFS_ADDRESS 0x00001030 /* DCU global SIFS settings */
#define MAC_DMA_D0_LCL_IFS_ADDRESS 0x00001040 /* MAC DCU-specific IFS settings */
#define MAC_DMA_D1_LCL_IFS_ADDRESS 0x00001044 /* MAC DCU-specific IFS settings */
#define MAC_DMA_D2_LCL_IFS_ADDRESS 0x00001048 /* MAC DCU-specific IFS settings */
#define MAC_DMA_D3_LCL_IFS_ADDRESS 0x0000104C /* MAC DCU-specific IFS settings */
#define MAC_DMA_D4_LCL_IFS_ADDRESS 0x00001050 /* MAC DCU-specific IFS settings */
#define MAC_DMA_D5_LCL_IFS_ADDRESS 0x00001054 /* MAC DCU-specific IFS settings */
#define MAC_DMA_D6_LCL_IFS_ADDRESS 0x00001058 /* MAC DCU-specific IFS settings */
#define MAC_DMA_D7_LCL_IFS_ADDRESS 0x0000105C /* MAC DCU-specific IFS settings */
#define MAC_DMA_D8_LCL_IFS_ADDRESS 0x00001060 /* MAC DCU-specific IFS settings */
#define MAC_DMA_D9_LCL_IFS_ADDRESS 0x00001064 /* MAC DCU-specific IFS settings */
#define MAC_DMA_DLCL_IFS_ADDRESS(_i) (MAC_DMA_D0_LCL_IFS_ADDRESS + ((_i)<<2))
#define MAC_DMA_D_LCL_IFS_CWMIN_MASK 0x000003FF /* Mask for CW_MIN */
#define MAC_DMA_D_LCL_IFS_CWMIN_LSB 0
#define MAC_DMA_D_LCL_IFS_CWMAX_MASK 0x000FFC00 /* Mask for CW_MAX */
#define MAC_DMA_D_LCL_IFS_CWMAX_LSB 10
#define MAC_DMA_D_LCL_IFS_AIFS_MASK 0x0FF00000 /* Mask for AIFS */
#define MAC_DMA_D_LCL_IFS_AIFS_LSB 20
/*
* Note: even though this field is 8 bits wide the
* maximum supported AIFS value is 0xFc. Setting the AIFS value
* to 0xFd 0xFe, or 0xFf will not work correctly and will cause
* the DCU to hang.
*/
#define MAC_DMA_D_GBL_IFS_SLOT_ADDRESS 0x00001070 /* DC global slot interval */
#define MAC_DMA_D0_RETRY_LIMIT_ADDRESS 0x00001080 /* MAC Retry limits */
#define MAC_DMA_D1_RETRY_LIMIT_ADDRESS 0x00001084 /* MAC Retry limits */
#define MAC_DMA_D2_RETRY_LIMIT_ADDRESS 0x00001088 /* MAC Retry limits */
#define MAC_DMA_D3_RETRY_LIMIT_ADDRESS 0x0000108C /* MAC Retry limits */
#define MAC_DMA_D4_RETRY_LIMIT_ADDRESS 0x00001090 /* MAC Retry limits */
#define MAC_DMA_D5_RETRY_LIMIT_ADDRESS 0x00001094 /* MAC Retry limits */
#define MAC_DMA_D6_RETRY_LIMIT_ADDRESS 0x00001098 /* MAC Retry limits */
#define MAC_DMA_D7_RETRY_LIMIT_ADDRESS 0x0000109C /* MAC Retry limits */
#define MAC_DMA_D8_RETRY_LIMIT_ADDRESS 0x000010A0 /* MAC Retry limits */
#define MAC_DMA_D9_RETRY_LIMIT_ADDRESS 0x000010A4 /* MAC Retry limits */
#define MAC_DMA_DRETRY_LIMIT_ADDRESS(_i) (MAC_DMA_D0_RETRY_LIMIT_ADDRESS + ((_i)<<2))
#define MAC_DMA_D_RETRY_LIMIT_FR_RTS_MASK 0x0000000F /* frame RTS failure limit */
#define MAC_DMA_D_RETRY_LIMIT_FR_RTS_LSB 0
#define MAC_DMA_D_RETRY_LIMIT_STA_RTS_MASK 0x00003F00 /* station RTS failure limit */
#define MAC_DMA_D_RETRY_LIMIT_STA_RTS_LSB 8
#define MAC_DMA_D_RETRY_LIMIT_STA_DATA_MASK 0x000FC000 /* station short retry limit */
#define MAC_DMA_D_RETRY_LIMIT_STA_DATA_LSB 14
#define MAC_DMA_D_GBL_IFS_EIFS_ADDRESS 0x000010B0 /* DCU global EIFS setting */
#define MAC_DMA_D0_CHNTIME_ADDRESS 0x000010C0 /* MAC ChannelTime settings */
#define MAC_DMA_D1_CHNTIME_ADDRESS 0x000010C4 /* MAC ChannelTime settings */
#define MAC_DMA_D2_CHNTIME_ADDRESS 0x000010C8 /* MAC ChannelTime settings */
#define MAC_DMA_D3_CHNTIME_ADDRESS 0x000010CC /* MAC ChannelTime settings */
#define MAC_DMA_D4_CHNTIME_ADDRESS 0x000010D0 /* MAC ChannelTime settings */
#define MAC_DMA_D5_CHNTIME_ADDRESS 0x000010D4 /* MAC ChannelTime settings */
#define MAC_DMA_D6_CHNTIME_ADDRESS 0x000010D8 /* MAC ChannelTime settings */
#define MAC_DMA_D7_CHNTIME_ADDRESS 0x000010DC /* MAC ChannelTime settings */
#define MAC_DMA_D8_CHNTIME_ADDRESS 0x000010E0 /* MAC ChannelTime settings */
#define MAC_DMA_D9_CHNTIME_ADDRESS 0x000010E4 /* MAC ChannelTime settings */
#define MAC_DMA_DCHNTIME_ADDRESS(_i) (MAC_DMA_D0_CHNTIME_ADDRESS + ((_i)<<2))
#define MAC_DMA_D_CHNTIME_DUR_MASK 0x000FFFFF /* ChannelTime duration (us) */
#define MAC_DMA_D_CHNTIME_DUR_LSB 0 /* Shift for ChannelTime duration */
#define MAC_DMA_D_CHNTIME_EN_MASK 0x00100000 /* ChannelTime enable */
#define MAC_DMA_D_GBL_IFS_MISC_ADDRESS 0x000010f0 /* DCU global misc. IFS settings */
#define MAC_DMA_D_GBL_IFS_MISC_LFSR_SLICE_SEL_MASK 0x00000007 /* LFSR slice select */
#define MAC_DMA_D_GBL_IFS_MISC_TURBO_MODE_MASK 0x00000008 /* Turbo mode indication */
#define MAC_DMA_D_GBL_IFS_MISC_DCU_ARBITER_DLY_MASK 0x00300000 /* DCU arbiter delay */
#define MAC_DMA_D_GBL_IFS_IGNORE_BACKOFF_MASK 0x10000000
#define MAC_DMA_D0_MISC_ADDRESS 0x00001100 /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_D1_MISC_ADDRESS 0x00001104 /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_D2_MISC_ADDRESS 0x00001108 /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_D3_MISC_ADDRESS 0x0000110C /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_D4_MISC_ADDRESS 0x00001110 /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_D5_MISC_ADDRESS 0x00001114 /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_D6_MISC_ADDRESS 0x00001118 /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_D7_MISC_ADDRESS 0x0000111C /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_D8_MISC_ADDRESS 0x00001120 /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_D9_MISC_ADDRESS 0x00001124 /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_DMISC_ADDRESS(_i) (MAC_DMA_D0_MISC_ADDRESS + ((_i)<<2))
#define MAC_DMA_D0_EOL_ADDRESS 0x00001180
#define MAC_DMA_D1_EOL_ADDRESS 0x00001184
#define MAC_DMA_D2_EOL_ADDRESS 0x00001188
#define MAC_DMA_D3_EOL_ADDRESS 0x0000118C
#define MAC_DMA_D4_EOL_ADDRESS 0x00001190
#define MAC_DMA_D5_EOL_ADDRESS 0x00001194
#define MAC_DMA_D6_EOL_ADDRESS 0x00001198
#define MAC_DMA_D7_EOL_ADDRESS 0x0000119C
#define MAC_DMA_D8_EOL_ADDRESS 0x00001200
#define MAC_DMA_D9_EOL_ADDRESS 0x00001204
#define MAC_DMA_DEOL_ADDRESS(_i) (MAC_DMA_D0_EOL_ADDRESS + ((_i)<<2))
#define MAC_DMA_D_MISC_BKOFF_THRESH_MASK 0x0000003F /* Backoff threshold */
#define MAC_DMA_D_MISC_BACK_OFF_THRESH_LSB 0
#define MAC_DMA_D_MISC_ETS_RTS_MASK 0x00000040 /* End of transmission series
station RTS/data failure
count reset policy */
#define MAC_DMA_D_MISC_ETS_CW_MASK 0x00000080 /* End of transmission series
CW reset policy */
#define MAC_DMA_D_MISC_FRAG_WAIT_EN_MASK 0x00000100 /* Fragment Starvation Policy */
#define MAC_DMA_D_MISC_FRAG_BKOFF_EN_MASK 0x00000200 /* Backoff during a frag burst */
#define MAC_DMA_D_MISC_HCF_POLL_EN_MASK 0x00000800 /* HFC poll enable */
#define MAC_DMA_D_MISC_BKOFF_PERSISTENCE_MASK 0x00001000 /* Backoff persistence factor
setting */
#define MAC_DMA_D_MISC_VIR_COL_HANDLING_MASK 0x0000C000 /* Mask for Virtual collision
handling policy */
#define MAC_DMA_D_MISC_VIR_COL_HANDLING_LSB 14
#define MAC_DMA_D_MISC_VIR_COL_HANDLING_DEFAULT 0 /* Normal */
#define MAC_DMA_D_MISC_VIR_COL_HANDLING_IGNORE 1 /* Ignore */
#define MAC_DMA_D_MISC_BEACON_USE_MASK 0x00010000 /* Beacon use indication */
#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_MASK 0x00060000 /* Mask for DCU arbiter lockout control */
#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_LSB 17
#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 /* No lockout*/
#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 /* Intra-frame*/
#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 /* Global */
#define MAC_DMA_D_MISC_ARB_LOCKOUT_IGNORE_MASK 0x00080000 /* DCU arbiter lockout ignore control */
#define MAC_DMA_D_MISC_SEQ_NUM_INCR_DIS_MASK 0x00100000 /* Sequence number increment disable */
#define MAC_DMA_D_MISC_POST_FR_BKOFF_DIS_MASK 0x00200000 /* Post-frame backoff disable */
#define MAC_DMA_D_MISC_VIRT_COLL_POLICY_MASK 0x00400000 /* Virtual coll. handling policy */
#define MAC_DMA_D_MISC_BLOWN_IFS_POLICY_MASK 0x00800000 /* Blown IFS handling policy */
#define MAC_DMA_D_SEQNUM_ADDRESS 0x00001140 /* MAC Frame sequence number */
#define MAC_DMA_D_FPCTL_ADDRESS 0x00001230 /* DCU frame prefetch settings */
#define MAC_DMA_D_TXPSE_ADDRESS 0x00001270 /* DCU transmit pause control/status */
#endif /* _AR6000_DMMAEG_H_ */
drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_pcu_reg.h deleted 100644 → 0
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drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rdma_reg.h deleted 100644 → 0
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// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifndef _RDMA_REG_REG_H_
#define _RDMA_REG_REG_H_
#define DMA_CONFIG_ADDRESS 0x00000000
#define DMA_CONFIG_OFFSET 0x00000000
#define DMA_CONFIG_WLBB_PWD_EN_MSB 4
#define DMA_CONFIG_WLBB_PWD_EN_LSB 4
#define DMA_CONFIG_WLBB_PWD_EN_MASK 0x00000010
#define DMA_CONFIG_WLBB_PWD_EN_GET(x) (((x) & DMA_CONFIG_WLBB_PWD_EN_MASK) >> DMA_CONFIG_WLBB_PWD_EN_LSB)
#define DMA_CONFIG_WLBB_PWD_EN_SET(x) (((x) << DMA_CONFIG_WLBB_PWD_EN_LSB) & DMA_CONFIG_WLBB_PWD_EN_MASK)
#define DMA_CONFIG_WLMAC_PWD_EN_MSB 3
#define DMA_CONFIG_WLMAC_PWD_EN_LSB 3
#define DMA_CONFIG_WLMAC_PWD_EN_MASK 0x00000008
#define DMA_CONFIG_WLMAC_PWD_EN_GET(x) (((x) & DMA_CONFIG_WLMAC_PWD_EN_MASK) >> DMA_CONFIG_WLMAC_PWD_EN_LSB)
#define DMA_CONFIG_WLMAC_PWD_EN_SET(x) (((x) << DMA_CONFIG_WLMAC_PWD_EN_LSB) & DMA_CONFIG_WLMAC_PWD_EN_MASK)
#define DMA_CONFIG_ENABLE_RETENTION_MSB 2
#define DMA_CONFIG_ENABLE_RETENTION_LSB 2
#define DMA_CONFIG_ENABLE_RETENTION_MASK 0x00000004
#define DMA_CONFIG_ENABLE_RETENTION_GET(x) (((x) & DMA_CONFIG_ENABLE_RETENTION_MASK) >> DMA_CONFIG_ENABLE_RETENTION_LSB)
#define DMA_CONFIG_ENABLE_RETENTION_SET(x) (((x) << DMA_CONFIG_ENABLE_RETENTION_LSB) & DMA_CONFIG_ENABLE_RETENTION_MASK)
#define DMA_CONFIG_RTC_PRIORITY_MSB 1
#define DMA_CONFIG_RTC_PRIORITY_LSB 1
#define DMA_CONFIG_RTC_PRIORITY_MASK 0x00000002
#define DMA_CONFIG_RTC_PRIORITY_GET(x) (((x) & DMA_CONFIG_RTC_PRIORITY_MASK) >> DMA_CONFIG_RTC_PRIORITY_LSB)
#define DMA_CONFIG_RTC_PRIORITY_SET(x) (((x) << DMA_CONFIG_RTC_PRIORITY_LSB) & DMA_CONFIG_RTC_PRIORITY_MASK)
#define DMA_CONFIG_DMA_TYPE_MSB 0
#define DMA_CONFIG_DMA_TYPE_LSB 0
#define DMA_CONFIG_DMA_TYPE_MASK 0x00000001
#define DMA_CONFIG_DMA_TYPE_GET(x) (((x) & DMA_CONFIG_DMA_TYPE_MASK) >> DMA_CONFIG_DMA_TYPE_LSB)
#define DMA_CONFIG_DMA_TYPE_SET(x) (((x) << DMA_CONFIG_DMA_TYPE_LSB) & DMA_CONFIG_DMA_TYPE_MASK)
#define DMA_CONTROL_ADDRESS 0x00000004
#define DMA_CONTROL_OFFSET 0x00000004
#define DMA_CONTROL_START_MSB 1
#define DMA_CONTROL_START_LSB 1
#define DMA_CONTROL_START_MASK 0x00000002
#define DMA_CONTROL_START_GET(x) (((x) & DMA_CONTROL_START_MASK) >> DMA_CONTROL_START_LSB)
#define DMA_CONTROL_START_SET(x) (((x) << DMA_CONTROL_START_LSB) & DMA_CONTROL_START_MASK)
#define DMA_CONTROL_STOP_MSB 0
#define DMA_CONTROL_STOP_LSB 0
#define DMA_CONTROL_STOP_MASK 0x00000001
#define DMA_CONTROL_STOP_GET(x) (((x) & DMA_CONTROL_STOP_MASK) >> DMA_CONTROL_STOP_LSB)
#define DMA_CONTROL_STOP_SET(x) (((x) << DMA_CONTROL_STOP_LSB) & DMA_CONTROL_STOP_MASK)
#define DMA_SRC_ADDRESS 0x00000008
#define DMA_SRC_OFFSET 0x00000008
#define DMA_SRC_ADDR_MSB 31
#define DMA_SRC_ADDR_LSB 2
#define DMA_SRC_ADDR_MASK 0xfffffffc
#define DMA_SRC_ADDR_GET(x) (((x) & DMA_SRC_ADDR_MASK) >> DMA_SRC_ADDR_LSB)
#define DMA_SRC_ADDR_SET(x) (((x) << DMA_SRC_ADDR_LSB) & DMA_SRC_ADDR_MASK)
#define DMA_DEST_ADDRESS 0x0000000c
#define DMA_DEST_OFFSET 0x0000000c
#define DMA_DEST_ADDR_MSB 31
#define DMA_DEST_ADDR_LSB 2
#define DMA_DEST_ADDR_MASK 0xfffffffc
#define DMA_DEST_ADDR_GET(x) (((x) & DMA_DEST_ADDR_MASK) >> DMA_DEST_ADDR_LSB)
#define DMA_DEST_ADDR_SET(x) (((x) << DMA_DEST_ADDR_LSB) & DMA_DEST_ADDR_MASK)
#define DMA_LENGTH_ADDRESS 0x00000010
#define DMA_LENGTH_OFFSET 0x00000010
#define DMA_LENGTH_WORDS_MSB 11
#define DMA_LENGTH_WORDS_LSB 0
#define DMA_LENGTH_WORDS_MASK 0x00000fff
#define DMA_LENGTH_WORDS_GET(x) (((x) & DMA_LENGTH_WORDS_MASK) >> DMA_LENGTH_WORDS_LSB)
#define DMA_LENGTH_WORDS_SET(x) (((x) << DMA_LENGTH_WORDS_LSB) & DMA_LENGTH_WORDS_MASK)
#define VMC_BASE_ADDRESS 0x00000014
#define VMC_BASE_OFFSET 0x00000014
#define VMC_BASE_ADDR_MSB 31
#define VMC_BASE_ADDR_LSB 2
#define VMC_BASE_ADDR_MASK 0xfffffffc
#define VMC_BASE_ADDR_GET(x) (((x) & VMC_BASE_ADDR_MASK) >> VMC_BASE_ADDR_LSB)
#define VMC_BASE_ADDR_SET(x) (((x) << VMC_BASE_ADDR_LSB) & VMC_BASE_ADDR_MASK)
#define INDIRECT_REG_ADDRESS 0x00000018
#define INDIRECT_REG_OFFSET 0x00000018
#define INDIRECT_REG_ID_MSB 31
#define INDIRECT_REG_ID_LSB 2
#define INDIRECT_REG_ID_MASK 0xfffffffc
#define INDIRECT_REG_ID_GET(x) (((x) & INDIRECT_REG_ID_MASK) >> INDIRECT_REG_ID_LSB)
#define INDIRECT_REG_ID_SET(x) (((x) << INDIRECT_REG_ID_LSB) & INDIRECT_REG_ID_MASK)
#define INDIRECT_RETURN_ADDRESS 0x0000001c
#define INDIRECT_RETURN_OFFSET 0x0000001c
#define INDIRECT_RETURN_ADDR_MSB 31
#define INDIRECT_RETURN_ADDR_LSB 2
#define INDIRECT_RETURN_ADDR_MASK 0xfffffffc
#define INDIRECT_RETURN_ADDR_GET(x) (((x) & INDIRECT_RETURN_ADDR_MASK) >> INDIRECT_RETURN_ADDR_LSB)
#define INDIRECT_RETURN_ADDR_SET(x) (((x) << INDIRECT_RETURN_ADDR_LSB) & INDIRECT_RETURN_ADDR_MASK)
#define RDMA_REGION_0__ADDRESS 0x00000020
#define RDMA_REGION_0__OFFSET 0x00000020
#define RDMA_REGION_0__ADDR_MSB 31
#define RDMA_REGION_0__ADDR_LSB 13
#define RDMA_REGION_0__ADDR_MASK 0xffffe000
#define RDMA_REGION_0__ADDR_GET(x) (((x) & RDMA_REGION_0__ADDR_MASK) >> RDMA_REGION_0__ADDR_LSB)
#define RDMA_REGION_0__ADDR_SET(x) (((x) << RDMA_REGION_0__ADDR_LSB) & RDMA_REGION_0__ADDR_MASK)
#define RDMA_REGION_0__LENGTH_MSB 12
#define RDMA_REGION_0__LENGTH_LSB 2
#define RDMA_REGION_0__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_0__LENGTH_GET(x) (((x) & RDMA_REGION_0__LENGTH_MASK) >> RDMA_REGION_0__LENGTH_LSB)
#define RDMA_REGION_0__LENGTH_SET(x) (((x) << RDMA_REGION_0__LENGTH_LSB) & RDMA_REGION_0__LENGTH_MASK)
#define RDMA_REGION_0__INDI_MSB 1
#define RDMA_REGION_0__INDI_LSB 1
#define RDMA_REGION_0__INDI_MASK 0x00000002
#define RDMA_REGION_0__INDI_GET(x) (((x) & RDMA_REGION_0__INDI_MASK) >> RDMA_REGION_0__INDI_LSB)
#define RDMA_REGION_0__INDI_SET(x) (((x) << RDMA_REGION_0__INDI_LSB) & RDMA_REGION_0__INDI_MASK)
#define RDMA_REGION_0__NEXT_MSB 0
#define RDMA_REGION_0__NEXT_LSB 0
#define RDMA_REGION_0__NEXT_MASK 0x00000001
#define RDMA_REGION_0__NEXT_GET(x) (((x) & RDMA_REGION_0__NEXT_MASK) >> RDMA_REGION_0__NEXT_LSB)
#define RDMA_REGION_0__NEXT_SET(x) (((x) << RDMA_REGION_0__NEXT_LSB) & RDMA_REGION_0__NEXT_MASK)
#define RDMA_REGION_1__ADDRESS 0x00000024
#define RDMA_REGION_1__OFFSET 0x00000024
#define RDMA_REGION_1__ADDR_MSB 31
#define RDMA_REGION_1__ADDR_LSB 13
#define RDMA_REGION_1__ADDR_MASK 0xffffe000
#define RDMA_REGION_1__ADDR_GET(x) (((x) & RDMA_REGION_1__ADDR_MASK) >> RDMA_REGION_1__ADDR_LSB)
#define RDMA_REGION_1__ADDR_SET(x) (((x) << RDMA_REGION_1__ADDR_LSB) & RDMA_REGION_1__ADDR_MASK)
#define RDMA_REGION_1__LENGTH_MSB 12
#define RDMA_REGION_1__LENGTH_LSB 2
#define RDMA_REGION_1__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_1__LENGTH_GET(x) (((x) & RDMA_REGION_1__LENGTH_MASK) >> RDMA_REGION_1__LENGTH_LSB)
#define RDMA_REGION_1__LENGTH_SET(x) (((x) << RDMA_REGION_1__LENGTH_LSB) & RDMA_REGION_1__LENGTH_MASK)
#define RDMA_REGION_1__INDI_MSB 1
#define RDMA_REGION_1__INDI_LSB 1
#define RDMA_REGION_1__INDI_MASK 0x00000002
#define RDMA_REGION_1__INDI_GET(x) (((x) & RDMA_REGION_1__INDI_MASK) >> RDMA_REGION_1__INDI_LSB)
#define RDMA_REGION_1__INDI_SET(x) (((x) << RDMA_REGION_1__INDI_LSB) & RDMA_REGION_1__INDI_MASK)
#define RDMA_REGION_1__NEXT_MSB 0
#define RDMA_REGION_1__NEXT_LSB 0
#define RDMA_REGION_1__NEXT_MASK 0x00000001
#define RDMA_REGION_1__NEXT_GET(x) (((x) & RDMA_REGION_1__NEXT_MASK) >> RDMA_REGION_1__NEXT_LSB)
#define RDMA_REGION_1__NEXT_SET(x) (((x) << RDMA_REGION_1__NEXT_LSB) & RDMA_REGION_1__NEXT_MASK)
#define RDMA_REGION_2__ADDRESS 0x00000028
#define RDMA_REGION_2__OFFSET 0x00000028
#define RDMA_REGION_2__ADDR_MSB 31
#define RDMA_REGION_2__ADDR_LSB 13
#define RDMA_REGION_2__ADDR_MASK 0xffffe000
#define RDMA_REGION_2__ADDR_GET(x) (((x) & RDMA_REGION_2__ADDR_MASK) >> RDMA_REGION_2__ADDR_LSB)
#define RDMA_REGION_2__ADDR_SET(x) (((x) << RDMA_REGION_2__ADDR_LSB) & RDMA_REGION_2__ADDR_MASK)
#define RDMA_REGION_2__LENGTH_MSB 12
#define RDMA_REGION_2__LENGTH_LSB 2
#define RDMA_REGION_2__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_2__LENGTH_GET(x) (((x) & RDMA_REGION_2__LENGTH_MASK) >> RDMA_REGION_2__LENGTH_LSB)
#define RDMA_REGION_2__LENGTH_SET(x) (((x) << RDMA_REGION_2__LENGTH_LSB) & RDMA_REGION_2__LENGTH_MASK)
#define RDMA_REGION_2__INDI_MSB 1
#define RDMA_REGION_2__INDI_LSB 1
#define RDMA_REGION_2__INDI_MASK 0x00000002
#define RDMA_REGION_2__INDI_GET(x) (((x) & RDMA_REGION_2__INDI_MASK) >> RDMA_REGION_2__INDI_LSB)
#define RDMA_REGION_2__INDI_SET(x) (((x) << RDMA_REGION_2__INDI_LSB) & RDMA_REGION_2__INDI_MASK)
#define RDMA_REGION_2__NEXT_MSB 0
#define RDMA_REGION_2__NEXT_LSB 0
#define RDMA_REGION_2__NEXT_MASK 0x00000001
#define RDMA_REGION_2__NEXT_GET(x) (((x) & RDMA_REGION_2__NEXT_MASK) >> RDMA_REGION_2__NEXT_LSB)
#define RDMA_REGION_2__NEXT_SET(x) (((x) << RDMA_REGION_2__NEXT_LSB) & RDMA_REGION_2__NEXT_MASK)
#define RDMA_REGION_3__ADDRESS 0x0000002c
#define RDMA_REGION_3__OFFSET 0x0000002c
#define RDMA_REGION_3__ADDR_MSB 31
#define RDMA_REGION_3__ADDR_LSB 13
#define RDMA_REGION_3__ADDR_MASK 0xffffe000
#define RDMA_REGION_3__ADDR_GET(x) (((x) & RDMA_REGION_3__ADDR_MASK) >> RDMA_REGION_3__ADDR_LSB)
#define RDMA_REGION_3__ADDR_SET(x) (((x) << RDMA_REGION_3__ADDR_LSB) & RDMA_REGION_3__ADDR_MASK)
#define RDMA_REGION_3__LENGTH_MSB 12
#define RDMA_REGION_3__LENGTH_LSB 2
#define RDMA_REGION_3__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_3__LENGTH_GET(x) (((x) & RDMA_REGION_3__LENGTH_MASK) >> RDMA_REGION_3__LENGTH_LSB)
#define RDMA_REGION_3__LENGTH_SET(x) (((x) << RDMA_REGION_3__LENGTH_LSB) & RDMA_REGION_3__LENGTH_MASK)
#define RDMA_REGION_3__INDI_MSB 1
#define RDMA_REGION_3__INDI_LSB 1
#define RDMA_REGION_3__INDI_MASK 0x00000002
#define RDMA_REGION_3__INDI_GET(x) (((x) & RDMA_REGION_3__INDI_MASK) >> RDMA_REGION_3__INDI_LSB)
#define RDMA_REGION_3__INDI_SET(x) (((x) << RDMA_REGION_3__INDI_LSB) & RDMA_REGION_3__INDI_MASK)
#define RDMA_REGION_3__NEXT_MSB 0
#define RDMA_REGION_3__NEXT_LSB 0
#define RDMA_REGION_3__NEXT_MASK 0x00000001
#define RDMA_REGION_3__NEXT_GET(x) (((x) & RDMA_REGION_3__NEXT_MASK) >> RDMA_REGION_3__NEXT_LSB)
#define RDMA_REGION_3__NEXT_SET(x) (((x) << RDMA_REGION_3__NEXT_LSB) & RDMA_REGION_3__NEXT_MASK)
#define RDMA_REGION_4__ADDRESS 0x00000030
#define RDMA_REGION_4__OFFSET 0x00000030
#define RDMA_REGION_4__ADDR_MSB 31
#define RDMA_REGION_4__ADDR_LSB 13
#define RDMA_REGION_4__ADDR_MASK 0xffffe000
#define RDMA_REGION_4__ADDR_GET(x) (((x) & RDMA_REGION_4__ADDR_MASK) >> RDMA_REGION_4__ADDR_LSB)
#define RDMA_REGION_4__ADDR_SET(x) (((x) << RDMA_REGION_4__ADDR_LSB) & RDMA_REGION_4__ADDR_MASK)
#define RDMA_REGION_4__LENGTH_MSB 12
#define RDMA_REGION_4__LENGTH_LSB 2
#define RDMA_REGION_4__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_4__LENGTH_GET(x) (((x) & RDMA_REGION_4__LENGTH_MASK) >> RDMA_REGION_4__LENGTH_LSB)
#define RDMA_REGION_4__LENGTH_SET(x) (((x) << RDMA_REGION_4__LENGTH_LSB) & RDMA_REGION_4__LENGTH_MASK)
#define RDMA_REGION_4__INDI_MSB 1
#define RDMA_REGION_4__INDI_LSB 1
#define RDMA_REGION_4__INDI_MASK 0x00000002
#define RDMA_REGION_4__INDI_GET(x) (((x) & RDMA_REGION_4__INDI_MASK) >> RDMA_REGION_4__INDI_LSB)
#define RDMA_REGION_4__INDI_SET(x) (((x) << RDMA_REGION_4__INDI_LSB) & RDMA_REGION_4__INDI_MASK)
#define RDMA_REGION_4__NEXT_MSB 0
#define RDMA_REGION_4__NEXT_LSB 0
#define RDMA_REGION_4__NEXT_MASK 0x00000001
#define RDMA_REGION_4__NEXT_GET(x) (((x) & RDMA_REGION_4__NEXT_MASK) >> RDMA_REGION_4__NEXT_LSB)
#define RDMA_REGION_4__NEXT_SET(x) (((x) << RDMA_REGION_4__NEXT_LSB) & RDMA_REGION_4__NEXT_MASK)
#define RDMA_REGION_5__ADDRESS 0x00000034
#define RDMA_REGION_5__OFFSET 0x00000034
#define RDMA_REGION_5__ADDR_MSB 31
#define RDMA_REGION_5__ADDR_LSB 13
#define RDMA_REGION_5__ADDR_MASK 0xffffe000
#define RDMA_REGION_5__ADDR_GET(x) (((x) & RDMA_REGION_5__ADDR_MASK) >> RDMA_REGION_5__ADDR_LSB)
#define RDMA_REGION_5__ADDR_SET(x) (((x) << RDMA_REGION_5__ADDR_LSB) & RDMA_REGION_5__ADDR_MASK)
#define RDMA_REGION_5__LENGTH_MSB 12
#define RDMA_REGION_5__LENGTH_LSB 2
#define RDMA_REGION_5__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_5__LENGTH_GET(x) (((x) & RDMA_REGION_5__LENGTH_MASK) >> RDMA_REGION_5__LENGTH_LSB)
#define RDMA_REGION_5__LENGTH_SET(x) (((x) << RDMA_REGION_5__LENGTH_LSB) & RDMA_REGION_5__LENGTH_MASK)
#define RDMA_REGION_5__INDI_MSB 1
#define RDMA_REGION_5__INDI_LSB 1
#define RDMA_REGION_5__INDI_MASK 0x00000002
#define RDMA_REGION_5__INDI_GET(x) (((x) & RDMA_REGION_5__INDI_MASK) >> RDMA_REGION_5__INDI_LSB)
#define RDMA_REGION_5__INDI_SET(x) (((x) << RDMA_REGION_5__INDI_LSB) & RDMA_REGION_5__INDI_MASK)
#define RDMA_REGION_5__NEXT_MSB 0
#define RDMA_REGION_5__NEXT_LSB 0
#define RDMA_REGION_5__NEXT_MASK 0x00000001
#define RDMA_REGION_5__NEXT_GET(x) (((x) & RDMA_REGION_5__NEXT_MASK) >> RDMA_REGION_5__NEXT_LSB)
#define RDMA_REGION_5__NEXT_SET(x) (((x) << RDMA_REGION_5__NEXT_LSB) & RDMA_REGION_5__NEXT_MASK)
#define RDMA_REGION_6__ADDRESS 0x00000038
#define RDMA_REGION_6__OFFSET 0x00000038
#define RDMA_REGION_6__ADDR_MSB 31
#define RDMA_REGION_6__ADDR_LSB 13
#define RDMA_REGION_6__ADDR_MASK 0xffffe000
#define RDMA_REGION_6__ADDR_GET(x) (((x) & RDMA_REGION_6__ADDR_MASK) >> RDMA_REGION_6__ADDR_LSB)
#define RDMA_REGION_6__ADDR_SET(x) (((x) << RDMA_REGION_6__ADDR_LSB) & RDMA_REGION_6__ADDR_MASK)
#define RDMA_REGION_6__LENGTH_MSB 12
#define RDMA_REGION_6__LENGTH_LSB 2
#define RDMA_REGION_6__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_6__LENGTH_GET(x) (((x) & RDMA_REGION_6__LENGTH_MASK) >> RDMA_REGION_6__LENGTH_LSB)
#define RDMA_REGION_6__LENGTH_SET(x) (((x) << RDMA_REGION_6__LENGTH_LSB) & RDMA_REGION_6__LENGTH_MASK)
#define RDMA_REGION_6__INDI_MSB 1
#define RDMA_REGION_6__INDI_LSB 1
#define RDMA_REGION_6__INDI_MASK 0x00000002
#define RDMA_REGION_6__INDI_GET(x) (((x) & RDMA_REGION_6__INDI_MASK) >> RDMA_REGION_6__INDI_LSB)
#define RDMA_REGION_6__INDI_SET(x) (((x) << RDMA_REGION_6__INDI_LSB) & RDMA_REGION_6__INDI_MASK)
#define RDMA_REGION_6__NEXT_MSB 0
#define RDMA_REGION_6__NEXT_LSB 0
#define RDMA_REGION_6__NEXT_MASK 0x00000001
#define RDMA_REGION_6__NEXT_GET(x) (((x) & RDMA_REGION_6__NEXT_MASK) >> RDMA_REGION_6__NEXT_LSB)
#define RDMA_REGION_6__NEXT_SET(x) (((x) << RDMA_REGION_6__NEXT_LSB) & RDMA_REGION_6__NEXT_MASK)
#define RDMA_REGION_7__ADDRESS 0x0000003c
#define RDMA_REGION_7__OFFSET 0x0000003c
#define RDMA_REGION_7__ADDR_MSB 31
#define RDMA_REGION_7__ADDR_LSB 13
#define RDMA_REGION_7__ADDR_MASK 0xffffe000
#define RDMA_REGION_7__ADDR_GET(x) (((x) & RDMA_REGION_7__ADDR_MASK) >> RDMA_REGION_7__ADDR_LSB)
#define RDMA_REGION_7__ADDR_SET(x) (((x) << RDMA_REGION_7__ADDR_LSB) & RDMA_REGION_7__ADDR_MASK)
#define RDMA_REGION_7__LENGTH_MSB 12
#define RDMA_REGION_7__LENGTH_LSB 2
#define RDMA_REGION_7__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_7__LENGTH_GET(x) (((x) & RDMA_REGION_7__LENGTH_MASK) >> RDMA_REGION_7__LENGTH_LSB)
#define RDMA_REGION_7__LENGTH_SET(x) (((x) << RDMA_REGION_7__LENGTH_LSB) & RDMA_REGION_7__LENGTH_MASK)
#define RDMA_REGION_7__INDI_MSB 1
#define RDMA_REGION_7__INDI_LSB 1
#define RDMA_REGION_7__INDI_MASK 0x00000002
#define RDMA_REGION_7__INDI_GET(x) (((x) & RDMA_REGION_7__INDI_MASK) >> RDMA_REGION_7__INDI_LSB)
#define RDMA_REGION_7__INDI_SET(x) (((x) << RDMA_REGION_7__INDI_LSB) & RDMA_REGION_7__INDI_MASK)
#define RDMA_REGION_7__NEXT_MSB 0
#define RDMA_REGION_7__NEXT_LSB 0
#define RDMA_REGION_7__NEXT_MASK 0x00000001
#define RDMA_REGION_7__NEXT_GET(x) (((x) & RDMA_REGION_7__NEXT_MASK) >> RDMA_REGION_7__NEXT_LSB)
#define RDMA_REGION_7__NEXT_SET(x) (((x) << RDMA_REGION_7__NEXT_LSB) & RDMA_REGION_7__NEXT_MASK)
#define RDMA_REGION_8__ADDRESS 0x00000040
#define RDMA_REGION_8__OFFSET 0x00000040
#define RDMA_REGION_8__ADDR_MSB 31
#define RDMA_REGION_8__ADDR_LSB 13
#define RDMA_REGION_8__ADDR_MASK 0xffffe000
#define RDMA_REGION_8__ADDR_GET(x) (((x) & RDMA_REGION_8__ADDR_MASK) >> RDMA_REGION_8__ADDR_LSB)
#define RDMA_REGION_8__ADDR_SET(x) (((x) << RDMA_REGION_8__ADDR_LSB) & RDMA_REGION_8__ADDR_MASK)
#define RDMA_REGION_8__LENGTH_MSB 12
#define RDMA_REGION_8__LENGTH_LSB 2
#define RDMA_REGION_8__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_8__LENGTH_GET(x) (((x) & RDMA_REGION_8__LENGTH_MASK) >> RDMA_REGION_8__LENGTH_LSB)
#define RDMA_REGION_8__LENGTH_SET(x) (((x) << RDMA_REGION_8__LENGTH_LSB) & RDMA_REGION_8__LENGTH_MASK)
#define RDMA_REGION_8__INDI_MSB 1
#define RDMA_REGION_8__INDI_LSB 1
#define RDMA_REGION_8__INDI_MASK 0x00000002
#define RDMA_REGION_8__INDI_GET(x) (((x) & RDMA_REGION_8__INDI_MASK) >> RDMA_REGION_8__INDI_LSB)
#define RDMA_REGION_8__INDI_SET(x) (((x) << RDMA_REGION_8__INDI_LSB) & RDMA_REGION_8__INDI_MASK)
#define RDMA_REGION_8__NEXT_MSB 0
#define RDMA_REGION_8__NEXT_LSB 0
#define RDMA_REGION_8__NEXT_MASK 0x00000001
#define RDMA_REGION_8__NEXT_GET(x) (((x) & RDMA_REGION_8__NEXT_MASK) >> RDMA_REGION_8__NEXT_LSB)
#define RDMA_REGION_8__NEXT_SET(x) (((x) << RDMA_REGION_8__NEXT_LSB) & RDMA_REGION_8__NEXT_MASK)
#define RDMA_REGION_9__ADDRESS 0x00000044
#define RDMA_REGION_9__OFFSET 0x00000044
#define RDMA_REGION_9__ADDR_MSB 31
#define RDMA_REGION_9__ADDR_LSB 13
#define RDMA_REGION_9__ADDR_MASK 0xffffe000
#define RDMA_REGION_9__ADDR_GET(x) (((x) & RDMA_REGION_9__ADDR_MASK) >> RDMA_REGION_9__ADDR_LSB)
#define RDMA_REGION_9__ADDR_SET(x) (((x) << RDMA_REGION_9__ADDR_LSB) & RDMA_REGION_9__ADDR_MASK)
#define RDMA_REGION_9__LENGTH_MSB 12
#define RDMA_REGION_9__LENGTH_LSB 2
#define RDMA_REGION_9__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_9__LENGTH_GET(x) (((x) & RDMA_REGION_9__LENGTH_MASK) >> RDMA_REGION_9__LENGTH_LSB)
#define RDMA_REGION_9__LENGTH_SET(x) (((x) << RDMA_REGION_9__LENGTH_LSB) & RDMA_REGION_9__LENGTH_MASK)
#define RDMA_REGION_9__INDI_MSB 1
#define RDMA_REGION_9__INDI_LSB 1
#define RDMA_REGION_9__INDI_MASK 0x00000002
#define RDMA_REGION_9__INDI_GET(x) (((x) & RDMA_REGION_9__INDI_MASK) >> RDMA_REGION_9__INDI_LSB)
#define RDMA_REGION_9__INDI_SET(x) (((x) << RDMA_REGION_9__INDI_LSB) & RDMA_REGION_9__INDI_MASK)
#define RDMA_REGION_9__NEXT_MSB 0
#define RDMA_REGION_9__NEXT_LSB 0
#define RDMA_REGION_9__NEXT_MASK 0x00000001
#define RDMA_REGION_9__NEXT_GET(x) (((x) & RDMA_REGION_9__NEXT_MASK) >> RDMA_REGION_9__NEXT_LSB)
#define RDMA_REGION_9__NEXT_SET(x) (((x) << RDMA_REGION_9__NEXT_LSB) & RDMA_REGION_9__NEXT_MASK)
#define RDMA_REGION_10__ADDRESS 0x00000048
#define RDMA_REGION_10__OFFSET 0x00000048
#define RDMA_REGION_10__ADDR_MSB 31
#define RDMA_REGION_10__ADDR_LSB 13
#define RDMA_REGION_10__ADDR_MASK 0xffffe000
#define RDMA_REGION_10__ADDR_GET(x) (((x) & RDMA_REGION_10__ADDR_MASK) >> RDMA_REGION_10__ADDR_LSB)
#define RDMA_REGION_10__ADDR_SET(x) (((x) << RDMA_REGION_10__ADDR_LSB) & RDMA_REGION_10__ADDR_MASK)
#define RDMA_REGION_10__LENGTH_MSB 12
#define RDMA_REGION_10__LENGTH_LSB 2
#define RDMA_REGION_10__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_10__LENGTH_GET(x) (((x) & RDMA_REGION_10__LENGTH_MASK) >> RDMA_REGION_10__LENGTH_LSB)
#define RDMA_REGION_10__LENGTH_SET(x) (((x) << RDMA_REGION_10__LENGTH_LSB) & RDMA_REGION_10__LENGTH_MASK)
#define RDMA_REGION_10__INDI_MSB 1
#define RDMA_REGION_10__INDI_LSB 1
#define RDMA_REGION_10__INDI_MASK 0x00000002
#define RDMA_REGION_10__INDI_GET(x) (((x) & RDMA_REGION_10__INDI_MASK) >> RDMA_REGION_10__INDI_LSB)
#define RDMA_REGION_10__INDI_SET(x) (((x) << RDMA_REGION_10__INDI_LSB) & RDMA_REGION_10__INDI_MASK)
#define RDMA_REGION_10__NEXT_MSB 0
#define RDMA_REGION_10__NEXT_LSB 0
#define RDMA_REGION_10__NEXT_MASK 0x00000001
#define RDMA_REGION_10__NEXT_GET(x) (((x) & RDMA_REGION_10__NEXT_MASK) >> RDMA_REGION_10__NEXT_LSB)
#define RDMA_REGION_10__NEXT_SET(x) (((x) << RDMA_REGION_10__NEXT_LSB) & RDMA_REGION_10__NEXT_MASK)
#define RDMA_REGION_11__ADDRESS 0x0000004c
#define RDMA_REGION_11__OFFSET 0x0000004c
#define RDMA_REGION_11__ADDR_MSB 31
#define RDMA_REGION_11__ADDR_LSB 13
#define RDMA_REGION_11__ADDR_MASK 0xffffe000
#define RDMA_REGION_11__ADDR_GET(x) (((x) & RDMA_REGION_11__ADDR_MASK) >> RDMA_REGION_11__ADDR_LSB)
#define RDMA_REGION_11__ADDR_SET(x) (((x) << RDMA_REGION_11__ADDR_LSB) & RDMA_REGION_11__ADDR_MASK)
#define RDMA_REGION_11__LENGTH_MSB 12
#define RDMA_REGION_11__LENGTH_LSB 2
#define RDMA_REGION_11__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_11__LENGTH_GET(x) (((x) & RDMA_REGION_11__LENGTH_MASK) >> RDMA_REGION_11__LENGTH_LSB)
#define RDMA_REGION_11__LENGTH_SET(x) (((x) << RDMA_REGION_11__LENGTH_LSB) & RDMA_REGION_11__LENGTH_MASK)
#define RDMA_REGION_11__INDI_MSB 1
#define RDMA_REGION_11__INDI_LSB 1
#define RDMA_REGION_11__INDI_MASK 0x00000002
#define RDMA_REGION_11__INDI_GET(x) (((x) & RDMA_REGION_11__INDI_MASK) >> RDMA_REGION_11__INDI_LSB)
#define RDMA_REGION_11__INDI_SET(x) (((x) << RDMA_REGION_11__INDI_LSB) & RDMA_REGION_11__INDI_MASK)
#define RDMA_REGION_11__NEXT_MSB 0
#define RDMA_REGION_11__NEXT_LSB 0
#define RDMA_REGION_11__NEXT_MASK 0x00000001
#define RDMA_REGION_11__NEXT_GET(x) (((x) & RDMA_REGION_11__NEXT_MASK) >> RDMA_REGION_11__NEXT_LSB)
#define RDMA_REGION_11__NEXT_SET(x) (((x) << RDMA_REGION_11__NEXT_LSB) & RDMA_REGION_11__NEXT_MASK)
#define RDMA_REGION_12__ADDRESS 0x00000050
#define RDMA_REGION_12__OFFSET 0x00000050
#define RDMA_REGION_12__ADDR_MSB 31
#define RDMA_REGION_12__ADDR_LSB 13
#define RDMA_REGION_12__ADDR_MASK 0xffffe000
#define RDMA_REGION_12__ADDR_GET(x) (((x) & RDMA_REGION_12__ADDR_MASK) >> RDMA_REGION_12__ADDR_LSB)
#define RDMA_REGION_12__ADDR_SET(x) (((x) << RDMA_REGION_12__ADDR_LSB) & RDMA_REGION_12__ADDR_MASK)
#define RDMA_REGION_12__LENGTH_MSB 12
#define RDMA_REGION_12__LENGTH_LSB 2
#define RDMA_REGION_12__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_12__LENGTH_GET(x) (((x) & RDMA_REGION_12__LENGTH_MASK) >> RDMA_REGION_12__LENGTH_LSB)
#define RDMA_REGION_12__LENGTH_SET(x) (((x) << RDMA_REGION_12__LENGTH_LSB) & RDMA_REGION_12__LENGTH_MASK)
#define RDMA_REGION_12__INDI_MSB 1
#define RDMA_REGION_12__INDI_LSB 1
#define RDMA_REGION_12__INDI_MASK 0x00000002
#define RDMA_REGION_12__INDI_GET(x) (((x) & RDMA_REGION_12__INDI_MASK) >> RDMA_REGION_12__INDI_LSB)
#define RDMA_REGION_12__INDI_SET(x) (((x) << RDMA_REGION_12__INDI_LSB) & RDMA_REGION_12__INDI_MASK)
#define RDMA_REGION_12__NEXT_MSB 0
#define RDMA_REGION_12__NEXT_LSB 0
#define RDMA_REGION_12__NEXT_MASK 0x00000001
#define RDMA_REGION_12__NEXT_GET(x) (((x) & RDMA_REGION_12__NEXT_MASK) >> RDMA_REGION_12__NEXT_LSB)
#define RDMA_REGION_12__NEXT_SET(x) (((x) << RDMA_REGION_12__NEXT_LSB) & RDMA_REGION_12__NEXT_MASK)
#define RDMA_REGION_13__ADDRESS 0x00000054
#define RDMA_REGION_13__OFFSET 0x00000054
#define RDMA_REGION_13__ADDR_MSB 31
#define RDMA_REGION_13__ADDR_LSB 13
#define RDMA_REGION_13__ADDR_MASK 0xffffe000
#define RDMA_REGION_13__ADDR_GET(x) (((x) & RDMA_REGION_13__ADDR_MASK) >> RDMA_REGION_13__ADDR_LSB)
#define RDMA_REGION_13__ADDR_SET(x) (((x) << RDMA_REGION_13__ADDR_LSB) & RDMA_REGION_13__ADDR_MASK)
#define RDMA_REGION_13__LENGTH_MSB 12
#define RDMA_REGION_13__LENGTH_LSB 2
#define RDMA_REGION_13__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_13__LENGTH_GET(x) (((x) & RDMA_REGION_13__LENGTH_MASK) >> RDMA_REGION_13__LENGTH_LSB)
#define RDMA_REGION_13__LENGTH_SET(x) (((x) << RDMA_REGION_13__LENGTH_LSB) & RDMA_REGION_13__LENGTH_MASK)
#define RDMA_REGION_13__INDI_MSB 1
#define RDMA_REGION_13__INDI_LSB 1
#define RDMA_REGION_13__INDI_MASK 0x00000002
#define RDMA_REGION_13__INDI_GET(x) (((x) & RDMA_REGION_13__INDI_MASK) >> RDMA_REGION_13__INDI_LSB)
#define RDMA_REGION_13__INDI_SET(x) (((x) << RDMA_REGION_13__INDI_LSB) & RDMA_REGION_13__INDI_MASK)
#define RDMA_REGION_13__NEXT_MSB 0
#define RDMA_REGION_13__NEXT_LSB 0
#define RDMA_REGION_13__NEXT_MASK 0x00000001
#define RDMA_REGION_13__NEXT_GET(x) (((x) & RDMA_REGION_13__NEXT_MASK) >> RDMA_REGION_13__NEXT_LSB)
#define RDMA_REGION_13__NEXT_SET(x) (((x) << RDMA_REGION_13__NEXT_LSB) & RDMA_REGION_13__NEXT_MASK)
#define RDMA_REGION_14__ADDRESS 0x00000058
#define RDMA_REGION_14__OFFSET 0x00000058
#define RDMA_REGION_14__ADDR_MSB 31
#define RDMA_REGION_14__ADDR_LSB 13
#define RDMA_REGION_14__ADDR_MASK 0xffffe000
#define RDMA_REGION_14__ADDR_GET(x) (((x) & RDMA_REGION_14__ADDR_MASK) >> RDMA_REGION_14__ADDR_LSB)
#define RDMA_REGION_14__ADDR_SET(x) (((x) << RDMA_REGION_14__ADDR_LSB) & RDMA_REGION_14__ADDR_MASK)
#define RDMA_REGION_14__LENGTH_MSB 12
#define RDMA_REGION_14__LENGTH_LSB 2
#define RDMA_REGION_14__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_14__LENGTH_GET(x) (((x) & RDMA_REGION_14__LENGTH_MASK) >> RDMA_REGION_14__LENGTH_LSB)
#define RDMA_REGION_14__LENGTH_SET(x) (((x) << RDMA_REGION_14__LENGTH_LSB) & RDMA_REGION_14__LENGTH_MASK)
#define RDMA_REGION_14__INDI_MSB 1
#define RDMA_REGION_14__INDI_LSB 1
#define RDMA_REGION_14__INDI_MASK 0x00000002
#define RDMA_REGION_14__INDI_GET(x) (((x) & RDMA_REGION_14__INDI_MASK) >> RDMA_REGION_14__INDI_LSB)
#define RDMA_REGION_14__INDI_SET(x) (((x) << RDMA_REGION_14__INDI_LSB) & RDMA_REGION_14__INDI_MASK)
#define RDMA_REGION_14__NEXT_MSB 0
#define RDMA_REGION_14__NEXT_LSB 0
#define RDMA_REGION_14__NEXT_MASK 0x00000001
#define RDMA_REGION_14__NEXT_GET(x) (((x) & RDMA_REGION_14__NEXT_MASK) >> RDMA_REGION_14__NEXT_LSB)
#define RDMA_REGION_14__NEXT_SET(x) (((x) << RDMA_REGION_14__NEXT_LSB) & RDMA_REGION_14__NEXT_MASK)
#define RDMA_REGION_15__ADDRESS 0x0000005c
#define RDMA_REGION_15__OFFSET 0x0000005c
#define RDMA_REGION_15__ADDR_MSB 31
#define RDMA_REGION_15__ADDR_LSB 13
#define RDMA_REGION_15__ADDR_MASK 0xffffe000
#define RDMA_REGION_15__ADDR_GET(x) (((x) & RDMA_REGION_15__ADDR_MASK) >> RDMA_REGION_15__ADDR_LSB)
#define RDMA_REGION_15__ADDR_SET(x) (((x) << RDMA_REGION_15__ADDR_LSB) & RDMA_REGION_15__ADDR_MASK)
#define RDMA_REGION_15__LENGTH_MSB 12
#define RDMA_REGION_15__LENGTH_LSB 2
#define RDMA_REGION_15__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_15__LENGTH_GET(x) (((x) & RDMA_REGION_15__LENGTH_MASK) >> RDMA_REGION_15__LENGTH_LSB)
#define RDMA_REGION_15__LENGTH_SET(x) (((x) << RDMA_REGION_15__LENGTH_LSB) & RDMA_REGION_15__LENGTH_MASK)
#define RDMA_REGION_15__INDI_MSB 1
#define RDMA_REGION_15__INDI_LSB 1
#define RDMA_REGION_15__INDI_MASK 0x00000002
#define RDMA_REGION_15__INDI_GET(x) (((x) & RDMA_REGION_15__INDI_MASK) >> RDMA_REGION_15__INDI_LSB)
#define RDMA_REGION_15__INDI_SET(x) (((x) << RDMA_REGION_15__INDI_LSB) & RDMA_REGION_15__INDI_MASK)
#define RDMA_REGION_15__NEXT_MSB 0
#define RDMA_REGION_15__NEXT_LSB 0
#define RDMA_REGION_15__NEXT_MASK 0x00000001
#define RDMA_REGION_15__NEXT_GET(x) (((x) & RDMA_REGION_15__NEXT_MASK) >> RDMA_REGION_15__NEXT_LSB)
#define RDMA_REGION_15__NEXT_SET(x) (((x) << RDMA_REGION_15__NEXT_LSB) & RDMA_REGION_15__NEXT_MASK)
#define DMA_STATUS_ADDRESS 0x00000060
#define DMA_STATUS_OFFSET 0x00000060
#define DMA_STATUS_ERROR_CODE_MSB 14
#define DMA_STATUS_ERROR_CODE_LSB 4
#define DMA_STATUS_ERROR_CODE_MASK 0x00007ff0
#define DMA_STATUS_ERROR_CODE_GET(x) (((x) & DMA_STATUS_ERROR_CODE_MASK) >> DMA_STATUS_ERROR_CODE_LSB)
#define DMA_STATUS_ERROR_CODE_SET(x) (((x) << DMA_STATUS_ERROR_CODE_LSB) & DMA_STATUS_ERROR_CODE_MASK)
#define DMA_STATUS_ERROR_MSB 3
#define DMA_STATUS_ERROR_LSB 3
#define DMA_STATUS_ERROR_MASK 0x00000008
#define DMA_STATUS_ERROR_GET(x) (((x) & DMA_STATUS_ERROR_MASK) >> DMA_STATUS_ERROR_LSB)
#define DMA_STATUS_ERROR_SET(x) (((x) << DMA_STATUS_ERROR_LSB) & DMA_STATUS_ERROR_MASK)
#define DMA_STATUS_DONE_MSB 2
#define DMA_STATUS_DONE_LSB 2
#define DMA_STATUS_DONE_MASK 0x00000004
#define DMA_STATUS_DONE_GET(x) (((x) & DMA_STATUS_DONE_MASK) >> DMA_STATUS_DONE_LSB)
#define DMA_STATUS_DONE_SET(x) (((x) << DMA_STATUS_DONE_LSB) & DMA_STATUS_DONE_MASK)
#define DMA_STATUS_STOPPED_MSB 1
#define DMA_STATUS_STOPPED_LSB 1
#define DMA_STATUS_STOPPED_MASK 0x00000002
#define DMA_STATUS_STOPPED_GET(x) (((x) & DMA_STATUS_STOPPED_MASK) >> DMA_STATUS_STOPPED_LSB)
#define DMA_STATUS_STOPPED_SET(x) (((x) << DMA_STATUS_STOPPED_LSB) & DMA_STATUS_STOPPED_MASK)
#define DMA_STATUS_RUNNING_MSB 0
#define DMA_STATUS_RUNNING_LSB 0
#define DMA_STATUS_RUNNING_MASK 0x00000001
#define DMA_STATUS_RUNNING_GET(x) (((x) & DMA_STATUS_RUNNING_MASK) >> DMA_STATUS_RUNNING_LSB)
#define DMA_STATUS_RUNNING_SET(x) (((x) << DMA_STATUS_RUNNING_LSB) & DMA_STATUS_RUNNING_MASK)
#define DMA_INT_EN_ADDRESS 0x00000064
#define DMA_INT_EN_OFFSET 0x00000064
#define DMA_INT_EN_ERROR_ENA_MSB 3
#define DMA_INT_EN_ERROR_ENA_LSB 3
#define DMA_INT_EN_ERROR_ENA_MASK 0x00000008
#define DMA_INT_EN_ERROR_ENA_GET(x) (((x) & DMA_INT_EN_ERROR_ENA_MASK) >> DMA_INT_EN_ERROR_ENA_LSB)
#define DMA_INT_EN_ERROR_ENA_SET(x) (((x) << DMA_INT_EN_ERROR_ENA_LSB) & DMA_INT_EN_ERROR_ENA_MASK)
#define DMA_INT_EN_DONE_ENA_MSB 2
#define DMA_INT_EN_DONE_ENA_LSB 2
#define DMA_INT_EN_DONE_ENA_MASK 0x00000004
#define DMA_INT_EN_DONE_ENA_GET(x) (((x) & DMA_INT_EN_DONE_ENA_MASK) >> DMA_INT_EN_DONE_ENA_LSB)
#define DMA_INT_EN_DONE_ENA_SET(x) (((x) << DMA_INT_EN_DONE_ENA_LSB) & DMA_INT_EN_DONE_ENA_MASK)
#define DMA_INT_EN_STOPPED_ENA_MSB 1
#define DMA_INT_EN_STOPPED_ENA_LSB 1
#define DMA_INT_EN_STOPPED_ENA_MASK 0x00000002
#define DMA_INT_EN_STOPPED_ENA_GET(x) (((x) & DMA_INT_EN_STOPPED_ENA_MASK) >> DMA_INT_EN_STOPPED_ENA_LSB)
#define DMA_INT_EN_STOPPED_ENA_SET(x) (((x) << DMA_INT_EN_STOPPED_ENA_LSB) & DMA_INT_EN_STOPPED_ENA_MASK)
#ifndef __ASSEMBLER__
typedef struct rdma_reg_reg_s {
volatile unsigned int dma_config;
volatile unsigned int dma_control;
volatile unsigned int dma_src;
volatile unsigned int dma_dest;
volatile unsigned int dma_length;
volatile unsigned int vmc_base;
volatile unsigned int indirect_reg;
volatile unsigned int indirect_return;
volatile unsigned int rdma_region_0_;
volatile unsigned int rdma_region_1_;
volatile unsigned int rdma_region_2_;
volatile unsigned int rdma_region_3_;
volatile unsigned int rdma_region_4_;
volatile unsigned int rdma_region_5_;
volatile unsigned int rdma_region_6_;
volatile unsigned int rdma_region_7_;
volatile unsigned int rdma_region_8_;
volatile unsigned int rdma_region_9_;
volatile unsigned int rdma_region_10_;
volatile unsigned int rdma_region_11_;
volatile unsigned int rdma_region_12_;
volatile unsigned int rdma_region_13_;
volatile unsigned int rdma_region_14_;
volatile unsigned int rdma_region_15_;
volatile unsigned int dma_status;
volatile unsigned int dma_int_en;
} rdma_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _RDMA_REG_H_ */
drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_reg.h deleted 100644 → 0
View file @ 053db306
// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#include "umbox_wlan_reg.h"
drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_wlan_reg.h deleted 100644 → 0
View file @ 053db306
// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifndef _UMBOX_WLAN_REG_REG_H_
#define _UMBOX_WLAN_REG_REG_H_
#define UMBOX_FIFO_ADDRESS 0x00000000
#define UMBOX_FIFO_OFFSET 0x00000000
#define UMBOX_FIFO_DATA_MSB 8
#define UMBOX_FIFO_DATA_LSB 0
#define UMBOX_FIFO_DATA_MASK 0x000001ff
#define UMBOX_FIFO_DATA_GET(x) (((x) & UMBOX_FIFO_DATA_MASK) >> UMBOX_FIFO_DATA_LSB)
#define UMBOX_FIFO_DATA_SET(x) (((x) << UMBOX_FIFO_DATA_LSB) & UMBOX_FIFO_DATA_MASK)
#define UMBOX_FIFO_STATUS_ADDRESS 0x00000008
#define UMBOX_FIFO_STATUS_OFFSET 0x00000008
#define UMBOX_FIFO_STATUS_TX_EMPTY_MSB 3
#define UMBOX_FIFO_STATUS_TX_EMPTY_LSB 3
#define UMBOX_FIFO_STATUS_TX_EMPTY_MASK 0x00000008
#define UMBOX_FIFO_STATUS_TX_EMPTY_GET(x) (((x) & UMBOX_FIFO_STATUS_TX_EMPTY_MASK) >> UMBOX_FIFO_STATUS_TX_EMPTY_LSB)
#define UMBOX_FIFO_STATUS_TX_EMPTY_SET(x) (((x) << UMBOX_FIFO_STATUS_TX_EMPTY_LSB) & UMBOX_FIFO_STATUS_TX_EMPTY_MASK)
#define UMBOX_FIFO_STATUS_TX_FULL_MSB 2
#define UMBOX_FIFO_STATUS_TX_FULL_LSB 2
#define UMBOX_FIFO_STATUS_TX_FULL_MASK 0x00000004
#define UMBOX_FIFO_STATUS_TX_FULL_GET(x) (((x) & UMBOX_FIFO_STATUS_TX_FULL_MASK) >> UMBOX_FIFO_STATUS_TX_FULL_LSB)
#define UMBOX_FIFO_STATUS_TX_FULL_SET(x) (((x) << UMBOX_FIFO_STATUS_TX_FULL_LSB) & UMBOX_FIFO_STATUS_TX_FULL_MASK)
#define UMBOX_FIFO_STATUS_RX_EMPTY_MSB 1
#define UMBOX_FIFO_STATUS_RX_EMPTY_LSB 1
#define UMBOX_FIFO_STATUS_RX_EMPTY_MASK 0x00000002
#define UMBOX_FIFO_STATUS_RX_EMPTY_GET(x) (((x) & UMBOX_FIFO_STATUS_RX_EMPTY_MASK) >> UMBOX_FIFO_STATUS_RX_EMPTY_LSB)
#define UMBOX_FIFO_STATUS_RX_EMPTY_SET(x) (((x) << UMBOX_FIFO_STATUS_RX_EMPTY_LSB) & UMBOX_FIFO_STATUS_RX_EMPTY_MASK)
#define UMBOX_FIFO_STATUS_RX_FULL_MSB 0
#define UMBOX_FIFO_STATUS_RX_FULL_LSB 0
#define UMBOX_FIFO_STATUS_RX_FULL_MASK 0x00000001
#define UMBOX_FIFO_STATUS_RX_FULL_GET(x) (((x) & UMBOX_FIFO_STATUS_RX_FULL_MASK) >> UMBOX_FIFO_STATUS_RX_FULL_LSB)
#define UMBOX_FIFO_STATUS_RX_FULL_SET(x) (((x) << UMBOX_FIFO_STATUS_RX_FULL_LSB) & UMBOX_FIFO_STATUS_RX_FULL_MASK)
#define UMBOX_DMA_POLICY_ADDRESS 0x0000000c
#define UMBOX_DMA_POLICY_OFFSET 0x0000000c
#define UMBOX_DMA_POLICY_TX_QUANTUM_MSB 3
#define UMBOX_DMA_POLICY_TX_QUANTUM_LSB 3
#define UMBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008
#define UMBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & UMBOX_DMA_POLICY_TX_QUANTUM_MASK) >> UMBOX_DMA_POLICY_TX_QUANTUM_LSB)
#define UMBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << UMBOX_DMA_POLICY_TX_QUANTUM_LSB) & UMBOX_DMA_POLICY_TX_QUANTUM_MASK)
#define UMBOX_DMA_POLICY_TX_ORDER_MSB 2
#define UMBOX_DMA_POLICY_TX_ORDER_LSB 2
#define UMBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004
#define UMBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & UMBOX_DMA_POLICY_TX_ORDER_MASK) >> UMBOX_DMA_POLICY_TX_ORDER_LSB)
#define UMBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << UMBOX_DMA_POLICY_TX_ORDER_LSB) & UMBOX_DMA_POLICY_TX_ORDER_MASK)
#define UMBOX_DMA_POLICY_RX_QUANTUM_MSB 1
#define UMBOX_DMA_POLICY_RX_QUANTUM_LSB 1
#define UMBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002
#define UMBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & UMBOX_DMA_POLICY_RX_QUANTUM_MASK) >> UMBOX_DMA_POLICY_RX_QUANTUM_LSB)
#define UMBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << UMBOX_DMA_POLICY_RX_QUANTUM_LSB) & UMBOX_DMA_POLICY_RX_QUANTUM_MASK)
#define UMBOX_DMA_POLICY_RX_ORDER_MSB 0
#define UMBOX_DMA_POLICY_RX_ORDER_LSB 0
#define UMBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001
#define UMBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & UMBOX_DMA_POLICY_RX_ORDER_MASK) >> UMBOX_DMA_POLICY_RX_ORDER_LSB)
#define UMBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << UMBOX_DMA_POLICY_RX_ORDER_LSB) & UMBOX_DMA_POLICY_RX_ORDER_MASK)
#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000010
#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000010
#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define UMBOX0_DMA_RX_CONTROL_ADDRESS 0x00000014
#define UMBOX0_DMA_RX_CONTROL_OFFSET 0x00000014
#define UMBOX0_DMA_RX_CONTROL_RESUME_MSB 2
#define UMBOX0_DMA_RX_CONTROL_RESUME_LSB 2
#define UMBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004
#define UMBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_RESUME_MASK) >> UMBOX0_DMA_RX_CONTROL_RESUME_LSB)
#define UMBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_RESUME_LSB) & UMBOX0_DMA_RX_CONTROL_RESUME_MASK)
#define UMBOX0_DMA_RX_CONTROL_START_MSB 1
#define UMBOX0_DMA_RX_CONTROL_START_LSB 1
#define UMBOX0_DMA_RX_CONTROL_START_MASK 0x00000002
#define UMBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_START_MASK) >> UMBOX0_DMA_RX_CONTROL_START_LSB)
#define UMBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_START_LSB) & UMBOX0_DMA_RX_CONTROL_START_MASK)
#define UMBOX0_DMA_RX_CONTROL_STOP_MSB 0
#define UMBOX0_DMA_RX_CONTROL_STOP_LSB 0
#define UMBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001
#define UMBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_STOP_MASK) >> UMBOX0_DMA_RX_CONTROL_STOP_LSB)
#define UMBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_STOP_LSB) & UMBOX0_DMA_RX_CONTROL_STOP_MASK)
#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000018
#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000018
#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define UMBOX0_DMA_TX_CONTROL_ADDRESS 0x0000001c
#define UMBOX0_DMA_TX_CONTROL_OFFSET 0x0000001c
#define UMBOX0_DMA_TX_CONTROL_RESUME_MSB 2
#define UMBOX0_DMA_TX_CONTROL_RESUME_LSB 2
#define UMBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004
#define UMBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_RESUME_MASK) >> UMBOX0_DMA_TX_CONTROL_RESUME_LSB)
#define UMBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_RESUME_LSB) & UMBOX0_DMA_TX_CONTROL_RESUME_MASK)
#define UMBOX0_DMA_TX_CONTROL_START_MSB 1
#define UMBOX0_DMA_TX_CONTROL_START_LSB 1
#define UMBOX0_DMA_TX_CONTROL_START_MASK 0x00000002
#define UMBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_START_MASK) >> UMBOX0_DMA_TX_CONTROL_START_LSB)
#define UMBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_START_LSB) & UMBOX0_DMA_TX_CONTROL_START_MASK)
#define UMBOX0_DMA_TX_CONTROL_STOP_MSB 0
#define UMBOX0_DMA_TX_CONTROL_STOP_LSB 0
#define UMBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001
#define UMBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_STOP_MASK) >> UMBOX0_DMA_TX_CONTROL_STOP_LSB)
#define UMBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_STOP_LSB) & UMBOX0_DMA_TX_CONTROL_STOP_MASK)
#define UMBOX_FIFO_TIMEOUT_ADDRESS 0x00000020
#define UMBOX_FIFO_TIMEOUT_OFFSET 0x00000020
#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_MSB 8
#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB 8
#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000100
#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK) >> UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB)
#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB) & UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK)
#define UMBOX_FIFO_TIMEOUT_VALUE_MSB 7
#define UMBOX_FIFO_TIMEOUT_VALUE_LSB 0
#define UMBOX_FIFO_TIMEOUT_VALUE_MASK 0x000000ff
#define UMBOX_FIFO_TIMEOUT_VALUE_GET(x) (((x) & UMBOX_FIFO_TIMEOUT_VALUE_MASK) >> UMBOX_FIFO_TIMEOUT_VALUE_LSB)
#define UMBOX_FIFO_TIMEOUT_VALUE_SET(x) (((x) << UMBOX_FIFO_TIMEOUT_VALUE_LSB) & UMBOX_FIFO_TIMEOUT_VALUE_MASK)
#define UMBOX_INT_STATUS_ADDRESS 0x00000024
#define UMBOX_INT_STATUS_OFFSET 0x00000024
#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MSB 9
#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB 9
#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK 0x00000200
#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB)
#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK)
#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MSB 8
#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB 8
#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK 0x00000100
#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB)
#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK)
#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 7
#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 7
#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0x00000080
#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 6
#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 6
#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x00000040
#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 5
#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 5
#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00000020
#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_MSB 4
#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB 4
#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK 0x00000010
#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_GET(x) (((x) & UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK) >> UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB)
#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_SET(x) (((x) << UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB) & UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK)
#define UMBOX_INT_STATUS_TX_OVERFLOW_MSB 3
#define UMBOX_INT_STATUS_TX_OVERFLOW_LSB 3
#define UMBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00000008
#define UMBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_TX_OVERFLOW_MASK) >> UMBOX_INT_STATUS_TX_OVERFLOW_LSB)
#define UMBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_TX_OVERFLOW_LSB) & UMBOX_INT_STATUS_TX_OVERFLOW_MASK)
#define UMBOX_INT_STATUS_RX_UNDERFLOW_MSB 2
#define UMBOX_INT_STATUS_RX_UNDERFLOW_LSB 2
#define UMBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00000004
#define UMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> UMBOX_INT_STATUS_RX_UNDERFLOW_LSB)
#define UMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_RX_UNDERFLOW_LSB) & UMBOX_INT_STATUS_RX_UNDERFLOW_MASK)
#define UMBOX_INT_STATUS_TX_NOT_EMPTY_MSB 1
#define UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB 1
#define UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x00000002
#define UMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
#define UMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
#define UMBOX_INT_STATUS_RX_NOT_FULL_MSB 0
#define UMBOX_INT_STATUS_RX_NOT_FULL_LSB 0
#define UMBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000001
#define UMBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & UMBOX_INT_STATUS_RX_NOT_FULL_MASK) >> UMBOX_INT_STATUS_RX_NOT_FULL_LSB)
#define UMBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << UMBOX_INT_STATUS_RX_NOT_FULL_LSB) & UMBOX_INT_STATUS_RX_NOT_FULL_MASK)
#define UMBOX_INT_ENABLE_ADDRESS 0x00000028
#define UMBOX_INT_ENABLE_OFFSET 0x00000028
#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MSB 9
#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB 9
#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK 0x00000200
#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB)
#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK)
#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MSB 8
#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB 8
#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK 0x00000100
#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB)
#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK)
#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 7
#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 7
#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0x00000080
#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 6
#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 6
#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x00000040
#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 5
#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 5
#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00000020
#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MSB 4
#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB 4
#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK 0x00000010
#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK) >> UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB)
#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB) & UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK)
#define UMBOX_INT_ENABLE_TX_OVERFLOW_MSB 3
#define UMBOX_INT_ENABLE_TX_OVERFLOW_LSB 3
#define UMBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00000008
#define UMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> UMBOX_INT_ENABLE_TX_OVERFLOW_LSB)
#define UMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_TX_OVERFLOW_LSB) & UMBOX_INT_ENABLE_TX_OVERFLOW_MASK)
#define UMBOX_INT_ENABLE_RX_UNDERFLOW_MSB 2
#define UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB 2
#define UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00000004
#define UMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
#define UMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 1
#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 1
#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x00000002
#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
#define UMBOX_INT_ENABLE_RX_NOT_FULL_MSB 0
#define UMBOX_INT_ENABLE_RX_NOT_FULL_LSB 0
#define UMBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000001
#define UMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & UMBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> UMBOX_INT_ENABLE_RX_NOT_FULL_LSB)
#define UMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << UMBOX_INT_ENABLE_RX_NOT_FULL_LSB) & UMBOX_INT_ENABLE_RX_NOT_FULL_MASK)
#define UMBOX_DEBUG_ADDRESS 0x0000002c
#define UMBOX_DEBUG_OFFSET 0x0000002c
#define UMBOX_DEBUG_SEL_MSB 2
#define UMBOX_DEBUG_SEL_LSB 0
#define UMBOX_DEBUG_SEL_MASK 0x00000007
#define UMBOX_DEBUG_SEL_GET(x) (((x) & UMBOX_DEBUG_SEL_MASK) >> UMBOX_DEBUG_SEL_LSB)
#define UMBOX_DEBUG_SEL_SET(x) (((x) << UMBOX_DEBUG_SEL_LSB) & UMBOX_DEBUG_SEL_MASK)
#define UMBOX_FIFO_RESET_ADDRESS 0x00000030
#define UMBOX_FIFO_RESET_OFFSET 0x00000030
#define UMBOX_FIFO_RESET_INIT_MSB 0
#define UMBOX_FIFO_RESET_INIT_LSB 0
#define UMBOX_FIFO_RESET_INIT_MASK 0x00000001
#define UMBOX_FIFO_RESET_INIT_GET(x) (((x) & UMBOX_FIFO_RESET_INIT_MASK) >> UMBOX_FIFO_RESET_INIT_LSB)
#define UMBOX_FIFO_RESET_INIT_SET(x) (((x) << UMBOX_FIFO_RESET_INIT_LSB) & UMBOX_FIFO_RESET_INIT_MASK)
#define UMBOX_HCI_FRAMER_ADDRESS 0x00000034
#define UMBOX_HCI_FRAMER_OFFSET 0x00000034
#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_MSB 6
#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB 6
#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK 0x00000040
#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_GET(x) (((x) & UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK) >> UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB)
#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_SET(x) (((x) << UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB) & UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK)
#define UMBOX_HCI_FRAMER_ENABLE_MSB 5
#define UMBOX_HCI_FRAMER_ENABLE_LSB 5
#define UMBOX_HCI_FRAMER_ENABLE_MASK 0x00000020
#define UMBOX_HCI_FRAMER_ENABLE_GET(x) (((x) & UMBOX_HCI_FRAMER_ENABLE_MASK) >> UMBOX_HCI_FRAMER_ENABLE_LSB)
#define UMBOX_HCI_FRAMER_ENABLE_SET(x) (((x) << UMBOX_HCI_FRAMER_ENABLE_LSB) & UMBOX_HCI_FRAMER_ENABLE_MASK)
#define UMBOX_HCI_FRAMER_SYNC_ERROR_MSB 4
#define UMBOX_HCI_FRAMER_SYNC_ERROR_LSB 4
#define UMBOX_HCI_FRAMER_SYNC_ERROR_MASK 0x00000010
#define UMBOX_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & UMBOX_HCI_FRAMER_SYNC_ERROR_MASK) >> UMBOX_HCI_FRAMER_SYNC_ERROR_LSB)
#define UMBOX_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << UMBOX_HCI_FRAMER_SYNC_ERROR_LSB) & UMBOX_HCI_FRAMER_SYNC_ERROR_MASK)
#define UMBOX_HCI_FRAMER_UNDERFLOW_MSB 3
#define UMBOX_HCI_FRAMER_UNDERFLOW_LSB 3
#define UMBOX_HCI_FRAMER_UNDERFLOW_MASK 0x00000008
#define UMBOX_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_HCI_FRAMER_UNDERFLOW_LSB)
#define UMBOX_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_HCI_FRAMER_UNDERFLOW_MASK)
#define UMBOX_HCI_FRAMER_OVERFLOW_MSB 2
#define UMBOX_HCI_FRAMER_OVERFLOW_LSB 2
#define UMBOX_HCI_FRAMER_OVERFLOW_MASK 0x00000004
#define UMBOX_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_HCI_FRAMER_OVERFLOW_LSB)
#define UMBOX_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_HCI_FRAMER_OVERFLOW_MASK)
#define UMBOX_HCI_FRAMER_CONFIG_MODE_MSB 1
#define UMBOX_HCI_FRAMER_CONFIG_MODE_LSB 0
#define UMBOX_HCI_FRAMER_CONFIG_MODE_MASK 0x00000003
#define UMBOX_HCI_FRAMER_CONFIG_MODE_GET(x) (((x) & UMBOX_HCI_FRAMER_CONFIG_MODE_MASK) >> UMBOX_HCI_FRAMER_CONFIG_MODE_LSB)
#define UMBOX_HCI_FRAMER_CONFIG_MODE_SET(x) (((x) << UMBOX_HCI_FRAMER_CONFIG_MODE_LSB) & UMBOX_HCI_FRAMER_CONFIG_MODE_MASK)
#ifndef __ASSEMBLER__
typedef struct umbox_wlan_reg_reg_s {
volatile unsigned int umbox_fifo[2];
volatile unsigned int umbox_fifo_status;
volatile unsigned int umbox_dma_policy;
volatile unsigned int umbox0_dma_rx_descriptor_base;
volatile unsigned int umbox0_dma_rx_control;
volatile unsigned int umbox0_dma_tx_descriptor_base;
volatile unsigned int umbox0_dma_tx_control;
volatile unsigned int umbox_fifo_timeout;
volatile unsigned int umbox_int_status;
volatile unsigned int umbox_int_enable;
volatile unsigned int umbox_debug;
volatile unsigned int umbox_fifo_reset;
volatile unsigned int umbox_hci_framer;
} umbox_wlan_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _UMBOX_WLAN_REG_H_ */
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