Commit 30edd98b authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'mvebu-dt64-4.13-2' of git://git.infradead.org/linux-mvebu into next/dt64

Pull "mvebu dt64 for 4.13 (part 2)" from Gregory CLEMENT:

- use new clock binding for Armada 7K/8K
- add pinctrl on Armada 7K/8K
- add GPIO on Armada 7K/8K
- switch from GIC to ICU on CP110 (Armada 7K/8K)
- enable the mdio node on the mcbin (Armada 8K based board)

* tag 'mvebu-dt64-4.13-2' of git://git.infradead.org/linux-mvebu:
  arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K
  arm64: dts: marvell: add gpio support for Armada 7K/8K
  arm64: dts: marvell: add pinctrl support for Armada 7K/8K
  arm64: dts: marvell: use new binding for the system controller on cp110
  arm64: dts: marvell: remove *-clock-output-names on cp110
  arm64: dts: marvell: use new bindings for xor clocks on ap806
  arm64: dts: marvell: mcbin: enable the mdio node
parents efd8b0dd 6ef84a82
......@@ -46,7 +46,7 @@
*/
#include "armada-ap806-dual.dtsi"
#include "armada-cp110-master.dtsi"
#include "armada-70x0.dtsi"
/ {
model = "Marvell Armada 7020";
......
......@@ -46,7 +46,7 @@
*/
#include "armada-ap806-quad.dtsi"
#include "armada-cp110-master.dtsi"
#include "armada-70x0.dtsi"
/ {
model = "Marvell Armada 7040";
......
/*
* Copyright (C) 2017 Marvell Technology Group Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Device Tree file for the Armada 70x0 SoC
*/
#include "armada-cp110-master.dtsi"
/ {
aliases {
gpio1 = &cpm_gpio1;
gpio2 = &cpm_gpio2;
};
};
&cpm_gpio1 {
status = "okay";
};
&cpm_gpio2 {
status = "okay";
};
&cpm_syscon0 {
cpm_pinctrl: pinctrl {
compatible = "marvell,armada-7k-pinctrl";
};
};
......@@ -46,8 +46,7 @@
*/
#include "armada-ap806-dual.dtsi"
#include "armada-cp110-master.dtsi"
#include "armada-cp110-slave.dtsi"
#include "armada-80x0.dtsi"
/ {
model = "Marvell Armada 8020";
......
......@@ -116,6 +116,8 @@ &cpm_i2c0 {
};
&cpm_mdio {
status = "okay";
ge_phy: ethernet-phy@0 {
reg = <0>;
};
......
......@@ -46,8 +46,7 @@
*/
#include "armada-ap806-quad.dtsi"
#include "armada-cp110-master.dtsi"
#include "armada-cp110-slave.dtsi"
#include "armada-80x0.dtsi"
/ {
model = "Marvell Armada 8040";
......
/*
* Copyright (C) 2017 Marvell Technology Group Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Device Tree file for the Armada 80x0 SoC family
*/
#include "armada-cp110-master.dtsi"
#include "armada-cp110-slave.dtsi"
/ {
aliases {
gpio1 = &cps_gpio1;
gpio2 = &cpm_gpio2;
};
};
/* The 80x0 has two CP blocks, but uses only one block from each. */
&cps_gpio1 {
status = "okay";
};
&cpm_gpio2 {
status = "okay";
};
&cpm_syscon0 {
cpm_pinctrl: pinctrl {
compatible = "marvell,armada-8k-cpm-pinctrl";
};
};
&cps_syscon0 {
cps_pinctrl: pinctrl {
compatible = "marvell,armada-8k-cps-pinctrl";
};
};
......@@ -57,6 +57,7 @@ / {
aliases {
serial0 = &uart0;
serial1 = &uart1;
gpio0 = &ap_gpio;
};
psci {
......@@ -146,6 +147,13 @@ odmi: odmi@300000 {
marvell,spi-base = <128>, <136>, <144>, <152>;
};
gicp: gicp@3f0040 {
compatible = "marvell,ap806-gicp";
reg = <0x3f0040 0x10>;
marvell,spi-ranges = <64 64>, <288 64>;
msi-controller;
};
pic: interrupt-controller@3f0100 {
compatible = "marvell,armada-8k-pic";
reg = <0x3f0100 0x10>;
......@@ -159,7 +167,7 @@ xor@400000 {
reg = <0x400000 0x1000>,
<0x410000 0x1000>;
msi-parent = <&gic_v2m0>;
clocks = <&ap_syscon 3>;
clocks = <&ap_clk 3>;
dma-coherent;
};
......@@ -168,7 +176,7 @@ xor@420000 {
reg = <0x420000 0x1000>,
<0x430000 0x1000>;
msi-parent = <&gic_v2m0>;
clocks = <&ap_syscon 3>;
clocks = <&ap_clk 3>;
dma-coherent;
};
......@@ -177,7 +185,7 @@ xor@440000 {
reg = <0x440000 0x1000>,
<0x450000 0x1000>;
msi-parent = <&gic_v2m0>;
clocks = <&ap_syscon 3>;
clocks = <&ap_clk 3>;
dma-coherent;
};
......@@ -186,7 +194,7 @@ xor@460000 {
reg = <0x460000 0x1000>,
<0x470000 0x1000>;
msi-parent = <&gic_v2m0>;
clocks = <&ap_syscon 3>;
clocks = <&ap_clk 3>;
dma-coherent;
};
......@@ -252,6 +260,19 @@ ap_clk: clock {
compatible = "marvell,ap806-clock";
#clock-cells = <1>;
};
ap_pinctrl: pinctrl {
compatible = "marvell,ap806-pinctrl";
};
ap_gpio: gpio {
compatible = "marvell,armada-8k-gpio";
offset = <0x1040>;
ngpios = <19>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&ap_pinctrl 0 0 19>;
};
};
};
};
......
......@@ -44,45 +44,46 @@
* Device Tree file for Marvell Armada CP110 Master.
*/
#define ICU_GRP_NSR 0x0
/ {
cp110-master {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
interrupt-parent = <&cpm_icu>;
ranges;
config-space@f2000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges = <0x0 0x0 0xf2000000 0x2000000>;
cpm_ethernet: ethernet@0 {
compatible = "marvell,armada-7k-pp22";
reg = <0x0 0x100000>, <0x129000 0xb000>;
clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>;
clocks = <&cpm_clk 1 3>, <&cpm_clk 1 9>, <&cpm_clk 1 5>;
clock-names = "pp_clk", "gop_clk", "mg_clk";
status = "disabled";
dma-coherent;
cpm_eth0: eth0 {
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>;
port-id = <0>;
gop-port-id = <0>;
status = "disabled";
};
cpm_eth1: eth1 {
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>;
port-id = <1>;
gop-port-id = <2>;
status = "disabled";
};
cpm_eth2: eth2 {
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>;
port-id = <2>;
gop-port-id = <3>;
status = "disabled";
......@@ -94,7 +95,7 @@ cpm_mdio: mdio@12a200 {
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0x12a200 0x10>;
clocks = <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>;
clocks = <&cpm_clk 1 9>, <&cpm_clk 1 5>;
status = "disabled";
};
......@@ -106,39 +107,58 @@ cpm_xmdio: mdio@12a600 {
status = "disabled";
};
cpm_icu: interrupt-controller@1e0000 {
compatible = "marvell,cp110-icu";
reg = <0x1e0000 0x10>;
#interrupt-cells = <3>;
interrupt-controller;
msi-parent = <&gicp>;
};
cpm_syscon0: system-controller@440000 {
compatible = "marvell,cp110-system-controller0",
"syscon";
compatible = "syscon", "simple-mfd";
reg = <0x440000 0x1000>;
cpm_clk: clock {
compatible = "marvell,cp110-clock";
#clock-cells = <2>;
core-clock-output-names =
"cpm-apll", "cpm-ppv2-core", "cpm-eip",
"cpm-core", "cpm-nand-core";
gate-clock-output-names =
"cpm-audio", "cpm-communit", "cpm-nand",
"cpm-ppv2", "cpm-sdio", "cpm-mg-domain",
"cpm-mg-core", "cpm-xor1", "cpm-xor0",
"cpm-gop-dp", "none", "cpm-pcie_x10",
"cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor",
"cpm-sata", "cpm-sata-usb", "cpm-main",
"cpm-sd-mmc-gop", "none", "none",
"cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1",
"cpm-usb3dev", "cpm-eip150", "cpm-eip197";
};
cpm_gpio1: gpio@100 {
compatible = "marvell,armada-8k-gpio";
offset = <0x100>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&cpm_pinctrl 0 0 32>;
status = "disabled";
};
cpm_gpio2: gpio@140 {
compatible = "marvell,armada-8k-gpio";
offset = <0x140>;
ngpios = <31>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&cpm_pinctrl 0 32 31>;
status = "disabled";
};
};
cpm_rtc: rtc@284000 {
compatible = "marvell,armada-8k-rtc";
reg = <0x284000 0x20>, <0x284080 0x24>;
reg-names = "rtc", "rtc-soc";
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
};
cpm_sata0: sata@540000 {
compatible = "marvell,armada-8k-ahci",
"generic-ahci";
reg = <0x540000 0x30000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_syscon0 1 15>;
interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_clk 1 15>;
status = "disabled";
};
......@@ -147,8 +167,8 @@ cpm_usb3_0: usb3@500000 {
"generic-xhci";
reg = <0x500000 0x4000>;
dma-coherent;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_syscon0 1 22>;
interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_clk 1 22>;
status = "disabled";
};
......@@ -157,8 +177,8 @@ cpm_usb3_1: usb3@510000 {
"generic-xhci";
reg = <0x510000 0x4000>;
dma-coherent;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_syscon0 1 23>;
interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_clk 1 23>;
status = "disabled";
};
......@@ -168,7 +188,7 @@ cpm_xor0: xor@6a0000 {
<0x6b0000 0x1000>;
dma-coherent;
msi-parent = <&gic_v2m0>;
clocks = <&cpm_syscon0 1 8>;
clocks = <&cpm_clk 1 8>;
};
cpm_xor1: xor@6c0000 {
......@@ -177,7 +197,7 @@ cpm_xor1: xor@6c0000 {
<0x6d0000 0x1000>;
dma-coherent;
msi-parent = <&gic_v2m0>;
clocks = <&cpm_syscon0 1 7>;
clocks = <&cpm_clk 1 7>;
};
cpm_spi0: spi@700600 {
......@@ -186,7 +206,7 @@ cpm_spi0: spi@700600 {
#address-cells = <0x1>;
#size-cells = <0x0>;
cell-index = <1>;
clocks = <&cpm_syscon0 1 21>;
clocks = <&cpm_clk 1 21>;
status = "disabled";
};
......@@ -196,7 +216,7 @@ cpm_spi1: spi@700680 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <2>;
clocks = <&cpm_syscon0 1 21>;
clocks = <&cpm_clk 1 21>;
status = "disabled";
};
......@@ -205,8 +225,8 @@ cpm_i2c0: i2c@701000 {
reg = <0x701000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_syscon0 1 21>;
interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_clk 1 21>;
status = "disabled";
};
......@@ -215,25 +235,25 @@ cpm_i2c1: i2c@701100 {
reg = <0x701100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_syscon0 1 21>;
interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_clk 1 21>;
status = "disabled";
};
cpm_trng: trng@760000 {
compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
reg = <0x760000 0x7d>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_syscon0 1 25>;
interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_clk 1 25>;
status = "okay";
};
cpm_sdhci0: sdhci@780000 {
compatible = "marvell,armada-cp110-sdhci";
reg = <0x780000 0x300>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core";
clocks = <&cpm_syscon0 1 4>;
clocks = <&cpm_clk 1 4>;
dma-coherent;
status = "disabled";
};
......@@ -241,16 +261,16 @@ cpm_sdhci0: sdhci@780000 {
cpm_crypto: crypto@800000 {
compatible = "inside-secure,safexcel-eip197";
reg = <0x800000 0x200000>;
interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING
interrupts = <ICU_GRP_NSR 87 (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_LEVEL_HIGH)>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
<ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
clocks = <&cpm_syscon0 1 26>;
clocks = <&cpm_clk 1 26>;
dma-mask = <0xff 0xffffffff>;
};
};
......@@ -274,10 +294,10 @@ cpm_pcie0: pcie@f2600000 {
/* non-prefetchable memory */
0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cpm_syscon0 1 13>;
clocks = <&cpm_clk 1 13>;
status = "disabled";
};
......@@ -300,11 +320,11 @@ cpm_pcie1: pcie@f2620000 {
/* non-prefetchable memory */
0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cpm_syscon0 1 11>;
clocks = <&cpm_clk 1 11>;
status = "disabled";
};
......@@ -327,11 +347,11 @@ cpm_pcie2: pcie@f2640000 {
/* non-prefetchable memory */
0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cpm_syscon0 1 12>;
clocks = <&cpm_clk 1 12>;
status = "disabled";
};
};
......
......@@ -44,19 +44,20 @@
* Device Tree file for Marvell Armada CP110 Slave.
*/
#define ICU_GRP_NSR 0x0
/ {
cp110-slave {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
interrupt-parent = <&cps_icu>;
ranges;
config-space@f4000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges = <0x0 0x0 0xf4000000 0x2000000>;
cps_rtc: rtc@284000 {
......@@ -69,27 +70,27 @@ cps_rtc: rtc@284000 {
cps_ethernet: ethernet@0 {
compatible = "marvell,armada-7k-pp22";
reg = <0x0 0x100000>, <0x129000 0xb000>;
clocks = <&cps_syscon0 1 3>, <&cps_syscon0 1 9>, <&cps_syscon0 1 5>;
clocks = <&cps_clk 1 3>, <&cps_clk 1 9>, <&cps_clk 1 5>;
clock-names = "pp_clk", "gop_clk", "mg_clk";
status = "disabled";
dma-coherent;
cps_eth0: eth0 {
interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>;
port-id = <0>;
gop-port-id = <0>;
status = "disabled";
};
cps_eth1: eth1 {
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>;
port-id = <1>;
gop-port-id = <2>;
status = "disabled";
};
cps_eth2: eth2 {
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>;
port-id = <2>;
gop-port-id = <3>;
status = "disabled";
......@@ -101,7 +102,7 @@ cps_mdio: mdio@12a200 {
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0x12a200 0x10>;
clocks = <&cps_syscon0 1 9>, <&cps_syscon0 1 5>;
clocks = <&cps_clk 1 9>, <&cps_clk 1 5>;
status = "disabled";
};
......@@ -113,32 +114,52 @@ cps_xmdio: mdio@12a600 {
status = "disabled";
};
cps_icu: interrupt-controller@1e0000 {
compatible = "marvell,cp110-icu";
reg = <0x1e0000 0x10>;
#interrupt-cells = <3>;
interrupt-controller;
msi-parent = <&gicp>;
};
cps_syscon0: system-controller@440000 {
compatible = "marvell,cp110-system-controller0",
"syscon";
compatible = "syscon", "simple-mfd";
reg = <0x440000 0x1000>;
cps_clk: clock {
compatible = "marvell,cp110-clock";
#clock-cells = <2>;
core-clock-output-names =
"cps-apll", "cps-ppv2-core", "cps-eip",
"cps-core", "cps-nand-core";
gate-clock-output-names =
"cps-audio", "cps-communit", "cps-nand",
"cps-ppv2", "cps-sdio", "cps-mg-domain",
"cps-mg-core", "cps-xor1", "cps-xor0",
"cps-gop-dp", "none", "cps-pcie_x10",
"cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
"cps-sata", "cps-sata-usb", "cps-main",
"cps-sd-mmc-gop", "none", "none",
"cps-slow-io", "cps-usb3h0", "cps-usb3h1",
"cps-usb3dev", "cps-eip150", "cps-eip197";
};
cps_gpio1: gpio@100 {
compatible = "marvell,armada-8k-gpio";
offset = <0x100>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&cps_pinctrl 0 0 32>;
status = "disabled";
};
cps_gpio2: gpio@140 {
compatible = "marvell,armada-8k-gpio";
offset = <0x140>;
ngpios = <31>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&cps_pinctrl 0 32 31>;
status = "disabled";
};
};
cps_sata0: sata@540000 {
compatible = "marvell,armada-8k-ahci",
"generic-ahci";
reg = <0x540000 0x30000>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_syscon0 1 15>;
interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_clk 1 15>;
status = "disabled";
};
......@@ -147,8 +168,8 @@ cps_usb3_0: usb3@500000 {
"generic-xhci";
reg = <0x500000 0x4000>;
dma-coherent;
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_syscon0 1 22>;
interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_clk 1 22>;
status = "disabled";
};
......@@ -157,8 +178,8 @@ cps_usb3_1: usb3@510000 {
"generic-xhci";
reg = <0x510000 0x4000>;
dma-coherent;
interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_syscon0 1 23>;
interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_clk 1 23>;
status = "disabled";
};
......@@ -168,7 +189,7 @@ cps_xor0: xor@6a0000 {
<0x6b0000 0x1000>;
dma-coherent;
msi-parent = <&gic_v2m0>;
clocks = <&cps_syscon0 1 8>;
clocks = <&cps_clk 1 8>;
};
cps_xor1: xor@6c0000 {
......@@ -177,7 +198,7 @@ cps_xor1: xor@6c0000 {
<0x6d0000 0x1000>;
dma-coherent;
msi-parent = <&gic_v2m0>;
clocks = <&cps_syscon0 1 7>;
clocks = <&cps_clk 1 7>;
};
cps_spi0: spi@700600 {
......@@ -186,7 +207,7 @@ cps_spi0: spi@700600 {
#address-cells = <0x1>;
#size-cells = <0x0>;
cell-index = <3>;
clocks = <&cps_syscon0 1 21>;
clocks = <&cps_clk 1 21>;
status = "disabled";
};
......@@ -196,7 +217,7 @@ cps_spi1: spi@700680 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <4>;
clocks = <&cps_syscon0 1 21>;
clocks = <&cps_clk 1 21>;
status = "disabled";
};
......@@ -205,8 +226,8 @@ cps_i2c0: i2c@701000 {
reg = <0x701000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_syscon0 1 21>;
interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_clk 1 21>;
status = "disabled";
};
......@@ -215,32 +236,32 @@ cps_i2c1: i2c@701100 {
reg = <0x701100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_syscon0 1 21>;
interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_clk 1 21>;
status = "disabled";
};
cps_trng: trng@760000 {
compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
reg = <0x760000 0x7d>;
interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_syscon0 1 25>;
interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_clk 1 25>;
status = "okay";
};
cps_crypto: crypto@800000 {
compatible = "inside-secure,safexcel-eip197";
reg = <0x800000 0x200000>;
interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING
interrupts = <ICU_GRP_NSR 87 (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_LEVEL_HIGH)>,
<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>;
<ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
clocks = <&cps_syscon0 1 26>;
clocks = <&cps_clk 1 26>;
dma-mask = <0xff 0xffffffff>;
/*
* The cryptographic engine found on the cp110
......@@ -272,10 +293,10 @@ cps_pcie0: pcie@f4600000 {
/* non-prefetchable memory */
0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cps_syscon0 1 13>;
clocks = <&cps_clk 1 13>;
status = "disabled";
};
......@@ -298,11 +319,11 @@ cps_pcie1: pcie@f4620000 {
/* non-prefetchable memory */
0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cps_syscon0 1 11>;
clocks = <&cps_clk 1 11>;
status = "disabled";
};
......@@ -325,11 +346,11 @@ cps_pcie2: pcie@f4640000 {
/* non-prefetchable memory */
0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cps_syscon0 1 12>;
clocks = <&cps_clk 1 12>;
status = "disabled";
};
};
......
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