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Commit 32457942 authored by Ben Dooks's avatar Ben Dooks
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ARM: Merge for-2635/fb-updates1 

Merge branch 'for-2635/fb-updates1' into for-linus/samsung2
parents 60713996 f64bea43
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arch/arm/Kconfig
View file @ 32457942
...@@ -647,7 +647,7 @@ config ARCH_SA1100 ...@@ -647,7 +647,7 @@ config ARCH_SA1100
Support for StrongARM 11x0 based boards. Support for StrongARM 11x0 based boards.
config ARCH_S3C2410 config ARCH_S3C2410
bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442, S3C2443" bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
select GENERIC_GPIO select GENERIC_GPIO
select ARCH_HAS_CPUFREQ select ARCH_HAS_CPUFREQ
select HAVE_CLK select HAVE_CLK
...@@ -656,6 +656,10 @@ config ARCH_S3C2410 ...@@ -656,6 +656,10 @@ config ARCH_S3C2410
BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
the Samsung SMDK2410 development board (and derivatives). the Samsung SMDK2410 development board (and derivatives).
Note, the S3C2416 and the S3C2450 are so close that they even share
the same SoC ID code. This means that there is no seperate machine
directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
config ARCH_S3C64XX config ARCH_S3C64XX
bool "Samsung S3C64XX" bool "Samsung S3C64XX"
select PLAT_SAMSUNG select PLAT_SAMSUNG
...@@ -892,6 +896,7 @@ if ARCH_S3C2410 ...@@ -892,6 +896,7 @@ if ARCH_S3C2410
source "arch/arm/mach-s3c2400/Kconfig" source "arch/arm/mach-s3c2400/Kconfig"
source "arch/arm/mach-s3c2410/Kconfig" source "arch/arm/mach-s3c2410/Kconfig"
source "arch/arm/mach-s3c2412/Kconfig" source "arch/arm/mach-s3c2412/Kconfig"
source "arch/arm/mach-s3c2416/Kconfig"
source "arch/arm/mach-s3c2440/Kconfig" source "arch/arm/mach-s3c2440/Kconfig"
source "arch/arm/mach-s3c2443/Kconfig" source "arch/arm/mach-s3c2443/Kconfig"
endif endif
......
arch/arm/Makefile
View file @ 32457942
...@@ -162,7 +162,7 @@ machine-$(CONFIG_ARCH_PNX4008) := pnx4008 ...@@ -162,7 +162,7 @@ machine-$(CONFIG_ARCH_PNX4008) := pnx4008
machine-$(CONFIG_ARCH_PXA) := pxa machine-$(CONFIG_ARCH_PXA) := pxa
machine-$(CONFIG_ARCH_REALVIEW) := realview machine-$(CONFIG_ARCH_REALVIEW) := realview
machine-$(CONFIG_ARCH_RPC) := rpc machine-$(CONFIG_ARCH_RPC) := rpc
machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2443 machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2416 s3c2440 s3c2443
machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0
machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx
machine-$(CONFIG_ARCH_S5P6440) := s5p6440 machine-$(CONFIG_ARCH_S5P6440) := s5p6440
......
arch/arm/mach-s3c2410/include/mach/dma.h
View file @ 32457942
...@@ -54,7 +54,7 @@ enum dma_ch { ...@@ -54,7 +54,7 @@ enum dma_ch {
#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */ #define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
/* we have 4 dma channels */ /* we have 4 dma channels */
#ifndef CONFIG_CPU_S3C2443 #if !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2416)
#define S3C_DMA_CHANNELS (4) #define S3C_DMA_CHANNELS (4)
#else #else
#define S3C_DMA_CHANNELS (6) #define S3C_DMA_CHANNELS (6)
......
arch/arm/mach-s3c2410/include/mach/irqs.h
View file @ 32457942
...@@ -115,6 +115,26 @@ ...@@ -115,6 +115,26 @@
#define IRQ_S3C2412_SDI S3C2410_IRQSUB(13) #define IRQ_S3C2412_SDI S3C2410_IRQSUB(13)
#define IRQ_S3C2412_CF S3C2410_IRQSUB(14) #define IRQ_S3C2412_CF S3C2410_IRQSUB(14)
#define IRQ_S3C2416_EINT8t15 S3C2410_IRQ(5)
#define IRQ_S3C2416_DMA S3C2410_IRQ(17)
#define IRQ_S3C2416_UART3 S3C2410_IRQ(18)
#define IRQ_S3C2416_SDI1 S3C2410_IRQ(20)
#define IRQ_S3C2416_SDI0 S3C2410_IRQ(21)
#define IRQ_S3C2416_LCD2 S3C2410_IRQSUB(15)
#define IRQ_S3C2416_LCD3 S3C2410_IRQSUB(16)
#define IRQ_S3C2416_LCD4 S3C2410_IRQSUB(17)
#define IRQ_S3C2416_DMA0 S3C2410_IRQSUB(18)
#define IRQ_S3C2416_DMA1 S3C2410_IRQSUB(19)
#define IRQ_S3C2416_DMA2 S3C2410_IRQSUB(20)
#define IRQ_S3C2416_DMA3 S3C2410_IRQSUB(21)
#define IRQ_S3C2416_DMA4 S3C2410_IRQSUB(22)
#define IRQ_S3C2416_DMA5 S3C2410_IRQSUB(23)
#define IRQ_S32416_WDT S3C2410_IRQSUB(27)
#define IRQ_S32416_AC97 S3C2410_IRQSUB(28)
/* extra irqs for s3c2440 */ /* extra irqs for s3c2440 */
#define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */ #define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */
...@@ -130,7 +150,10 @@ ...@@ -130,7 +150,10 @@
#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */ #define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */
#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */ #define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */
#define IRQ_S3C2416_HSMMC0 S3C2410_IRQ(21) /* S3C2416/S3C2450 */
#define IRQ_HSMMC0 IRQ_S3C2443_HSMMC #define IRQ_HSMMC0 IRQ_S3C2443_HSMMC
#define IRQ_HSMMC1 IRQ_S3C2416_HSMMC0
#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14) #define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14)
#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15) #define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15)
...@@ -152,7 +175,7 @@ ...@@ -152,7 +175,7 @@
#define IRQ_S3C2443_WDT S3C2410_IRQSUB(27) #define IRQ_S3C2443_WDT S3C2410_IRQSUB(27)
#define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28) #define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28)
#ifdef CONFIG_CPU_S3C2443 #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
#define NR_IRQS (IRQ_S3C2443_AC97+1) #define NR_IRQS (IRQ_S3C2443_AC97+1)
#else #else
#define NR_IRQS (IRQ_S3C2440_AC97+1) #define NR_IRQS (IRQ_S3C2440_AC97+1)
...@@ -164,6 +187,9 @@ ...@@ -164,6 +187,9 @@
#define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3 #define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3
#define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3 #define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3
#define IRQ_LCD_VSYNC IRQ_S3C2443_LCD3
#define IRQ_LCD_SYSTEM IRQ_S3C2443_LCD2
#ifdef CONFIG_CPU_S3C2440 #ifdef CONFIG_CPU_S3C2440
#define IRQ_S3C244x_AC97 IRQ_S3C2440_AC97 #define IRQ_S3C244x_AC97 IRQ_S3C2440_AC97
#else #else
......
arch/arm/mach-s3c2410/include/mach/map.h
View file @ 32457942
...@@ -63,9 +63,11 @@ ...@@ -63,9 +63,11 @@
#define S3C2440_PA_AC97 (0x5B000000) #define S3C2440_PA_AC97 (0x5B000000)
#define S3C2440_SZ_AC97 SZ_1M #define S3C2440_SZ_AC97 SZ_1M
/* S3C2443 High-speed SD/MMC */ /* S3C2443/S3C2416 High-speed SD/MMC */
#define S3C2443_PA_HSMMC (0x4A800000) #define S3C2443_PA_HSMMC (0x4A800000)
#define S3C2443_SZ_HSMMC (256) #define S3C2416_PA_HSMMC0 (0x4AC00000)
#define S3C2443_PA_FB (0x4C800000)
/* S3C2412 memory and IO controls */ /* S3C2412 memory and IO controls */
#define S3C2412_PA_SSMC (0x4F000000) #define S3C2412_PA_SSMC (0x4F000000)
...@@ -106,10 +108,12 @@ ...@@ -106,10 +108,12 @@
#define S3C24XX_PA_SDI S3C2410_PA_SDI #define S3C24XX_PA_SDI S3C2410_PA_SDI
#define S3C24XX_PA_NAND S3C2410_PA_NAND #define S3C24XX_PA_NAND S3C2410_PA_NAND
#define S3C_PA_FB S3C2443_PA_FB
#define S3C_PA_IIC S3C2410_PA_IIC #define S3C_PA_IIC S3C2410_PA_IIC
#define S3C_PA_UART S3C24XX_PA_UART #define S3C_PA_UART S3C24XX_PA_UART
#define S3C_PA_USBHOST S3C2410_PA_USBHOST #define S3C_PA_USBHOST S3C2410_PA_USBHOST
#define S3C_PA_HSMMC0 S3C2443_PA_HSMMC #define S3C_PA_HSMMC0 S3C2443_PA_HSMMC
#define S3C_PA_HSMMC1 S3C2416_PA_HSMMC0
#define S3C_PA_NAND S3C24XX_PA_NAND #define S3C_PA_NAND S3C24XX_PA_NAND
#endif /* __ASM_ARCH_MAP_H */ #endif /* __ASM_ARCH_MAP_H */
arch/arm/mach-s3c2410/include/mach/regs-clock.h
View file @ 32457942
...@@ -161,4 +161,6 @@ ...@@ -161,4 +161,6 @@
#endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */ #endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */
#define S3C2416_CLKDIV2 S3C2410_CLKREG(0x28)
#endif /* __ASM_ARM_REGS_CLOCK */ #endif /* __ASM_ARM_REGS_CLOCK */
arch/arm/mach-s3c2410/include/mach/regs-dsc.h
View file @ 32457942
...@@ -19,6 +19,42 @@ ...@@ -19,6 +19,42 @@
#define S3C2412_DSC1 S3C2410_GPIOREG(0xe0) #define S3C2412_DSC1 S3C2410_GPIOREG(0xe0)
#endif #endif
#if defined(CONFIG_CPU_S3C2416)
#define S3C2416_DSC0 S3C2410_GPIOREG(0xc0)
#define S3C2416_DSC1 S3C2410_GPIOREG(0xc4)
#define S3C2416_DSC2 S3C2410_GPIOREG(0xc8)
#define S3C2416_DSC3 S3C2410_GPIOREG(0x110)
#define S3C2416_SELECT_DSC0 (0 << 30)
#define S3C2416_SELECT_DSC1 (1 << 30)
#define S3C2416_SELECT_DSC2 (2 << 30)
#define S3C2416_SELECT_DSC3 (3 << 30)
#define S3C2416_DSC_GETSHIFT(x) (x & 30)
#define S3C2416_DSC0_CF (S3C2416_SELECT_DSC0 | 28)
#define S3C2416_DSC0_CF_5mA (0 << 28)
#define S3C2416_DSC0_CF_10mA (1 << 28)
#define S3C2416_DSC0_CF_15mA (2 << 28)
#define S3C2416_DSC0_CF_21mA (3 << 28)
#define S3C2416_DSC0_CF_MASK (3 << 28)
#define S3C2416_DSC0_nRBE (S3C2416_SELECT_DSC0 | 26)
#define S3C2416_DSC0_nRBE_5mA (0 << 26)
#define S3C2416_DSC0_nRBE_10mA (1 << 26)
#define S3C2416_DSC0_nRBE_15mA (2 << 26)
#define S3C2416_DSC0_nRBE_21mA (3 << 26)
#define S3C2416_DSC0_nRBE_MASK (3 << 26)
#define S3C2416_DSC0_nROE (S3C2416_SELECT_DSC0 | 24)
#define S3C2416_DSC0_nROE_5mA (0 << 24)
#define S3C2416_DSC0_nROE_10mA (1 << 24)
#define S3C2416_DSC0_nROE_15mA (2 << 24)
#define S3C2416_DSC0_nROE_21mA (3 << 24)
#define S3C2416_DSC0_nROE_MASK (3 << 24)
#endif
#if defined(CONFIG_CPU_S3C244X) #if defined(CONFIG_CPU_S3C244X)
#define S3C2440_DSC0 S3C2410_GPIOREG(0xc4) #define S3C2440_DSC0 S3C2410_GPIOREG(0xc4)
......
arch/arm/mach-s3c2410/include/mach/regs-gpio.h
View file @ 32457942
...@@ -592,29 +592,50 @@ ...@@ -592,29 +592,50 @@
#define S3C2410_GPHUP S3C2410_GPIOREG(0x78) #define S3C2410_GPHUP S3C2410_GPIOREG(0x78)
#define S3C2410_GPH0_nCTS0 (0x02 << 0) #define S3C2410_GPH0_nCTS0 (0x02 << 0)
#define S3C2416_GPH0_TXD0 (0x02 << 0)
#define S3C2410_GPH1_nRTS0 (0x02 << 2) #define S3C2410_GPH1_nRTS0 (0x02 << 2)
#define S3C2416_GPH1_RXD0 (0x02 << 2)
#define S3C2410_GPH2_TXD0 (0x02 << 4) #define S3C2410_GPH2_TXD0 (0x02 << 4)
#define S3C2416_GPH2_TXD1 (0x02 << 4)
#define S3C2410_GPH3_RXD0 (0x02 << 6) #define S3C2410_GPH3_RXD0 (0x02 << 6)
#define S3C2416_GPH3_RXD1 (0x02 << 6)
#define S3C2410_GPH4_TXD1 (0x02 << 8) #define S3C2410_GPH4_TXD1 (0x02 << 8)
#define S3C2416_GPH4_TXD2 (0x02 << 8)
#define S3C2410_GPH5_RXD1 (0x02 << 10) #define S3C2410_GPH5_RXD1 (0x02 << 10)
#define S3C2416_GPH5_RXD2 (0x02 << 10)
#define S3C2410_GPH6_TXD2 (0x02 << 12) #define S3C2410_GPH6_TXD2 (0x02 << 12)
#define S3C2416_GPH6_TXD3 (0x02 << 12)
#define S3C2410_GPH6_nRTS1 (0x03 << 12) #define S3C2410_GPH6_nRTS1 (0x03 << 12)
#define S3C2416_GPH6_nRTS2 (0x03 << 12)
#define S3C2410_GPH7_RXD2 (0x02 << 14) #define S3C2410_GPH7_RXD2 (0x02 << 14)
#define S3C2416_GPH7_RXD3 (0x02 << 14)
#define S3C2410_GPH7_nCTS1 (0x03 << 14) #define S3C2410_GPH7_nCTS1 (0x03 << 14)
#define S3C2416_GPH7_nCTS2 (0x03 << 14)
#define S3C2410_GPH8_UCLK (0x02 << 16) #define S3C2410_GPH8_UCLK (0x02 << 16)
#define S3C2416_GPH8_nCTS0 (0x02 << 16)
#define S3C2410_GPH9_CLKOUT0 (0x02 << 18) #define S3C2410_GPH9_CLKOUT0 (0x02 << 18)
#define S3C2442_GPH9_nSPICS0 (0x03 << 18) #define S3C2442_GPH9_nSPICS0 (0x03 << 18)
#define S3C2416_GPH9_nRTS0 (0x02 << 18)
#define S3C2410_GPH10_CLKOUT1 (0x02 << 20) #define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
#define S3C2416_GPH10_nCTS1 (0x02 << 20)
#define S3C2416_GPH11_nRTS1 (0x02 << 22)
#define S3C2416_GPH12_EXTUARTCLK (0x02 << 24)
#define S3C2416_GPH13_CLKOUT0 (0x02 << 26)
#define S3C2416_GPH14_CLKOUT1 (0x02 << 28)
/* The S3C2412 and S3C2413 move the GPJ register set to after /* The S3C2412 and S3C2413 move the GPJ register set to after
* GPH, which means all registers after 0x80 are now offset by 0x10 * GPH, which means all registers after 0x80 are now offset by 0x10
...@@ -685,6 +706,7 @@ ...@@ -685,6 +706,7 @@
#define S3C2412_MISCCR_CLK1_CLKsrc (0<<8) #define S3C2412_MISCCR_CLK1_CLKsrc (0<<8)
#define S3C2410_MISCCR_USBSUSPND0 (1<<12) #define S3C2410_MISCCR_USBSUSPND0 (1<<12)
#define S3C2416_MISCCR_SEL_SUSPND (1<<12)
#define S3C2410_MISCCR_USBSUSPND1 (1<<13) #define S3C2410_MISCCR_USBSUSPND1 (1<<13)
#define S3C2410_MISCCR_nRSTCON (1<<16) #define S3C2410_MISCCR_nRSTCON (1<<16)
...@@ -694,6 +716,9 @@ ...@@ -694,6 +716,9 @@
#define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */ #define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */
#define S3C2410_MISCCR_SDSLEEP (7<<17) #define S3C2410_MISCCR_SDSLEEP (7<<17)
#define S3C2416_MISCCR_FLT_I2C (1<<24)
#define S3C2416_MISCCR_HSSPI_EN2 (1<<31)
/* external interrupt control... */ /* external interrupt control... */
/* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7 /* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7
* S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15 * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15
...@@ -761,8 +786,11 @@ ...@@ -761,8 +786,11 @@
#define S3C2410_GSTATUS1_IDMASK (0xffff0000) #define S3C2410_GSTATUS1_IDMASK (0xffff0000)
#define S3C2410_GSTATUS1_2410 (0x32410000) #define S3C2410_GSTATUS1_2410 (0x32410000)
#define S3C2410_GSTATUS1_2412 (0x32412001) #define S3C2410_GSTATUS1_2412 (0x32412001)
#define S3C2410_GSTATUS1_2416 (0x32416003)
#define S3C2410_GSTATUS1_2440 (0x32440000) #define S3C2410_GSTATUS1_2440 (0x32440000)
#define S3C2410_GSTATUS1_2442 (0x32440aaa) #define S3C2410_GSTATUS1_2442 (0x32440aaa)
/* some 2416 CPUs report this value also */
#define S3C2410_GSTATUS1_2450 (0x32450003)
#define S3C2410_GSTATUS2_WTRESET (1<<2) #define S3C2410_GSTATUS2_WTRESET (1<<2)
#define S3C2410_GSTATUS2_OFFRESET (1<<1) #define S3C2410_GSTATUS2_OFFRESET (1<<1)
......
arch/arm/mach-s3c2410/include/mach/regs-irq.h
View file @ 32457942
...@@ -27,6 +27,16 @@ ...@@ -27,6 +27,16 @@
#define S3C2410_SUBSRCPND S3C2410_IRQREG(0x018) #define S3C2410_SUBSRCPND S3C2410_IRQREG(0x018)
#define S3C2410_INTSUBMSK S3C2410_IRQREG(0x01C) #define S3C2410_INTSUBMSK S3C2410_IRQREG(0x01C)
#define S3C2416_PRIORITY_MODE1 S3C2410_IRQREG(0x030)
#define S3C2416_PRIORITY_UPDATE1 S3C2410_IRQREG(0x034)
#define S3C2416_SRCPND2 S3C2410_IRQREG(0x040)
#define S3C2416_INTMOD2 S3C2410_IRQREG(0x044)
#define S3C2416_INTMSK2 S3C2410_IRQREG(0x048)
#define S3C2416_INTPND2 S3C2410_IRQREG(0x050)
#define S3C2416_INTOFFSET2 S3C2410_IRQREG(0x054)
#define S3C2416_PRIORITY_MODE2 S3C2410_IRQREG(0x070)
#define S3C2416_PRIORITY_UPDATE2 S3C2410_IRQREG(0x074)
/* mask: 0=enable, 1=disable /* mask: 0=enable, 1=disable
* 1 bit EINT, 4=EINT4, 23=EINT23 * 1 bit EINT, 4=EINT4, 23=EINT23
* EINT0,1,2,3 are not handled here. * EINT0,1,2,3 are not handled here.
......
arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h 0 → 100644
View file @ 32457942
/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h
*
* Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
* as part of OpenInkpot project
* Copyright (c) 2009 Promwad Innovation Company
* Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C2416 memory register definitions
*/
#ifndef __ASM_ARM_REGS_S3C2416_MEM
#define __ASM_ARM_REGS_S3C2416_MEM
#ifndef S3C2416_MEMREG
#define S3C2416_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
#endif
#define S3C2416_BANKCFG S3C2416_MEMREG(0x00)
#define S3C2416_BANKCON1 S3C2416_MEMREG(0x04)
#define S3C2416_BANKCON2 S3C2416_MEMREG(0x08)
#define S3C2416_BANKCON3 S3C2416_MEMREG(0x0C)
#define S3C2416_REFRESH S3C2416_MEMREG(0x10)
#define S3C2416_TIMEOUT S3C2416_MEMREG(0x14)
#endif /* __ASM_ARM_REGS_S3C2416_MEM */
arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h 0 → 100644
View file @ 32457942
/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h
*
* Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
* as part of OpenInkpot project
* Copyright (c) 2009 Promwad Innovation Company
* Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S3C2416 specific register definitions
*/
#ifndef __ASM_ARCH_REGS_S3C2416_H
#define __ASM_ARCH_REGS_S3C2416_H "s3c2416"
#define S3C2416_SWRST (S3C24XX_VA_CLKPWR + 0x44)
#define S3C2416_SWRST_RESET (0x533C2416)
/* see regs-power.h for the other registers in the power block. */
#endif /* __ASM_ARCH_REGS_S3C2416_H */
arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
View file @ 32457942
...@@ -83,8 +83,7 @@ ...@@ -83,8 +83,7 @@
#define S3C2443_HCLKCON_DMA4 (1<<4) #define S3C2443_HCLKCON_DMA4 (1<<4)
#define S3C2443_HCLKCON_DMA5 (1<<5) #define S3C2443_HCLKCON_DMA5 (1<<5)
#define S3C2443_HCLKCON_CAMIF (1<<8) #define S3C2443_HCLKCON_CAMIF (1<<8)
#define S3C2443_HCLKCON_DISP (1<<9) #define S3C2443_HCLKCON_LCDC (1<<9)
#define S3C2443_HCLKCON_LCDC (1<<10)
#define S3C2443_HCLKCON_USBH (1<<11) #define S3C2443_HCLKCON_USBH (1<<11)
#define S3C2443_HCLKCON_USBD (1<<12) #define S3C2443_HCLKCON_USBD (1<<12)
#define S3C2443_HCLKCON_HSMMC (1<<16) #define S3C2443_HCLKCON_HSMMC (1<<16)
......
arch/arm/mach-s3c2410/include/mach/uncompress.h
View file @ 32457942
...@@ -40,7 +40,9 @@ static void arch_detect_cpu(void) ...@@ -40,7 +40,9 @@ static void arch_detect_cpu(void)
cpuid &= S3C2410_GSTATUS1_IDMASK; cpuid &= S3C2410_GSTATUS1_IDMASK;
if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 || if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 ||
cpuid == S3C2410_GSTATUS1_2442) { cpuid == S3C2410_GSTATUS1_2442 ||
cpuid == S3C2410_GSTATUS1_2416 ||
cpuid == S3C2410_GSTATUS1_2450) {
fifo_mask = S3C2440_UFSTAT_TXMASK; fifo_mask = S3C2440_UFSTAT_TXMASK;
fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT; fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
} else { } else {
......
arch/arm/mach-s3c2412/Kconfig
View file @ 32457942
...@@ -16,7 +16,8 @@ config CPU_S3C2412 ...@@ -16,7 +16,8 @@ config CPU_S3C2412
config CPU_S3C2412_ONLY config CPU_S3C2412_ONLY
bool bool
depends on ARCH_S3C2410 && !CPU_S3C2400 && !CPU_S3C2410 && \ depends on ARCH_S3C2410 && !CPU_S3C2400 && !CPU_S3C2410 && \
!CPU_S3C2440 && !CPU_S3C2442 && !CPU_S3C2443 && CPU_S3C2412 !CPU_2416 && !CPU_S3C2440 && !CPU_S3C2442 && \
!CPU_S3C2443 && CPU_S3C2412
default y if CPU_S3C2412 default y if CPU_S3C2412
config S3C2412_DMA config S3C2412_DMA
......
arch/arm/mach-s3c2416/Kconfig 0 → 100644
View file @ 32457942
# arch/arm/mach-s3c2416/Kconfig
#
# Copyright 2009 Yauhen Kharuzhy <jekhor@gmail.com>
#
# Licensed under GPLv2
# note, this also supports the S3C2450 which is so similar it has the same
# ID code as the S3C2416.
config CPU_S3C2416
bool
depends on ARCH_S3C2410
select CPU_ARM926T
select S3C2416_DMA if S3C2410_DMA
select CPU_LLSERIAL_S3C2440
select S3C_GPIO_PULL_UPDOWN
select SAMSUNG_CLKSRC
select S3C2443_CLOCK
help
Support for the S3C2416 SoC from the S3C24XX line
config S3C2416_DMA
bool
depends on CPU_S3C2416
help
Internal config node for S3C2416 DMA support
menu "S3C2416 Machines"
config MACH_SMDK2416
bool "SMDK2416"
select CPU_S3C2416
select S3C_DEV_FB
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
help
Say Y here if you are using an SMDK2416
endmenu
arch/arm/mach-s3c2416/Makefile 0 → 100644
View file @ 32457942
# arch/arm/mach-s3c2416/Makefile
#
# Copyright 2009 Yauhen Kharuzhy <jekhor@gmail.com>
#
# Licensed under GPLv2
obj-y :=
obj-m :=
obj-n :=
obj- :=
obj-$(CONFIG_CPU_S3C2416) += s3c2416.o clock.o
obj-$(CONFIG_CPU_S3C2416) += irq.o
#obj-$(CONFIG_S3C2416_DMA) += dma.o
# Machine support
obj-$(CONFIG_MACH_SMDK2416) += mach-smdk2416.o
arch/arm/mach-s3c2416/clock.c 0 → 100644
View file @ 32457942
/* linux/arch/arm/mach-s3c2416/clock.c
*
* Copyright (c) 2010 Simtec Electronics
* Copyright (c) 2010 Ben Dooks <ben-linux@fluff.org>
*
* S3C2416 Clock control support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/init.h>
#include <linux/clk.h>
#include <plat/s3c2416.h>
#include <plat/s3c2443.h>
#include <plat/clock.h>
#include <plat/clock-clksrc.h>
#include <plat/cpu.h>
#include <plat/cpu-freq.h>
#include <plat/pll6553x.h>
#include <plat/pll.h>
#include <asm/mach/map.h>
#include <mach/regs-clock.h>
#include <mach/regs-s3c2443-clock.h>
static unsigned int armdiv[8] = {
[0] = 1,
[1] = 2,
[2] = 3,
[3] = 4,
[5] = 6,
[7] = 8,
};
/* ID to hardware numbering, 0 is HSMMC1, 1 is HSMMC0 */
static struct clksrc_clk hsmmc_div[] = {
[0] = {
.clk = {
.name = "hsmmc-div",
.id = 1,
.parent = &clk_esysclk.clk,
},
.reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
},
[1] = {
.clk = {
.name = "hsmmc-div",
.id = 0,
.parent = &clk_esysclk.clk,
},
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
},
};
static struct clksrc_clk hsmmc_mux[] = {
[0] = {
.clk = {
.id = 1,
.name = "hsmmc-if",
.ctrlbit = (1 << 6),
.enable = s3c2443_clkcon_enable_s,
},
.sources = &(struct clksrc_sources) {
.nr_sources = 2,
.sources = (struct clk *[]) {
[0] = &hsmmc_div[0].clk,
[1] = NULL, /* to fix */
},
},
.reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
},
[1] = {
.clk = {
.id = 0,
.name = "hsmmc-if",
.ctrlbit = (1 << 12),
.enable = s3c2443_clkcon_enable_s,
},
.sources = &(struct clksrc_sources) {
.nr_sources = 2,
.sources = (struct clk *[]) {
[0] = &hsmmc_div[1].clk,
[1] = NULL, /* to fix */
},
},
.reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
},
};
static inline unsigned int s3c2416_fclk_div(unsigned long clkcon0)
{
clkcon0 &= 7 << S3C2443_CLKDIV0_ARMDIV_SHIFT;
return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
}
void __init_or_cpufreq s3c2416_setup_clocks(void)
{
s3c2443_common_setup_clocks(s3c2416_get_pll, s3c2416_fclk_div);
}
static struct clksrc_clk *clksrcs[] __initdata = {
&hsmmc_div[0],
&hsmmc_div[1],
&hsmmc_mux[0],
&hsmmc_mux[1],
};
void __init s3c2416_init_clocks(int xtal)
{
u32 epllcon = __raw_readl(S3C2443_EPLLCON);
u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4);
int ptr;
/* s3c2416 EPLL compatible with s3c64xx */
clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1);
clk_epll.parent = &clk_epllref.clk;
s3c2443_common_init_clocks(xtal, s3c2416_get_pll, s3c2416_fclk_div);
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_register_clksrc(clksrcs[ptr], 1);
s3c_pwmclk_init();
}
arch/arm/mach-s3c2416/irq.c 0 → 100644
View file @ 32457942
/* linux/arch/arm/mach-s3c2416/irq.c
*
* Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
* as part of OpenInkpot project
* Copyright (c) 2009 Promwad Innovation Company
* Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/sysdev.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/irq.h>
#include <mach/regs-irq.h>
#include <mach/regs-gpio.h>
#include <plat/cpu.h>
#include <plat/pm.h>
#include <plat/irq.h>
#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
static inline void s3c2416_irq_demux(unsigned int irq, unsigned int len)
{
unsigned int subsrc, submsk;
unsigned int end;
/* read the current pending interrupts, and the mask
* for what it is available */
subsrc = __raw_readl(S3C2410_SUBSRCPND);
submsk = __raw_readl(S3C2410_INTSUBMSK);
subsrc &= ~submsk;
subsrc >>= (irq - S3C2410_IRQSUB(0));
subsrc &= (1 << len)-1;
end = len + irq;
for (; irq < end && subsrc; irq++) {
if (subsrc & 1)
generic_handle_irq(irq);
subsrc >>= 1;
}
}
/* WDT/AC97 sub interrupts */
static void s3c2416_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
{
s3c2416_irq_demux(IRQ_S3C2443_WDT, 4);
}
#define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0))
#define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
static void s3c2416_irq_wdtac97_mask(unsigned int irqno)
{
s3c_irqsub_mask(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97);
}
static void s3c2416_irq_wdtac97_unmask(unsigned int irqno)
{
s3c_irqsub_unmask(irqno, INTMSK_WDTAC97);
}
static void s3c2416_irq_wdtac97_ack(unsigned int irqno)
{
s3c_irqsub_maskack(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97);
}
static struct irq_chip s3c2416_irq_wdtac97 = {
.mask = s3c2416_irq_wdtac97_mask,
.unmask = s3c2416_irq_wdtac97_unmask,
.ack = s3c2416_irq_wdtac97_ack,
};
/* LCD sub interrupts */
static void s3c2416_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
{
s3c2416_irq_demux(IRQ_S3C2443_LCD1, 4);
}
#define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0))
#define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
static void s3c2416_irq_lcd_mask(unsigned int irqno)
{
s3c_irqsub_mask(irqno, INTMSK_LCD, SUBMSK_LCD);
}
static void s3c2416_irq_lcd_unmask(unsigned int irqno)
{
s3c_irqsub_unmask(irqno, INTMSK_LCD);
}
static void s3c2416_irq_lcd_ack(unsigned int irqno)
{
s3c_irqsub_maskack(irqno, INTMSK_LCD, SUBMSK_LCD);
}
static struct irq_chip s3c2416_irq_lcd = {
.mask = s3c2416_irq_lcd_mask,
.unmask = s3c2416_irq_lcd_unmask,
.ack = s3c2416_irq_lcd_ack,
};
/* DMA sub interrupts */
static void s3c2416_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
{
s3c2416_irq_demux(IRQ_S3C2443_DMA0, 6);
}
#define INTMSK_DMA (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0))
#define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
static void s3c2416_irq_dma_mask(unsigned int irqno)
{
s3c_irqsub_mask(irqno, INTMSK_DMA, SUBMSK_DMA);
}
static void s3c2416_irq_dma_unmask(unsigned int irqno)
{
s3c_irqsub_unmask(irqno, INTMSK_DMA);
}
static void s3c2416_irq_dma_ack(unsigned int irqno)
{
s3c_irqsub_maskack(irqno, INTMSK_DMA, SUBMSK_DMA);
}
static struct irq_chip s3c2416_irq_dma = {
.mask = s3c2416_irq_dma_mask,
.unmask = s3c2416_irq_dma_unmask,
.ack = s3c2416_irq_dma_ack,
};
/* UART3 sub interrupts */
static void s3c2416_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
{
s3c2416_irq_demux(IRQ_S3C2443_UART3, 3);
}
#define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
#define SUBMSK_UART3 (0xf << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
static void s3c2416_irq_uart3_mask(unsigned int irqno)
{
s3c_irqsub_mask(irqno, INTMSK_UART3, SUBMSK_UART3);
}
static void s3c2416_irq_uart3_unmask(unsigned int irqno)
{
s3c_irqsub_unmask(irqno, INTMSK_UART3);
}
static void s3c2416_irq_uart3_ack(unsigned int irqno)
{
s3c_irqsub_maskack(irqno, INTMSK_UART3, SUBMSK_UART3);
}
static struct irq_chip s3c2416_irq_uart3 = {
.mask = s3c2416_irq_uart3_mask,
.unmask = s3c2416_irq_uart3_unmask,
.ack = s3c2416_irq_uart3_ack,
};
/* IRQ initialisation code */
static int __init s3c2416_add_sub(unsigned int base,
void (*demux)(unsigned int,
struct irq_desc *),
struct irq_chip *chip,
unsigned int start, unsigned int end)
{
unsigned int irqno;
set_irq_chip(base, &s3c_irq_level_chip);
set_irq_handler(base, handle_level_irq);
set_irq_chained_handler(base, demux);
for (irqno = start; irqno <= end; irqno++) {
set_irq_chip(irqno, chip);
set_irq_handler(irqno, handle_level_irq);
set_irq_flags(irqno, IRQF_VALID);
}
return 0;
}
static int __init s3c2416_irq_add(struct sys_device *sysdev)
{
printk(KERN_INFO "S3C2416: IRQ Support\n");
s3c2416_add_sub(IRQ_LCD, s3c2416_irq_demux_lcd, &s3c2416_irq_lcd,
IRQ_S3C2443_LCD2, IRQ_S3C2443_LCD4);
s3c2416_add_sub(IRQ_S3C2443_DMA, s3c2416_irq_demux_dma,
&s3c2416_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5);
s3c2416_add_sub(IRQ_S3C2443_UART3, s3c2416_irq_demux_uart3,
&s3c2416_irq_uart3,
IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3);
s3c2416_add_sub(IRQ_WDT, s3c2416_irq_demux_wdtac97,
&s3c2416_irq_wdtac97,
IRQ_S3C2443_WDT, IRQ_S3C2443_AC97);
return 0;
}
static struct sysdev_driver s3c2416_irq_driver = {
.add = s3c2416_irq_add,
};
static int __init s3c2416_irq_init(void)
{
return sysdev_driver_register(&s3c2416_sysclass, &s3c2416_irq_driver);
}
arch_initcall(s3c2416_irq_init);
arch/arm/mach-s3c2416/mach-smdk2416.c 0 → 100644
View file @ 32457942
/* linux/arch/arm/mach-s3c2416/mach-hanlin_v3c.c
*
* Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
* as part of OpenInkpot project
* Copyright (c) 2009 Promwad Innovation Company
* Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/mtd/partitions.h>
#include <linux/gpio.h>
#include <linux/fb.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <mach/regs-lcd.h>
#include <mach/idle.h>
#include <mach/leds-gpio.h>
#include <plat/iic.h>
#include <plat/s3c2416.h>
#include <plat/gpio-cfg.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/nand.h>
#include <plat/regs-fb-v4.h>
#include <plat/fb.h>
#include <plat/common-smdk.h>
static struct map_desc smdk2416_iodesc[] __initdata = {
/* ISA IO Space map (memory space selected by A24) */
{
.virtual = (u32)S3C24XX_VA_ISA_WORD,
.pfn = __phys_to_pfn(S3C2410_CS2),
.length = 0x10000,
.type = MT_DEVICE,
}, {
.virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000,
.pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
.length = SZ_4M,
.type = MT_DEVICE,
}, {
.virtual = (u32)S3C24XX_VA_ISA_BYTE,
.pfn = __phys_to_pfn(S3C2410_CS2),
.length = 0x10000,
.type = MT_DEVICE,
}, {
.virtual = (u32)S3C24XX_VA_ISA_BYTE + 0x10000,
.pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
.length = SZ_4M,
.type = MT_DEVICE,
}
};
#define UCON (S3C2410_UCON_DEFAULT | \
S3C2440_UCON_PCLK | \
S3C2443_UCON_RXERR_IRQEN)
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
#define UFCON (S3C2410_UFCON_RXTRIG8 | \
S3C2410_UFCON_FIFOMODE | \
S3C2440_UFCON_TXTRIG16)
static struct s3c2410_uartcfg smdk2416_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = UCON,
.ulcon = ULCON,
.ufcon = UFCON,
},
/* IR port */
[2] = {
.hwport = 2,
.flags = 0,
.ucon = UCON,
.ulcon = ULCON | 0x50,
.ufcon = UFCON,
}
};
struct s3c_fb_pd_win smdk2416_fb_win[] = {
[0] = {
/* think this is the same as the smdk6410 */
.win_mode = {
.pixclock = 41094,
.left_margin = 8,
.right_margin = 13,
.upper_margin = 7,
.lower_margin = 5,
.hsync_len = 3,
.vsync_len = 1,
.xres = 800,
.yres = 480,
},
.default_bpp = 16,
.max_bpp = 32,
},
};
static void s3c2416_fb_gpio_setup_24bpp(void)
{
unsigned int gpio;
for (gpio = S3C2410_GPC(1); gpio <= S3C2410_GPC(4); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
for (gpio = S3C2410_GPC(8); gpio <= S3C2410_GPC(15); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
for (gpio = S3C2410_GPD(0); gpio <= S3C2410_GPD(15); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
}
static struct s3c_fb_platdata smdk2416_fb_platdata = {
.win[0] = &smdk2416_fb_win[0],
.setup_gpio = s3c2416_fb_gpio_setup_24bpp,
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
};
static struct platform_device *smdk2416_devices[] __initdata = {
&s3c_device_fb,
&s3c_device_wdt,
&s3c_device_ohci,
&s3c_device_i2c0,
&s3c_device_hsmmc0,
&s3c_device_hsmmc1,
};
static void __init smdk2416_map_io(void)
{
s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc));
s3c24xx_init_clocks(12000000);
s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs));
}
static void __init smdk2416_machine_init(void)
{
s3c_i2c0_set_platdata(NULL);
s3c_fb_set_platdata(&smdk2416_fb_platdata);
gpio_request(S3C2410_GPB(4), "USBHost Power");
gpio_direction_output(S3C2410_GPB(4), 1);
gpio_request(S3C2410_GPB(3), "Display Power");
gpio_direction_output(S3C2410_GPB(3), 1);
gpio_request(S3C2410_GPB(1), "Display Reset");
gpio_direction_output(S3C2410_GPB(1), 1);
platform_add_devices(smdk2416_devices, ARRAY_SIZE(smdk2416_devices));
smdk_machine_init();
}
MACHINE_START(SMDK2416, "SMDK2416")
/* Maintainer: Yauhen Kharuzhy <jekhor@gmail.com> */
.phys_io = S3C2410_PA_UART,
.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C2410_SDRAM_PA + 0x100,
.init_irq = s3c24xx_init_irq,
.map_io = smdk2416_map_io,
.init_machine = smdk2416_machine_init,
.timer = &s3c24xx_timer,
MACHINE_END
arch/arm/mach-s3c2416/s3c2416.c 0 → 100644
View file @ 32457942
/* linux/arch/arm/mach-s3c2416/s3c2416.c
*
* Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
* as part of OpenInkpot project
* Copyright (c) 2009 Promwad Innovation Company
* Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
*
* Samsung S3C2416 Mobile CPU support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/serial_core.h>
#include <linux/sysdev.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <asm/proc-fns.h>
#include <asm/irq.h>
#include <mach/reset.h>
#include <mach/idle.h>
#include <mach/regs-s3c2443-clock.h>
#include <plat/gpio-core.h>
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>
#include <plat/s3c2416.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/iic-core.h>
static struct map_desc s3c2416_iodesc[] __initdata = {
IODESC_ENT(WATCHDOG),
IODESC_ENT(CLKPWR),
IODESC_ENT(TIMER),
};
struct sysdev_class s3c2416_sysclass = {
.name = "s3c2416-core",
};
static struct sys_device s3c2416_sysdev = {
.cls = &s3c2416_sysclass,
};
static void s3c2416_hard_reset(void)
{
__raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
}
int __init s3c2416_init(void)
{
printk(KERN_INFO "S3C2416: Initializing architecture\n");
s3c24xx_reset_hook = s3c2416_hard_reset;
/* s3c24xx_idle = s3c2416_idle; */
/* change WDT IRQ number */
s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
s3c_device_wdt.resource[1].end = IRQ_S3C2443_WDT;
/* the i2c devices are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
s3c_device_fb.name = "s3c2443-fb";
return sysdev_register(&s3c2416_sysdev);
}
void __init s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
s3c_device_nand.name = "s3c2416-nand";
}
/* s3c2416_map_io
*
* register the standard cpu IO areas, and any passed in from the
* machine specific initialisation.
*/
void __init s3c2416_map_io(void)
{
s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_updown;
s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_updown;
iotable_init(s3c2416_iodesc, ARRAY_SIZE(s3c2416_iodesc));
}
/* need to register class before we actually register the device, and
* we also need to ensure that it has been initialised before any of the
* drivers even try to use it (even if not on an s3c2416 based system)
* as a driver which may support both 2443 and 2440 may try and use it.
*/
static int __init s3c2416_core_init(void)
{
return sysdev_class_register(&s3c2416_sysclass);
}
core_initcall(s3c2416_core_init);
arch/arm/mach-s3c2443/Kconfig
View file @ 32457942
...@@ -8,6 +8,7 @@ config CPU_S3C2443 ...@@ -8,6 +8,7 @@ config CPU_S3C2443
select S3C2443_DMA if S3C2410_DMA select S3C2443_DMA if S3C2410_DMA
select CPU_LLSERIAL_S3C2440 select CPU_LLSERIAL_S3C2440
select SAMSUNG_CLKSRC select SAMSUNG_CLKSRC
select S3C2443_CLOCK
help help
Support for the S3C2443 SoC from the S3C24XX line Support for the S3C2443 SoC from the S3C24XX line
......
arch/arm/mach-s3c2443/clock.c
View file @ 32457942
...@@ -21,6 +21,7 @@ ...@@ -21,6 +21,7 @@
*/ */
#include <linux/init.h> #include <linux/init.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/list.h> #include <linux/list.h>
...@@ -54,111 +55,13 @@ ...@@ -54,111 +55,13 @@
* set the correct muxing at initialisation * set the correct muxing at initialisation
*/ */
static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable)
{
u32 ctrlbit = clk->ctrlbit;
u32 con = __raw_readl(reg);
if (enable)
con |= ctrlbit;
else
con &= ~ctrlbit;
__raw_writel(con, reg);
return 0;
}
static int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
{
return s3c2443_gate(S3C2443_HCLKCON, clk, enable);
}
static int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
{
return s3c2443_gate(S3C2443_PCLKCON, clk, enable);
}
static int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
{
return s3c2443_gate(S3C2443_SCLKCON, clk, enable);
}
/* clock selections */ /* clock selections */
/* mpllref is a direct descendant of clk_xtal by default, but it is not
* elided as the EPLL can be either sourced by the XTAL or EXTCLK and as
* such directly equating the two source clocks is impossible.
*/
static struct clk clk_mpllref = {
.name = "mpllref",
.parent = &clk_xtal,
.id = -1,
};
static struct clk clk_i2s_ext = { static struct clk clk_i2s_ext = {
.name = "i2s-ext", .name = "i2s-ext",
.id = -1, .id = -1,
}; };
static struct clk *clk_epllref_sources[] = {
[0] = &clk_mpllref,
[1] = &clk_mpllref,
[2] = &clk_xtal,
[3] = &clk_ext,
};
static struct clksrc_clk clk_epllref = {
.clk = {
.name = "epllref",
.id = -1,
},
.sources = &(struct clksrc_sources) {
.sources = clk_epllref_sources,
.nr_sources = ARRAY_SIZE(clk_epllref_sources),
},
.reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 },
};
static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
{
unsigned long parent_rate = clk_get_rate(clk->parent);
unsigned long div = __raw_readl(S3C2443_CLKDIV0);
div &= S3C2443_CLKDIV0_EXTDIV_MASK;
div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1); /* x2 */
return parent_rate / (div + 1);
}
static struct clk clk_mdivclk = {
.name = "mdivclk",
.parent = &clk_mpllref,
.id = -1,
.ops = &(struct clk_ops) {
.get_rate = s3c2443_getrate_mdivclk,
},
};
static struct clk *clk_msysclk_sources[] = {
[0] = &clk_mpllref,
[1] = &clk_mpll,
[2] = &clk_mdivclk,
[3] = &clk_mpllref,
};
static struct clksrc_clk clk_msysclk = {
.clk = {
.name = "msysclk",
.parent = &clk_xtal,
.id = -1,
},
.sources = &(struct clksrc_sources) {
.sources = clk_msysclk_sources,
.nr_sources = ARRAY_SIZE(clk_msysclk_sources),
},
.reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 },
};
/* armdiv /* armdiv
* *
* this clock is sourced from msysclk and can have a number of * this clock is sourced from msysclk and can have a number of
...@@ -266,44 +169,6 @@ static struct clksrc_clk clk_arm = { ...@@ -266,44 +169,6 @@ static struct clksrc_clk clk_arm = {
.reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 }, .reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 },
}; };
/* esysclk
*
* this is sourced from either the EPLL or the EPLLref clock
*/
static struct clk *clk_sysclk_sources[] = {
[0] = &clk_epllref.clk,
[1] = &clk_epll,
};
static struct clksrc_clk clk_esysclk = {
.clk = {
.name = "esysclk",
.parent = &clk_epll,
.id = -1,
},
.sources = &(struct clksrc_sources) {
.sources = clk_sysclk_sources,
.nr_sources = ARRAY_SIZE(clk_sysclk_sources),
},
.reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 },
};
/* uartclk
*
* UART baud-rate clock sourced from esysclk via a divisor
*/
static struct clksrc_clk clk_uart = {
.clk = {
.name = "uartclk",
.id = -1,
.parent = &clk_esysclk.clk,
},
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
};
/* hsspi /* hsspi
* *
* high-speed spi clock, sourced from esysclk * high-speed spi clock, sourced from esysclk
...@@ -320,21 +185,6 @@ static struct clksrc_clk clk_hsspi = { ...@@ -320,21 +185,6 @@ static struct clksrc_clk clk_hsspi = {
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 }, .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
}; };
/* usbhost
*
* usb host bus-clock, usually 48MHz to provide USB bus clock timing
*/
static struct clksrc_clk clk_usb_bus_host = {
.clk = {
.name = "usb-bus-host-parent",
.id = -1,
.parent = &clk_esysclk.clk,
.ctrlbit = S3C2443_SCLKCON_USBHOST,
.enable = s3c2443_clkcon_enable_s,
},
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
};
/* clk_hsmcc_div /* clk_hsmcc_div
* *
...@@ -433,88 +283,15 @@ static struct clksrc_clk clk_i2s = { ...@@ -433,88 +283,15 @@ static struct clksrc_clk clk_i2s = {
.reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 }, .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
}; };
/* cam-if
*
* camera interface bus-clock, divided down from esysclk
*/
static struct clksrc_clk clk_cam = {
.clk = {
.name = "camif-upll", /* same as 2440 name */
.id = -1,
.parent = &clk_esysclk.clk,
.ctrlbit = S3C2443_SCLKCON_CAMCLK,
.enable = s3c2443_clkcon_enable_s,
},
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 },
};
/* display-if
*
* display interface clock, divided from esysclk
*/
static struct clksrc_clk clk_display = {
.clk = {
.name = "display-if",
.id = -1,
.parent = &clk_esysclk.clk,
.ctrlbit = S3C2443_SCLKCON_DISPCLK,
.enable = s3c2443_clkcon_enable_s,
},
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 },
};
/* prediv
*
* this divides the msysclk down to pass to h/p/etc.
*/
static unsigned long s3c2443_prediv_getrate(struct clk *clk)
{
unsigned long rate = clk_get_rate(clk->parent);
unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK;
clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
return rate / (clkdiv0 + 1);
}
static struct clk clk_prediv = {
.name = "prediv",
.id = -1,
.parent = &clk_msysclk.clk,
.ops = &(struct clk_ops) {
.get_rate = s3c2443_prediv_getrate,
},
};
/* standard clock definitions */ /* standard clock definitions */
static struct clk init_clocks_disable[] = { static struct clk init_clocks_off[] = {
{ {
.name = "nand",
.id = -1,
.parent = &clk_h,
}, {
.name = "sdi", .name = "sdi",
.id = -1, .id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s3c2443_clkcon_enable_p, .enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_SDI, .ctrlbit = S3C2443_PCLKCON_SDI,
}, {
.name = "adc",
.id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_ADC,
}, {
.name = "i2c",
.id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_IIC,
}, { }, {
.name = "iis", .name = "iis",
.id = -1, .id = -1,
...@@ -537,179 +314,12 @@ static struct clk init_clocks_disable[] = { ...@@ -537,179 +314,12 @@ static struct clk init_clocks_disable[] = {
}; };
static struct clk init_clocks[] = { static struct clk init_clocks[] = {
{
.name = "dma",
.id = 0,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA0,
}, {
.name = "dma",
.id = 1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA1,
}, {
.name = "dma",
.id = 2,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA2,
}, {
.name = "dma",
.id = 3,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA3,
}, {
.name = "dma",
.id = 4,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA4,
}, {
.name = "dma",
.id = 5,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA5,
}, {
.name = "lcd",
.id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_LCDC,
}, {
.name = "gpio",
.id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_GPIO,
}, {
.name = "usb-host",
.id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_USBH,
}, {
.name = "usb-device",
.id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_USBD,
}, {
.name = "hsmmc",
.id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_HSMMC,
}, {
.name = "cfc",
.id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_CFC,
}, {
.name = "ssmc",
.id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_SSMC,
}, {
.name = "timers",
.id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_PWMT,
}, {
.name = "uart",
.id = 0,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_UART0,
}, {
.name = "uart",
.id = 1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_UART1,
}, {
.name = "uart",
.id = 2,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_UART2,
}, {
.name = "uart",
.id = 3,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_UART3,
}, {
.name = "rtc",
.id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_RTC,
}, {
.name = "watchdog",
.id = -1,
.parent = &clk_p,
.ctrlbit = S3C2443_PCLKCON_WDT,
}, {
.name = "usb-bus-host",
.id = -1,
.parent = &clk_usb_bus_host.clk,
}, {
.name = "ac97",
.id = -1,
.parent = &clk_p,
.ctrlbit = S3C2443_PCLKCON_AC97,
}
};
/* clocks to add where we need to check their parentage */
static struct clksrc_clk __initdata *init_list[] = {
&clk_epllref, /* should be first */
&clk_esysclk,
&clk_msysclk,
&clk_arm,
&clk_i2s_eplldiv,
&clk_i2s,
&clk_cam,
&clk_uart,
&clk_display,
&clk_hsmmc_div,
&clk_usb_bus_host,
}; };
static void __init s3c2443_clk_initparents(void)
{
int ptr;
for (ptr = 0; ptr < ARRAY_SIZE(init_list); ptr++)
s3c_set_clksrc(init_list[ptr], true);
}
static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
{
clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
return clkcon0 + 1;
}
/* clocks to add straight away */ /* clocks to add straight away */
static struct clksrc_clk *clksrcs[] __initdata = { static struct clksrc_clk *clksrcs[] __initdata = {
&clk_usb_bus_host,
&clk_epllref,
&clk_esysclk,
&clk_msysclk,
&clk_arm, &clk_arm,
&clk_uart,
&clk_display,
&clk_cam,
&clk_i2s_eplldiv, &clk_i2s_eplldiv,
&clk_i2s, &clk_i2s,
&clk_hsspi, &clk_hsspi,
...@@ -717,92 +327,32 @@ static struct clksrc_clk *clksrcs[] __initdata = { ...@@ -717,92 +327,32 @@ static struct clksrc_clk *clksrcs[] __initdata = {
}; };
static struct clk *clks[] __initdata = { static struct clk *clks[] __initdata = {
&clk_ext,
&clk_epll,
&clk_usb_bus,
&clk_mpllref,
&clk_hsmmc, &clk_hsmmc,
&clk_armdiv, &clk_armdiv,
&clk_prediv,
}; };
void __init_or_cpufreq s3c2443_setup_clocks(void) void __init_or_cpufreq s3c2443_setup_clocks(void)
{ {
unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON); s3c2443_common_setup_clocks(s3c2443_get_mpll, s3c2443_fclk_div);
unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
struct clk *xtal_clk;
unsigned long xtal;
unsigned long pll;
unsigned long fclk;
unsigned long hclk;
unsigned long pclk;
xtal_clk = clk_get(NULL, "xtal");
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
pll = s3c2443_get_mpll(mpllcon, xtal);
clk_msysclk.clk.rate = pll;
fclk = pll / s3c2443_fclk_div(clkdiv0);
hclk = s3c2443_prediv_getrate(&clk_prediv);
hclk /= s3c2443_get_hdiv(clkdiv0);
pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
s3c24xx_setup_clocks(fclk, hclk, pclk);
printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
(mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
print_mhz(pll), print_mhz(fclk),
print_mhz(hclk), print_mhz(pclk));
s3c24xx_setup_clocks(fclk, hclk, pclk);
} }
void __init s3c2443_init_clocks(int xtal) void __init s3c2443_init_clocks(int xtal)
{ {
struct clk *clkp;
unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
int ret;
int ptr; int ptr;
/* s3c2443 parents h and p clocks from prediv */ clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
clk_h.parent = &clk_prediv; clk_epll.parent = &clk_epllref.clk;
clk_p.parent = &clk_prediv;
s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, s3c2443_fclk_div);
s3c24xx_register_baseclocks(xtal);
s3c2443_setup_clocks(); s3c2443_setup_clocks();
s3c2443_clk_initparents();
for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
clkp = clks[ptr];
ret = s3c24xx_register_clock(clkp); s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
}
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_register_clksrc(clksrcs[ptr], 1); s3c_register_clksrc(clksrcs[ptr], 1);
clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
clk_epll.parent = &clk_epllref.clk;
clk_usb_bus.parent = &clk_usb_bus_host.clk;
/* ensure usb bus clock is within correct rate of 48MHz */
if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) {
printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000);
}
printk("S3C2443: epll %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
(epllcon & S3C2443_PLLCON_OFF) ? "off":"on",
print_mhz(clk_get_rate(&clk_epll)),
print_mhz(clk_get_rate(&clk_usb_bus)));
/* register clocks from clock array */ /* register clocks from clock array */
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
...@@ -819,17 +369,8 @@ void __init s3c2443_init_clocks(int xtal) ...@@ -819,17 +369,8 @@ void __init s3c2443_init_clocks(int xtal)
/* install (and disable) the clocks we do not need immediately */ /* install (and disable) the clocks we do not need immediately */
clkp = init_clocks_disable; s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
(clkp->enable)(clkp, 0);
}
s3c_pwmclk_init(); s3c_pwmclk_init();
} }
arch/arm/mach-s3c64xx/include/mach/pll.h
View file @ 32457942
...@@ -20,6 +20,7 @@ ...@@ -20,6 +20,7 @@
#define S3C6400_PLL_SDIV_SHIFT (0) #define S3C6400_PLL_SDIV_SHIFT (0)
#include <asm/div64.h> #include <asm/div64.h>
#include <plat/pll6553x.h>
static inline unsigned long s3c6400_get_pll(unsigned long baseclk, static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
u32 pllcon) u32 pllcon)
...@@ -37,38 +38,8 @@ static inline unsigned long s3c6400_get_pll(unsigned long baseclk, ...@@ -37,38 +38,8 @@ static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
return (unsigned long)fvco; return (unsigned long)fvco;
} }
#define S3C6400_EPLL_MDIV_MASK ((1 << (23-16)) - 1)
#define S3C6400_EPLL_PDIV_MASK ((1 << (13-8)) - 1)
#define S3C6400_EPLL_SDIV_MASK ((1 << (2-0)) - 1)
#define S3C6400_EPLL_MDIV_SHIFT (16)
#define S3C6400_EPLL_PDIV_SHIFT (8)
#define S3C6400_EPLL_SDIV_SHIFT (0)
#define S3C6400_EPLL_KDIV_MASK (0xffff)
static inline unsigned long s3c6400_get_epll(unsigned long baseclk) static inline unsigned long s3c6400_get_epll(unsigned long baseclk)
{ {
unsigned long result; return s3c_get_pll6553x(baseclk, __raw_readl(S3C_EPLL_CON0),
u32 epll0 = __raw_readl(S3C_EPLL_CON0); __raw_readl(S3C_EPLL_CON1));
u32 epll1 = __raw_readl(S3C_EPLL_CON1);
u32 mdiv, pdiv, sdiv, kdiv;
u64 tmp;
mdiv = (epll0 >> S3C6400_EPLL_MDIV_SHIFT) & S3C6400_EPLL_MDIV_MASK;
pdiv = (epll0 >> S3C6400_EPLL_PDIV_SHIFT) & S3C6400_EPLL_PDIV_MASK;
sdiv = (epll0 >> S3C6400_EPLL_SDIV_SHIFT) & S3C6400_EPLL_SDIV_MASK;
kdiv = epll1 & S3C6400_EPLL_KDIV_MASK;
/* We need to multiple baseclk by mdiv (the integer part) and kdiv
* which is in 2^16ths, so shift mdiv up (does not overflow) and
* add kdiv before multiplying. The use of tmp is to avoid any
* overflows before shifting bac down into result when multipling
* by the mdiv and kdiv pair.
*/
tmp = baseclk;
tmp *= (mdiv << 16) + kdiv;
do_div(tmp, (pdiv << sdiv));
result = tmp >> 16;
return result;
} }
arch/arm/plat-s3c24xx/Kconfig
View file @ 32457942
...@@ -45,6 +45,12 @@ config S3C2410_CLOCK ...@@ -45,6 +45,12 @@ config S3C2410_CLOCK
Clock code for the S3C2410, and similar processors which Clock code for the S3C2410, and similar processors which
is currently includes the S3C2410, S3C2440, S3C2442. is currently includes the S3C2410, S3C2440, S3C2442.
config S3C2443_CLOCK
bool
help
Clock code for the S3C2443 and similar processors, which includes
the S3C2416 and S3C2450.
config S3C24XX_DCLK config S3C24XX_DCLK
bool bool
help help
......
arch/arm/plat-s3c24xx/Makefile
View file @ 32457942
...@@ -30,6 +30,7 @@ obj-$(CONFIG_PM) += pm.o ...@@ -30,6 +30,7 @@ obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_PM) += irq-pm.o obj-$(CONFIG_PM) += irq-pm.o
obj-$(CONFIG_PM) += sleep.o obj-$(CONFIG_PM) += sleep.o
obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o
obj-$(CONFIG_S3C2443_CLOCK) += s3c2443-clock.o
obj-$(CONFIG_S3C2410_DMA) += dma.o obj-$(CONFIG_S3C2410_DMA) += dma.o
obj-$(CONFIG_S3C2410_IOTIMING) += s3c2410-iotiming.o obj-$(CONFIG_S3C2410_IOTIMING) += s3c2410-iotiming.o
obj-$(CONFIG_S3C2412_IOTIMING) += s3c2412-iotiming.o obj-$(CONFIG_S3C2412_IOTIMING) += s3c2412-iotiming.o
......
arch/arm/plat-s3c24xx/cpu.c
View file @ 32457942
...@@ -49,6 +49,7 @@ ...@@ -49,6 +49,7 @@
#include <plat/s3c2400.h> #include <plat/s3c2400.h>
#include <plat/s3c2410.h> #include <plat/s3c2410.h>
#include <plat/s3c2412.h> #include <plat/s3c2412.h>
#include <plat/s3c2416.h>
#include <plat/s3c244x.h> #include <plat/s3c244x.h>
#include <plat/s3c2443.h> #include <plat/s3c2443.h>
...@@ -57,6 +58,7 @@ ...@@ -57,6 +58,7 @@
static const char name_s3c2400[] = "S3C2400"; static const char name_s3c2400[] = "S3C2400";
static const char name_s3c2410[] = "S3C2410"; static const char name_s3c2410[] = "S3C2410";
static const char name_s3c2412[] = "S3C2412"; static const char name_s3c2412[] = "S3C2412";
static const char name_s3c2416[] = "S3C2416/S3C2450";
static const char name_s3c2440[] = "S3C2440"; static const char name_s3c2440[] = "S3C2440";
static const char name_s3c2442[] = "S3C2442"; static const char name_s3c2442[] = "S3C2442";
static const char name_s3c2442b[] = "S3C2442B"; static const char name_s3c2442b[] = "S3C2442B";
...@@ -137,6 +139,15 @@ static struct cpu_table cpu_ids[] __initdata = { ...@@ -137,6 +139,15 @@ static struct cpu_table cpu_ids[] __initdata = {
.init = s3c2412_init, .init = s3c2412_init,
.name = name_s3c2412, .name = name_s3c2412,
}, },
{ /* a strange version of the s3c2416 */
.idcode = 0x32450003,
.idmask = 0xffffffff,
.map_io = s3c2416_map_io,
.init_clocks = s3c2416_init_clocks,
.init_uarts = s3c2416_init_uarts,
.init = s3c2416_init,
.name = name_s3c2416,
},
{ {
.idcode = 0x32443001, .idcode = 0x32443001,
.idmask = 0xffffffff, .idmask = 0xffffffff,
...@@ -170,6 +181,16 @@ static struct map_desc s3c_iodesc[] __initdata = { ...@@ -170,6 +181,16 @@ static struct map_desc s3c_iodesc[] __initdata = {
static unsigned long s3c24xx_read_idcode_v5(void) static unsigned long s3c24xx_read_idcode_v5(void)
{ {
#if defined(CONFIG_CPU_S3C2416)
/* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
u32 gs = __raw_readl(S3C24XX_GSTATUS1);
/* test for s3c2416 or similar device */
if ((gs >> 16) == 0x3245)
return gs;
#endif
#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
return __raw_readl(S3C2412_GSTATUS1); return __raw_readl(S3C2412_GSTATUS1);
#else #else
......
arch/arm/plat-s3c24xx/include/plat/pll.h
View file @ 32457942
...@@ -35,3 +35,28 @@ s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk) ...@@ -35,3 +35,28 @@ s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk)
return (unsigned int)fvco; return (unsigned int)fvco;
} }
#define S3C2416_PLL_M_SHIFT (14)
#define S3C2416_PLL_P_SHIFT (5)
#define S3C2416_PLL_S_MASK (7)
#define S3C2416_PLL_M_MASK ((1 << 10) - 1)
#define S3C2416_PLL_P_MASK (63)
static inline unsigned int
s3c2416_get_pll(unsigned int pllval, unsigned int baseclk)
{
unsigned int m, p, s;
uint64_t fvco;
m = pllval >> S3C2416_PLL_M_SHIFT;
p = pllval >> S3C2416_PLL_P_SHIFT;
s = pllval & S3C2416_PLL_S_MASK;
m &= S3C2416_PLL_M_MASK;
p &= S3C2416_PLL_P_MASK;
fvco = (uint64_t)baseclk * m;
do_div(fvco, (p << s));
return (unsigned int)fvco;
}
arch/arm/plat-s3c24xx/include/plat/s3c2416.h 0 → 100644
View file @ 32457942
/* linux/include/asm-arm/plat-s3c24xx/s3c2443.h
*
* Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>
*
* Header file for s3c2416 cpu support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifdef CONFIG_CPU_S3C2416
struct s3c2410_uartcfg;
extern int s3c2416_init(void);
extern void s3c2416_map_io(void);
extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no);
extern void s3c2416_init_clocks(int xtal);
extern int s3c2416_baseclk_add(void);
#else
#define s3c2416_init_clocks NULL
#define s3c2416_init_uarts NULL
#define s3c2416_map_io NULL
#define s3c2416_init NULL
#endif
arch/arm/plat-s3c24xx/include/plat/s3c2443.h
View file @ 32457942
...@@ -30,3 +30,22 @@ extern int s3c2443_baseclk_add(void); ...@@ -30,3 +30,22 @@ extern int s3c2443_baseclk_add(void);
#define s3c2443_map_io NULL #define s3c2443_map_io NULL
#define s3c2443_init NULL #define s3c2443_init NULL
#endif #endif
/* common code used by s3c2443 and others.
* note, not to be used outside of arch/arm/mach-s3c* */
struct clk; /* some files don't need clk.h otherwise */
typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base);
typedef unsigned int (*fdiv_fn)(unsigned long clkcon0);
extern void s3c2443_common_setup_clocks(pll_fn get_mpll, fdiv_fn fdiv);
extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, fdiv_fn fdiv);
extern int s3c2443_clkcon_enable_h(struct clk *clk, int enable);
extern int s3c2443_clkcon_enable_p(struct clk *clk, int enable);
extern int s3c2443_clkcon_enable_s(struct clk *clk, int enable);
extern struct clksrc_clk clk_epllref;
extern struct clksrc_clk clk_esysclk;
extern struct clksrc_clk clk_msysclk;
arch/arm/plat-s3c24xx/s3c2410-clock.c
View file @ 32457942
...@@ -87,7 +87,7 @@ static int s3c2410_upll_enable(struct clk *clk, int enable) ...@@ -87,7 +87,7 @@ static int s3c2410_upll_enable(struct clk *clk, int enable)
/* standard clock definitions */ /* standard clock definitions */
static struct clk init_clocks_disable[] = { static struct clk init_clocks_off[] = {
{ {
.name = "nand", .name = "nand",
.id = -1, .id = -1,
...@@ -249,17 +249,8 @@ int __init s3c2410_baseclk_add(void) ...@@ -249,17 +249,8 @@ int __init s3c2410_baseclk_add(void)
/* install (and disable) the clocks we do not need immediately */ /* install (and disable) the clocks we do not need immediately */
clkp = init_clocks_disable; s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
ret = s3c24xx_register_clock(clkp);
if (ret < 0) {
printk(KERN_ERR "Failed to register clock %s (%d)\n",
clkp->name, ret);
}
s3c2410_clkcon_enable(clkp, 0);
}
/* show the clock-slow value */ /* show the clock-slow value */
......
arch/arm/plat-s3c24xx/s3c2443-clock.c 0 → 100644
View file @ 32457942
/* linux/arch/arm/plat-s3c24xx/s3c2443-clock.c
*
* Copyright (c) 2007, 2010 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2443 Clock control suport - common code
*/
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <mach/regs-s3c2443-clock.h>
#include <plat/s3c2443.h>
#include <plat/clock.h>
#include <plat/clock-clksrc.h>
#include <plat/cpu.h>
#include <plat/cpu-freq.h>
static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable)
{
u32 ctrlbit = clk->ctrlbit;
u32 con = __raw_readl(reg);
if (enable)
con |= ctrlbit;
else
con &= ~ctrlbit;
__raw_writel(con, reg);
return 0;
}
int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
{
return s3c2443_gate(S3C2443_HCLKCON, clk, enable);
}
int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
{
return s3c2443_gate(S3C2443_PCLKCON, clk, enable);
}
int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
{
return s3c2443_gate(S3C2443_SCLKCON, clk, enable);
}
/* mpllref is a direct descendant of clk_xtal by default, but it is not
* elided as the EPLL can be either sourced by the XTAL or EXTCLK and as
* such directly equating the two source clocks is impossible.
*/
struct clk clk_mpllref = {
.name = "mpllref",
.parent = &clk_xtal,
.id = -1,
};
static struct clk *clk_epllref_sources[] = {
[0] = &clk_mpllref,
[1] = &clk_mpllref,
[2] = &clk_xtal,
[3] = &clk_ext,
};
struct clksrc_clk clk_epllref = {
.clk = {
.name = "epllref",
.id = -1,
},
.sources = &(struct clksrc_sources) {
.sources = clk_epllref_sources,
.nr_sources = ARRAY_SIZE(clk_epllref_sources),
},
.reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 },
};
/* esysclk
*
* this is sourced from either the EPLL or the EPLLref clock
*/
static struct clk *clk_sysclk_sources[] = {
[0] = &clk_epllref.clk,
[1] = &clk_epll,
};
struct clksrc_clk clk_esysclk = {
.clk = {
.name = "esysclk",
.parent = &clk_epll,
.id = -1,
},
.sources = &(struct clksrc_sources) {
.sources = clk_sysclk_sources,
.nr_sources = ARRAY_SIZE(clk_sysclk_sources),
},
.reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 },
};
static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
{
unsigned long parent_rate = clk_get_rate(clk->parent);
unsigned long div = __raw_readl(S3C2443_CLKDIV0);
div &= S3C2443_CLKDIV0_EXTDIV_MASK;
div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1); /* x2 */
return parent_rate / (div + 1);
}
static struct clk clk_mdivclk = {
.name = "mdivclk",
.parent = &clk_mpllref,
.id = -1,
.ops = &(struct clk_ops) {
.get_rate = s3c2443_getrate_mdivclk,
},
};
static struct clk *clk_msysclk_sources[] = {
[0] = &clk_mpllref,
[1] = &clk_mpll,
[2] = &clk_mdivclk,
[3] = &clk_mpllref,
};
struct clksrc_clk clk_msysclk = {
.clk = {
.name = "msysclk",
.parent = &clk_xtal,
.id = -1,
},
.sources = &(struct clksrc_sources) {
.sources = clk_msysclk_sources,
.nr_sources = ARRAY_SIZE(clk_msysclk_sources),
},
.reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 },
};
/* prediv
*
* this divides the msysclk down to pass to h/p/etc.
*/
static unsigned long s3c2443_prediv_getrate(struct clk *clk)
{
unsigned long rate = clk_get_rate(clk->parent);
unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK;
clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
return rate / (clkdiv0 + 1);
}
static struct clk clk_prediv = {
.name = "prediv",
.id = -1,
.parent = &clk_msysclk.clk,
.ops = &(struct clk_ops) {
.get_rate = s3c2443_prediv_getrate,
},
};
/* usbhost
*
* usb host bus-clock, usually 48MHz to provide USB bus clock timing
*/
static struct clksrc_clk clk_usb_bus_host = {
.clk = {
.name = "usb-bus-host-parent",
.id = -1,
.parent = &clk_esysclk.clk,
.ctrlbit = S3C2443_SCLKCON_USBHOST,
.enable = s3c2443_clkcon_enable_s,
},
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
};
/* common clksrc clocks */
static struct clksrc_clk clksrc_clks[] = {
{
/* ART baud-rate clock sourced from esysclk via a divisor */
.clk = {
.name = "uartclk",
.id = -1,
.parent = &clk_esysclk.clk,
},
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
}, {
/* camera interface bus-clock, divided down from esysclk */
.clk = {
.name = "camif-upll", /* same as 2440 name */
.id = -1,
.parent = &clk_esysclk.clk,
.ctrlbit = S3C2443_SCLKCON_CAMCLK,
.enable = s3c2443_clkcon_enable_s,
},
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 },
}, {
.clk = {
.name = "display-if",
.id = -1,
.parent = &clk_esysclk.clk,
.ctrlbit = S3C2443_SCLKCON_DISPCLK,
.enable = s3c2443_clkcon_enable_s,
},
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 },
},
};
static struct clk init_clocks_off[] = {
{
.name = "adc",
.id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_ADC,
}, {
.name = "i2c",
.id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_IIC,
}
};
static struct clk init_clocks[] = {
{
.name = "dma",
.id = 0,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA0,
}, {
.name = "dma",
.id = 1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA1,
}, {
.name = "dma",
.id = 2,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA2,
}, {
.name = "dma",
.id = 3,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA3,
}, {
.name = "dma",
.id = 4,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA4,
}, {
.name = "dma",
.id = 5,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA5,
}, {
.name = "hsmmc",
.id = 0,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_HSMMC,
}, {
.name = "gpio",
.id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_GPIO,
}, {
.name = "usb-host",
.id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_USBH,
}, {
.name = "usb-device",
.id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_USBD,
}, {
.name = "lcd",
.id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_LCDC,
}, {
.name = "timers",
.id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_PWMT,
}, {
.name = "cfc",
.id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_CFC,
}, {
.name = "ssmc",
.id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_SSMC,
}, {
.name = "uart",
.id = 0,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_UART0,
}, {
.name = "uart",
.id = 1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_UART1,
}, {
.name = "uart",
.id = 2,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_UART2,
}, {
.name = "uart",
.id = 3,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_UART3,
}, {
.name = "rtc",
.id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_RTC,
}, {
.name = "watchdog",
.id = -1,
.parent = &clk_p,
.ctrlbit = S3C2443_PCLKCON_WDT,
}, {
.name = "ac97",
.id = -1,
.parent = &clk_p,
.ctrlbit = S3C2443_PCLKCON_AC97,
}, {
.name = "nand",
.id = -1,
.parent = &clk_h,
}, {
.name = "usb-bus-host",
.id = -1,
.parent = &clk_usb_bus_host.clk,
}
};
static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
{
clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
return clkcon0 + 1;
}
/* EPLLCON compatible enough to get on/off information */
void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll,
fdiv_fn get_fdiv)
{
unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
struct clk *xtal_clk;
unsigned long xtal;
unsigned long pll;
unsigned long fclk;
unsigned long hclk;
unsigned long pclk;
int ptr;
xtal_clk = clk_get(NULL, "xtal");
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
pll = get_mpll(mpllcon, xtal);
clk_msysclk.clk.rate = pll;
fclk = pll / get_fdiv(clkdiv0);
hclk = s3c2443_prediv_getrate(&clk_prediv);
hclk /= s3c2443_get_hdiv(clkdiv0);
pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
s3c24xx_setup_clocks(fclk, hclk, pclk);
printk("CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
(mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
print_mhz(pll), print_mhz(fclk),
print_mhz(hclk), print_mhz(pclk));
for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
s3c_set_clksrc(&clksrc_clks[ptr], true);
/* ensure usb bus clock is within correct rate of 48MHz */
if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) {
printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000);
}
printk("CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
(epllcon & S3C2443_PLLCON_OFF) ? "off":"on",
print_mhz(clk_get_rate(&clk_epll)),
print_mhz(clk_get_rate(&clk_usb_bus)));
}
static struct clk *clks[] __initdata = {
&clk_prediv,
&clk_mpllref,
&clk_mdivclk,
&clk_ext,
&clk_epll,
&clk_usb_bus,
};
static struct clksrc_clk *clksrcs[] __initdata = {
&clk_usb_bus_host,
&clk_epllref,
&clk_esysclk,
&clk_msysclk,
};
void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
fdiv_fn get_fdiv)
{
int ptr;
/* s3c2443 parents h and p clocks from prediv */
clk_h.parent = &clk_prediv;
clk_p.parent = &clk_prediv;
clk_usb_bus.parent = &clk_usb_bus_host.clk;
clk_epll.parent = &clk_epllref.clk;
s3c24xx_register_baseclocks(xtal);
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_register_clksrc(clksrcs[ptr], 1);
s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
/* See s3c2443/etc notes on disabling clocks at init time */
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c2443_common_setup_clocks(get_mpll, get_fdiv);
}
arch/arm/plat-samsung/clock.c
View file @ 32457942
...@@ -376,6 +376,21 @@ void __init s3c_register_clocks(struct clk *clkp, int nr_clks) ...@@ -376,6 +376,21 @@ void __init s3c_register_clocks(struct clk *clkp, int nr_clks)
} }
} }
/**
* s3c_disable_clocks() - disable an array of clocks
* @clkp: Pointer to the first clock in the array.
* @nr_clks: Number of clocks to register.
*
* for internal use only at initialisation time. disable the clocks in the
* @clkp array.
*/
void __init s3c_disable_clocks(struct clk *clkp, int nr_clks)
{
for (; nr_clks > 0; nr_clks--, clkp++)
(clkp->enable)(clkp, 0);
}
/* initalise all the clocks */ /* initalise all the clocks */
int __init s3c24xx_register_baseclocks(unsigned long xtal) int __init s3c24xx_register_baseclocks(unsigned long xtal)
......
arch/arm/plat-samsung/dev-fb.c
View file @ 32457942
...@@ -19,7 +19,6 @@ ...@@ -19,7 +19,6 @@
#include <mach/irqs.h> #include <mach/irqs.h>
#include <mach/map.h> #include <mach/map.h>
#include <mach/regs-fb.h>
#include <plat/fb.h> #include <plat/fb.h>
#include <plat/devs.h> #include <plat/devs.h>
......
arch/arm/plat-samsung/include/plat/clock.h
View file @ 32457942
...@@ -92,6 +92,7 @@ extern int s3c24xx_register_clock(struct clk *clk); ...@@ -92,6 +92,7 @@ extern int s3c24xx_register_clock(struct clk *clk);
extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks); extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
extern void s3c_register_clocks(struct clk *clk, int nr_clks); extern void s3c_register_clocks(struct clk *clk, int nr_clks);
extern void s3c_disable_clocks(struct clk *clkp, int nr_clks);
extern int s3c24xx_register_baseclocks(unsigned long xtal); extern int s3c24xx_register_baseclocks(unsigned long xtal);
......
arch/arm/plat-samsung/include/plat/cpu.h
View file @ 32457942
...@@ -73,6 +73,7 @@ extern struct sys_timer s3c24xx_timer; ...@@ -73,6 +73,7 @@ extern struct sys_timer s3c24xx_timer;
extern struct sysdev_class s3c2410_sysclass; extern struct sysdev_class s3c2410_sysclass;
extern struct sysdev_class s3c2410a_sysclass; extern struct sysdev_class s3c2410a_sysclass;
extern struct sysdev_class s3c2412_sysclass; extern struct sysdev_class s3c2412_sysclass;
extern struct sysdev_class s3c2416_sysclass;
extern struct sysdev_class s3c2440_sysclass; extern struct sysdev_class s3c2440_sysclass;
extern struct sysdev_class s3c2442_sysclass; extern struct sysdev_class s3c2442_sysclass;
extern struct sysdev_class s3c2443_sysclass; extern struct sysdev_class s3c2443_sysclass;
......
arch/arm/plat-samsung/include/plat/fb.h
View file @ 32457942
...@@ -15,6 +15,13 @@ ...@@ -15,6 +15,13 @@
#ifndef __PLAT_S3C_FB_H #ifndef __PLAT_S3C_FB_H
#define __PLAT_S3C_FB_H __FILE__ #define __PLAT_S3C_FB_H __FILE__
/* S3C_FB_MAX_WIN
* Set to the maximum number of windows that any of the supported hardware
* can use. Since the platform data uses this for an array size, having it
* set to the maximum of any version of the hardware can do is safe.
*/
#define S3C_FB_MAX_WIN (5)
/** /**
* struct s3c_fb_pd_win - per window setup data * struct s3c_fb_pd_win - per window setup data
* @win_mode: The display parameters to initialise (not for window 0) * @win_mode: The display parameters to initialise (not for window 0)
......
arch/arm/plat-samsung/include/plat/pll6553x.h 0 → 100644
View file @ 32457942
/* arch/arm/plat-samsung/include/plat/pll6553x.h
* partially from arch/arm/mach-s3c64xx/include/mach/pll.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* Samsung PLL6553x PLL code
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* S3C6400 and compatible (S3C2416, etc.) EPLL code */
#define PLL6553X_MDIV_MASK ((1 << (23-16)) - 1)
#define PLL6553X_PDIV_MASK ((1 << (13-8)) - 1)
#define PLL6553X_SDIV_MASK ((1 << (2-0)) - 1)
#define PLL6553X_MDIV_SHIFT (16)
#define PLL6553X_PDIV_SHIFT (8)
#define PLL6553X_SDIV_SHIFT (0)
#define PLL6553X_KDIV_MASK (0xffff)
static inline unsigned long s3c_get_pll6553x(unsigned long baseclk,
u32 pll0, u32 pll1)
{
unsigned long result;
u32 mdiv, pdiv, sdiv, kdiv;
u64 tmp;
mdiv = (pll0 >> PLL6553X_MDIV_SHIFT) & PLL6553X_MDIV_MASK;
pdiv = (pll0 >> PLL6553X_PDIV_SHIFT) & PLL6553X_PDIV_MASK;
sdiv = (pll0 >> PLL6553X_SDIV_SHIFT) & PLL6553X_SDIV_MASK;
kdiv = pll1 & PLL6553X_KDIV_MASK;
/* We need to multiple baseclk by mdiv (the integer part) and kdiv
* which is in 2^16ths, so shift mdiv up (does not overflow) and
* add kdiv before multiplying. The use of tmp is to avoid any
* overflows before shifting bac down into result when multipling
* by the mdiv and kdiv pair.
*/
tmp = baseclk;
tmp *= (mdiv << 16) + kdiv;
do_div(tmp, (pdiv << sdiv));
result = tmp >> 16;
return result;
}
drivers/serial/Kconfig
View file @ 32457942
...@@ -518,12 +518,13 @@ config SERIAL_S3C2412 ...@@ -518,12 +518,13 @@ config SERIAL_S3C2412
Serial port support for the Samsung S3C2412 and S3C2413 SoC Serial port support for the Samsung S3C2412 and S3C2413 SoC
config SERIAL_S3C2440 config SERIAL_S3C2440
tristate "Samsung S3C2440/S3C2442 Serial port support" tristate "Samsung S3C2440/S3C2442/S3C2416 Serial port support"
depends on SERIAL_SAMSUNG && (CPU_S3C2440 || CPU_S3C2442) depends on SERIAL_SAMSUNG && (CPU_S3C2440 || CPU_S3C2442 || CPU_S3C2416)
default y if CPU_S3C2440 default y if CPU_S3C2440
default y if CPU_S3C2442 default y if CPU_S3C2442
select SERIAL_SAMSUNG_UARTS_4 if CPU_S3C2416
help help
Serial port support for the Samsung S3C2440 and S3C2442 SoC Serial port support for the Samsung S3C2440, S3C2416 and S3C2442 SoC
config SERIAL_S3C24A0 config SERIAL_S3C24A0
tristate "Samsung S3C24A0 Serial port support" tristate "Samsung S3C24A0 Serial port support"
......
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