Commit 32db09d9 authored by Aneesh Kumar K.V's avatar Aneesh Kumar K.V Committed by Michael Ellerman

powerpc/pmem: Add new instructions for persistent storage and sync

POWER10 introduces two new variants of dcbf instructions (dcbstps and dcbfps)
that can be used to write modified locations back to persistent storage.

Additionally, POWER10 also introduce phwsync and plwsync which can be used
to establish order of these writes to persistent storage.

This patch exposes these instructions to the rest of the kernel. The existing
dcbf and hwsync instructions in P8 and P9 are adequate to enable appropriate
synchronization with OpenCAPI-hosted persistent storage. Hence the new
instructions are added as a variant of the old ones that old hardware
won't differentiate.
Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200701072235.223558-3-aneesh.kumar@linux.ibm.com
parent c8304019
...@@ -219,6 +219,8 @@ ...@@ -219,6 +219,8 @@
#define PPC_INST_STWCX 0x7c00012d #define PPC_INST_STWCX 0x7c00012d
#define PPC_INST_LWSYNC 0x7c2004ac #define PPC_INST_LWSYNC 0x7c2004ac
#define PPC_INST_SYNC 0x7c0004ac #define PPC_INST_SYNC 0x7c0004ac
#define PPC_INST_PHWSYNC 0x7c8004ac
#define PPC_INST_PLWSYNC 0x7ca004ac
#define PPC_INST_SYNC_MASK 0xfc0007fe #define PPC_INST_SYNC_MASK 0xfc0007fe
#define PPC_INST_ISYNC 0x4c00012c #define PPC_INST_ISYNC 0x4c00012c
#define PPC_INST_LXVD2X 0x7c000698 #define PPC_INST_LXVD2X 0x7c000698
...@@ -284,6 +286,8 @@ ...@@ -284,6 +286,8 @@
#define PPC_INST_TABORT 0x7c00071d #define PPC_INST_TABORT 0x7c00071d
#define PPC_INST_TSR 0x7c0005dd #define PPC_INST_TSR 0x7c0005dd
#define PPC_INST_DCBF 0x7c0000ac
#define PPC_INST_NAP 0x4c000364 #define PPC_INST_NAP 0x4c000364
#define PPC_INST_SLEEP 0x4c0003a4 #define PPC_INST_SLEEP 0x4c0003a4
#define PPC_INST_WINKLE 0x4c0003e4 #define PPC_INST_WINKLE 0x4c0003e4
...@@ -533,6 +537,14 @@ ...@@ -533,6 +537,14 @@
#define STBCIX(s,a,b) stringify_in_c(.long PPC_INST_STBCIX | \ #define STBCIX(s,a,b) stringify_in_c(.long PPC_INST_STBCIX | \
__PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b)) __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
#define PPC_DCBFPS(a, b) stringify_in_c(.long PPC_INST_DCBF | \
___PPC_RA(a) | ___PPC_RB(b) | (4 << 21))
#define PPC_DCBSTPS(a, b) stringify_in_c(.long PPC_INST_DCBF | \
___PPC_RA(a) | ___PPC_RB(b) | (6 << 21))
#define PPC_PHWSYNC stringify_in_c(.long PPC_INST_PHWSYNC)
#define PPC_PLWSYNC stringify_in_c(.long PPC_INST_PLWSYNC)
/* /*
* Define what the VSX XX1 form instructions will look like, then add * Define what the VSX XX1 form instructions will look like, then add
* the 128 bit load store instructions based on that. * the 128 bit load store instructions based on that.
......
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