Commit 35c638d0 authored by Stephan Gerhold's avatar Stephan Gerhold Committed by Mark Brown

ASoC: qdsp6: Suggest more generic node names

Change the listed examples to use more generic node names, representing
the class of the device nodes:

  - apr-service@<id>
  - dai@<id>

Both names are already in use in arch/arm64/boot/dts/qcom/sdm845.dtsi.

Also add #address-cells + #size-cells to the q6asm example,
without them the example produces dtc warnings.
Signed-off-by: default avatarStephan Gerhold <stephan@gerhold.net>
Reviewed-by: default avatarSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20200415081159.1098-1-stephan@gerhold.netSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent 217a5879
...@@ -29,7 +29,7 @@ used by the apr service device. ...@@ -29,7 +29,7 @@ used by the apr service device.
Definition: Must be 0 Definition: Must be 0
= EXAMPLE = EXAMPLE
q6adm@8 { apr-service@8 {
compatible = "qcom,q6adm"; compatible = "qcom,q6adm";
reg = <APR_SVC_ADM>; reg = <APR_SVC_ADM>;
q6routing: routing { q6routing: routing {
......
...@@ -100,7 +100,7 @@ configuration of each dai. Must contain the following properties. ...@@ -100,7 +100,7 @@ configuration of each dai. Must contain the following properties.
= EXAMPLE = EXAMPLE
q6afe@4 { apr-service@4 {
compatible = "qcom,q6afe"; compatible = "qcom,q6afe";
reg = <APR_SVC_AFE>; reg = <APR_SVC_AFE>;
...@@ -110,12 +110,12 @@ q6afe@4 { ...@@ -110,12 +110,12 @@ q6afe@4 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
hdmi@1 { dai@1 {
reg = <1>; reg = <HDMI_RX>;
}; };
tdm@24 { dai@24 {
reg = <24>; reg = <PRIMARY_TDM_RX_0>;
qcom,tdm-sync-mode = <1>: qcom,tdm-sync-mode = <1>:
qcom,tdm-sync-src = <1>; qcom,tdm-sync-src = <1>;
qcom,tdm-data-out = <0>; qcom,tdm-data-out = <0>;
...@@ -125,8 +125,8 @@ q6afe@4 { ...@@ -125,8 +125,8 @@ q6afe@4 {
}; };
tdm@25 { dai@25 {
reg = <25>; reg = <PRIMARY_TDM_TX_0>;
qcom,tdm-sync-mode = <1>: qcom,tdm-sync-mode = <1>:
qcom,tdm-sync-src = <1>; qcom,tdm-sync-src = <1>;
qcom,tdm-data-out = <0>; qcom,tdm-data-out = <0>;
...@@ -135,43 +135,43 @@ q6afe@4 { ...@@ -135,43 +135,43 @@ q6afe@4 {
qcom,tdm-data-align = <0>; qcom,tdm-data-align = <0>;
}; };
prim-mi2s-rx@16 { dai@16 {
reg = <16>; reg = <PRIMARY_MI2S_RX>;
qcom,sd-lines = <0 2>; qcom,sd-lines = <0 2>;
}; };
prim-mi2s-tx@17 { dai@17 {
reg = <17>; reg = <PRIMARY_MI2S_TX>;
qcom,sd-lines = <1>; qcom,sd-lines = <1>;
}; };
sec-mi2s-rx@18 { dai@18 {
reg = <18>; reg = <SECONDARY_MI2S_RX>;
qcom,sd-lines = <0 3>; qcom,sd-lines = <0 3>;
}; };
sec-mi2s-tx@19 { dai@19 {
reg = <19>; reg = <SECONDARY_MI2S_TX>;
qcom,sd-lines = <1>; qcom,sd-lines = <1>;
}; };
tert-mi2s-rx@20 { dai@20 {
reg = <20>; reg = <TERTIARY_MI2S_RX>;
qcom,sd-lines = <1 3>; qcom,sd-lines = <1 3>;
}; };
tert-mi2s-tx@21 { dai@21 {
reg = <21>; reg = <TERTIARY_MI2S_TX>;
qcom,sd-lines = <0>; qcom,sd-lines = <0>;
}; };
quat-mi2s-rx@22 { dai@22 {
reg = <22>; reg = <QUATERNARY_MI2S_RX>;
qcom,sd-lines = <0>; qcom,sd-lines = <0>;
}; };
quat-mi2s-tx@23 { dai@23 {
reg = <23>; reg = <QUATERNARY_MI2S_TX>;
qcom,sd-lines = <1>; qcom,sd-lines = <1>;
}; };
}; };
......
...@@ -51,13 +51,16 @@ configuration of each dai. Must contain the following properties. ...@@ -51,13 +51,16 @@ configuration of each dai. Must contain the following properties.
= EXAMPLE = EXAMPLE
q6asm@7 { apr-service@7 {
compatible = "qcom,q6asm"; compatible = "qcom,q6asm";
reg = <APR_SVC_ASM>; reg = <APR_SVC_ASM>;
q6asmdai: dais { q6asmdai: dais {
compatible = "qcom,q6asm-dais"; compatible = "qcom,q6asm-dais";
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <1>; #sound-dai-cells = <1>;
mm@0 {
dai@0 {
reg = <0>; reg = <0>;
direction = <2>; direction = <2>;
is-compress-dai; is-compress-dai;
......
...@@ -15,7 +15,7 @@ used by the apr service device. ...@@ -15,7 +15,7 @@ used by the apr service device.
example "qcom,q6core-v2.0" example "qcom,q6core-v2.0"
= EXAMPLE = EXAMPLE
q6core@3 { apr-service@3 {
compatible = "qcom,q6core"; compatible = "qcom,q6core";
reg = <APR_SVC_ADSP_CORE>; reg = <APR_SVC_ADSP_CORE>;
}; };
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