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Commit 38b2df95 authored by Devin Heitmueller's avatar Devin Heitmueller Committed by Mauro Carvalho Chehab
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[media] drx-j: add a driver for Trident drx-j frontend 

Add support for the Trident DRX-J driver, including a card profile for the
PCTV 80e which uses the chip.

Thanks to Trident for allowing the release of this code under a BSD license,
and of course Hauppauge/PCTV for pushing for its release to the community.

[pdickeybeta@gmail.com: modified to fix compilation errors and also to move
 the driver files from the drx39xy subdirectory to the frontends directory]

[m.chehab@samsung.com: fix merge conflicts, commented drx-j compilation and
 added EM28XX_R06_I2C_CLK setup also to the board setup]
Signed-off-by: default avatarDevin Heitmueller <dheitmueller@kernellabs.com>
Signed-off-by: default avatarMauro Carvalho Chehab <m.chehab@samsung.com>
parent 4872b46b
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Documentation/video4linux/CARDLIST.em28xx
View file @ 38b2df95
......@@ -57,6 +57,7 @@
56 -> Pinnacle Hybrid Pro (330e) (em2882) [2304:0226]
57 -> Kworld PlusTV HD Hybrid 330 (em2883) [eb1a:a316]
58 -> Compro VideoMate ForYou/Stereo (em2820/em2840) [185b:2041]
59 -> Pinnacle PCTV HD Mini (em2874) [2304:023f]
60 -> Hauppauge WinTV HVR 850 (em2883) [2040:651f]
61 -> Pixelview PlayTV Box 4 USB 2.0 (em2820/em2840)
62 -> Gadmei TVR200 (em2820/em2840)
......
drivers/media/dvb-frontends/Kconfig
View file @ 38b2df95
......@@ -650,6 +650,8 @@ config DVB_TUNER_DIB0090
comment "SEC control devices for DVB-S"
depends on DVB_CORE
source "drivers/media/dvb-frontends/drx39xyj/Kconfig"
config DVB_LNBP21
tristate "LNBP21/LNBH24 SEC controllers"
depends on DVB_CORE && I2C
......
drivers/media/dvb-frontends/Makefile
View file @ 38b2df95
......@@ -92,6 +92,7 @@ obj-$(CONFIG_DVB_HD29L2) += hd29l2.o
obj-$(CONFIG_DVB_DS3000) += ds3000.o
obj-$(CONFIG_DVB_TS2020) += ts2020.o
obj-$(CONFIG_DVB_MB86A16) += mb86a16.o
obj-$(CONFIG_DVB_DRX39XYJ) += drx39xyj/
obj-$(CONFIG_DVB_MB86A20S) += mb86a20s.o
obj-$(CONFIG_DVB_IX2505V) += ix2505v.o
obj-$(CONFIG_DVB_STV0367) += stv0367.o
......
drivers/media/dvb-frontends/drx39xyj/Kconfig 0 → 100644
View file @ 38b2df95
config DVB_DRX39XYJ
tristate "Micronas DRX-J demodulator"
depends on DVB_CORE && I2C
default m if DVB_FE_CUSTOMISE
depends on BROKEN
help
An ATSC 8VSB and QAM64/256 tuner module. Say Y when you want
to support this frontend.
drivers/media/dvb-frontends/drx39xyj/Makefile 0 → 100644
View file @ 38b2df95
drx39xyj-objs := drx39xxj.o drx_driver.o drx39xxj_dummy.o drxj.o drx_dap_fasi.o
obj-$(CONFIG_DVB_DRX39XYJ) += drx39xyj.o
drivers/media/dvb-frontends/drx39xyj/bsp_host.h 0 → 100644
View file @ 38b2df95
/**
* \file $Id: bsp_host.h,v 1.3 2009/07/07 14:20:30 justin Exp $
*
* \brief Host and OS dependent type definitions, macro's and functions
*
*/
/*
* $(c) 2004-2005,2007-2009 Trident Microsystems, Inc. - All rights reserved.
*
* This software and related documentation (the 'Software') are intellectual
* property owned by Trident and are copyright of Trident, unless specifically
* noted otherwise.
*
* Any use of the Software is permitted only pursuant to the terms of the
* license agreement, if any, which accompanies, is included with or applicable
* to the Software ('License Agreement') or upon express written consent of
* Trident. Any copying, reproduction or redistribution of the Software in
* whole or in part by any means not in accordance with the License Agreement
* or as agreed in writing by Trident is expressly prohibited.
*
* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE
* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE
* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND
* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES
* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT
* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY
* TO USE THE SOFTWARE.
*
* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL,
* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION,
* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS
* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE
* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM
* TRIDENT'S NEGLIGENCE. $
*
*/
#ifndef __DRXBSP_HOST_H__
#define __DRXBSP_HOST_H__
/*-------------------------------------------------------------------------
INCLUDES
-------------------------------------------------------------------------*/
#include "bsp_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/*-------------------------------------------------------------------------
TYPEDEFS
-------------------------------------------------------------------------*/
/*-------------------------------------------------------------------------
DEFINES
-------------------------------------------------------------------------*/
/*-------------------------------------------------------------------------
Exported FUNCTIONS
-------------------------------------------------------------------------*/
DRXStatus_t DRXBSP_HST_Init( void );
DRXStatus_t DRXBSP_HST_Term( void );
void* DRXBSP_HST_Memcpy( void *to, void *from, u32_t n);
int DRXBSP_HST_Memcmp( void *s1, void *s2, u32_t n);
u32_t DRXBSP_HST_Clock( void );
DRXStatus_t DRXBSP_HST_Sleep( u32_t n );
/*-------------------------------------------------------------------------
THE END
-------------------------------------------------------------------------*/
#ifdef __cplusplus
}
#endif
#endif /* __DRXBSP_HOST_H__ */
drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h 0 → 100644
View file @ 38b2df95
/**
* \file $Id: bsp_i2c.h,v 1.5 2009/07/07 14:20:30 justin Exp $
*
* \brief I2C API, implementation depends on board specifics
*
* This module encapsulates I2C access.In some applications several devices
* share one I2C bus. If these devices have the same I2C address some kind
* off "switch" must be implemented to ensure error free communication with
* one device. In case such a "switch" is used, the device ID can be used
* to implement control over this "switch".
*
*
*/
/*
* $(c) 2004-2005,2008-2009 Trident Microsystems, Inc. - All rights reserved.
*
* This software and related documentation (the 'Software') are intellectual
* property owned by Trident and are copyright of Trident, unless specifically
* noted otherwise.
*
* Any use of the Software is permitted only pursuant to the terms of the
* license agreement, if any, which accompanies, is included with or applicable
* to the Software ('License Agreement') or upon express written consent of
* Trident. Any copying, reproduction or redistribution of the Software in
* whole or in part by any means not in accordance with the License Agreement
* or as agreed in writing by Trident is expressly prohibited.
*
* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE
* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE
* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND
* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES
* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT
* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY
* TO USE THE SOFTWARE.
*
* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL,
* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION,
* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS
* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE
* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM
* TRIDENT'S NEGLIGENCE. $
*
*/
#ifndef __BSPI2C_H__
#define __BSPI2C_H__
/*------------------------------------------------------------------------------
INCLUDES
------------------------------------------------------------------------------*/
#include "bsp_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------
TYPEDEFS
------------------------------------------------------------------------------*/
/**
* \typedef I2Caddr_t
* \brief I2C device address (7-bit or 10-bit)
*/
typedef u16_t I2Caddr_t;
/**
* \typedef I2CdevId_t
* \brief Device identifier.
*
* The device ID can be useful if several devices share an I2C address,
* or if multiple I2C busses are used.
* It can be used to control a "switch" selecting the correct device and/or
* I2C bus.
*
*/
typedef u16_t I2CdevId_t;
/**
* \struct _I2CDeviceAddr_t
* \brief I2C device parameters.
*
* This structure contains the I2C address, the device ID and a userData pointer.
* The userData pointer can be used for application specific purposes.
*
*/
struct _I2CDeviceAddr_t {
I2Caddr_t i2cAddr; /**< The I2C address of the device. */
I2CdevId_t i2cDevId; /**< The device identifier. */
void *userData; /**< User data pointer */
};
/**
* \typedef I2CDeviceAddr_t
* \brief I2C device parameters.
*
* This structure contains the I2C address and the device ID.
*
*/
typedef struct _I2CDeviceAddr_t I2CDeviceAddr_t;
/**
* \typedef pI2CDeviceAddr_t
* \brief Pointer to I2C device parameters.
*/
typedef I2CDeviceAddr_t *pI2CDeviceAddr_t;
/*------------------------------------------------------------------------------
DEFINES
------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------
MACROS
------------------------------------------------------------------------------*/
/**
* \def IS_I2C_10BIT( addr )
* \brief Determine if I2C address 'addr' is a 10 bits address or not.
* \param addr The I2C address.
* \return int.
* \retval 0 if address is not a 10 bits I2C address.
* \retval 1 if address is a 10 bits I2C address.
*/
#define IS_I2C_10BIT(addr) \
(((addr) & 0xF8) == 0xF0)
/*------------------------------------------------------------------------------
ENUM
------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------
STRUCTS
------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------
Exported FUNCTIONS
------------------------------------------------------------------------------*/
/**
* \fn DRXBSP_I2C_Init()
* \brief Initialize I2C communication module.
* \return DRXStatus_t Return status.
* \retval DRX_STS_OK Initialization successful.
* \retval DRX_STS_ERROR Initialization failed.
*/
DRXStatus_t DRXBSP_I2C_Init( void );
/**
* \fn DRXBSP_I2C_Term()
* \brief Terminate I2C communication module.
* \return DRXStatus_t Return status.
* \retval DRX_STS_OK Termination successful.
* \retval DRX_STS_ERROR Termination failed.
*/
DRXStatus_t DRXBSP_I2C_Term( void );
/**
* \fn DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr,
* u16_t wCount,
* pu8_t wData,
* pI2CDeviceAddr_t rDevAddr,
* u16_t rCount,
* pu8_t rData)
* \brief Read and/or write count bytes from I2C bus, store them in data[].
* \param wDevAddr The device i2c address and the device ID to write to
* \param wCount The number of bytes to write
* \param wData The array to write the data to
* \param rDevAddr The device i2c address and the device ID to read from
* \param rCount The number of bytes to read
* \param rData The array to read the data from
* \return DRXStatus_t Return status.
* \retval DRX_STS_OK Succes.
* \retval DRX_STS_ERROR Failure.
* \retval DRX_STS_INVALID_ARG Parameter 'wcount' is not zero but parameter
* 'wdata' contains NULL.
* Idem for 'rcount' and 'rdata'.
* Both wDevAddr and rDevAddr are NULL.
*
* This function must implement an atomic write and/or read action on the I2C bus
* No other process may use the I2C bus when this function is executing.
* The critical section of this function runs from and including the I2C
* write, up to and including the I2C read action.
*
* The device ID can be useful if several devices share an I2C address.
* It can be used to control a "switch" on the I2C bus to the correct device.
*/
DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr,
u16_t wCount,
pu8_t wData,
pI2CDeviceAddr_t rDevAddr,
u16_t rCount,
pu8_t rData);
/**
* \fn DRXBSP_I2C_ErrorText()
* \brief Returns a human readable error.
* Counter part of numerical DRX_I2C_Error_g.
*
* \return char* Pointer to human readable error text.
*/
char* DRXBSP_I2C_ErrorText( void );
/**
* \var DRX_I2C_Error_g;
* \brief I2C specific error codes, platform dependent.
*/
extern int DRX_I2C_Error_g;
/*------------------------------------------------------------------------------
THE END
------------------------------------------------------------------------------*/
#ifdef __cplusplus
}
#endif
#endif /* __BSPI2C_H__ */
drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h 0 → 100644
View file @ 38b2df95
/**
* \file $Id: bsp_tuner.h,v 1.5 2009/10/19 22:15:13 dingtao Exp $
*
* \brief Tuner dependable type definitions, macro's and functions
*
*/
/*
* $(c) 2004-2006,2008-2009 Trident Microsystems, Inc. - All rights reserved.
*
* This software and related documentation (the 'Software') are intellectual
* property owned by Trident and are copyright of Trident, unless specifically
* noted otherwise.
*
* Any use of the Software is permitted only pursuant to the terms of the
* license agreement, if any, which accompanies, is included with or applicable
* to the Software ('License Agreement') or upon express written consent of
* Trident. Any copying, reproduction or redistribution of the Software in
* whole or in part by any means not in accordance with the License Agreement
* or as agreed in writing by Trident is expressly prohibited.
*
* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE
* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE
* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND
* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES
* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT
* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY
* TO USE THE SOFTWARE.
*
* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL,
* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION,
* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS
* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE
* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM
* TRIDENT'S NEGLIGENCE. $
*
*/
#ifndef __DRXBSP_TUNER_H__
#define __DRXBSP_TUNER_H__
/*------------------------------------------------------------------------------
INCLUDES
------------------------------------------------------------------------------*/
#include "bsp_types.h"
#include "bsp_i2c.h"
#ifdef __cplusplus
extern "C" {
#endif
/*------------------------------------------------------------------------------
DEFINES
------------------------------------------------------------------------------*/
/* Sub-mode bits should be adjacent and incremental */
#define TUNER_MODE_SUB0 0x0001 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB1 0x0002 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB2 0x0004 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB3 0x0008 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB4 0x0010 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB5 0x0020 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB6 0x0040 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB7 0x0080 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_DIGITAL 0x0100 /* for digital channel (e.g. DVB-T) */
#define TUNER_MODE_ANALOG 0x0200 /* for analog channel (e.g. PAL) */
#define TUNER_MODE_SWITCH 0x0400 /* during channel switch & scanning */
#define TUNER_MODE_LOCK 0x0800 /* after tuner has locked */
#define TUNER_MODE_6MHZ 0x1000 /* for 6MHz bandwidth channels */
#define TUNER_MODE_7MHZ 0x2000 /* for 7MHz bandwidth channels */
#define TUNER_MODE_8MHZ 0x4000 /* for 8MHz bandwidth channels */
#define TUNER_MODE_SUB_MAX 8
#define TUNER_MODE_SUBALL ( TUNER_MODE_SUB0 | TUNER_MODE_SUB1 | \
TUNER_MODE_SUB2 | TUNER_MODE_SUB3 | \
TUNER_MODE_SUB4 | TUNER_MODE_SUB5 | \
TUNER_MODE_SUB6 | TUNER_MODE_SUB7 )
/*------------------------------------------------------------------------------
TYPEDEFS
------------------------------------------------------------------------------*/
typedef u32_t TUNERMode_t;
typedef pu32_t pTUNERMode_t;
typedef char* TUNERSubMode_t; /* description of submode */
typedef TUNERSubMode_t *pTUNERSubMode_t;
typedef enum {
TUNER_LOCKED,
TUNER_NOT_LOCKED
} TUNERLockStatus_t, *pTUNERLockStatus_t;
typedef struct {
char *name; /* Tuner brand & type name */
DRXFrequency_t minFreqRF; /* Lowest RF input frequency, in kHz */
DRXFrequency_t maxFreqRF; /* Highest RF input frequency, in kHz */
u8_t subMode; /* Index to sub-mode in use */
pTUNERSubMode_t subModeDescriptions; /* Pointer to description of sub-modes*/
u8_t subModes; /* Number of available sub-modes */
/* The following fields will be either 0, NULL or FALSE and do not need
initialisation */
void *selfCheck; /* gives proof of initialization */
Bool_t programmed; /* only valid if selfCheck is OK */
DRXFrequency_t RFfrequency; /* only valid if programmed */
DRXFrequency_t IFfrequency; /* only valid if programmed */
void* myUserData; /* pointer to associated demod instance */
u16_t myCapabilities; /* value for storing application flags */
} TUNERCommonAttr_t, *pTUNERCommonAttr_t;
/*
* Generic functions for DRX devices.
*/
typedef struct TUNERInstance_s *pTUNERInstance_t;
typedef DRXStatus_t (*TUNEROpenFunc_t)( pTUNERInstance_t tuner );
typedef DRXStatus_t (*TUNERCloseFunc_t)( pTUNERInstance_t tuner );
typedef DRXStatus_t (*TUNERSetFrequencyFunc_t)( pTUNERInstance_t tuner,
TUNERMode_t mode,
DRXFrequency_t frequency );
typedef DRXStatus_t (*TUNERGetFrequencyFunc_t)( pTUNERInstance_t tuner,
TUNERMode_t mode,
pDRXFrequency_t RFfrequency,
pDRXFrequency_t IFfrequency );
typedef DRXStatus_t (*TUNERLockStatusFunc_t)( pTUNERInstance_t tuner,
pTUNERLockStatus_t lockStat );
typedef DRXStatus_t (*TUNERi2cWriteReadFunc_t)( pTUNERInstance_t tuner,
pI2CDeviceAddr_t wDevAddr,
u16_t wCount,
pu8_t wData,
pI2CDeviceAddr_t rDevAddr,
u16_t rCount,
pu8_t rData );
typedef struct
{
TUNEROpenFunc_t openFunc;
TUNERCloseFunc_t closeFunc;
TUNERSetFrequencyFunc_t setFrequencyFunc;
TUNERGetFrequencyFunc_t getFrequencyFunc;
TUNERLockStatusFunc_t lockStatusFunc;
TUNERi2cWriteReadFunc_t i2cWriteReadFunc;
} TUNERFunc_t, *pTUNERFunc_t;
typedef struct TUNERInstance_s {
I2CDeviceAddr_t myI2CDevAddr;
pTUNERCommonAttr_t myCommonAttr;
void* myExtAttr;
pTUNERFunc_t myFunct;
} TUNERInstance_t;
/*------------------------------------------------------------------------------
ENUM
------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------
STRUCTS
------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------
Exported FUNCTIONS
------------------------------------------------------------------------------*/
DRXStatus_t DRXBSP_TUNER_Open( pTUNERInstance_t tuner );
DRXStatus_t DRXBSP_TUNER_Close( pTUNERInstance_t tuner );
DRXStatus_t DRXBSP_TUNER_SetFrequency( pTUNERInstance_t tuner,
TUNERMode_t mode,
DRXFrequency_t frequency );
DRXStatus_t DRXBSP_TUNER_GetFrequency( pTUNERInstance_t tuner,
TUNERMode_t mode,
pDRXFrequency_t RFfrequency,
pDRXFrequency_t IFfrequency );
DRXStatus_t DRXBSP_TUNER_LockStatus( pTUNERInstance_t tuner,
pTUNERLockStatus_t lockStat );
DRXStatus_t DRXBSP_TUNER_DefaultI2CWriteRead( pTUNERInstance_t tuner,
pI2CDeviceAddr_t wDevAddr,
u16_t wCount,
pu8_t wData,
pI2CDeviceAddr_t rDevAddr,
u16_t rCount,
pu8_t rData);
/*------------------------------------------------------------------------------
THE END
------------------------------------------------------------------------------*/
#ifdef __cplusplus
}
#endif
#endif /* __DRXBSP_TUNER_H__ */
/* End of file */
drivers/media/dvb-frontends/drx39xyj/bsp_types.h 0 → 100644
View file @ 38b2df95
/**
* \file $Id: bsp_types.h,v 1.5 2009/08/06 12:55:57 carlo Exp $
*
* \brief General type definitions for board support packages
*
* This file contains type definitions that are needed for almost any
* board support package.
* The definitions are host and project independent.
*
*/
/*
* $(c) 2004-2006,2008-2009 Trident Microsystems, Inc. - All rights reserved.
*
* This software and related documentation (the 'Software') are intellectual
* property owned by Trident and are copyright of Trident, unless specifically
* noted otherwise.
*
* Any use of the Software is permitted only pursuant to the terms of the
* license agreement, if any, which accompanies, is included with or applicable
* to the Software ('License Agreement') or upon express written consent of
* Trident. Any copying, reproduction or redistribution of the Software in
* whole or in part by any means not in accordance with the License Agreement
* or as agreed in writing by Trident is expressly prohibited.
*
* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE
* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE
* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND
* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES
* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT
* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY
* TO USE THE SOFTWARE.
*
* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL,
* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION,
* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS
* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE
* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM
* TRIDENT'S NEGLIGENCE. $
*
*/
#ifndef __BSP_TYPES_H__
#define __BSP_TYPES_H__
/*-------------------------------------------------------------------------
INCLUDES
-------------------------------------------------------------------------*/
#ifdef __cplusplus
extern "C" {
#endif
/*-------------------------------------------------------------------------
TYPEDEFS
-------------------------------------------------------------------------*/
/**
* \typedef unsigned char u8_t
* \brief type definition of an unsigned 8 bits integer
*/
typedef unsigned char u8_t;
/**
* \typedef char s8_t
* \brief type definition of a signed 8 bits integer
*/
typedef char s8_t;
/**
* \typedef unsigned short u16_t *pu16_t
* \brief type definition of an unsigned 16 bits integer
*/
typedef unsigned short u16_t;
/**
* \typedef short s16_t
* \brief type definition of a signed 16 bits integer
*/
typedef short s16_t;
/**
* \typedef unsigned long u32_t
* \brief type definition of an unsigned 32 bits integer
*/
typedef unsigned long u32_t;
/**
* \typedef long s32_t
* \brief type definition of a signed 32 bits integer
*/
typedef long s32_t;
/*
* \typedef struct ... u64_t
* \brief type definition of an usigned 64 bits integer
*/
typedef struct {
u32_t MSLW;
u32_t LSLW;
} u64_t;
/*
* \typedef struct ... i64_t
* \brief type definition of a signed 64 bits integer
*/
typedef struct {
s32_t MSLW;
u32_t LSLW;
} s64_t;
/**
* \typedef u8_t *pu8_t
* \brief type definition of pointer to an unsigned 8 bits integer
*/
typedef u8_t *pu8_t;
/**
* \typedef s8_t *ps8_t
* \brief type definition of pointer to a signed 8 bits integer
*/
typedef s8_t *ps8_t;
/**
* \typedef u16_t *pu16_t
* \brief type definition of pointer to an unsigned 16 bits integer
*/
typedef u16_t *pu16_t;
/**
* \typedef s16_t *ps16_t
* \brief type definition of pointer to a signed 16 bits integer
*/
typedef s16_t *ps16_t;
/**
* \typedef u32_t *pu32_t
* \brief type definition of pointer to an unsigned 32 bits integer
*/
typedef u32_t *pu32_t;
/**
* \typedef s32_t *ps32_t
* \brief type definition of pointer to a signed 32 bits integer
*/
typedef s32_t *ps32_t;
/**
* \typedef u64_t *pu64_t
* \brief type definition of pointer to an usigned 64 bits integer
*/
typedef u64_t *pu64_t;
/**
* \typedef s64_t *ps64_t
* \brief type definition of pointer to a signed 64 bits integer
*/
typedef s64_t *ps64_t;
/**
* \typedef s32_t DRXFrequency_t
* \brief type definition of frequency
*/
typedef s32_t DRXFrequency_t;
/**
* \typedef DRXFrequency_t *pDRXFrequency_t
* \brief type definition of a pointer to a frequency
*/
typedef DRXFrequency_t *pDRXFrequency_t;
/**
* \typedef u32_t DRXSymbolrate_t
* \brief type definition of symbol rate
*/
typedef u32_t DRXSymbolrate_t;
/**
* \typedef DRXSymbolrate_t *pDRXSymbolrate_t
* \brief type definition of a pointer to a symbol rate
*/
typedef DRXSymbolrate_t *pDRXSymbolrate_t;
/*-------------------------------------------------------------------------
DEFINES
-------------------------------------------------------------------------*/
/**
* \def NULL
* \brief Define NULL for target.
*/
#ifndef NULL
#define NULL (0)
#endif
/*-------------------------------------------------------------------------
ENUM
-------------------------------------------------------------------------*/
/*
* Boolean datatype. Only define if not already defined TRUE or FALSE.
*/
#if defined (TRUE) || defined (FALSE)
typedef int Bool_t;
#else
/**
* \enum Bool_t
* \brief Boolean type
*/
typedef enum {
FALSE = 0,
TRUE
} Bool_t;
#endif
typedef Bool_t *pBool_t;
/**
* \enum DRXStatus_t
* \brief Various return statusses
*/
typedef enum {
DRX_STS_READY = 3, /**< device/service is ready */
DRX_STS_BUSY = 2, /**< device/service is busy */
DRX_STS_OK = 1, /**< everything is OK */
DRX_STS_INVALID_ARG = -1, /**< invalid arguments */
DRX_STS_ERROR = -2, /**< general error */
DRX_STS_FUNC_NOT_AVAILABLE = -3 /**< unavailable functionality */
} DRXStatus_t, *pDRXStatus_t;
/*-------------------------------------------------------------------------
STRUCTS
-------------------------------------------------------------------------*/
/**
Exported FUNCTIONS
-------------------------------------------------------------------------*/
/*-------------------------------------------------------------------------
THE END
-------------------------------------------------------------------------*/
#ifdef __cplusplus
}
#endif
#endif /* __BSP_TYPES_H__ */
drivers/media/dvb-frontends/drx39xyj/drx39xxj.c 0 → 100644
View file @ 38b2df95
/*
* Driver for Micronas DRX39xx family (drx3933j)
*
* Written by Devin Heitmueller <devin.heitmueller@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/slab.h>
#include "dvb_frontend.h"
#include "drx39xxj.h"
#include "drx_driver.h"
#include "bsp_types.h"
#include "bsp_tuner.h"
#include "drxj_mc.h"
#include "drxj.h"
static int drx39xxj_set_powerstate(struct dvb_frontend* fe, int enable)
{
struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
DRXStatus_t result;
DRXPowerMode_t powerMode;
if (enable)
powerMode = DRX_POWER_UP;
else
powerMode = DRX_POWER_DOWN;
result = DRX_Ctrl(demod, DRX_CTRL_POWER_MODE, &powerMode);
if (result != DRX_STS_OK) {
printk("Power state change failed\n");
return 0;
}
state->powered_up = enable;
return 0;
}
static int drx39xxj_read_status(struct dvb_frontend* fe, fe_status_t* status)
{
struct drx39xxj_state* state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
DRXStatus_t result;
DRXLockStatus_t lock_status;
*status = 0;
result = DRX_Ctrl(demod, DRX_CTRL_LOCK_STATUS, &lock_status);
if (result != DRX_STS_OK) {
printk("drx39xxj: could not get lock status!\n");
*status = 0;
}
switch (lock_status) {
case DRX_NEVER_LOCK:
*status = 0;
printk("drx says NEVER_LOCK\n");
break;
case DRX_NOT_LOCKED:
*status = 0;
break;
case DRX_LOCK_STATE_1:
case DRX_LOCK_STATE_2:
case DRX_LOCK_STATE_3:
case DRX_LOCK_STATE_4:
case DRX_LOCK_STATE_5:
case DRX_LOCK_STATE_6:
case DRX_LOCK_STATE_7:
case DRX_LOCK_STATE_8:
case DRX_LOCK_STATE_9:
*status = FE_HAS_SIGNAL
| FE_HAS_CARRIER
| FE_HAS_VITERBI
| FE_HAS_SYNC;
break;
case DRX_LOCKED:
*status = FE_HAS_SIGNAL
| FE_HAS_CARRIER
| FE_HAS_VITERBI
| FE_HAS_SYNC
| FE_HAS_LOCK;
break;
default:
printk("Lock state unknown %d\n", lock_status);
}
return 0;
}
static int drx39xxj_read_ber(struct dvb_frontend* fe, u32* ber)
{
struct drx39xxj_state* state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
DRXStatus_t result;
DRXSigQuality_t sig_quality;
result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality);
if (result != DRX_STS_OK) {
printk("drx39xxj: could not get ber!\n");
*ber = 0;
return 0;
}
*ber = sig_quality.postReedSolomonBER;
return 0;
}
static int drx39xxj_read_signal_strength(struct dvb_frontend* fe, u16* strength)
{
struct drx39xxj_state* state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
DRXStatus_t result;
DRXSigQuality_t sig_quality;
result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality);
if (result != DRX_STS_OK) {
printk("drx39xxj: could not get signal strength!\n");
*strength = 0;
return 0;
}
/* 1-100% scaled to 0-65535 */
*strength = (sig_quality.indicator * 65535 / 100);
return 0;
}
static int drx39xxj_read_snr(struct dvb_frontend* fe, u16* snr)
{
struct drx39xxj_state* state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
DRXStatus_t result;
DRXSigQuality_t sig_quality;
result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality);
if (result != DRX_STS_OK) {
printk("drx39xxj: could not read snr!\n");
*snr = 0;
return 0;
}
*snr = sig_quality.MER;
return 0;
}
static int drx39xxj_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
{
struct drx39xxj_state* state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
DRXStatus_t result;
DRXSigQuality_t sig_quality;
result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality);
if (result != DRX_STS_OK) {
printk("drx39xxj: could not get uc blocks!\n");
*ucblocks = 0;
return 0;
}
*ucblocks = sig_quality.packetError;
return 0;
}
static int drx39xxj_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
{
return 0;
}
static int drx39xxj_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
{
#ifdef DJH_DEBUG
int i;
#endif
struct drx39xxj_state* state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
DRXStandard_t standard = DRX_STANDARD_8VSB;
DRXChannel_t channel;
DRXStatus_t result;
DRXUIOData_t uioData;
DRXChannel_t defChannel = {/* frequency */ 0,
/* bandwidth */ DRX_BANDWIDTH_6MHZ,
/* mirror */ DRX_MIRROR_NO,
/* constellation */ DRX_CONSTELLATION_AUTO,
/* hierarchy */ DRX_HIERARCHY_UNKNOWN,
/* priority */ DRX_PRIORITY_UNKNOWN,
/* coderate */ DRX_CODERATE_UNKNOWN,
/* guard */ DRX_GUARD_UNKNOWN,
/* fftmode */ DRX_FFTMODE_UNKNOWN,
/* classification */ DRX_CLASSIFICATION_AUTO,
/* symbolrate */ 5057000,
/* interleavemode */ DRX_INTERLEAVEMODE_UNKNOWN,
/* ldpc */ DRX_LDPC_UNKNOWN,
/* carrier */ DRX_CARRIER_UNKNOWN,
/* frame mode */ DRX_FRAMEMODE_UNKNOWN
};
/* Bring the demod out of sleep */
drx39xxj_set_powerstate(fe, 1);
/* Now make the tuner do it's thing... */
if (fe->ops.tuner_ops.set_params) {
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1);
fe->ops.tuner_ops.set_params(fe, p);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0);
}
if (standard != state->current_standard || state->powered_up == 0) {
/* Set the standard (will be powered up if necessary */
result = DRX_Ctrl(demod, DRX_CTRL_SET_STANDARD, &standard);
if (result != DRX_STS_OK) {
printk("Failed to set standard! result=%02x\n", result);
return -EINVAL;
}
state->powered_up = 1;
state->current_standard = standard;
}
/* set channel parameters */
channel = defChannel;
channel.frequency = p->frequency / 1000;
channel.bandwidth = DRX_BANDWIDTH_6MHZ;
channel.constellation = DRX_CONSTELLATION_AUTO;
/* program channel */
result = DRX_Ctrl(demod, DRX_CTRL_SET_CHANNEL, &channel);
if (result != DRX_STS_OK) {
printk("Failed to set channel!\n");
return -EINVAL;
}
// Just for giggles, let's shut off the LNA again....
uioData.uio = DRX_UIO1;
uioData.value = FALSE;
result = DRX_Ctrl(demod, DRX_CTRL_UIO_WRITE, &uioData);
if (result != DRX_STS_OK) {
printk("Failed to disable LNA!\n");
return 0;
}
#ifdef DJH_DEBUG
for(i = 0; i < 2000; i++) {
fe_status_t status;
drx39xxj_read_status(fe, &status);
printk("i=%d status=%d\n", i, status);
msleep(100);
i += 100;
}
#endif
return 0;
}
static int drx39xxj_sleep(struct dvb_frontend* fe)
{
/* power-down the demodulator */
return drx39xxj_set_powerstate(fe, 0);
}
static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
Bool_t i2c_gate_state;
DRXStatus_t result;
#ifdef DJH_DEBUG
printk("i2c gate call: enable=%d state=%d\n", enable,
state->i2c_gate_open);
#endif
if (enable)
i2c_gate_state = TRUE;
else
i2c_gate_state = FALSE;
if (state->i2c_gate_open == enable) {
/* We're already in the desired state */
return 0;
}
result = DRX_Ctrl(demod, DRX_CTRL_I2C_BRIDGE, &i2c_gate_state);
if (result != DRX_STS_OK) {
printk("drx39xxj: could not open i2c gate [%d]\n", result);
dump_stack();
} else {
state->i2c_gate_open = enable;
}
return 0;
}
static int drx39xxj_init(struct dvb_frontend* fe)
{
/* Bring the demod out of sleep */
drx39xxj_set_powerstate(fe, 1);
return 0;
}
static int drx39xxj_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *tune)
{
tune->min_delay_ms = 1000;
return 0;
}
static void drx39xxj_release(struct dvb_frontend* fe)
{
struct drx39xxj_state* state = fe->demodulator_priv;
kfree(state);
}
static struct dvb_frontend_ops drx39xxj_ops;
struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c)
{
struct drx39xxj_state* state = NULL;
I2CDeviceAddr_t *demodAddr = NULL;
DRXCommonAttr_t *demodCommAttr = NULL;
DRXJData_t *demodExtAttr = NULL;
DRXDemodInstance_t *demod = NULL;
DRXUIOCfg_t uioCfg;
DRXUIOData_t uioData;
DRXStatus_t result;
/* allocate memory for the internal state */
state = kmalloc(sizeof(struct drx39xxj_state), GFP_KERNEL);
if (state == NULL) goto error;
demod = kmalloc(sizeof(DRXDemodInstance_t), GFP_KERNEL);
if (demod == NULL) goto error;
demodAddr = kmalloc(sizeof(I2CDeviceAddr_t), GFP_KERNEL);
if (demodAddr == NULL) goto error;
demodCommAttr = kmalloc(sizeof(DRXCommonAttr_t), GFP_KERNEL);
if (demodCommAttr == NULL) goto error;
demodExtAttr = kmalloc(sizeof(DRXJData_t), GFP_KERNEL);
if (demodExtAttr == NULL) goto error;
/* setup the state */
state->i2c = i2c;
state->demod = demod;
memcpy(demod, &DRXJDefaultDemod_g, sizeof(DRXDemodInstance_t));
demod->myI2CDevAddr = demodAddr;
memcpy(demod->myI2CDevAddr, &DRXJDefaultAddr_g,
sizeof(I2CDeviceAddr_t));
demod->myI2CDevAddr->userData = state;
demod->myCommonAttr = demodCommAttr;
memcpy(demod->myCommonAttr, &DRXJDefaultCommAttr_g,
sizeof(DRXCommonAttr_t));
demod->myCommonAttr->microcode = DRXJ_MC_MAIN;
// demod->myCommonAttr->verifyMicrocode = FALSE;
demod->myCommonAttr->verifyMicrocode = TRUE;
demod->myCommonAttr->intermediateFreq = 5000;
demod->myExtAttr = demodExtAttr;
memcpy(demod->myExtAttr, &DRXJData_g, sizeof(DRXJData_t));
((DRXJData_t *) demod->myExtAttr)->uioSmaTxMode = DRX_UIO_MODE_READWRITE;
demod->myTuner = NULL;
result = DRX_Open(demod);
if (result != DRX_STS_OK) {
printk("DRX open failed! Aborting\n");
kfree(state);
return NULL;
}
/* Turn off the LNA */
uioCfg.uio = DRX_UIO1;
uioCfg.mode = DRX_UIO_MODE_READWRITE;
/* Configure user-I/O #3: enable read/write */
result = DRX_Ctrl(demod, DRX_CTRL_UIO_CFG, &uioCfg);
if (result != DRX_STS_OK) {
printk("Failed to setup LNA GPIO!\n");
return NULL;
}
uioData.uio = DRX_UIO1;
uioData.value = FALSE;
result = DRX_Ctrl(demod, DRX_CTRL_UIO_WRITE, &uioData);
if (result != DRX_STS_OK) {
printk("Failed to disable LNA!\n");
return NULL;
}
/* create dvb_frontend */
memcpy(&state->frontend.ops, &drx39xxj_ops,
sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
return &state->frontend;
error:
if (state != NULL)
kfree(state);
if (demod != NULL)
kfree(demod);
return NULL;
}
static struct dvb_frontend_ops drx39xxj_ops = {
.info = {
.name = "Micronas DRX39xxj family Frontend",
.type = FE_ATSC | FE_QAM,
.frequency_stepsize = 62500,
.frequency_min = 51000000,
.frequency_max = 858000000,
.caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
},
.init = drx39xxj_init,
.i2c_gate_ctrl = drx39xxj_i2c_gate_ctrl,
.sleep = drx39xxj_sleep,
.set_frontend = drx39xxj_set_frontend,
.get_frontend = drx39xxj_get_frontend,
.get_tune_settings = drx39xxj_get_tune_settings,
.read_status = drx39xxj_read_status,
.read_ber = drx39xxj_read_ber,
.read_signal_strength = drx39xxj_read_signal_strength,
.read_snr = drx39xxj_read_snr,
.read_ucblocks = drx39xxj_read_ucblocks,
.release = drx39xxj_release,
};
MODULE_DESCRIPTION("Micronas DRX39xxj Frontend");
MODULE_AUTHOR("Devin Heitmueller");
MODULE_LICENSE("GPL");
EXPORT_SYMBOL(drx39xxj_attach);
drivers/media/dvb-frontends/drx39xyj/drx39xxj.h 0 → 100644
View file @ 38b2df95
/*
* Driver for Micronas DRX39xx family (drx3933j)
*
* Written by Devin Heitmueller <devin.heitmueller@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
*/
#ifndef DRX39XXJ_H
#define DRX39XXJ_H
#include <linux/dvb/frontend.h>
#include "dvb_frontend.h"
#include "drx_driver.h"
struct drx39xxj_state {
struct i2c_adapter *i2c;
DRXDemodInstance_t *demod;
DRXStandard_t current_standard;
struct dvb_frontend frontend;
int powered_up:1;
unsigned int i2c_gate_open:1;
};
extern struct dvb_frontend* drx39xxj_attach(struct i2c_adapter *i2c);
#endif // DVB_DUMMY_FE_H
drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c 0 → 100644
View file @ 38b2df95
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/jiffies.h>
#include <linux/types.h>
#include "drx_driver.h"
#include "bsp_types.h"
#include "bsp_tuner.h"
#include "drx39xxj.h"
/* Dummy function to satisfy drxj.c */
DRXStatus_t DRXBSP_TUNER_Open( pTUNERInstance_t tuner )
{
return DRX_STS_OK;
}
DRXStatus_t DRXBSP_TUNER_Close( pTUNERInstance_t tuner )
{
return DRX_STS_OK;
}
DRXStatus_t DRXBSP_TUNER_SetFrequency( pTUNERInstance_t tuner,
TUNERMode_t mode,
DRXFrequency_t centerFrequency )
{
return DRX_STS_OK;
}
DRXStatus_t
DRXBSP_TUNER_GetFrequency( pTUNERInstance_t tuner,
TUNERMode_t mode,
pDRXFrequency_t RFfrequency,
pDRXFrequency_t IFfrequency )
{
return DRX_STS_OK;
}
DRXStatus_t DRXBSP_HST_Sleep( u32_t n )
{
msleep(n);
return DRX_STS_OK;
}
u32_t DRXBSP_HST_Clock( void )
{
return jiffies_to_msecs(jiffies);
}
int DRXBSP_HST_Memcmp( void *s1, void *s2, u32_t n)
{
return ( memcmp( s1, s2, (size_t) n) );
}
void* DRXBSP_HST_Memcpy( void *to, void *from, u32_t n)
{
return ( memcpy( to, from, (size_t) n) );
}
DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr,
u16_t wCount,
pu8_t wData,
pI2CDeviceAddr_t rDevAddr,
u16_t rCount,
pu8_t rData )
{
struct drx39xxj_state *state;
struct i2c_msg msg[2];
unsigned int num_msgs;
if (wDevAddr == NULL) {
/* Read only */
state = rDevAddr->userData;
msg[0].addr = rDevAddr->i2cAddr >> 1;
msg[0].flags = I2C_M_RD;
msg[0].buf = rData;
msg[0].len = rCount;
num_msgs = 1;
} else if (rDevAddr == NULL) {
/* Write only */
state = wDevAddr->userData;
msg[0].addr = wDevAddr->i2cAddr >> 1;
msg[0].flags = 0;
msg[0].buf = wData;
msg[0].len = wCount;
num_msgs = 1;
} else {
/* Both write and read */
state = wDevAddr->userData;
msg[0].addr = wDevAddr->i2cAddr >> 1;
msg[0].flags = 0;
msg[0].buf = wData;
msg[0].len = wCount;
msg[1].addr = rDevAddr->i2cAddr >> 1;
msg[1].flags = I2C_M_RD;
msg[1].buf = rData;
msg[1].len = rCount;
num_msgs = 2;
}
if (state->i2c == NULL) {
printk("i2c was zero, aborting\n");
return 0;
}
if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) {
printk(KERN_WARNING "drx3933: I2C write/read failed\n");
return -EREMOTEIO;
}
return DRX_STS_OK;
#ifdef DJH_DEBUG
struct drx39xxj_state *state = wDevAddr->userData;
struct i2c_msg msg[2] = {
{ .addr = wDevAddr->i2cAddr,
.flags = 0, .buf = wData, .len = wCount },
{ .addr = rDevAddr->i2cAddr,
.flags = I2C_M_RD, .buf = rData, .len = rCount },
};
printk("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n",
wDevAddr->i2cAddr, state->i2c, wCount, rCount);
if (i2c_transfer(state->i2c, msg, 2) != 2) {
printk(KERN_WARNING "drx3933: I2C write/read failed\n");
return -EREMOTEIO;
}
#endif
return 0;
}
drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c 0 → 100644
View file @ 38b2df95
/*******************************************************************************
* FILENAME: $Id: drx_dap_fasi.c,v 1.7 2009/12/28 14:36:21 carlo Exp $
*
* DESCRIPTION:
* Part of DRX driver.
* Data access protocol: Fast Access Sequential Interface (fasi)
* Fast access, because of short addressing format (16 instead of 32 bits addr)
* Sequential, because of I2C.
* These functions know how the chip's memory and registers are to be accessed,
* but nothing more.
*
* These functions should not need adapting to a new platform.
*
* USAGE:
* -
*
* NOTES:
* $(c) 2009 Trident Microsystems, Inc. - All rights reserved.
*
* This software and related documentation (the 'Software') are intellectual
* property owned by Trident and are copyright of Trident, unless specifically
* noted otherwise.
*
* Any use of the Software is permitted only pursuant to the terms of the
* license agreement, if any, which accompanies, is included with or applicable
* to the Software ('License Agreement') or upon express written consent of
* Trident. Any copying, reproduction or redistribution of the Software in
* whole or in part by any means not in accordance with the License Agreement
* or as agreed in writing by Trident is expressly prohibited.
*
* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE
* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE
* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND
* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES
* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT
* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY
* TO USE THE SOFTWARE.
*
* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL,
* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION,
* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS
* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE
* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM
* TRIDENT'S NEGLIGENCE. $
*
*
*******************************************************************************/
#include "drx_dap_fasi.h"
#include "bsp_host.h" /* for DRXBSP_HST_Memcpy() */
/*============================================================================*/
/* Function prototypes */
static DRXStatus_t DRXDAP_FASI_WriteBlock (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
u16_t datasize, /* size of data */
pu8_t data, /* data to send */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadBlock (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
u16_t datasize, /* size of data */
pu8_t data, /* data to send */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_WriteReg8 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
u8_t data, /* data to write */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadReg8 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
pu8_t data, /* buffer to receive data */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
u8_t datain, /* data to send */
pu8_t dataout); /* data to receive back */
static DRXStatus_t DRXDAP_FASI_WriteReg16 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
u16_t data, /* data to write */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadReg16 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
pu16_t data, /* buffer to receive data */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
u16_t datain, /* data to send */
pu16_t dataout); /* data to receive back */
static DRXStatus_t DRXDAP_FASI_WriteReg32 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
u32_t data, /* data to write */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadReg32 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
pu32_t data, /* buffer to receive data */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
u32_t datain, /* data to send */
pu32_t dataout); /* data to receive back */
/* The version structure of this protocol implementation */
char drxDapFASIModuleName[] = "FASI Data Access Protocol";
char drxDapFASIVersionText[] = "";
DRXVersion_t drxDapFASIVersion =
{
DRX_MODULE_DAP, /**< type identifier of the module */
drxDapFASIModuleName, /**< name or description of module */
0, /**< major version number */
0, /**< minor version number */
0, /**< patch version number */
drxDapFASIVersionText /**< version as text string */
};
/* The structure containing the protocol interface */
DRXAccessFunc_t drxDapFASIFunct_g =
{
&drxDapFASIVersion,
DRXDAP_FASI_WriteBlock, /* Supported */
DRXDAP_FASI_ReadBlock, /* Supported */
DRXDAP_FASI_WriteReg8, /* Not supported */
DRXDAP_FASI_ReadReg8, /* Not supported */
DRXDAP_FASI_ReadModifyWriteReg8, /* Not supported */
DRXDAP_FASI_WriteReg16, /* Supported */
DRXDAP_FASI_ReadReg16, /* Supported */
DRXDAP_FASI_ReadModifyWriteReg16, /* Supported */
DRXDAP_FASI_WriteReg32, /* Supported */
DRXDAP_FASI_ReadReg32, /* Supported */
DRXDAP_FASI_ReadModifyWriteReg32 /* Not supported */
};
/*============================================================================*/
/* Functions not supported by protocol*/
static DRXStatus_t DRXDAP_FASI_WriteReg8 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
u8_t data, /* data to write */
DRXflags_t flags) /* special device flags */
{
return DRX_STS_ERROR;
}
static DRXStatus_t DRXDAP_FASI_ReadReg8 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
pu8_t data, /* buffer to receive data */
DRXflags_t flags) /* special device flags */
{
return DRX_STS_ERROR;
}
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
u8_t datain, /* data to send */
pu8_t dataout) /* data to receive back */
{
return DRX_STS_ERROR;
}
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
u32_t datain, /* data to send */
pu32_t dataout) /* data to receive back */
{
return DRX_STS_ERROR;
}
/*============================================================================*/
/******************************
*
* DRXStatus_t DRXDAP_FASI_ReadBlock (
* pI2CDeviceAddr_t devAddr, -- address of I2C device
* DRXaddr_t addr, -- address of chip register/memory
* u16_t datasize, -- number of bytes to read
* pu8_t data, -- data to receive
* DRXflags_t flags) -- special device flags
*
* Read block data from chip address. Because the chip is word oriented,
* the number of bytes to read must be even.
*
* Make sure that the buffer to receive the data is large enough.
*
* Although this function expects an even number of bytes, it is still byte
* oriented, and the data read back is NOT translated to the endianness of
* the target platform.
*
* Output:
* - DRX_STS_OK if reading was successful
* in that case: data read is in *data.
* - DRX_STS_ERROR if anything went wrong
*
******************************/
static DRXStatus_t DRXDAP_FASI_ReadBlock ( pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
u16_t datasize,
pu8_t data,
DRXflags_t flags )
{
u8_t buf[4];
u16_t bufx;
DRXStatus_t rc;
u16_t overheadSize = 0;
/* Check parameters ********************************************************/
if ( devAddr == NULL )
{
return DRX_STS_INVALID_ARG;
}
overheadSize = (IS_I2C_10BIT (devAddr->i2cAddr) ? 2 : 1) +
(DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2 );
if ( ( DRXDAP_FASI_OFFSET_TOO_LARGE(addr) ) ||
( ( !(DRXDAPFASI_LONG_ADDR_ALLOWED) ) &&
DRXDAP_FASI_LONG_FORMAT( addr ) ) ||
(overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) ||
((datasize!=0) && (data==NULL)) ||
((datasize & 1)==1 ) )
{
return DRX_STS_INVALID_ARG;
}
/* ReadModifyWrite & mode flag bits are not allowed */
flags &= (~DRXDAP_FASI_RMW & ~DRXDAP_FASI_MODEFLAGS);
#if DRXDAP_SINGLE_MASTER
flags |= DRXDAP_FASI_SINGLE_MASTER;
#endif
/* Read block from I2C *****************************************************/
do {
u16_t todo = ( datasize < DRXDAP_MAX_RCHUNKSIZE ?
datasize : DRXDAP_MAX_RCHUNKSIZE);
bufx = 0;
addr &= ~DRXDAP_FASI_FLAGS;
addr |= flags;
#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \
( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) )
/* short format address preferred but long format otherwise */
if ( DRXDAP_FASI_LONG_FORMAT(addr) )
{
#endif
#if ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 )
buf[bufx++] = (u8_t) (((addr << 1) & 0xFF)|0x01);
buf[bufx++] = (u8_t) ((addr >> 16) & 0xFF);
buf[bufx++] = (u8_t) ((addr >> 24) & 0xFF);
buf[bufx++] = (u8_t) ((addr >> 7) & 0xFF);
#endif
#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \
( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) )
} else {
#endif
#if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 )
buf[bufx++] = (u8_t) ((addr << 1) & 0xFF);
buf[bufx++] = (u8_t) ( ((addr >> 16) & 0x0F) | ((addr >> 18) & 0xF0) );
#endif
#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \
( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) )
}
#endif
#if DRXDAP_SINGLE_MASTER
/*
* In single master mode, split the read and write actions.
* No special action is needed for write chunks here.
*/
rc = DRXBSP_I2C_WriteRead (devAddr, bufx, buf, 0, 0, 0);
if (rc == DRX_STS_OK)
{
rc = DRXBSP_I2C_WriteRead (0, 0, 0, devAddr, todo, data);
}
#else
/* In multi master mode, do everything in one RW action */
rc = DRXBSP_I2C_WriteRead (devAddr, bufx, buf, devAddr, todo, data);
#endif
data += todo;
addr += (todo >> 1);
datasize -= todo;
} while (datasize && rc == DRX_STS_OK);
return rc;
}
/******************************
*
* DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 (
* pI2CDeviceAddr_t devAddr, -- address of I2C device
* DRXaddr_t waddr, -- address of chip register/memory
* DRXaddr_t raddr, -- chip address to read back from
* u16_t wdata, -- data to send
* pu16_t rdata) -- data to receive back
*
* Write 16-bit data, then read back the original contents of that location.
* Requires long addressing format to be allowed.
*
* Before sending data, the data is converted to little endian. The
* data received back is converted back to the target platform's endianness.
*
* WARNING: This function is only guaranteed to work if there is one
* master on the I2C bus.
*
* Output:
* - DRX_STS_OK if reading was successful
* in that case: read back data is at *rdata
* - DRX_STS_ERROR if anything went wrong
*
******************************/
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 ( pI2CDeviceAddr_t devAddr,
DRXaddr_t waddr,
DRXaddr_t raddr,
u16_t wdata,
pu16_t rdata )
{
DRXStatus_t rc=DRX_STS_ERROR;
#if ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 )
if (rdata == NULL)
{
return DRX_STS_INVALID_ARG;
}
rc = DRXDAP_FASI_WriteReg16 (devAddr, waddr, wdata, DRXDAP_FASI_RMW);
if (rc == DRX_STS_OK)
{
rc = DRXDAP_FASI_ReadReg16 (devAddr, raddr, rdata, 0);
}
#endif
return rc;
}
/******************************
*
* DRXStatus_t DRXDAP_FASI_ReadReg16 (
* pI2CDeviceAddr_t devAddr, -- address of I2C device
* DRXaddr_t addr, -- address of chip register/memory
* pu16_t data, -- data to receive
* DRXflags_t flags) -- special device flags
*
* Read one 16-bit register or memory location. The data received back is
* converted back to the target platform's endianness.
*
* Output:
* - DRX_STS_OK if reading was successful
* in that case: read data is at *data
* - DRX_STS_ERROR if anything went wrong
*
******************************/
static DRXStatus_t DRXDAP_FASI_ReadReg16 ( pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
pu16_t data,
DRXflags_t flags )
{
u8_t buf[sizeof (*data)];
DRXStatus_t rc;
if (!data)
{
return DRX_STS_INVALID_ARG;
}
rc = DRXDAP_FASI_ReadBlock (devAddr, addr, sizeof (*data), buf, flags);
*data = buf[0] + (((u16_t) buf[1]) << 8);
return rc;
}
/******************************
*
* DRXStatus_t DRXDAP_FASI_ReadReg32 (
* pI2CDeviceAddr_t devAddr, -- address of I2C device
* DRXaddr_t addr, -- address of chip register/memory
* pu32_t data, -- data to receive
* DRXflags_t flags) -- special device flags
*
* Read one 32-bit register or memory location. The data received back is
* converted back to the target platform's endianness.
*
* Output:
* - DRX_STS_OK if reading was successful
* in that case: read data is at *data
* - DRX_STS_ERROR if anything went wrong
*
******************************/
static DRXStatus_t DRXDAP_FASI_ReadReg32 ( pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
pu32_t data,
DRXflags_t flags )
{
u8_t buf[sizeof (*data)];
DRXStatus_t rc;
if (!data)
{
return DRX_STS_INVALID_ARG;
}
rc = DRXDAP_FASI_ReadBlock (devAddr, addr, sizeof (*data), buf, flags);
*data = (((u32_t) buf[0]) << 0) +
(((u32_t) buf[1]) << 8) +
(((u32_t) buf[2]) << 16) +
(((u32_t) buf[3]) << 24);
return rc;
}
/******************************
*
* DRXStatus_t DRXDAP_FASI_WriteBlock (
* pI2CDeviceAddr_t devAddr, -- address of I2C device
* DRXaddr_t addr, -- address of chip register/memory
* u16_t datasize, -- number of bytes to read
* pu8_t data, -- data to receive
* DRXflags_t flags) -- special device flags
*
* Write block data to chip address. Because the chip is word oriented,
* the number of bytes to write must be even.
*
* Although this function expects an even number of bytes, it is still byte
* oriented, and the data being written is NOT translated from the endianness of
* the target platform.
*
* Output:
* - DRX_STS_OK if writing was successful
* - DRX_STS_ERROR if anything went wrong
*
******************************/
static DRXStatus_t DRXDAP_FASI_WriteBlock ( pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
u16_t datasize,
pu8_t data,
DRXflags_t flags )
{
u8_t buf[ DRXDAP_MAX_WCHUNKSIZE ];
DRXStatus_t st = DRX_STS_ERROR;
DRXStatus_t firstErr = DRX_STS_OK;
u16_t overheadSize = 0;
u16_t blockSize = 0;
/* Check parameters ********************************************************/
if ( devAddr == NULL )
{
return DRX_STS_INVALID_ARG;
}
overheadSize = (IS_I2C_10BIT (devAddr->i2cAddr) ? 2 : 1) +
(DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2 );
if ( ( DRXDAP_FASI_OFFSET_TOO_LARGE(addr) ) ||
( ( !(DRXDAPFASI_LONG_ADDR_ALLOWED) ) &&
DRXDAP_FASI_LONG_FORMAT( addr ) ) ||
(overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) ||
((datasize!=0) && (data==NULL)) ||
((datasize & 1)==1 ) )
{
return DRX_STS_INVALID_ARG;
}
flags &= DRXDAP_FASI_FLAGS;
flags &= ~DRXDAP_FASI_MODEFLAGS;
#if DRXDAP_SINGLE_MASTER
flags |= DRXDAP_FASI_SINGLE_MASTER;
#endif
/* Write block to I2C ******************************************************/
blockSize = ( (DRXDAP_MAX_WCHUNKSIZE) - overheadSize) & ~1;
do
{
u16_t todo = 0;
u16_t bufx = 0;
/* Buffer device address */
addr &= ~DRXDAP_FASI_FLAGS;
addr |= flags;
#if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \
( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) )
/* short format address preferred but long format otherwise */
if ( DRXDAP_FASI_LONG_FORMAT(addr) )
{
#endif
#if ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 )
buf[bufx++] = (u8_t) (((addr << 1) & 0xFF)|0x01);
buf[bufx++] = (u8_t) ((addr >> 16) & 0xFF);
buf[bufx++] = (u8_t) ((addr >> 24) & 0xFF);
buf[bufx++] = (u8_t) ((addr >> 7) & 0xFF);
#endif
#if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \
( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) )
} else {
#endif
#if ( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 )
buf[bufx++] = (u8_t) ((addr << 1) & 0xFF);
buf[bufx++] = (u8_t) ( ((addr >> 16) & 0x0F) | ((addr >> 18) & 0xF0) );
#endif
#if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \
( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) )
}
#endif
/*
In single master mode blockSize can be 0. In such a case this I2C
sequense will be visible: (1) write address {i2c addr,
4 bytes chip address} (2) write data {i2c addr, 4 bytes data }
(3) write address (4) write data etc...
Addres must be rewriten because HI is reset after data transport and
expects an address.
*/
todo = (blockSize < datasize ? blockSize : datasize);
if (todo==0)
{
u16_t overheadSizeI2cAddr = 0;
u16_t dataBlockSize = 0;
overheadSizeI2cAddr = (IS_I2C_10BIT (devAddr->i2cAddr) ? 2 : 1);
dataBlockSize = ( DRXDAP_MAX_WCHUNKSIZE - overheadSizeI2cAddr) & ~1;
/* write device address */
st = DRXBSP_I2C_WriteRead( devAddr,
(u16_t) (bufx),
buf,
(pI2CDeviceAddr_t)(NULL),
0,
(pu8_t)(NULL) );
if ( ( st != DRX_STS_OK ) && ( firstErr == DRX_STS_OK ) )
{
/* at the end, return the first error encountered */
firstErr = st;
}
bufx = 0;
todo = (dataBlockSize < datasize ? dataBlockSize : datasize);
}
DRXBSP_HST_Memcpy (&buf[bufx], data, todo);
/* write (address if can do and) data */
st = DRXBSP_I2C_WriteRead( devAddr,
(u16_t)(bufx + todo),
buf,
(pI2CDeviceAddr_t)(NULL),
0,
(pu8_t)(NULL) );
if ( ( st != DRX_STS_OK ) && ( firstErr == DRX_STS_OK ) )
{
/* at the end, return the first error encountered */
firstErr = st;
}
datasize -= todo;
data += todo;
addr += (todo >> 1);
} while (datasize);
return firstErr;
}
/******************************
*
* DRXStatus_t DRXDAP_FASI_WriteReg16 (
* pI2CDeviceAddr_t devAddr, -- address of I2C device
* DRXaddr_t addr, -- address of chip register/memory
* u16_t data, -- data to send
* DRXflags_t flags) -- special device flags
*
* Write one 16-bit register or memory location. The data being written is
* converted from the target platform's endianness to little endian.
*
* Output:
* - DRX_STS_OK if writing was successful
* - DRX_STS_ERROR if anything went wrong
*
******************************/
static DRXStatus_t DRXDAP_FASI_WriteReg16 ( pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
u16_t data,
DRXflags_t flags )
{
u8_t buf[sizeof (data)];
buf[0] = (u8_t) ( (data >> 0 ) & 0xFF );
buf[1] = (u8_t) ( (data >> 8 ) & 0xFF );
return DRXDAP_FASI_WriteBlock (devAddr, addr, sizeof (data), buf, flags);
}
/******************************
*
* DRXStatus_t DRXDAP_FASI_WriteReg32 (
* pI2CDeviceAddr_t devAddr, -- address of I2C device
* DRXaddr_t addr, -- address of chip register/memory
* u32_t data, -- data to send
* DRXflags_t flags) -- special device flags
*
* Write one 32-bit register or memory location. The data being written is
* converted from the target platform's endianness to little endian.
*
* Output:
* - DRX_STS_OK if writing was successful
* - DRX_STS_ERROR if anything went wrong
*
******************************/
static DRXStatus_t DRXDAP_FASI_WriteReg32 ( pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
u32_t data,
DRXflags_t flags )
{
u8_t buf[sizeof (data)];
buf[0] = (u8_t) ( (data >> 0 ) & 0xFF );
buf[1] = (u8_t) ( (data >> 8 ) & 0xFF );
buf[2] = (u8_t) ( (data >> 16) & 0xFF );
buf[3] = (u8_t) ( (data >> 24) & 0xFF );
return DRXDAP_FASI_WriteBlock (devAddr, addr, sizeof (data), buf, flags);
}
drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h 0 → 100644
View file @ 38b2df95
/*******************************************************************************
* FILENAME: $Id: drx_dap_fasi.h,v 1.5 2009/07/07 14:21:40 justin Exp $
*
* DESCRIPTION:
* Part of DRX driver.
* Data access protocol: Fast Access Sequential Interface (fasi)
* Fast access, because of short addressing format (16 instead of 32 bits addr)
* Sequential, because of I2C.
*
* USAGE:
* Include.
*
* NOTES:
* $(c) 2008-2009 Trident Microsystems, Inc. - All rights reserved.
*
* This software and related documentation (the 'Software') are intellectual
* property owned by Trident and are copyright of Trident, unless specifically
* noted otherwise.
*
* Any use of the Software is permitted only pursuant to the terms of the
* license agreement, if any, which accompanies, is included with or applicable
* to the Software ('License Agreement') or upon express written consent of
* Trident. Any copying, reproduction or redistribution of the Software in
* whole or in part by any means not in accordance with the License Agreement
* or as agreed in writing by Trident is expressly prohibited.
*
* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE
* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE
* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND
* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES
* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT
* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY
* TO USE THE SOFTWARE.
*
* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL,
* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION,
* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS
* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE
* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM
* TRIDENT'S NEGLIGENCE. $
*
*
*******************************************************************************/
/*-------- compilation control switches --------------------------------------*/
#ifndef __DRX_DAP_FASI_H__
#define __DRX_DAP_FASI_H__
/*-------- Required includes -------------------------------------------------*/
#include "drx_driver.h"
/*-------- Defines, configuring the API --------------------------------------*/
/********************************************
* Allowed address formats
********************************************/
/*
* Comments about short/long addressing format:
*
* The DAP FASI offers long address format (4 bytes) and short address format
* (2 bytes). The DAP can operate in 3 modes:
* (1) only short
* (2) only long
* (3) both long and short but short preferred and long only when necesarry
*
* These modes must be selected compile time via compile switches.
* Compile switch settings for the diffrent modes:
* (1) DRXDAPFASI_LONG_ADDR_ALLOWED=0, DRXDAPFASI_SHORT_ADDR_ALLOWED=1
* (2) DRXDAPFASI_LONG_ADDR_ALLOWED=1, DRXDAPFASI_SHORT_ADDR_ALLOWED=0
* (3) DRXDAPFASI_LONG_ADDR_ALLOWED=1, DRXDAPFASI_SHORT_ADDR_ALLOWED=1
*
* The default setting will be (3) both long and short.
* The default setting will need no compile switches.
* The default setting must be overridden if compile switches are already
* defined.
*
*/
/* set default */
#if !defined( DRXDAPFASI_LONG_ADDR_ALLOWED )
#define DRXDAPFASI_LONG_ADDR_ALLOWED 1
#endif
/* set default */
#if !defined( DRXDAPFASI_SHORT_ADDR_ALLOWED )
#define DRXDAPFASI_SHORT_ADDR_ALLOWED 1
#endif
/* check */
#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==0 ) && \
( DRXDAPFASI_SHORT_ADDR_ALLOWED==0 ) )
#error At least one of short- or long-addressing format must be allowed.
*; /* illegal statement to force compiler error */
#endif
/********************************************
* Single/master multi master setting
********************************************/
/*
* Comments about SINGLE MASTER/MULTI MASTER modes:
*
* Consider the two sides:1) the master and 2)the slave.
*
* Master:
* Single/multimaster operation set via DRXDAP_SINGLE_MASTER compile switch
* + single master mode means no use of repeated starts
* + multi master mode means use of repeated starts
* Default is single master.
* Default can be overriden by setting the compile switch DRXDAP_SINGLE_MASTER.
*
* Slave:
* Single/multi master selected via the flags in the FASI protocol.
* + single master means remember memory address between i2c packets
* + multimaster means flush memory address between i2c packets
* Default is single master, DAP FASI changes multi-master setting silently
* into single master setting. This cannot be overrriden.
*
*/
/* set default */
#ifndef DRXDAP_SINGLE_MASTER
#define DRXDAP_SINGLE_MASTER 0
#endif
/********************************************
* Chunk/mode checking
********************************************/
/*
* Comments about DRXDAP_MAX_WCHUNKSIZE in single or multi master mode and
* in combination with short and long addressing format. All text below
* assumes long addressing format. The table also includes information
* for short ADDRessing format.
*
* In single master mode, data can be written by sending the register address
* first, then two or four bytes of data in the next packet.
* Because the device address plus a register address equals five bytes,
* the mimimum chunk size must be five.
* If ten-bit I2C device addresses are used, the minimum chunk size must be six,
* because the I2C device address will then occupy two bytes when writing.
*
* Data in single master mode is transferred as follows:
* <S> <devW> a0 a1 a2 a3 <P>
* <S> <devW> d0 d1 [d2 d3] <P>
* ..
* or
* ..
* <S> <devW> a0 a1 a2 a3 <P>
* <S> <devR> --- <P>
*
* In multi-master mode, the data must immediately follow the address (an I2C
* stop resets the internal address), and hence the minimum chunk size is
* 1 <I2C address> + 4 (register address) + 2 (data to send) = 7 bytes (8 if
* 10-bit I2C device addresses are used).
*
* The 7-bit or 10-bit i2c address parameters is a runtime parameter.
* The other parameters can be limited via compile time switches.
*
*-------------------------------------------------------------------------------
*
* Minimum chunk size table (in bytes):
*
* +----------------+----------------+
* | 7b i2c addr | 10b i2c addr |
* +----------------+----------------+
* | single | multi | single | multi |
* ------+--------+-------+--------+-------+
* short | 3 | 5 | 4 | 6 |
* long | 5 | 7 | 6 | 8 |
* ------+--------+-------+--------+-------+
*
*/
/* set default */
#if !defined( DRXDAP_MAX_WCHUNKSIZE)
#define DRXDAP_MAX_WCHUNKSIZE 254
#endif
/* check */
#if ( (DRXDAPFASI_LONG_ADDR_ALLOWED==0)&&(DRXDAPFASI_SHORT_ADDR_ALLOWED==1) )
#if DRXDAP_SINGLE_MASTER
#define DRXDAP_MAX_WCHUNKSIZE_MIN 3
#else
#define DRXDAP_MAX_WCHUNKSIZE_MIN 5
#endif
#else
#if DRXDAP_SINGLE_MASTER
#define DRXDAP_MAX_WCHUNKSIZE_MIN 5
#else
#define DRXDAP_MAX_WCHUNKSIZE_MIN 7
#endif
#endif
#if DRXDAP_MAX_WCHUNKSIZE < DRXDAP_MAX_WCHUNKSIZE_MIN
#if ( (DRXDAPFASI_LONG_ADDR_ALLOWED==0)&&(DRXDAPFASI_SHORT_ADDR_ALLOWED==1) )
#if DRXDAP_SINGLE_MASTER
#error DRXDAP_MAX_WCHUNKSIZE must be at least 3 in single master mode
*; /* illegal statement to force compiler error */
#else
#error DRXDAP_MAX_WCHUNKSIZE must be at least 5 in multi master mode
*; /* illegal statement to force compiler error */
#endif
#else
#if DRXDAP_SINGLE_MASTER
#error DRXDAP_MAX_WCHUNKSIZE must be at least 5 in single master mode
*; /* illegal statement to force compiler error */
#else
#error DRXDAP_MAX_WCHUNKSIZE must be at least 7 in multi master mode
*; /* illegal statement to force compiler error */
#endif
#endif
#endif
/* set default */
#if !defined( DRXDAP_MAX_RCHUNKSIZE)
#define DRXDAP_MAX_RCHUNKSIZE 254
#endif
/* check */
#if DRXDAP_MAX_RCHUNKSIZE < 2
#error DRXDAP_MAX_RCHUNKSIZE must be at least 2
*; /* illegal statement to force compiler error */
#endif
/* check */
#if DRXDAP_MAX_RCHUNKSIZE & 1
#error DRXDAP_MAX_RCHUNKSIZE must be even
*; /* illegal statement to force compiler error */
#endif
/*-------- Public API functions ----------------------------------------------*/
#ifdef __cplusplus
extern "C" {
#endif
extern DRXAccessFunc_t drxDapFASIFunct_g;
#define DRXDAP_FASI_RMW 0x10000000
#define DRXDAP_FASI_BROADCAST 0x20000000
#define DRXDAP_FASI_CLEARCRC 0x80000000
#define DRXDAP_FASI_SINGLE_MASTER 0xC0000000
#define DRXDAP_FASI_MULTI_MASTER 0x40000000
#define DRXDAP_FASI_SMM_SWITCH 0x40000000 /* single/multi master switch */
#define DRXDAP_FASI_MODEFLAGS 0xC0000000
#define DRXDAP_FASI_FLAGS 0xF0000000
#define DRXDAP_FASI_ADDR2BLOCK( addr ) (((addr)>>22)&0x3F)
#define DRXDAP_FASI_ADDR2BANK( addr ) (((addr)>>16)&0x3F)
#define DRXDAP_FASI_ADDR2OFFSET( addr ) ((addr)&0x7FFF)
#define DRXDAP_FASI_SHORT_FORMAT( addr ) (((addr)& 0xFC30FF80)==0)
#define DRXDAP_FASI_LONG_FORMAT( addr ) (((addr)& 0xFC30FF80)!=0)
#define DRXDAP_FASI_OFFSET_TOO_LARGE( addr ) (((addr)& 0x00008000)!=0)
#ifdef __cplusplus
}
#endif
#endif /* __DRX_DAP_FASI_H__ */
drivers/media/dvb-frontends/drx39xyj/drx_driver.c 0 → 100644
View file @ 38b2df95
/**
* \file $Id: drx_driver.c,v 1.40 2010/01/12 01:24:56 lfeng Exp $
*
* \brief Generic DRX functionality, DRX driver core.
*
* $(c) 2004-2010 Trident Microsystems, Inc. - All rights reserved.
*
* This software and related documentation (the 'Software') are intellectual
* property owned by Trident and are copyright of Trident, unless specifically
* noted otherwise.
*
* Any use of the Software is permitted only pursuant to the terms of the
* license agreement, if any, which accompanies, is included with or applicable
* to the Software ('License Agreement') or upon express written consent of
* Trident. Any copying, reproduction or redistribution of the Software in
* whole or in part by any means not in accordance with the License Agreement
* or as agreed in writing by Trident is expressly prohibited.
*
* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE
* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE
* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND
* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES
* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT
* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY
* TO USE THE SOFTWARE.
*
* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL,
* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION,
* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS
* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE
* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM
* TRIDENT'S NEGLIGENCE. $
*
*/
/*------------------------------------------------------------------------------
INCLUDE FILES
------------------------------------------------------------------------------*/
#include "drx_driver.h"
#include "bsp_host.h"
#define VERSION_FIXED 0
#if VERSION_FIXED
#define VERSION_MAJOR 0
#define VERSION_MINOR 0
#define VERSION_PATCH 0
#else
#include "drx_driver_version.h"
#endif
/*------------------------------------------------------------------------------
DEFINES
------------------------------------------------------------------------------*/
/*============================================================================*/
/*=== MICROCODE RELATED DEFINES ==============================================*/
/*============================================================================*/
/** \brief Magic word for checking correct Endianess of microcode data. */
#ifndef DRX_UCODE_MAGIC_WORD
#define DRX_UCODE_MAGIC_WORD ((((u16_t)'H')<<8)+((u16_t)'L'))
#endif
/** \brief CRC flag in ucode header, flags field. */
#ifndef DRX_UCODE_CRC_FLAG
#define DRX_UCODE_CRC_FLAG (0x0001)
#endif
/** \brief Compression flag in ucode header, flags field. */
#ifndef DRX_UCODE_COMPRESSION_FLAG
#define DRX_UCODE_COMPRESSION_FLAG (0x0002)
#endif
/** \brief Maximum size of buffer used to verify the microcode.
Must be an even number. */
#ifndef DRX_UCODE_MAX_BUF_SIZE
#define DRX_UCODE_MAX_BUF_SIZE (DRXDAP_MAX_RCHUNKSIZE)
#endif
#if DRX_UCODE_MAX_BUF_SIZE & 1
#error DRX_UCODE_MAX_BUF_SIZE must be an even number
#endif
/*============================================================================*/
/*=== CHANNEL SCAN RELATED DEFINES ===========================================*/
/*============================================================================*/
/**
* \brief Maximum progress indication.
*
* Progress indication will run from 0 upto DRX_SCAN_MAX_PROGRESS during scan.
*
*/
#ifndef DRX_SCAN_MAX_PROGRESS
#define DRX_SCAN_MAX_PROGRESS 1000
#endif
/*============================================================================*/
/*=== MACROS =================================================================*/
/*============================================================================*/
#define DRX_ISPOWERDOWNMODE( mode ) ( ( mode == DRX_POWER_MODE_9 ) || \
( mode == DRX_POWER_MODE_10 ) || \
( mode == DRX_POWER_MODE_11 ) || \
( mode == DRX_POWER_MODE_12 ) || \
( mode == DRX_POWER_MODE_13 ) || \
( mode == DRX_POWER_MODE_14 ) || \
( mode == DRX_POWER_MODE_15 ) || \
( mode == DRX_POWER_MODE_16 ) || \
( mode == DRX_POWER_DOWN ) )
/*------------------------------------------------------------------------------
GLOBAL VARIABLES
------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------
STRUCTURES
------------------------------------------------------------------------------*/
/** \brief Structure of the microcode block headers */
typedef struct {
u32_t addr; /**< Destination address of the data in this block */
u16_t size; /**< Size of the block data following this header counted in
16 bits words */
u16_t flags; /**< Flags for this data block:
- bit[0]= CRC on/off
- bit[1]= compression on/off
- bit[15..2]=reserved */
u16_t CRC; /**< CRC value of the data block, only valid if CRC flag is
set. */
} DRXUCodeBlockHdr_t, *pDRXUCodeBlockHdr_t;
/*------------------------------------------------------------------------------
FUNCTIONS
------------------------------------------------------------------------------*/
/*============================================================================*/
/*============================================================================*/
/*== Channel Scan Functions ==================================================*/
/*============================================================================*/
/*============================================================================*/
#ifndef DRX_EXCLUDE_SCAN
/* Prototype of default scanning function */
static DRXStatus_t
ScanFunctionDefault( void *scanContext,
DRXScanCommand_t scanCommand,
pDRXChannel_t scanChannel,
pBool_t getNextChannel );
/**
* \brief Get pointer to scanning function.
* \param demod: Pointer to demodulator instance.
* \return DRXScanFunc_t.
*/
static DRXScanFunc_t
GetScanFunction( pDRXDemodInstance_t demod )
{
pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL);
DRXScanFunc_t scanFunc = (DRXScanFunc_t)(NULL);
/* get scan function from common attributes */
commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr;
scanFunc = commonAttr->scanFunction;
if ( scanFunc != NULL )
{
/* return device-specific scan function if it's not NULL */
return scanFunc;
}
/* otherwise return default scan function in core driver */
return &ScanFunctionDefault;
}
/**
* \brief Get Context pointer.
* \param demod: Pointer to demodulator instance.
* \param scanContext: Context Pointer.
* \return DRXScanFunc_t.
*/
void *GetScanContext( pDRXDemodInstance_t demod,
void *scanContext)
{
pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL);
/* get scan function from common attributes */
commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr;
scanContext = commonAttr->scanContext;
if ( scanContext == NULL )
{
scanContext = (void *) demod;
}
return scanContext;
}
/**
* \brief Wait for lock while scanning.
* \param demod: Pointer to demodulator instance.
* \param lockStat: Pointer to bool indicating if end result is lock or not.
* \return DRXStatus_t.
* \retval DRX_STS_OK: Success
* \retval DRX_STS_ERROR: I2C failure or bsp function failure.
*
* Wait until timeout, desired lock or NEVER_LOCK.
* Assume:
* - lock function returns : at least DRX_NOT_LOCKED and a lock state
* higher than DRX_NOT_LOCKED.
* - BSP has a clock function to retrieve a millisecond ticker value.
* - BSP has a sleep function to enable sleep of n millisecond.
*
* In case DRX_NEVER_LOCK is returned the poll-wait will be aborted.
*
*/
static DRXStatus_t
ScanWaitForLock( pDRXDemodInstance_t demod,
pBool_t isLocked )
{
Bool_t doneWaiting = FALSE;
DRXLockStatus_t lockState = DRX_NOT_LOCKED;
DRXLockStatus_t desiredLockState = DRX_NOT_LOCKED;
u32_t timeoutValue = 0;
u32_t startTimeLockStage = 0;
u32_t currentTime = 0;
u32_t timerValue = 0;
*isLocked = FALSE;
timeoutValue = (u32_t) demod->myCommonAttr->scanDemodLockTimeout;
desiredLockState = demod->myCommonAttr->scanDesiredLock;
startTimeLockStage = DRXBSP_HST_Clock();
/* Start polling loop, checking for lock & timeout */
while ( doneWaiting == FALSE )
{
if ( DRX_Ctrl( demod, DRX_CTRL_LOCK_STATUS, &lockState ) != DRX_STS_OK )
{
return DRX_STS_ERROR;
}
currentTime = DRXBSP_HST_Clock();
timerValue = currentTime - startTimeLockStage;
if ( lockState >= desiredLockState )
{
*isLocked = TRUE;
doneWaiting = TRUE;
} /* if ( lockState >= desiredLockState ) .. */
else if ( lockState == DRX_NEVER_LOCK )
{
doneWaiting = TRUE;
} /* if ( lockState == DRX_NEVER_LOCK ) .. */
else if ( timerValue > timeoutValue )
{
/* lockState == DRX_NOT_LOCKED and timeout */
doneWaiting = TRUE;
}
else
{
if ( DRXBSP_HST_Sleep( 10 ) != DRX_STS_OK )
{
return DRX_STS_ERROR;
}
} /* if ( timerValue > timeoutValue ) .. */
} /* while */
return DRX_STS_OK;
}
/*============================================================================*/
/**
* \brief Determine next frequency to scan.
* \param demod: Pointer to demodulator instance.
* \param skip : Minimum frequency step to take.
* \return DRXStatus_t.
* \retval DRX_STS_OK: Succes.
* \retval DRX_STS_INVALID_ARG: Invalid frequency plan.
*
* Helper function for CtrlScanNext() function.
* Compute next frequency & index in frequency plan.
* Check if scan is ready.
*
*/
static DRXStatus_t
ScanPrepareNextScan ( pDRXDemodInstance_t demod,
DRXFrequency_t skip )
{
pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL);
u16_t tableIndex = 0;
u16_t frequencyPlanSize = 0;
pDRXFrequencyPlan_t frequencyPlan = (pDRXFrequencyPlan_t)(NULL);
DRXFrequency_t nextFrequency = 0;
DRXFrequency_t tunerMinFrequency = 0;
DRXFrequency_t tunerMaxFrequency = 0;
commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr;
tableIndex = commonAttr->scanFreqPlanIndex;
frequencyPlan = commonAttr->scanParam->frequencyPlan;
nextFrequency = commonAttr->scanNextFrequency;
tunerMinFrequency = commonAttr->tunerMinFreqRF;
tunerMaxFrequency = commonAttr->tunerMaxFreqRF;
do
{
/* Search next frequency to scan */
/* always take at least one step */
(commonAttr->scanChannelsScanned) ++;
nextFrequency += frequencyPlan[tableIndex].step;
skip -= frequencyPlan[tableIndex].step;
/* and then as many steps necessary to exceed 'skip'
without exceeding end of the band */
while ( ( skip > 0 ) &&
( nextFrequency <= frequencyPlan[tableIndex].last ) )
{
(commonAttr->scanChannelsScanned) ++;
nextFrequency += frequencyPlan[tableIndex].step;
skip -= frequencyPlan[tableIndex].step;
}
/* reset skip, in case we move to the next band later */
skip = 0;
if ( nextFrequency > frequencyPlan[tableIndex].last )
{
/* reached end of this band */
tableIndex++;
frequencyPlanSize = commonAttr->scanParam->frequencyPlanSize;
if ( tableIndex >= frequencyPlanSize )
{
/* reached end of frequency plan */
commonAttr->scanReady = TRUE;
}
else
{
nextFrequency = frequencyPlan[tableIndex].first;
}
}
if ( nextFrequency > (tunerMaxFrequency) )
{
/* reached end of tuner range */
commonAttr->scanReady = TRUE;
}
} while( ( nextFrequency < tunerMinFrequency ) &&
( commonAttr->scanReady == FALSE ) );
/* Store new values */
commonAttr->scanFreqPlanIndex = tableIndex;
commonAttr->scanNextFrequency = nextFrequency;
return DRX_STS_OK;
}
/*============================================================================*/
/**
* \brief Default DTV scanning function.
*
* \param demod: Pointer to demodulator instance.
* \param scanCommand: Scanning command: INIT, NEXT or STOP.
* \param scanChannel: Channel to check: frequency and bandwidth, others AUTO
* \param getNextChannel: Return TRUE if next frequency is desired at next call
*
* \return DRXStatus_t.
* \retval DRX_STS_OK: Channel found, DRX_CTRL_GET_CHANNEL can be used
* to retrieve channel parameters.
* \retval DRX_STS_BUSY: Channel not found (yet).
* \retval DRX_STS_ERROR: Something went wrong.
*
* scanChannel and getNextChannel will be NULL for INIT and STOP.
*/
static DRXStatus_t
ScanFunctionDefault ( void *scanContext,
DRXScanCommand_t scanCommand,
pDRXChannel_t scanChannel,
pBool_t getNextChannel )
{
pDRXDemodInstance_t demod = NULL;
DRXStatus_t status = DRX_STS_ERROR;
Bool_t isLocked = FALSE;
demod = (pDRXDemodInstance_t) scanContext;
if ( scanCommand != DRX_SCAN_COMMAND_NEXT )
{
/* just return OK if not doing "scan next" */
return DRX_STS_OK;
}
*getNextChannel = FALSE;
status = DRX_Ctrl ( demod, DRX_CTRL_SET_CHANNEL, scanChannel );
if ( status != DRX_STS_OK )
{
return (status);
}
status = ScanWaitForLock ( demod, &isLocked );
if ( status != DRX_STS_OK )
{
return status;
}
/* done with this channel, move to next one */
*getNextChannel = TRUE;
if ( isLocked == FALSE )
{
/* no channel found */
return DRX_STS_BUSY;
}
/* channel found */
return DRX_STS_OK;
}
/*============================================================================*/
/**
* \brief Initialize for channel scan.
* \param demod: Pointer to demodulator instance.
* \param scanParam: Pointer to scan parameters.
* \return DRXStatus_t.
* \retval DRX_STS_OK: Initialized for scan.
* \retval DRX_STS_ERROR: No overlap between frequency plan and tuner
* range.
* \retval DRX_STS_INVALID_ARG: Wrong parameters.
*
* This function should be called before starting a complete channel scan.
* It will prepare everything for a complete channel scan.
* After calling this function the DRX_CTRL_SCAN_NEXT control function can be
* used to perform the actual scanning. Scanning will start at the first
* center frequency of the frequency plan that is within the tuner range.
*
*/
static DRXStatus_t
CtrlScanInit( pDRXDemodInstance_t demod,
pDRXScanParam_t scanParam )
{
DRXStatus_t status = DRX_STS_ERROR;
pDRXCommonAttr_t commonAttr =(pDRXCommonAttr_t)(NULL);
DRXFrequency_t maxTunerFreq = 0;
DRXFrequency_t minTunerFreq = 0;
u16_t nrChannelsInPlan = 0;
u16_t i = 0;
void *scanContext = NULL;
commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr;
commonAttr->scanActive = TRUE;
/* invalidate a previous SCAN_INIT */
commonAttr->scanParam = (pDRXScanParam_t)(NULL);
commonAttr->scanNextFrequency = 0;
/* Check parameters */
if ( ( ( demod->myTuner == NULL ) &&
( scanParam->numTries !=1) ) ||
( scanParam == NULL) ||
( scanParam->numTries == 0) ||
( scanParam->frequencyPlan == NULL) ||
( scanParam->frequencyPlanSize == 0 )
)
{
commonAttr->scanActive = FALSE;
return DRX_STS_INVALID_ARG;
}
/* Check frequency plan contents */
maxTunerFreq = commonAttr->tunerMaxFreqRF;
minTunerFreq = commonAttr->tunerMinFreqRF;
for( i = 0; i < (scanParam->frequencyPlanSize); i++ )
{
DRXFrequency_t width = 0;
DRXFrequency_t step = scanParam->frequencyPlan[i].step;
DRXFrequency_t firstFreq = scanParam->frequencyPlan[i].first;
DRXFrequency_t lastFreq = scanParam->frequencyPlan[i].last;
DRXFrequency_t minFreq = 0;
DRXFrequency_t maxFreq = 0;
if ( step <= 0 )
{
/* Step must be positive and non-zero */
commonAttr->scanActive = FALSE;
return DRX_STS_INVALID_ARG;
}
if ( firstFreq > lastFreq )
{
/* First center frequency is higher than last center frequency */
commonAttr->scanActive = FALSE;
return DRX_STS_INVALID_ARG;
}
width = lastFreq - firstFreq;
if ( ( width % step ) != 0 )
{
/* Difference between last and first center frequency is not
an integer number of steps */
commonAttr->scanActive = FALSE;
return DRX_STS_INVALID_ARG;
}
/* Check if frequency plan entry intersects with tuner range */
if ( lastFreq >= minTunerFreq )
{
if ( firstFreq <= maxTunerFreq )
{
if ( firstFreq >= minTunerFreq )
{
minFreq = firstFreq;
}
else
{
DRXFrequency_t n = 0;
n = ( minTunerFreq - firstFreq ) / step;
if ( ( ( minTunerFreq - firstFreq ) % step ) != 0 )
{
n++;
}
minFreq = firstFreq + n*step;
}
if ( lastFreq <= maxTunerFreq )
{
maxFreq = lastFreq;
}
else
{
DRXFrequency_t n=0;
n=( lastFreq - maxTunerFreq )/step;
if ( (( lastFreq - maxTunerFreq )%step) !=0 )
{
n++;
}
maxFreq = lastFreq - n*step;
}
}
}
/* Keep track of total number of channels within tuner range
in this frequency plan. */
if ( (minFreq !=0 ) && ( maxFreq != 0 ) )
{
nrChannelsInPlan += (u16_t)( ( ( maxFreq-minFreq ) / step ) +1 );
/* Determine first frequency (within tuner range) to scan */
if ( commonAttr->scanNextFrequency == 0 )
{
commonAttr->scanNextFrequency = minFreq;
commonAttr->scanFreqPlanIndex = i;
}
}
}/* for ( ... ) */
if ( nrChannelsInPlan == 0 )
{
/* Tuner range and frequency plan ranges do not overlap */
commonAttr->scanActive = FALSE;
return DRX_STS_ERROR;
}
/* Store parameters */
commonAttr->scanReady = FALSE;
commonAttr->scanMaxChannels = nrChannelsInPlan;
commonAttr->scanChannelsScanned = 0;
commonAttr->scanParam = scanParam; /* SCAN_NEXT is now allowed */
scanContext = GetScanContext(demod, scanContext);
status = (*(GetScanFunction( demod )))
( scanContext, DRX_SCAN_COMMAND_INIT, NULL, NULL );
commonAttr->scanActive = FALSE;
return DRX_STS_OK;
}
/*============================================================================*/
/**
* \brief Stop scanning.
* \param demod: Pointer to demodulator instance.
* \return DRXStatus_t.
* \retval DRX_STS_OK: Scan stopped.
* \retval DRX_STS_ERROR: Something went wrong.
* \retval DRX_STS_INVALID_ARG: Wrong parameters.
*/
static DRXStatus_t
CtrlScanStop( pDRXDemodInstance_t demod )
{
DRXStatus_t status = DRX_STS_ERROR;
pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL);
void *scanContext = NULL;
commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr;
commonAttr->scanActive = TRUE;
if ( ( commonAttr->scanParam == NULL ) ||
( commonAttr->scanMaxChannels == 0 ) )
{
/* Scan was not running, just return OK */
commonAttr->scanActive = FALSE;
return DRX_STS_OK;
}
/* Call default or device-specific scanning stop function */
scanContext = GetScanContext(demod, scanContext);
status = (*(GetScanFunction( demod )))
( scanContext, DRX_SCAN_COMMAND_STOP, NULL, NULL );
/* All done, invalidate scan-init */
commonAttr->scanParam = NULL;
commonAttr->scanMaxChannels = 0;
commonAttr->scanActive = FALSE;
return status;
}
/*============================================================================*/
/**
* \brief Scan for next channel.
* \param demod: Pointer to demodulator instance.
* \param scanProgress: Pointer to scan progress.
* \return DRXStatus_t.
* \retval DRX_STS_OK: Channel found, DRX_CTRL_GET_CHANNEL can be used
* to retrieve channel parameters.
* \retval DRX_STS_BUSY: Tried part of the channels, as specified in
* numTries field of scan parameters. At least one
* more call to DRX_CTRL_SCAN_NEXT is needed to
* complete scanning.
* \retval DRX_STS_READY: Reached end of scan range.
* \retval DRX_STS_ERROR: Something went wrong.
* \retval DRX_STS_INVALID_ARG: Wrong parameters. The scanProgress may be NULL.
*
* Progress indication will run from 0 upto DRX_SCAN_MAX_PROGRESS during scan.
*
*/
static DRXStatus_t
CtrlScanNext ( pDRXDemodInstance_t demod,
pu16_t scanProgress )
{
pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL);
pBool_t scanReady = (pBool_t)(NULL);
u16_t maxProgress = DRX_SCAN_MAX_PROGRESS;
u32_t numTries = 0;
u32_t i = 0;
commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr;
/* Check scan parameters */
if ( scanProgress == NULL )
{
commonAttr->scanActive = FALSE;
return DRX_STS_INVALID_ARG;
}
*scanProgress = 0;
commonAttr->scanActive = TRUE;
if ( ( commonAttr->scanParam == NULL) ||
( commonAttr->scanMaxChannels == 0 ) )
{
/* CtrlScanInit() was not called succesfully before CtrlScanNext() */
commonAttr->scanActive = FALSE;
return DRX_STS_ERROR;
}
*scanProgress = (u16_t)( ( ( commonAttr->scanChannelsScanned)*
( (u32_t)(maxProgress) ) ) /
( commonAttr->scanMaxChannels ) );
/* Scan */
numTries = commonAttr->scanParam->numTries;
scanReady = &(commonAttr->scanReady);
for ( i = 0; ( (i < numTries) && ( (*scanReady) == FALSE) ); i++)
{
DRXChannel_t scanChannel = { 0 };
DRXStatus_t status = DRX_STS_ERROR;
pDRXFrequencyPlan_t freqPlan = (pDRXFrequencyPlan_t) (NULL);
Bool_t nextChannel = FALSE;
void *scanContext = NULL;
/* Next channel to scan */
freqPlan =
&(commonAttr->scanParam->frequencyPlan[commonAttr->scanFreqPlanIndex]);
scanChannel.frequency = commonAttr->scanNextFrequency;
scanChannel.bandwidth = freqPlan->bandwidth;
scanChannel.mirror = DRX_MIRROR_AUTO;
scanChannel.constellation = DRX_CONSTELLATION_AUTO;
scanChannel.hierarchy = DRX_HIERARCHY_AUTO;
scanChannel.priority = DRX_PRIORITY_HIGH;
scanChannel.coderate = DRX_CODERATE_AUTO;
scanChannel.guard = DRX_GUARD_AUTO;
scanChannel.fftmode = DRX_FFTMODE_AUTO;
scanChannel.classification = DRX_CLASSIFICATION_AUTO;
scanChannel.symbolrate = 0;
scanChannel.interleavemode = DRX_INTERLEAVEMODE_AUTO;
scanChannel.ldpc = DRX_LDPC_AUTO;
scanChannel.carrier = DRX_CARRIER_AUTO;
scanChannel.framemode = DRX_FRAMEMODE_AUTO;
scanChannel.pilot = DRX_PILOT_AUTO;
/* Call default or device-specific scanning function */
scanContext = GetScanContext(demod, scanContext);
status = (*(GetScanFunction( demod )))
( scanContext,DRX_SCAN_COMMAND_NEXT,&scanChannel,&nextChannel );
/* Proceed to next channel if requested */
if ( nextChannel == TRUE )
{
DRXStatus_t nextStatus = DRX_STS_ERROR;
DRXFrequency_t skip = 0;
if ( status == DRX_STS_OK )
{
/* a channel was found, so skip some frequency steps */
skip = commonAttr->scanParam->skip;
}
nextStatus = ScanPrepareNextScan( demod, skip );
/* keep track of progress */
*scanProgress = (u16_t)(((commonAttr->scanChannelsScanned)*
((u32_t)(maxProgress)))/
(commonAttr->scanMaxChannels));
if ( nextStatus != DRX_STS_OK )
{
commonAttr->scanActive = FALSE;
return (nextStatus);
}
}
if ( status != DRX_STS_BUSY )
{
/* channel found or error */
commonAttr->scanActive = FALSE;
return status;
}
} /* for ( i = 0; i < ( ... numTries); i++) */
if ( (*scanReady) == TRUE )
{
/* End of scan reached: call stop-scan, ignore any error */
CtrlScanStop( demod );
commonAttr->scanActive = FALSE;
return (DRX_STS_READY);
}
commonAttr->scanActive = FALSE;
return DRX_STS_BUSY;
}
#endif /* #ifndef DRX_EXCLUDE_SCAN */
/*============================================================================*/
/**
* \brief Program tuner.
* \param demod: Pointer to demodulator instance.
* \param tunerChannel: Pointer to tuning parameters.
* \return DRXStatus_t.
* \retval DRX_STS_OK: Tuner programmed successfully.
* \retval DRX_STS_ERROR: Something went wrong.
* \retval DRX_STS_INVALID_ARG: Wrong parameters.
*
* tunerChannel passes parameters to program the tuner,
* but also returns the actual RF and IF frequency from the tuner.
*
*/
static DRXStatus_t
CtrlProgramTuner( pDRXDemodInstance_t demod,
pDRXChannel_t channel )
{
pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL);
DRXStandard_t standard = DRX_STANDARD_UNKNOWN;
TUNERMode_t tunerMode = 0;
DRXStatus_t status = DRX_STS_ERROR;
DRXFrequency_t ifFrequency = 0;
Bool_t tunerSlowMode = FALSE;
/* can't tune without a tuner */
if ( demod->myTuner == NULL )
{
return DRX_STS_INVALID_ARG;
}
commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr;
/* select analog or digital tuner mode based on current standard */
if ( DRX_Ctrl( demod, DRX_CTRL_GET_STANDARD, &standard ) != DRX_STS_OK )
{
return DRX_STS_ERROR;
}
if ( DRX_ISATVSTD( standard ) )
{
tunerMode |= TUNER_MODE_ANALOG;
}
else /* note: also for unknown standard */
{
tunerMode |= TUNER_MODE_DIGITAL;
}
/* select tuner bandwidth */
switch ( channel->bandwidth )
{
case DRX_BANDWIDTH_6MHZ:
tunerMode |= TUNER_MODE_6MHZ;
break;
case DRX_BANDWIDTH_7MHZ:
tunerMode |= TUNER_MODE_7MHZ;
break;
case DRX_BANDWIDTH_8MHZ:
tunerMode |= TUNER_MODE_8MHZ;
break;
default: /* note: also for unknown bandwidth */
return DRX_STS_INVALID_ARG;
}
DRX_GET_TUNERSLOWMODE (demod, tunerSlowMode);
/* select fast (switch) or slow (lock) tuner mode */
if ( tunerSlowMode )
{
tunerMode |= TUNER_MODE_LOCK;
}
else
{
tunerMode |= TUNER_MODE_SWITCH;
}
if ( commonAttr->tunerPortNr == 1 )
{
Bool_t bridgeClosed = TRUE;
DRXStatus_t statusBridge = DRX_STS_ERROR;
statusBridge = DRX_Ctrl( demod, DRX_CTRL_I2C_BRIDGE, &bridgeClosed );
if ( statusBridge != DRX_STS_OK )
{
return statusBridge;
}
}
status = DRXBSP_TUNER_SetFrequency( demod->myTuner,
tunerMode,
channel->frequency );
/* attempt restoring bridge before checking status of SetFrequency */
if ( commonAttr->tunerPortNr == 1 )
{
Bool_t bridgeClosed = FALSE;
DRXStatus_t statusBridge = DRX_STS_ERROR;
statusBridge = DRX_Ctrl( demod, DRX_CTRL_I2C_BRIDGE, &bridgeClosed );
if ( statusBridge != DRX_STS_OK )
{
return statusBridge;
}
}
/* now check status of DRXBSP_TUNER_SetFrequency */
if ( status != DRX_STS_OK )
{
return status;
}
/* get actual RF and IF frequencies from tuner */
status = DRXBSP_TUNER_GetFrequency( demod->myTuner,
tunerMode,
&(channel->frequency),
&(ifFrequency) );
if ( status != DRX_STS_OK )
{
return status;
}
/* update common attributes with information available from this function;
TODO: check if this is required and safe */
DRX_SET_INTERMEDIATEFREQ( demod, ifFrequency );
return DRX_STS_OK;
}
/*============================================================================*/
/**
* \brief function to do a register dump.
* \param demod: Pointer to demodulator instance.
* \param registers: Registers to dump.
* \return DRXStatus_t.
* \retval DRX_STS_OK: Dump executed successfully.
* \retval DRX_STS_ERROR: Something went wrong.
* \retval DRX_STS_INVALID_ARG: Wrong parameters.
*
*/
DRXStatus_t CtrlDumpRegisters( pDRXDemodInstance_t demod,
pDRXRegDump_t registers )
{
u16_t i = 0;
if ( registers == NULL )
{
/* registers not supplied */
return DRX_STS_INVALID_ARG;
}
/* start dumping registers */
while ( registers[i].address != 0 )
{
DRXStatus_t status = DRX_STS_ERROR;
u16_t value = 0;
u32_t data = 0;
status = demod->myAccessFunct->readReg16Func(
demod->myI2CDevAddr, registers[i].address, &value, 0 );
data = (u32_t)value;
if ( status != DRX_STS_OK )
{
/* no breakouts;
depending on device ID, some HW blocks might not be available */
data |= ( (u32_t)status ) << 16;
}
registers[i].data = data;
i++;
}
/* all done, all OK (any errors are saved inside data) */
return DRX_STS_OK;
}
/*============================================================================*/
/*============================================================================*/
/*===Microcode related functions==============================================*/
/*============================================================================*/
/*============================================================================*/
/**
* \brief Read a 16 bits word, expects big endian data.
* \param addr: Pointer to memory from which to read the 16 bits word.
* \return u16_t The data read.
*
* This function takes care of the possible difference in endianness between the
* host and the data contained in the microcode image file.
*
*/
static u16_t
UCodeRead16( pu8_t addr)
{
/* Works fo any host processor */
u16_t word=0;
word = ((u16_t)addr[0]);
word <<= 8;
word |=((u16_t)addr[1]);
return word;
}
/*============================================================================*/
/**
* \brief Read a 32 bits word, expects big endian data.
* \param addr: Pointer to memory from which to read the 32 bits word.
* \return u32_t The data read.
*
* This function takes care of the possible difference in endianness between the
* host and the data contained in the microcode image file.
*
*/
static u32_t
UCodeRead32( pu8_t addr)
{
/* Works fo any host processor */
u32_t word=0;
word = ((u16_t)addr[0]);
word <<= 8;
word |= ((u16_t)addr[1]);
word <<= 8;
word |= ((u16_t)addr[2]);
word <<= 8;
word |= ((u16_t)addr[3]);
return word ;
}
/*============================================================================*/
/**
* \brief Compute CRC of block of microcode data.
* \param blockData: Pointer to microcode data.
* \param nrWords: Size of microcode block (number of 16 bits words).
* \return u16_t The computed CRC residu.
*/
static u16_t
UCodeComputeCRC (pu8_t blockData, u16_t nrWords)
{
u16_t i = 0;
u16_t j = 0;
u32_t CRCWord = 0;
u32_t carry = 0;
while ( i < nrWords )
{
CRCWord |= (u32_t) UCodeRead16(blockData);
for (j = 0; j < 16; j++)
{
CRCWord <<= 1;
if (carry != 0)
{
CRCWord ^= 0x80050000UL;
}
carry = CRCWord & 0x80000000UL;
}
i++;
blockData+=(sizeof(u16_t));
}
return ((u16_t) (CRCWord >> 16));
}
/*============================================================================*/
/**
* \brief Handle microcode upload or verify.
* \param devAddr: Address of device.
* \param mcInfo: Pointer to information about microcode data.
* \param action: Either UCODE_UPLOAD or UCODE_VERIFY
* \return DRXStatus_t.
* \retval DRX_STS_OK:
* - In case of UCODE_UPLOAD: code is successfully uploaded.
* - In case of UCODE_VERIFY: image on device is equal to
* image provided to this control function.
* \retval DRX_STS_ERROR:
* - In case of UCODE_UPLOAD: I2C error.
* - In case of UCODE_VERIFY: I2C error or image on device
* is not equal to image provided to this control function.
* \retval DRX_STS_INVALID_ARG:
* - Invalid arguments.
* - Provided image is corrupt
*/
static DRXStatus_t
CtrlUCode( pDRXDemodInstance_t demod,
pDRXUCodeInfo_t mcInfo,
DRXUCodeAction_t action)
{
DRXStatus_t rc;
u16_t i = 0;
u16_t mcNrOfBlks = 0;
u16_t mcMagicWord = 0;
pu8_t mcData = (pu8_t)(NULL);
pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)(NULL);
devAddr = demod -> myI2CDevAddr;
/* Check arguments */
if ( ( mcInfo == NULL ) ||
( mcInfo->mcData == NULL ) )
{
return DRX_STS_INVALID_ARG;
}
mcData = mcInfo->mcData;
/* Check data */
mcMagicWord = UCodeRead16( mcData );
mcData += sizeof( u16_t );
mcNrOfBlks = UCodeRead16( mcData );
mcData += sizeof( u16_t );
if ( ( mcMagicWord != DRX_UCODE_MAGIC_WORD ) ||
( mcNrOfBlks == 0 ) )
{
/* wrong endianess or wrong data ? */
return DRX_STS_INVALID_ARG;
}
/* Scan microcode blocks first for version info if uploading */
if (action == UCODE_UPLOAD)
{
/* Clear version block */
DRX_SET_MCVERTYPE (demod, 0);
DRX_SET_MCDEV (demod, 0);
DRX_SET_MCVERSION (demod, 0);
DRX_SET_MCPATCH (demod, 0);
for (i = 0; i < mcNrOfBlks; i++)
{
DRXUCodeBlockHdr_t blockHdr;
/* Process block header */
blockHdr.addr = UCodeRead32( mcData );
mcData += sizeof(u32_t);
blockHdr.size = UCodeRead16( mcData );
mcData += sizeof(u16_t);
blockHdr.flags = UCodeRead16( mcData );
mcData += sizeof(u16_t);
blockHdr.CRC = UCodeRead16( mcData );
mcData += sizeof(u16_t);
if (blockHdr.flags & 0x8)
{
/* Aux block. Check type */
pu8_t auxblk = mcInfo->mcData + blockHdr.addr;
u16_t auxtype = UCodeRead16 (auxblk);
if (DRX_ISMCVERTYPE (auxtype))
{
DRX_SET_MCVERTYPE (demod, UCodeRead16 (auxblk));
auxblk += sizeof (u16_t);
DRX_SET_MCDEV (demod, UCodeRead32 (auxblk));
auxblk += sizeof (u32_t);
DRX_SET_MCVERSION (demod, UCodeRead32 (auxblk));
auxblk += sizeof (u32_t);
DRX_SET_MCPATCH (demod, UCodeRead32 (auxblk));
}
}
/* Next block */
mcData += blockHdr.size * sizeof (u16_t);
}
/* After scanning, validate the microcode.
It is also valid if no validation control exists.
*/
rc = DRX_Ctrl (demod, DRX_CTRL_VALIDATE_UCODE, NULL);
if (rc != DRX_STS_OK && rc != DRX_STS_FUNC_NOT_AVAILABLE)
{
return rc;
}
/* Restore data pointer */
mcData = mcInfo->mcData + 2 * sizeof( u16_t );
}
/* Process microcode blocks */
for( i = 0 ; i<mcNrOfBlks ; i++ )
{
DRXUCodeBlockHdr_t blockHdr;
u16_t mcBlockNrBytes = 0;
/* Process block header */
blockHdr.addr = UCodeRead32( mcData );
mcData += sizeof(u32_t);
blockHdr.size = UCodeRead16( mcData );
mcData += sizeof(u16_t);
blockHdr.flags = UCodeRead16( mcData );
mcData += sizeof(u16_t);
blockHdr.CRC = UCodeRead16( mcData );
mcData += sizeof(u16_t);
/* Check block header on:
- data larger than 64Kb
- if CRC enabled check CRC
*/
if ( ( blockHdr.size > 0x7FFF ) ||
( ( ( blockHdr.flags & DRX_UCODE_CRC_FLAG ) != 0 ) &&
( blockHdr.CRC != UCodeComputeCRC ( mcData, blockHdr.size) ) )
)
{
/* Wrong data ! */
return DRX_STS_INVALID_ARG;
}
mcBlockNrBytes = blockHdr.size * ((u16_t)sizeof( u16_t ));
if ( blockHdr.size != 0 )
{
/* Perform the desired action */
switch ( action ) {
/*================================================================*/
case UCODE_UPLOAD :
{
/* Upload microcode */
if ( demod->myAccessFunct->writeBlockFunc(
devAddr,
(DRXaddr_t) blockHdr.addr,
mcBlockNrBytes,
mcData,
0x0000) != DRX_STS_OK)
{
return (DRX_STS_ERROR);
} /* if */
};
break;
/*================================================================*/
case UCODE_VERIFY :
{
int result = 0;
u8_t mcDataBuffer[DRX_UCODE_MAX_BUF_SIZE];
u32_t bytesToCompare=0;
u32_t bytesLeftToCompare=0;
DRXaddr_t currAddr = (DRXaddr_t)0;
pu8_t currPtr =NULL;
bytesLeftToCompare = mcBlockNrBytes;
currAddr = blockHdr.addr;
currPtr = mcData;
while( bytesLeftToCompare != 0 )
{
if (bytesLeftToCompare > ( (u32_t)DRX_UCODE_MAX_BUF_SIZE) )
{
bytesToCompare = ( (u32_t)DRX_UCODE_MAX_BUF_SIZE );
}
else
{
bytesToCompare = bytesLeftToCompare;
}
if ( demod->myAccessFunct->readBlockFunc(
devAddr,
currAddr,
(u16_t)bytesToCompare,
(pu8_t)mcDataBuffer,
0x0000) != DRX_STS_OK)
{
return (DRX_STS_ERROR);
}
result = DRXBSP_HST_Memcmp( currPtr,
mcDataBuffer,
bytesToCompare);
if ( result != 0 )
{
return DRX_STS_ERROR;
}
currAddr += ((DRXaddr_t)(bytesToCompare/2));
currPtr = &(currPtr[bytesToCompare]);
bytesLeftToCompare -= ((u32_t)bytesToCompare);
} /* while( bytesToCompare > DRX_UCODE_MAX_BUF_SIZE ) */
};
break;
/*================================================================*/
default:
return DRX_STS_INVALID_ARG;
break;
} /* switch ( action ) */
} /* if (blockHdr.size != 0 ) */
/* Next block */
mcData += mcBlockNrBytes;
} /* for( i = 0 ; i<mcNrOfBlks ; i++ ) */
return DRX_STS_OK;
}
/*============================================================================*/
/**
* \brief Build list of version information.
* \param demod: A pointer to a demodulator instance.
* \param versionList: Pointer to linked list of versions.
* \return DRXStatus_t.
* \retval DRX_STS_OK: Version information stored in versionList
* \retval DRX_STS_INVALID_ARG: Invalid arguments.
*/
static DRXStatus_t
CtrlVersion( pDRXDemodInstance_t demod,
pDRXVersionList_t *versionList )
{
static char drxDriverCoreModuleName[] = "Core driver";
static char drxDriverCoreVersionText[] =
DRX_VERSIONSTRING( VERSION_MAJOR, VERSION_MINOR, VERSION_PATCH );
static DRXVersion_t drxDriverCoreVersion;
static DRXVersionList_t drxDriverCoreVersionList;
pDRXVersionList_t demodVersionList = (pDRXVersionList_t)(NULL);
DRXStatus_t returnStatus = DRX_STS_ERROR;
/* Check arguments */
if ( versionList == NULL )
{
return DRX_STS_INVALID_ARG;
}
/* Get version info list from demod */
returnStatus = (*(demod->myDemodFunct->ctrlFunc))(
demod,
DRX_CTRL_VERSION,
(void *) &demodVersionList );
/* Always fill in the information of the driver SW . */
drxDriverCoreVersion.moduleType = DRX_MODULE_DRIVERCORE;
drxDriverCoreVersion.moduleName = drxDriverCoreModuleName;
drxDriverCoreVersion.vMajor = VERSION_MAJOR;
drxDriverCoreVersion.vMinor = VERSION_MINOR;
drxDriverCoreVersion.vPatch = VERSION_PATCH;
drxDriverCoreVersion.vString = drxDriverCoreVersionText;
drxDriverCoreVersionList.version = &drxDriverCoreVersion;
drxDriverCoreVersionList.next = (pDRXVersionList_t)(NULL);
if ( ( returnStatus == DRX_STS_OK ) && ( demodVersionList != NULL ) )
{
/* Append versioninfo from driver to versioninfo from demod */
/* Return version info in "bottom-up" order. This way, multiple
devices can be handled without using malloc. */
pDRXVersionList_t currentListElement = demodVersionList;
while ( currentListElement->next != NULL )
{
currentListElement = currentListElement->next;
}
currentListElement->next = &drxDriverCoreVersionList;
*versionList = demodVersionList;
}
else
{
/* Just return versioninfo from driver */
*versionList = &drxDriverCoreVersionList;
}
return DRX_STS_OK;
}
/*============================================================================*/
/*============================================================================*/
/*== Exported functions ======================================================*/
/*============================================================================*/
/*============================================================================*/
/**
* \brief This function is obsolete.
* \param demods: Don't care, parameter is ignored.
* \return DRXStatus_t Return status.
* \retval DRX_STS_OK: Initialization completed.
*
* This function is obsolete, prototype available for backward compatability.
*
*/
DRXStatus_t
DRX_Init( pDRXDemodInstance_t demods[] )
{
return DRX_STS_OK;
}
/*============================================================================*/
/**
* \brief This function is obsolete.
* \return DRXStatus_t Return status.
* \retval DRX_STS_OK: Terminated driver successful.
*
* This function is obsolete, prototype available for backward compatability.
*
*/
DRXStatus_t
DRX_Term( void )
{
return DRX_STS_OK;
}
/*============================================================================*/
/**
* \brief Open a demodulator instance.
* \param demod: A pointer to a demodulator instance.
* \return DRXStatus_t Return status.
* \retval DRX_STS_OK: Opened demod instance with succes.
* \retval DRX_STS_ERROR: Driver not initialized or unable to initialize
* demod.
* \retval DRX_STS_INVALID_ARG: Demod instance has invalid content.
*
*/
DRXStatus_t
DRX_Open(pDRXDemodInstance_t demod)
{
DRXStatus_t status = DRX_STS_OK;
if ( ( demod == NULL ) ||
( demod->myDemodFunct == NULL ) ||
( demod->myCommonAttr == NULL ) ||
( demod->myExtAttr == NULL ) ||
( demod->myI2CDevAddr == NULL ) ||
( demod->myCommonAttr->isOpened == TRUE ))
{
return (DRX_STS_INVALID_ARG);
}
status = (*(demod->myDemodFunct->openFunc))( demod );
if ( status == DRX_STS_OK )
{
demod->myCommonAttr->isOpened = TRUE;
}
return status;
}
/*============================================================================*/
/**
* \brief Close device.
* \param demod: A pointer to a demodulator instance.
* \return DRXStatus_t Return status.
* \retval DRX_STS_OK: Closed demod instance with succes.
* \retval DRX_STS_ERROR: Driver not initialized or error during close
* demod.
* \retval DRX_STS_INVALID_ARG: Demod instance has invalid content.
*
* Free resources occupied by device instance.
* Put device into sleep mode.
*/
DRXStatus_t
DRX_Close(pDRXDemodInstance_t demod)
{
DRXStatus_t status = DRX_STS_OK;
if ( ( demod == NULL ) ||
( demod->myDemodFunct == NULL ) ||
( demod->myCommonAttr == NULL ) ||
( demod->myExtAttr == NULL ) ||
( demod->myI2CDevAddr == NULL ) ||
( demod->myCommonAttr->isOpened == FALSE ))
{
return DRX_STS_INVALID_ARG;
}
status = (*(demod->myDemodFunct->closeFunc))( demod );
DRX_SET_ISOPENED (demod, FALSE);
return status;
}
/*============================================================================*/
/**
* \brief Control the device.
* \param demod: A pointer to a demodulator instance.
* \param ctrl: Reference to desired control function.
* \param ctrlData: Pointer to data structure for control function.
* \return DRXStatus_t Return status.
* \retval DRX_STS_OK: Control function completed successfully.
* \retval DRX_STS_ERROR: Driver not initialized or error during
* control demod.
* \retval DRX_STS_INVALID_ARG: Demod instance or ctrlData has invalid
* content.
* \retval DRX_STS_FUNC_NOT_AVAILABLE: Specified control function is not
* available.
*
* Data needed or returned by the control function is stored in ctrlData.
*
*/
DRXStatus_t
DRX_Ctrl(pDRXDemodInstance_t demod, DRXCtrlIndex_t ctrl, void *ctrlData)
{
DRXStatus_t status = DRX_STS_ERROR;
if ( ( demod == NULL ) ||
( demod->myDemodFunct == NULL ) ||
( demod->myCommonAttr == NULL ) ||
( demod->myExtAttr == NULL ) ||
( demod->myI2CDevAddr == NULL )
)
{
return (DRX_STS_INVALID_ARG);
}
if ( ( ( demod->myCommonAttr->isOpened == FALSE ) &&
( ctrl != DRX_CTRL_PROBE_DEVICE ) &&
( ctrl != DRX_CTRL_VERSION) )
)
{
return (DRX_STS_INVALID_ARG);
}
if ( ( DRX_ISPOWERDOWNMODE( demod->myCommonAttr->currentPowerMode ) &&
( ctrl != DRX_CTRL_POWER_MODE ) &&
( ctrl != DRX_CTRL_PROBE_DEVICE ) &&
( ctrl != DRX_CTRL_NOP ) &&
( ctrl != DRX_CTRL_VERSION)
)
)
{
return DRX_STS_FUNC_NOT_AVAILABLE;
}
/* Fixed control functions */
switch ( ctrl ) {
/*======================================================================*/
case DRX_CTRL_NOP:
/* No operation */
return DRX_STS_OK;
break;
/*======================================================================*/
case DRX_CTRL_VERSION:
return CtrlVersion( demod, (pDRXVersionList_t *) ctrlData );
break;
/*======================================================================*/
default :
/* Do nothing */
break;
}
/* Virtual functions */
/* First try calling function from derived class */
status = (*(demod->myDemodFunct->ctrlFunc))( demod, ctrl, ctrlData );
if (status == DRX_STS_FUNC_NOT_AVAILABLE)
{
/* Now try calling a the base class function */
switch ( ctrl ) {
/*===================================================================*/
case DRX_CTRL_LOAD_UCODE:
return CtrlUCode ( demod,
(pDRXUCodeInfo_t) ctrlData,
UCODE_UPLOAD );
break;
/*===================================================================*/
case DRX_CTRL_VERIFY_UCODE:
{
return CtrlUCode ( demod,
(pDRXUCodeInfo_t) ctrlData,
UCODE_VERIFY);
}
break;
#ifndef DRX_EXCLUDE_SCAN
/*===================================================================*/
case DRX_CTRL_SCAN_INIT:
{
return CtrlScanInit( demod, (pDRXScanParam_t) ctrlData );
}
break;
/*===================================================================*/
case DRX_CTRL_SCAN_NEXT:
{
return CtrlScanNext( demod, (pu16_t) ctrlData );
}
break;
/*===================================================================*/
case DRX_CTRL_SCAN_STOP:
{
return CtrlScanStop( demod );
}
break;
#endif /* #ifndef DRX_EXCLUDE_SCAN */
/*===================================================================*/
case DRX_CTRL_PROGRAM_TUNER:
{
return CtrlProgramTuner( demod, (pDRXChannel_t) ctrlData );
}
break;
/*===================================================================*/
case DRX_CTRL_DUMP_REGISTERS:
{
return CtrlDumpRegisters( demod, (pDRXRegDump_t) ctrlData );
}
break;
/*===================================================================*/
default :
return DRX_STS_FUNC_NOT_AVAILABLE;
}
}
else
{
return (status);
}
return DRX_STS_OK;
}
/*============================================================================*/
/* END OF FILE */
drivers/media/dvb-frontends/drx39xyj/drx_driver.h 0 → 100644
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drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h 0 → 100644
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/*
*******************************************************************************
* WARNING - THIS FILE HAS BEEN GENERATED - DO NOT CHANGE
*
* Filename: drx_driver_version.h
* Generated on: Mon Jan 18 12:09:23 2010
* Generated by: IDF:x 1.3.0
* Generated from: ../../../device/drxj/version
* Output start: [entry point]
*
* filename last modified re-use
* -----------------------------------------------------
* version.idf Mon Jan 18 11:56:10 2010 -
*
* $(c) 2010 Trident Microsystems, Inc. - All rights reserved.
*
* This software and related documentation (the 'Software') are intellectual
* property owned by Trident and are copyright of Trident, unless specifically
* noted otherwise.
*
* Any use of the Software is permitted only pursuant to the terms of the
* license agreement, if any, which accompanies, is included with or applicable
* to the Software ('License Agreement') or upon express written consent of
* Trident. Any copying, reproduction or redistribution of the Software in
* whole or in part by any means not in accordance with the License Agreement
* or as agreed in writing by Trident is expressly prohibited.
*
* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE
* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE
* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND
* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES AND
* CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT
* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY TO
* USE THE SOFTWARE.
*
* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL,
* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION,
* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF
* BUSINESS INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF
* OR THE INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING
* FROM TRIDENT'S NEGLIGENCE. $
*
*******************************************************************************
*/
#ifndef __DRX_DRIVER_VERSION__H__
#define __DRX_DRIVER_VERSION__H__ INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
#ifdef _REGISTERTABLE_
#include <registertable.h>
extern RegisterTable_t drx_driver_version[];
extern RegisterTableInfo_t drx_driver_version_info[];
#endif /* _REGISTERTABLE_ */
/*
*==============================================================================
* VERSION
* version@/var/cvs/projects/drxj.cvsroot/hostcode/drxdriver/device/drxj
*==============================================================================
*/
#define VERSION__A 0x0
#define VERSION_MAJOR 1
#define VERSION_MINOR 0
#define VERSION_PATCH 56
#ifdef __cplusplus
}
#endif
#endif /* __DRX_DRIVER_VERSION__H__ */
/*
* End of file (drx_driver_version.h)
*******************************************************************************
*/
drivers/media/dvb-frontends/drx39xyj/drxj.c 0 → 100644
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drivers/media/dvb-frontends/drx39xyj/drxj.h 0 → 100644
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/**
* \file $Id: drxj.h,v 1.132 2009/12/22 12:13:48 danielg Exp $
*
* \brief DRXJ specific header file
*
* \author Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen
*/
/*
* $(c) 2006-2009 Trident Microsystems, Inc. - All rights reserved.
*
* This software and related documentation (the 'Software') are intellectual
* property owned by Trident and are copyright of Trident, unless specifically
* noted otherwise.
*
* Any use of the Software is permitted only pursuant to the terms of the
* license agreement, if any, which accompanies, is included with or applicable
* to the Software ('License Agreement') or upon express written consent of
* Trident. Any copying, reproduction or redistribution of the Software in
* whole or in part by any means not in accordance with the License Agreement
* or as agreed in writing by Trident is expressly prohibited.
*
* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE
* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE
* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND
* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES
* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT
* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY
* TO USE THE SOFTWARE.
*
* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL,
* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION,
* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS
* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE
* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM
* TRIDENT'S NEGLIGENCE. $
*
*/
#ifndef __DRXJ_H__
#define __DRXJ_H__
/*-------------------------------------------------------------------------
INCLUDES
-------------------------------------------------------------------------*/
#include "drx_driver.h"
#include "drx_dap_fasi.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Check DRX-J specific dap condition */
/* Multi master mode and short addr format only will not work.
RMW, CRC reset, broadcast and switching back to single master mode
cannot be done with short addr only in multi master mode. */
#if ((DRXDAP_SINGLE_MASTER==0)&&(DRXDAPFASI_LONG_ADDR_ALLOWED==0))
#error "Multi master mode and short addressing only is an illegal combination"
*; /* Generate a fatal compiler error to make sure it stops here,
this is necesarry because not all compilers stop after a #error. */
#endif
/*-------------------------------------------------------------------------
TYPEDEFS
-------------------------------------------------------------------------*/
/*============================================================================*/
/*============================================================================*/
/*== code support ============================================================*/
/*============================================================================*/
/*============================================================================*/
/*============================================================================*/
/*============================================================================*/
/*== SCU cmd if =============================================================*/
/*============================================================================*/
/*============================================================================*/
typedef struct {
u16_t command; /**< Command number */
u16_t parameterLen; /**< Data length in byte */
u16_t resultLen; /**< result length in byte */
u16_t *parameter; /**< General purpous param */
u16_t *result; /**< General purpous param */
} DRXJSCUCmd_t, *pDRXJSCUCmd_t;
/*============================================================================*/
/*============================================================================*/
/*== CTRL CFG related data structures ========================================*/
/*============================================================================*/
/*============================================================================*/
/* extra intermediate lock state for VSB,QAM,NTSC */
#define DRXJ_DEMOD_LOCK (DRX_LOCK_STATE_1)
/* OOB lock states */
#define DRXJ_OOB_AGC_LOCK (DRX_LOCK_STATE_1) /* analog gain control lock */
#define DRXJ_OOB_SYNC_LOCK (DRX_LOCK_STATE_2) /* digital gain control lock */
/* Intermediate powermodes for DRXJ */
#define DRXJ_POWER_DOWN_MAIN_PATH DRX_POWER_MODE_8
#define DRXJ_POWER_DOWN_CORE DRX_POWER_MODE_9
#define DRXJ_POWER_DOWN_PLL DRX_POWER_MODE_10
/* supstition for GPIO FNC mux */
#define APP_O (0x0000)
/*#define DRX_CTRL_BASE (0x0000)*/
#define DRXJ_CTRL_CFG_BASE (0x1000)
typedef enum {
DRXJ_CFG_AGC_RF = DRXJ_CTRL_CFG_BASE,
DRXJ_CFG_AGC_IF,
DRXJ_CFG_AGC_INTERNAL,
DRXJ_CFG_PRE_SAW,
DRXJ_CFG_AFE_GAIN,
DRXJ_CFG_SYMBOL_CLK_OFFSET,
DRXJ_CFG_ACCUM_CR_RS_CW_ERR,
DRXJ_CFG_FEC_MERS_SEQ_COUNT,
DRXJ_CFG_OOB_MISC,
DRXJ_CFG_SMART_ANT,
DRXJ_CFG_OOB_PRE_SAW,
DRXJ_CFG_VSB_MISC,
DRXJ_CFG_RESET_PACKET_ERR,
/* ATV (FM) */
DRXJ_CFG_ATV_OUTPUT, /* also for FM (SIF control) but not likely */
DRXJ_CFG_ATV_MISC,
DRXJ_CFG_ATV_EQU_COEF,
DRXJ_CFG_ATV_AGC_STATUS, /* also for FM ( IF,RF, audioAGC ) */
DRXJ_CFG_MPEG_OUTPUT_MISC,
DRXJ_CFG_HW_CFG,
DRXJ_CFG_OOB_LO_POW,
DRXJ_CFG_MAX /* dummy, never to be used */
} DRXJCfgType_t, *pDRXJCfgType_t;
/**
* /struct DRXJCfgSmartAntIO_t
* smart antenna i/o.
*/
typedef enum DRXJCfgSmartAntIO_t {
DRXJ_SMT_ANT_OUTPUT = 0,
DRXJ_SMT_ANT_INPUT
} DRXJCfgSmartAntIO_t, *pDRXJCfgSmartAntIO_t;
/**
* /struct DRXJCfgSmartAnt_t
* Set smart antenna.
*/
typedef struct {
DRXJCfgSmartAntIO_t io;
u16_t ctrlData;
} DRXJCfgSmartAnt_t, *pDRXJCfgSmartAnt_t;
/**
* /struct DRXJAGCSTATUS_t
* AGC status information from the DRXJ-IQM-AF.
*/
typedef struct {
u16_t IFAGC;
u16_t RFAGC;
u16_t DigitalAGC;
}DRXJAgcStatus_t, *pDRXJAgcStatus_t;
/* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */
/**
* /struct DRXJAgcCtrlMode_t
* Available AGCs modes in the DRXJ.
*/
typedef enum {
DRX_AGC_CTRL_AUTO = 0,
DRX_AGC_CTRL_USER,
DRX_AGC_CTRL_OFF
} DRXJAgcCtrlMode_t, *pDRXJAgcCtrlMode_t;
/**
* /struct DRXJCfgAgc_t
* Generic interface for all AGCs present on the DRXJ.
*/
typedef struct {
DRXStandard_t standard; /* standard for which these settings apply */
DRXJAgcCtrlMode_t ctrlMode; /* off, user, auto */
u16_t outputLevel; /* range dependent on AGC */
u16_t minOutputLevel; /* range dependent on AGC */
u16_t maxOutputLevel; /* range dependent on AGC */
u16_t speed; /* range dependent on AGC */
u16_t top; /* rf-agc take over point */
u16_t cutOffCurrent; /* rf-agc is accelerated if output current
is below cut-off current */
}DRXJCfgAgc_t, *pDRXJCfgAgc_t;
/* DRXJ_CFG_PRE_SAW */
/**
* /struct DRXJCfgPreSaw_t
* Interface to configure pre SAW sense.
*/
typedef struct {
DRXStandard_t standard; /* standard to which these settings apply */
u16_t reference; /* pre SAW reference value, range 0 .. 31 */
Bool_t usePreSaw; /* TRUE algorithms must use pre SAW sense */
} DRXJCfgPreSaw_t, *pDRXJCfgPreSaw_t;
/* DRXJ_CFG_AFE_GAIN */
/**
* /struct DRXJCfgAfeGain_t
* Interface to configure gain of AFE (LNA + PGA).
*/
typedef struct {
DRXStandard_t standard; /* standard to which these settings apply */
u16_t gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */
} DRXJCfgAfeGain_t, *pDRXJCfgAfeGain_t;
/**
* /struct DRXJRSErrors_t
* Available failure information in DRXJ_FEC_RS.
*
* Container for errors that are received in the most recently finished measurment period
*
*/
typedef struct {
u16_t nrBitErrors; /**< no of pre RS bit errors */
u16_t nrSymbolErrors; /**< no of pre RS symbol errors */
u16_t nrPacketErrors; /**< no of pre RS packet errors */
u16_t nrFailures; /**< no of post RS failures to decode */
u16_t nrSncParFailCount; /**< no of post RS bit erros */
} DRXJRSErrors_t, *pDRXJRSErrors_t;
/**
* /struct DRXJCfgVSBMisc_t
* symbol error rate
*/
typedef struct{
u32_t symbError; /**< symbol error rate sps */
}DRXJCfgVSBMisc_t, *pDRXJCfgVSBMisc_t;
/**
* /enum DRXJMpegOutputClockRate_t
* Mpeg output clock rate.
*
*/
typedef enum {
DRXJ_MPEG_START_WIDTH_1CLKCYC,
DRXJ_MPEG_START_WIDTH_8CLKCYC
} DRXJMpegStartWidth_t, *pDRXJMpegStartWidth_t;
/**
* /enum DRXJMpegOutputClockRate_t
* Mpeg output clock rate.
*
*/
typedef enum {
DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO,
DRXJ_MPEGOUTPUT_CLOCK_RATE_75973K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_50625K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_37968K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_30375K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K
} DRXJMpegOutputClockRate_t, *pDRXJMpegOutputClockRate_t;
/**
* /struct DRXJCfgMisc_t
* Change TEI bit of MPEG output
* reverse MPEG output bit order
* set MPEG output clock rate
*/
typedef struct{
Bool_t disableTEIHandling; /**< if TRUE pass (not change) TEI bit */
Bool_t bitReverseMpegOutout; /**< if TRUE, parallel: msb on MD0; serial: lsb out first */
DRXJMpegOutputClockRate_t mpegOutputClockRate; /**< set MPEG output clock rate that overwirtes the derived one from symbol rate */
DRXJMpegStartWidth_t mpegStartWidth; /**< set MPEG output start width */
}DRXJCfgMpegOutputMisc_t, *pDRXJCfgMpegOutputMisc_t;
/**
* /enum DRXJXtalFreq_t
* Supported external crystal reference frequency.
*/
typedef enum{
DRXJ_XTAL_FREQ_RSVD,
DRXJ_XTAL_FREQ_27MHZ,
DRXJ_XTAL_FREQ_20P25MHZ,
DRXJ_XTAL_FREQ_4MHZ
}DRXJXtalFreq_t, *pDRXJXtalFreq_t;
/**
* /enum DRXJXtalFreq_t
* Supported external crystal reference frequency.
*/
typedef enum{
DRXJ_I2C_SPEED_400KBPS,
DRXJ_I2C_SPEED_100KBPS
}DRXJI2CSpeed_t, *pDRXJI2CSpeed_t;
/**
* /struct DRXJCfgHwCfg_t
* Get hw configuration, such as crystal reference frequency, I2C speed, etc...
*/
typedef struct{
DRXJXtalFreq_t xtalFreq; /**< crystal reference frequency */
DRXJI2CSpeed_t i2cSpeed; /**< 100 or 400 kbps */
}DRXJCfgHwCfg_t, *pDRXJCfgHwCfg_t;
/*
* DRXJ_CFG_ATV_MISC
*/
typedef struct{
s16_t peakFilter; /* -8 .. 15 */
u16_t noiseFilter; /* 0 .. 15 */
}DRXJCfgAtvMisc_t, *pDRXJCfgAtvMisc_t;
/*
* DRXJCfgOOBMisc_t
*/
#define DRXJ_OOB_STATE_RESET 0x0
#define DRXJ_OOB_STATE_AGN_HUNT 0x1
#define DRXJ_OOB_STATE_DGN_HUNT 0x2
#define DRXJ_OOB_STATE_AGC_HUNT 0x3
#define DRXJ_OOB_STATE_FRQ_HUNT 0x4
#define DRXJ_OOB_STATE_PHA_HUNT 0x8
#define DRXJ_OOB_STATE_TIM_HUNT 0x10
#define DRXJ_OOB_STATE_EQU_HUNT 0x20
#define DRXJ_OOB_STATE_EQT_HUNT 0x30
#define DRXJ_OOB_STATE_SYNC 0x40
typedef struct{
DRXJAgcStatus_t agc;
Bool_t eqLock;
Bool_t symTimingLock;
Bool_t phaseLock;
Bool_t freqLock;
Bool_t digGainLock;
Bool_t anaGainLock;
u8_t state;
}DRXJCfgOOBMisc_t, *pDRXJCfgOOBMisc_t;
/*
* Index of in array of coef
*/
typedef enum {
DRXJ_OOB_LO_POW_MINUS0DB = 0,
DRXJ_OOB_LO_POW_MINUS5DB,
DRXJ_OOB_LO_POW_MINUS10DB,
DRXJ_OOB_LO_POW_MINUS15DB,
DRXJ_OOB_LO_POW_MAX
} DRXJCfgOobLoPower_t, *pDRXJCfgOobLoPower_t;
/*
* DRXJ_CFG_ATV_EQU_COEF
*/
typedef struct {
s16_t coef0; /* -256 .. 255 */
s16_t coef1; /* -256 .. 255 */
s16_t coef2; /* -256 .. 255 */
s16_t coef3; /* -256 .. 255 */
} DRXJCfgAtvEquCoef_t, *pDRXJCfgAtvEquCoef_t;
/*
* Index of in array of coef
*/
typedef enum {
DRXJ_COEF_IDX_MN = 0,
DRXJ_COEF_IDX_FM ,
DRXJ_COEF_IDX_L ,
DRXJ_COEF_IDX_LP ,
DRXJ_COEF_IDX_BG ,
DRXJ_COEF_IDX_DK ,
DRXJ_COEF_IDX_I ,
DRXJ_COEF_IDX_MAX
} DRXJCoefArrayIndex_t, *pDRXJCoefArrayIndex_t;
/*
* DRXJ_CFG_ATV_OUTPUT
*/
/**
* /enum DRXJAttenuation_t
* Attenuation setting for SIF AGC.
*
*/
typedef enum {
DRXJ_SIF_ATTENUATION_0DB,
DRXJ_SIF_ATTENUATION_3DB,
DRXJ_SIF_ATTENUATION_6DB,
DRXJ_SIF_ATTENUATION_9DB
} DRXJSIFAttenuation_t, *pDRXJSIFAttenuation_t;
/**
* /struct DRXJCfgAtvOutput_t
* SIF attenuation setting.
*
*/
typedef struct {
Bool_t enableCVBSOutput; /* TRUE= enabled */
Bool_t enableSIFOutput; /* TRUE= enabled */
DRXJSIFAttenuation_t sifAttenuation;
} DRXJCfgAtvOutput_t, *pDRXJCfgAtvOutput_t;
/*
DRXJ_CFG_ATV_AGC_STATUS (get only)
*/
/* TODO : AFE interface not yet finished, subject to change */
typedef struct {
u16_t rfAgcGain ; /* 0 .. 877 uA */
u16_t ifAgcGain ; /* 0 .. 877 uA */
s16_t videoAgcGain ; /* -75 .. 1972 in 0.1 dB steps */
s16_t audioAgcGain ; /* -4 .. 1020 in 0.1 dB steps */
u16_t rfAgcLoopGain ; /* 0 .. 7 */
u16_t ifAgcLoopGain ; /* 0 .. 7 */
u16_t videoAgcLoopGain; /* 0 .. 7 */
} DRXJCfgAtvAgcStatus_t, *pDRXJCfgAtvAgcStatus_t;
/*============================================================================*/
/*============================================================================*/
/*== CTRL related data structures ============================================*/
/*============================================================================*/
/*============================================================================*/
/* NONE */
/*============================================================================*/
/*============================================================================*/
/*========================================*/
/**
* /struct DRXJData_t
* DRXJ specific attributes.
*
* Global data container for DRXJ specific data.
*
*/
typedef struct {
/* device capabilties (determined during DRX_Open()) */
Bool_t hasLNA; /**< TRUE if LNA (aka PGA) present */
Bool_t hasOOB; /**< TRUE if OOB supported */
Bool_t hasNTSC; /**< TRUE if NTSC supported */
Bool_t hasBTSC; /**< TRUE if BTSC supported */
Bool_t hasSMATX; /**< TRUE if mat_tx is available */
Bool_t hasSMARX; /**< TRUE if mat_rx is available */
Bool_t hasGPIO; /**< TRUE if GPIO is available */
Bool_t hasIRQN; /**< TRUE if IRQN is available */
/* A1/A2/A... */
u8_t mfx; /**< metal fix */
/* tuner settings */
Bool_t mirrorFreqSpectOOB; /**< tuner inversion (TRUE = tuner mirrors the signal */
/* standard/channel settings */
DRXStandard_t standard; /**< current standard information */
DRXConstellation_t constellation; /**< current constellation */
DRXFrequency_t frequency; /**< center signal frequency in KHz */
DRXBandwidth_t currBandwidth; /**< current channel bandwidth */
DRXMirror_t mirror; /**< current channel mirror */
/* signal quality information */
u32_t fecBitsDesired; /**< BER accounting period */
u16_t fecVdPlen; /**< no of trellis symbols: VD SER measurement period */
u16_t qamVdPrescale; /**< Viterbi Measurement Prescale */
u16_t qamVdPeriod; /**< Viterbi Measurement period */
u16_t fecRsPlen; /**< defines RS BER measurement period */
u16_t fecRsPrescale; /**< ReedSolomon Measurement Prescale */
u16_t fecRsPeriod; /**< ReedSolomon Measurement period */
Bool_t resetPktErrAcc; /**< Set a flag to reset accumulated packet error */
u16_t pktErrAccStart; /**< Set a flag to reset accumulated packet error */
/* HI configuration */
u16_t HICfgTimingDiv; /**< HI Configure() parameter 2 */
u16_t HICfgBridgeDelay; /**< HI Configure() parameter 3 */
u16_t HICfgWakeUpKey; /**< HI Configure() parameter 4 */
u16_t HICfgCtrl; /**< HI Configure() parameter 5 */
u16_t HICfgTransmit; /**< HI Configure() parameter 6 */
/* UIO configuartion */
DRXUIOMode_t uioSmaRxMode; /**< current mode of SmaRx pin */
DRXUIOMode_t uioSmaTxMode; /**< current mode of SmaTx pin */
DRXUIOMode_t uioGPIOMode; /**< current mode of ASEL pin */
DRXUIOMode_t uioIRQNMode; /**< current mode of IRQN pin */
/* IQM fs frequecy shift and inversion */
u32_t iqmFsRateOfs; /**< frequency shifter setting after setchannel */
Bool_t posImage; /**< Ture: positive image */
/* IQM RC frequecy shift */
u32_t iqmRcRateOfs; /**< frequency shifter setting after setchannel */
/* ATV configuartion */
u32_t atvCfgChangedFlags; /**< flag: flags cfg changes */
s16_t atvTopEqu0[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU0__A */
s16_t atvTopEqu1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */
s16_t atvTopEqu2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */
s16_t atvTopEqu3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */
Bool_t phaseCorrectionBypass; /**< flag: TRUE=bypass */
s16_t atvTopVidPeak; /**< shadow of ATV_TOP_VID_PEAK__A */
u16_t atvTopNoiseTh; /**< shadow of ATV_TOP_NOISE_TH__A */
Bool_t enableCVBSOutput; /**< flag CVBS ouput enable */
Bool_t enableSIFOutput; /**< flag SIF ouput enable */
DRXJSIFAttenuation_t
sifAttenuation; /**< current SIF att setting */
/* Agc configuration for QAM and VSB */
DRXJCfgAgc_t qamRfAgcCfg; /**< qam RF AGC config */
DRXJCfgAgc_t qamIfAgcCfg; /**< qam IF AGC config */
DRXJCfgAgc_t vsbRfAgcCfg; /**< vsb RF AGC config */
DRXJCfgAgc_t vsbIfAgcCfg; /**< vsb IF AGC config */
/* PGA gain configuration for QAM and VSB */
u16_t qamPgaCfg; /**< qam PGA config */
u16_t vsbPgaCfg; /**< vsb PGA config */
/* Pre SAW configuration for QAM and VSB */
DRXJCfgPreSaw_t qamPreSawCfg; /**< qam pre SAW config */
DRXJCfgPreSaw_t vsbPreSawCfg; /**< qam pre SAW config */
/* Version information */
char vText[2][12]; /**< allocated text versions */
DRXVersion_t vVersion[2]; /**< allocated versions structs */
DRXVersionList_t vListElements[2]; /**< allocated version list */
/* smart antenna configuration */
Bool_t smartAntInverted;
/* Tracking filter setting for OOB */
u16_t oobTrkFilterCfg[8];
Bool_t oobPowerOn;
/* MPEG static bitrate setting */
u32_t mpegTsStaticBitrate; /**< bitrate static MPEG output */
Bool_t disableTEIhandling; /**< MPEG TS TEI handling */
Bool_t bitReverseMpegOutout; /**< MPEG output bit order */
DRXJMpegOutputClockRate_t
mpegOutputClockRate; /**< MPEG output clock rate */
DRXJMpegStartWidth_t
mpegStartWidth; /**< MPEG Start width */
/* Pre SAW & Agc configuration for ATV */
DRXJCfgPreSaw_t atvPreSawCfg; /**< atv pre SAW config */
DRXJCfgAgc_t atvRfAgcCfg; /**< atv RF AGC config */
DRXJCfgAgc_t atvIfAgcCfg; /**< atv IF AGC config */
u16_t atvPgaCfg; /**< atv pga config */
u32_t currSymbolRate;
/* pin-safe mode */
Bool_t pdrSafeMode; /**< PDR safe mode activated */
u16_t pdrSafeRestoreValGpio;
u16_t pdrSafeRestoreValVSync;
u16_t pdrSafeRestoreValSmaRx;
u16_t pdrSafeRestoreValSmaTx;
/* OOB pre-saw value */
u16_t oobPreSaw;
DRXJCfgOobLoPower_t oobLoPow;
DRXAudData_t audData; /**< audio storage */
} DRXJData_t, *pDRXJData_t;
/*-------------------------------------------------------------------------
Access MACROS
-------------------------------------------------------------------------*/
/**
* \brief Compilable references to attributes
* \param d pointer to demod instance
*
* Used as main reference to an attribute field.
* Can be used by both macro implementation and function implementation.
* These macros are defined to avoid duplication of code in macro and function
* definitions that handle access of demod common or extended attributes.
*
*/
#define DRXJ_ATTR_BTSC_DETECT( d ) \
(((pDRXJData_t)(d)->myExtAttr)->audData.btscDetect)
/**
* \brief Actual access macros
* \param d pointer to demod instance
* \param x value to set or to get
*
* SET macros must be used to set the value of an attribute.
* GET macros must be used to retrieve the value of an attribute.
* Depending on the value of DRX_USE_ACCESS_FUNCTIONS the macro's will be
* substituted by "direct-access-inline-code" or a function call.
*
*/
#define DRXJ_GET_BTSC_DETECT( d, x ) \
do { \
(x) = DRXJ_ATTR_BTSC_DETECT(( d ); \
} while(0)
#define DRXJ_SET_BTSC_DETECT( d, x ) \
do { \
DRXJ_ATTR_BTSC_DETECT( d ) = (x); \
} while(0)
/*-------------------------------------------------------------------------
DEFINES
-------------------------------------------------------------------------*/
/**
* \def DRXJ_NTSC_CARRIER_FREQ_OFFSET
* \brief Offset from picture carrier to centre frequency in kHz, in RF domain
*
* For NTSC standard.
* NTSC channels are listed by their picture carrier frequency (Fpc).
* The function DRX_CTRL_SET_CHANNEL requires the centre frequency as input.
* In case the tuner module is not used the DRX-J requires that the tuner is
* tuned to the centre frequency of the channel:
*
* Fcentre = Fpc + DRXJ_NTSC_CARRIER_FREQ_OFFSET
*
*/
#define DRXJ_NTSC_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(1750))
/**
* \def DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET
* \brief Offset from picture carrier to centre frequency in kHz, in RF domain
*
* For PAL/SECAM - BG standard. This define is needed in case the tuner module
* is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc).
* The DRX-J requires that the tuner is tuned to:
* Fpc + DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET
*
* In case the tuner module is used the drxdriver takes care of this.
* In case the tuner module is NOT used the application programmer must take
* care of this.
*
*/
#define DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(2375))
/**
* \def DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET
* \brief Offset from picture carrier to centre frequency in kHz, in RF domain
*
* For PAL/SECAM - DK, I, L standards. This define is needed in case the tuner module
* is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc).
* The DRX-J requires that the tuner is tuned to:
* Fpc + DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET
*
* In case the tuner module is used the drxdriver takes care of this.
* In case the tuner module is NOT used the application programmer must take
* care of this.
*
*/
#define DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(2775))
/**
* \def DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET
* \brief Offset from picture carrier to centre frequency in kHz, in RF domain
*
* For PAL/SECAM - LP standard. This define is needed in case the tuner module
* is NOT used. PAL/SECAM channels are listed by their picture carrier frequency (Fpc).
* The DRX-J requires that the tuner is tuned to:
* Fpc + DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET
*
* In case the tuner module is used the drxdriver takes care of this.
* In case the tuner module is NOT used the application programmer must take
* care of this.
*/
#define DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(-3255))
/**
* \def DRXJ_FM_CARRIER_FREQ_OFFSET
* \brief Offset from sound carrier to centre frequency in kHz, in RF domain
*
* For FM standard.
* FM channels are listed by their sound carrier frequency (Fsc).
* The function DRX_CTRL_SET_CHANNEL requires the Ffm frequency (see below) as
* input.
* In case the tuner module is not used the DRX-J requires that the tuner is
* tuned to the Ffm frequency of the channel.
*
* Ffm = Fsc + DRXJ_FM_CARRIER_FREQ_OFFSET
*
*/
#define DRXJ_FM_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(-3000))
/* Revision types -------------------------------------------------------*/
#define DRXJ_TYPE_ID (0x3946000DUL)
/* Macros ---------------------------------------------------------------*/
/* Convert OOB lock status to string */
#define DRXJ_STR_OOB_LOCKSTATUS(x) ( \
( x == DRX_NEVER_LOCK ) ? "Never" : \
( x == DRX_NOT_LOCKED ) ? "No" : \
( x == DRX_LOCKED ) ? "Locked" : \
( x == DRX_LOCK_STATE_1 ) ? "AGC lock" : \
( x == DRX_LOCK_STATE_2 ) ? "sync lock" : \
"(Invalid)" )
/*-------------------------------------------------------------------------
ENUM
-------------------------------------------------------------------------*/
/*-------------------------------------------------------------------------
STRUCTS
-------------------------------------------------------------------------*/
/*-------------------------------------------------------------------------
Exported FUNCTIONS
-------------------------------------------------------------------------*/
extern DRXStatus_t DRXJ_Open(pDRXDemodInstance_t demod);
extern DRXStatus_t DRXJ_Close(pDRXDemodInstance_t demod);
extern DRXStatus_t DRXJ_Ctrl(pDRXDemodInstance_t demod,
DRXCtrlIndex_t ctrl,
void *ctrlData);
/*-------------------------------------------------------------------------
Exported GLOBAL VARIABLES
-------------------------------------------------------------------------*/
extern DRXAccessFunc_t drxDapDRXJFunct_g;
extern DRXDemodFunc_t DRXJFunctions_g;
extern DRXJData_t DRXJData_g;
extern I2CDeviceAddr_t DRXJDefaultAddr_g;
extern DRXCommonAttr_t DRXJDefaultCommAttr_g;
extern DRXDemodInstance_t DRXJDefaultDemod_g;
/*-------------------------------------------------------------------------
THE END
-------------------------------------------------------------------------*/
#ifdef __cplusplus
}
#endif
#endif /* __DRXJ_H__ */
drivers/media/dvb-frontends/drx39xyj/drxj_map.h 0 → 100644
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drivers/media/dvb-frontends/drx39xyj/drxj_mc.h 0 → 100644
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drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h 0 → 100644
View file @ 38b2df95
/*-----------------------------------------------------------------------------
* DESCRIPTION:
* Contains firmware version: 1.0.8
*
* USAGE:
* Include.
*
* NOTES:
* (c) 2009 Trident Microsystems, Inc. - All rights reserved.
*
* This software and related documentation (the 'Software') are intellectual
* property owned by Trident and are copyright of Trident, unless specifically
* noted otherwise.
*
* Any use of the Software is permitted only pursuant to the terms of the
* license agreement, if any, which accompanies, is included with or applicable
* to the Software ('License Agreement') or upon express written consent of
* Trident. Any copying, reproduction or redistribution of the Software in
* whole or in part by any means not in accordance with the License Agreement
* or as agreed in writing by Trident is expressly prohibited.
*
* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE
* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE
* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND
* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES
* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT
* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY
* TO USE THE SOFTWARE.
*
* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL,
* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION,
* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS
* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE
* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM
* TRIDENT'S NEGLIGENCE.
*
* IN NO EVENT SHALL MICRONAS BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL,
* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION,
* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS
* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE
* INABILITY TO USE THE SOFTWARE, EVEN IF MICRONAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM
* MICRONAS' NEGLIGENCE.
*
----------------------------------------------------------------------------*/
#ifndef __DRXJ_MC_VSB_H__
#define __DRXJ_MC_VSB_H__
#define DRXJ_MC_VSB ((pu8_t) drxj_mc_vsb_g)
const u8_t drxj_mc_vsb_g[] = {
0x48, 0x4c, 0x00, 0x03, 0x00, 0x00, 0x2b, 0x62, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x82,
0x00, 0x00, 0x15, 0x9e, 0x00, 0x01, 0x92, 0x3b, 0x2a, 0x02, 0xe4, 0xf8, 0x7f, 0x90, 0xf0, 0xf8,
0xf0, 0xa3, 0x02, 0x22, 0xa6, 0x15, 0x23, 0x7f, 0x71, 0x7e, 0x29, 0x12, 0x90, 0x61, 0x19, 0x7b,
0xf0, 0xef, 0xd0, 0xc0, 0xaf, 0xa2, 0xd1, 0x92, 0xaf, 0xc2, 0x28, 0x12, 0x90, 0xb6, 0x19, 0x7b,
0xfd, 0xe0, 0x4d, 0xef, 0x90, 0xff, 0xf6, 0x7f, 0xf0, 0xee, 0xef, 0xa3, 0xa2, 0xf0, 0x92, 0xd1,
0xd0, 0xaf, 0xe4, 0xd0, 0x7f, 0x90, 0xf0, 0xf8, 0xf0, 0xa3, 0xe4, 0x22, 0x7f, 0x90, 0xf0, 0xf8,
0xf0, 0xa3, 0x02, 0x22, 0x70, 0x09, 0x00, 0x22, 0x00, 0x00, 0x02, 0x00, 0x00, 0x28, 0x7a, 0x90,
0xe0, 0xfa, 0xa3, 0xfe, 0xff, 0xe0, 0x30, 0x7d, 0x94, 0x7c, 0x29, 0x12, 0x90, 0xa5, 0xfc, 0x7a,
0xfe, 0xe0, 0xe0, 0xa3, 0x7d, 0xff, 0x7c, 0x31, 0x12, 0x94, 0xa5, 0x29, 0x7b, 0x90, 0xe0, 0x01,
0x7e, 0xff, 0x7d, 0x00, 0x7c, 0x2e, 0x12, 0x94, 0xa5, 0x29, 0x7b, 0x90, 0xe0, 0x02, 0x7e, 0xff,
0x7d, 0x00, 0x7c, 0x22, 0x12, 0x94, 0xa5, 0x29, 0x7b, 0x90, 0xe0, 0x03, 0x7e, 0xff, 0x7d, 0x00,
0x7c, 0x23, 0x02, 0x94, 0xa5, 0x29, 0x62, 0x30, 0x12, 0x06, 0xb5, 0x2a, 0x04, 0x7f, 0x7f, 0x22,
0x22, 0x00, 0x02, 0x00, 0x41, 0x28, 0x40, 0x30, 0xc2, 0xfd, 0x8e, 0x40, 0x8f, 0xd3, 0xed, 0xd2,
0xff, 0x24, 0xec, 0xff, 0xff, 0x34, 0xda, 0xf5, 0xd9, 0x8f, 0x02, 0x22, 0x82, 0x28, 0x7d, 0x90,
0xe0, 0x3b, 0xf0, 0x54, 0x03, 0x70, 0x80, 0xd3, 0xc3, 0x01, 0x92, 0xb3, 0x90, 0x05, 0x3a, 0x7d,
0xa3, 0xe0, 0xe4, 0xa2, 0x92, 0xb3, 0xe0, 0x02, 0x0f, 0x54, 0x03, 0x70, 0x80, 0xd3, 0xc3, 0x01,
0x92, 0xb3, 0x90, 0x06, 0x91, 0x7d, 0x30, 0xe0, 0x03, 0xe1, 0x02, 0x02, 0x90, 0x65, 0x5a, 0x7d,
0x70, 0xe0, 0xa3, 0x02, 0x70, 0xe0, 0x30, 0x31, 0x2e, 0x02, 0x7d, 0x90, 0xe0, 0x78, 0xa3, 0xfe,
0xff, 0xe0, 0x90, 0xc3, 0x75, 0x7d, 0x9f, 0xe0, 0x7d, 0x90, 0xe0, 0x74, 0x50, 0x9e, 0x90, 0x19,
0x65, 0x7d, 0x64, 0xe0, 0x94, 0x80, 0x40, 0x7f, 0x74, 0x03, 0xf0, 0xff, 0x5b, 0x20, 0xd2, 0x09,
0xe4, 0x5b, 0x7d, 0x90, 0xf0, 0x60, 0xf0, 0xa3, 0x7d, 0x90, 0xe0, 0x4a, 0x02, 0x70, 0xe0, 0xa3,
0x03, 0x70, 0x02, 0x20, 0x90, 0x17, 0x4a, 0x7d, 0x70, 0xe0, 0xa3, 0x02, 0x70, 0xe0, 0x90, 0x3c,
0x5a, 0x7d, 0x70, 0xe0, 0xa3, 0x02, 0x70, 0xe0, 0x20, 0x32, 0x2f, 0x02, 0x7d, 0x90, 0xe0, 0x6c,
0xa3, 0xfe, 0xff, 0xe0, 0x90, 0xd3, 0x6b, 0x7d, 0x9f, 0xe0, 0x7d, 0x90, 0xe0, 0x6a, 0x40, 0x9e,
0x90, 0x1a, 0x57, 0x7d, 0xd3, 0xe0, 0x80, 0x64, 0x7f, 0x94, 0x03, 0x40, 0xff, 0x74, 0x20, 0xf0,
0x09, 0x07, 0x07, 0xd2, 0x90, 0xe4, 0x52, 0x7d, 0xa3, 0xf0, 0x7f, 0xf0, 0x7e, 0x22, 0x12, 0x67,
0x61, 0x29, 0x14, 0x8e, 0x15, 0x8f, 0x27, 0x7f, 0x67, 0x7e, 0x29, 0x12, 0x8e, 0x61, 0x8f, 0x16,
0x90, 0x17, 0x5e, 0x7d, 0xfe, 0xe0, 0xe0, 0xa3, 0x03, 0x78, 0x33, 0xc3, 0x33, 0xce, 0xd8, 0xce,
0xff, 0xf9, 0xe5, 0xd3, 0x9f, 0x17, 0x16, 0xe5, 0x40, 0x9e, 0x20, 0x54, 0x0c, 0x02, 0x7d, 0x90,
0xe0, 0x57, 0x80, 0x64, 0x81, 0x94, 0x10, 0x50, 0x0b, 0x80, 0x7d, 0x90, 0xe0, 0x65, 0x64, 0xc3,
0x94, 0x80, 0x50, 0x81, 0x74, 0x03, 0xf0, 0x01, 0x5b, 0x20, 0xd2, 0x34, 0xe4, 0x5b, 0x7d, 0x90,
0xf0, 0x60, 0xf0, 0xa3, 0x7d, 0x90, 0xe0, 0x68, 0xa3, 0xfe, 0xff, 0xe0, 0x90, 0xc3, 0x6b, 0x7d,
0x9f, 0xe0, 0x7d, 0x90, 0xe0, 0x6a, 0x50, 0x9e, 0x90, 0x16, 0x91, 0x7d, 0x30, 0xe0, 0x0f, 0xe0,
0x7d, 0x90, 0xe0, 0x68, 0xa3, 0xff, 0x90, 0xe0, 0x6a, 0x7d, 0xf0, 0xcf, 0xef, 0xa3, 0x90, 0xf0,
0x4e, 0x7d, 0xfe, 0xe0, 0xe0, 0xa3, 0x03, 0x78, 0x33, 0xc3, 0x33, 0xce, 0xd8, 0xce, 0xff, 0xf9,
0xe5, 0xd3, 0x9f, 0x15, 0x14, 0xe5, 0x40, 0x9e, 0x90, 0x44, 0x57, 0x7d, 0x64, 0xe0, 0x94, 0x80,
0x50, 0x81, 0x74, 0x03, 0xf0, 0x01, 0x07, 0x20, 0xd2, 0x34, 0xe4, 0x07, 0x7d, 0x90, 0xf0, 0x52,
0xf0, 0xa3, 0x7d, 0x90, 0xe0, 0x68, 0xa3, 0xfe, 0xff, 0xe0, 0x90, 0xc3, 0x6b, 0x7d, 0x9f, 0xe0,
0x7d, 0x90, 0xe0, 0x6a, 0x50, 0x9e, 0x90, 0x16, 0x91, 0x7d, 0x30, 0xe0, 0x0f, 0xe0, 0x7d, 0x90,
0xe0, 0x68, 0xa3, 0xff, 0x90, 0xe0, 0x6a, 0x7d, 0xf0, 0xcf, 0xef, 0xa3, 0x90, 0xf0, 0x34, 0x7d,
0xf5, 0xe0, 0xa3, 0x16, 0xf5, 0xe0, 0x90, 0x17, 0x60, 0x7d, 0xf5, 0xe0, 0xa3, 0x1c, 0xf5, 0xe0,
0x05, 0x1d, 0xe5, 0x1d, 0x70, 0x1d, 0x05, 0x02, 0x90, 0x1c, 0x60, 0x7d, 0x1c, 0xe5, 0xa3, 0xf0,
0x1d, 0xe5, 0x30, 0xf0, 0x2f, 0x5b, 0x7d, 0x90, 0xe0, 0x7e, 0xa3, 0xfe, 0xff, 0xe0, 0x74, 0xc3,
0x9f, 0xf8, 0x74, 0xff, 0x9e, 0x2a, 0xd3, 0xfe, 0x7d, 0x90, 0xe0, 0x7b, 0x90, 0x9f, 0x7a, 0x7d,
0x9e, 0xe0, 0x07, 0x50, 0x70, 0xe0, 0xa3, 0x02, 0x70, 0xe0, 0x90, 0x0a, 0x2e, 0x7d, 0xf5, 0xe0,
0xa3, 0x16, 0xf5, 0xe0, 0xc3, 0x17, 0x1d, 0xe5, 0x17, 0x95, 0x1c, 0xe5, 0x16, 0x95, 0x03, 0x40,
0x80, 0xd3, 0xc3, 0x01, 0x04, 0x92, 0x7d, 0x90, 0xe0, 0x50, 0x16, 0xf5, 0xe0, 0xa3, 0x17, 0xf5,
0x7d, 0x90, 0xe0, 0x52, 0x1c, 0xf5, 0xe0, 0xa3, 0x1d, 0xf5, 0x1d, 0x05, 0x1d, 0xe5, 0x02, 0x70,
0x1c, 0x05, 0x7d, 0x90, 0xe5, 0x52, 0xf0, 0x1c, 0xe5, 0xa3, 0xf0, 0x1d, 0x07, 0x30, 0x90, 0x0a,
0x82, 0x7d, 0xf5, 0xe0, 0xa3, 0x16, 0xf5, 0xe0, 0x20, 0x17, 0x11, 0x04, 0xe5, 0xc3, 0x95, 0x1d,
0xe5, 0x17, 0x95, 0x1c, 0x40, 0x16, 0xd3, 0x03, 0x01, 0x80, 0x92, 0xc3, 0x20, 0x03, 0x03, 0x04,
0x03, 0x02, 0xc0, 0xfc, 0xa2, 0xd0, 0x92, 0xaf, 0xc2, 0xd1, 0xe4, 0xaf, 0x7d, 0x90, 0xf0, 0xa4,
0xf0, 0xa3, 0x7d, 0x7e, 0xa4, 0x7f, 0x01, 0x7d, 0x12, 0xfc, 0xae, 0x00, 0x27, 0x7b, 0x00, 0x7a,
0x07, 0x7d, 0x06, 0x7f, 0x2a, 0x12, 0x30, 0x38, 0xfd, 0x40, 0x7d, 0x90, 0xe0, 0xa4, 0xa3, 0xff,
0x90, 0xe0, 0x5a, 0x7d, 0xf0, 0xcf, 0xef, 0xa3, 0xa2, 0xf0, 0x92, 0xd1, 0xd0, 0xaf, 0xe4, 0xd0,
0x7d, 0x90, 0xf0, 0x60, 0xf0, 0xa3, 0x5b, 0xc2, 0x7d, 0x90, 0xe0, 0x63, 0x18, 0xf5, 0x7d, 0x90,
0xe0, 0x5a, 0x12, 0xf5, 0xe0, 0xa3, 0x13, 0xf5, 0x7d, 0x90, 0xe0, 0x5c, 0x1a, 0xf5, 0xe0, 0xa3,
0x1b, 0xf5, 0x7d, 0x90, 0xe0, 0x5e, 0x16, 0xf5, 0xe0, 0xa3, 0x17, 0xf5, 0x7d, 0x90, 0xe0, 0x66,
0x14, 0xf5, 0xe0, 0xa3, 0x15, 0xf5, 0x7d, 0x90, 0xe0, 0x65, 0x19, 0xf5, 0x7d, 0x90, 0xe0, 0x74,
0xa3, 0xfe, 0xff, 0xe0, 0x74, 0xc3, 0x9f, 0xff, 0x1d, 0xf5, 0x7f, 0x74, 0xf5, 0x9e, 0x90, 0x1c,
0x6e, 0x7d, 0xfe, 0xe0, 0xe0, 0xa3, 0x90, 0xff, 0x6a, 0x7d, 0xb5, 0xe0, 0x1e, 0x06, 0xe0, 0xa3,
0x07, 0xb5, 0xd3, 0x19, 0x7d, 0x90, 0xe0, 0x4b, 0x13, 0x95, 0x7d, 0x90, 0xe0, 0x4a, 0x12, 0x95,
0x0a, 0x40, 0x58, 0x20, 0xe0, 0x07, 0x12, 0xf5, 0xe0, 0xa3, 0x13, 0xf5, 0x90, 0xd3, 0x7b, 0x7d,
0x94, 0xe0, 0x90, 0xfe, 0x7a, 0x7d, 0x94, 0xe0, 0x40, 0x77, 0xd3, 0x0d, 0x13, 0xe5, 0x17, 0x95,
0x12, 0xe5, 0x16, 0x95, 0x02, 0x40, 0x04, 0xc2, 0x02, 0x30, 0x20, 0x03, 0x02, 0x05, 0x04, 0xc2,
0x04, 0xa2, 0x5a, 0x92, 0x03, 0x20, 0x02, 0x03, 0xa7, 0x04, 0xd0, 0xc0, 0xaf, 0xa2, 0xd1, 0x92,
0xaf, 0xc2, 0x90, 0xe4, 0xa4, 0x7d, 0xa3, 0xf0, 0x7e, 0xf0, 0x7f, 0x7d, 0x7d, 0xa4, 0xfc, 0x01,
0x00, 0x12, 0x7b, 0xae, 0x7a, 0x22, 0x7d, 0x00, 0x7f, 0x07, 0x12, 0x06, 0x38, 0x2a, 0x40, 0x30,
0x90, 0xfd, 0xa4, 0x7d, 0xff, 0xe0, 0xe0, 0xa3, 0x7d, 0x90, 0xcf, 0x4a, 0xa3, 0xf0, 0xf0, 0xef,
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0x19, 0x12, 0x7a, 0xed, 0x79, 0x23, 0x90, 0xaa, 0x5d, 0x7b, 0x19, 0x12, 0x43, 0xed, 0x18, 0xa9,
0xab, 0x43, 0xe4, 0x08, 0x7f, 0x90, 0xf0, 0xf8, 0xf0, 0xa3, 0xef, 0x22, 0xc4, 0x04, 0xf0, 0x54,
0x24, 0x14, 0xf5, 0x80, 0xe4, 0x82, 0x7a, 0x34, 0x83, 0xf5, 0x01, 0xd0, 0x07, 0xd0, 0x0f, 0x7e,
0x82, 0xe5, 0x02, 0x70, 0x83, 0x15, 0x82, 0x15, 0xe0, 0xd0, 0xde, 0xf0, 0xc0, 0xf3, 0xc0, 0x07,
0x22, 0x01, 0xa8, 0xc0, 0xd0, 0xc0, 0xd0, 0x75, 0x92, 0x00, 0xc0, 0xaf, 0x75, 0xf0, 0x05, 0xf0,
0xe0, 0xc0, 0xe0, 0x75, 0xc0, 0x55, 0x75, 0xe0, 0x29, 0xe0, 0xe0, 0xc0, 0xd5, 0x32, 0xf2, 0xf0,
0xe0, 0xd0, 0xf0, 0xd0, 0xd0, 0xd0, 0xa8, 0xd0, 0xc0, 0x22, 0xc2, 0xa8, 0x10, 0xaf, 0x04, 0x40,
0xa8, 0xd0, 0xf5, 0x80, 0xc2, 0x75, 0x75, 0x7d, 0xa0, 0xc1, 0xc3, 0x8e, 0xc5, 0x8f, 0x40, 0x30,
0x90, 0xfd, 0xa0, 0x7d, 0xfe, 0xe0, 0xe0, 0xa3, 0xd0, 0xff, 0x22, 0xa8, 0x00, 0x12, 0x90, 0x9e,
0xf6, 0x7f, 0xf0, 0xe4, 0xef, 0xa3, 0x53, 0xf0, 0xe7, 0xa9, 0xab, 0x53, 0x7f, 0xf7, 0x12, 0x04,
0x5c, 0x17, 0x29, 0x12, 0xe4, 0xe3, 0x7f, 0x90, 0xf0, 0xf8, 0xf0, 0xa3, 0xc0, 0x22, 0xc2, 0xa8,
0x10, 0xaf, 0x04, 0x40, 0xa8, 0xd0, 0xf5, 0x80, 0x7d, 0x90, 0xee, 0xa0, 0xa3, 0xf0, 0xf0, 0xef,
0xc2, 0x75, 0x75, 0x7d, 0xa0, 0xc1, 0xc3, 0x8c, 0xc4, 0x8d, 0xa8, 0xd0, 0xef, 0x22, 0x54, 0xc4,
0x24, 0xf0, 0xf5, 0x80, 0xe4, 0x82, 0x7a, 0x34, 0x83, 0xf5, 0x01, 0xd0, 0x07, 0xd0, 0x0f, 0x7e,
0xc0, 0xe0, 0xa3, 0xe0, 0xfa, 0xde, 0x07, 0xc0, 0x01, 0xc0, 0xe4, 0x22, 0x7f, 0x90, 0xf0, 0xae,
0xf0, 0xa3, 0x7f, 0x90, 0x74, 0xb0, 0xf0, 0x10, 0xe4, 0xa3, 0x90, 0xf0, 0xd2, 0x7f, 0xa3, 0xf0,
0x90, 0xf0, 0xd4, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, 0xf0, 0x8f, 0xf7, 0x30, 0x63, 0x03, 0xff, 0x07,
0xd4, 0x8f, 0xd5, 0x8d, 0xd7, 0x8a, 0xd6, 0x8b, 0xf7, 0x30, 0x7f, 0x04, 0x80, 0x06, 0x7f, 0x02,
0x8f, 0x02, 0x22, 0xdb, 0xf0, 0x8f, 0xf7, 0x30, 0x63, 0x03, 0xff, 0x07, 0xd4, 0x8f, 0xd5, 0x8d,
0xd7, 0x8a, 0xd6, 0x8b, 0xf7, 0x30, 0x7f, 0x04, 0x80, 0x05, 0x7f, 0x02, 0x8f, 0x01, 0x22, 0xdb,
0xf0, 0x8f, 0xf7, 0x30, 0x63, 0x03, 0xff, 0x07, 0xd4, 0x8f, 0xd5, 0x8d, 0xd7, 0x8a, 0xd6, 0x8b,
0xf7, 0x30, 0x7f, 0x04, 0x80, 0x07, 0x7f, 0x02, 0x8f, 0x03, 0x22, 0xdb, 0x7f, 0x90, 0xe0, 0xf8,
0xa3, 0xff, 0x90, 0xe0, 0xae, 0x7f, 0xf0, 0xcf, 0xef, 0xa3, 0x12, 0xf0, 0xdb, 0x2a, 0x90, 0xe4,
0xf8, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, 0x6d, 0xef, 0x02, 0x70, 0x6c, 0xee, 0x10, 0x60, 0xef, 0x0f,
0x06, 0xaa, 0x01, 0x70, 0x14, 0x0e, 0x82, 0xf5, 0x83, 0x8a, 0xf0, 0xe4, 0xe8, 0x80, 0x00, 0x22,
0x0a, 0x00, 0x00, 0xf4, 0x3f, 0x00, 0x00, 0xaf, 0xb5, 0x00, 0xff, 0x05, 0xf5, 0xff, 0x00, 0x4a,
0x3f, 0x00, 0xff, 0x5b, 0xca, 0xff, 0x7d, 0xe0, 0x7c, 0x16, 0x7f, 0x71, 0x7e, 0x04, 0x12, 0x00,
0xa5, 0x29, 0x18, 0x7d, 0x71, 0x7c, 0x03, 0x7f, 0x00, 0x7e, 0x29, 0x02, 0x53, 0xa5, 0xe7, 0xa9,
0xab, 0x53, 0x7f, 0xf7, 0x12, 0x04, 0x5c, 0x17, 0x62, 0xc2, 0x90, 0xe4, 0xf8, 0x7f, 0xa3, 0xf0,
0x22, 0xf0, 0x40, 0x30, 0xc2, 0xfd, 0xef, 0x40, 0xfe, 0x54, 0xc2, 0x8e, 0xc1, 0xf5, 0xc3, 0x8c,
0xc5, 0x8d, 0x12, 0x22, 0x4e, 0x00, 0x2a, 0x12, 0x12, 0x9f, 0x04, 0x2b, 0x24, 0x12, 0x02, 0xd8,
0x50, 0x24, 0x40, 0xc2, 0x54, 0xef, 0x8e, 0xfe, 0xf5, 0xc2, 0x8c, 0xc1, 0x8d, 0xc3, 0x22, 0xc4,
0x7f, 0x78, 0xf6, 0xe4, 0xfd, 0xd8, 0x81, 0x75, 0x02, 0x3b, 0x99, 0x16, 0x06, 0x7d, 0x90, 0x7c,
0x02, 0x7f, 0x00, 0x7e, 0x29, 0x02, 0x8e, 0xa5, 0x8f, 0x82, 0xa3, 0x83, 0x82, 0xae, 0x83, 0xaf,
0x12, 0x22, 0x00, 0xb2, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x74, 0x38, 0x90, 0xff, 0xf8, 0x7f,
0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f,
0xa3, 0xf0, 0x22, 0xf0, 0x00, 0x83, 0x1f, 0xfe, 0x00, 0x02, 0x00, 0x01, 0xe8, 0x03, 0x10, 0x00,
0x08, 0x00, 0x80, 0x00, 0x03, 0x94, 0x00, 0xd9, 0x00, 0x10, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00
};
#endif /* __DRXJ_MC_VSB_H__ */
drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h 0 → 100644
View file @ 38b2df95
This source diff could not be displayed because it is too large. You can view the blob instead.
drivers/media/dvb-frontends/drx39xyj/drxj_options.h 0 → 100644
View file @ 38b2df95
/**
* \file $Id: drxj_options.h,v 1.5 2009/10/05 21:32:49 dingtao Exp $
*
* \brief DRXJ optional settings
*
* \author Tao Ding
*/
/*
* $(c) 2006-2007,2009 Trident Microsystems, Inc. - All rights reserved.
*
* This software and related documentation (the 'Software') are intellectual
* property owned by Trident and are copyright of Trident, unless specifically
* noted otherwise.
*
* Any use of the Software is permitted only pursuant to the terms of the
* license agreement, if any, which accompanies, is included with or applicable
* to the Software ('License Agreement') or upon express written consent of
* Trident. Any copying, reproduction or redistribution of the Software in
* whole or in part by any means not in accordance with the License Agreement
* or as agreed in writing by Trident is expressly prohibited.
*
* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE
* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE
* IS DELIVERED 'AS IS' AND TRIDENT HEREBY DISCLAIMS ALL WARRANTIES AND
* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES
* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT
* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY
* TO USE THE SOFTWARE.
*
* IN NO EVENT SHALL TRIDENT BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL,
* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION,
* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS
* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE
* INABILITY TO USE THE SOFTWARE, EVEN IF TRIDENT HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM
* TRIDENT'S NEGLIGENCE. $
*
*/
/* Note: Please add preprocessor DRXJ_OPTIONS_H for drxj.c to include this file */
#ifndef __DRXJ_OPTIONS_H__
#define __DRXJ_OPTIONS_H__
#ifdef __cplusplus
extern "C" {
#endif
/* #define DRXJ_DIGITAL_ONLY */
/* #define DRXJ_VSB_ONLY */
/* #define DRXJ_SIGNAL_ACCUM_ERR */
/* #define MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH 0x03 */
/* #define MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH 0x04 */
/* #define MPEG_OUTPUT_CLK_DRIVE_STRENGTH 0x05 */
/* #define OOB_CRX_DRIVE_STRENGTH 0x04 */
/* #define OOB_DRX_DRIVE_STRENGTH 0x05 */
/* #define DRXJ_QAM_MAX_WAITTIME 1000 */
/* #define DRXJ_QAM_FEC_LOCK_WAITTIME 200 */
/* #define DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME 250 */
/*-------------------------------------------------------------------------
THE END
-------------------------------------------------------------------------*/
#ifdef __cplusplus
}
#endif
#endif /* __DRXJ_OPTIONS_H__ */
drivers/media/usb/em28xx/em28xx-cards.c
View file @ 38b2df95
......@@ -214,6 +214,17 @@ static struct em28xx_reg_seq terratec_cinergy_USB_XS_FR_digital[] = {
{ -1, -1, -1, -1},
};
/* PCTV HD Mini (80e) GPIOs
0-5: not used
6: demod reset, active low
7: LED on, active high */
static struct em28xx_reg_seq em2874_pctv_80e_digital[] = {
{EM28XX_R06_I2C_CLK, 0x45, 0xff, 10}, /*400 KHz*/
{EM2874_R80_GPIO_P0_CTRL, 0x80, 0xff, 100},/*Demod reset*/
{EM2874_R80_GPIO_P0_CTRL, 0xc0, 0xff, 10},
{ -1, -1, -1, -1},
};
/* eb1a:2868 Reddo DVB-C USB TV Box
GPIO4 - CU1216L NIM
Other GPIOs seems to be don't care. */
......@@ -2128,6 +2139,13 @@ struct em28xx_board em28xx_boards[] = {
.tuner_gpio = default_tuner_gpio,
.def_i2c_bus = 1,
},
[EM2874_BOARD_PCTV_HD_MINI_80E] = {
.name = "Pinnacle PCTV HD Mini",
.tuner_type = TUNER_ABSENT,
.has_dvb = 1,
.dvb_gpio = em2874_pctv_80e_digital,
.decoder = EM28XX_NODECODER,
},
/* 1ae7:9003/9004 SpeedLink Vicious And Devine Laplace webcam
* Empia EM2765 + OmniVision OV2640 */
[EM2765_BOARD_SPEEDLINK_VAD_LAPLACE] = {
......@@ -2290,6 +2308,8 @@ struct usb_device_id em28xx_id_table[] = {
.driver_info = EM2882_BOARD_PINNACLE_HYBRID_PRO_330E },
{ USB_DEVICE(0x2304, 0x0227),
.driver_info = EM2880_BOARD_PINNACLE_PCTV_HD_PRO },
{ USB_DEVICE(0x2304, 0x023f),
.driver_info = EM2874_BOARD_PCTV_HD_MINI_80E },
{ USB_DEVICE(0x0413, 0x6023),
.driver_info = EM2800_BOARD_LEADTEK_WINFAST_USBII },
{ USB_DEVICE(0x093b, 0xa003),
......
drivers/media/usb/em28xx/em28xx-dvb.c
View file @ 38b2df95
......@@ -41,6 +41,7 @@
#include "mt352.h"
#include "mt352_priv.h" /* FIXME */
#include "tda1002x.h"
#include "drx39xyj/drx39xxj.h"
#include "tda18271.h"
#include "s921.h"
#include "drxd.h"
......@@ -821,6 +822,20 @@ static const struct m88ds3103_config pctv_461e_m88ds3103_config = {
.agc = 0x99,
};
static struct tda18271_std_map drx_j_std_map = {
.atsc_6 = { .if_freq = 5000, .agc_mode = 3, .std = 0, .if_lvl = 1,
.rfagc_top = 0x37, },
.qam_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3, .if_lvl = 1,
.rfagc_top = 0x37, },
};
static struct tda18271_config pinnacle_80e_dvb_config = {
.std_map = &drx_j_std_map,
.gate = TDA18271_GATE_DIGITAL,
.role = TDA18271_MASTER,
};
/* ------------------------------------------------------------------ */
static int em28xx_attach_xc3028(u8 addr, struct em28xx *dev)
......@@ -1374,6 +1389,18 @@ static int em28xx_dvb_init(struct em28xx *dev)
goto out_free;
}
break;
case EM2874_BOARD_PCTV_HD_MINI_80E:
dvb->fe[0] = dvb_attach(drx39xxj_attach, &dev->i2c_adap[dev->def_i2c_bus]);
if (dvb->fe[0] != NULL) {
dvb->fe[0] = dvb_attach(tda18271_attach, dvb->fe[0], 0x60,
&dev->i2c_adap[dev->def_i2c_bus],
&pinnacle_80e_dvb_config);
if (!dvb->fe[0]) {
result = -EINVAL;
goto out_free;
}
}
break;
case EM28178_BOARD_PCTV_461E:
{
/* demod I2C adapter */
......
drivers/media/usb/em28xx/em28xx.h
View file @ 38b2df95
......@@ -104,6 +104,7 @@
#define EM2882_BOARD_PINNACLE_HYBRID_PRO_330E 56
#define EM2883_BOARD_KWORLD_HYBRID_330U 57
#define EM2820_BOARD_COMPRO_VIDEOMATE_FORYOU 58
#define EM2874_BOARD_PCTV_HD_MINI_80E 59
#define EM2883_BOARD_HAUPPAUGE_WINTV_HVR_850 60
#define EM2820_BOARD_PROLINK_PLAYTV_BOX4_USB2 61
#define EM2820_BOARD_GADMEI_TVR200 62
......
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