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Commit 3954b4e3 authored by Arnd Bergmann's avatar Arnd Bergmann Committed by Kalle Valo
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rt2x00: convert rt2x00mmio_register_read return type 

This is a semi-automated conversion to change rt2x00mmio_register_read
to return the register contents instead of passing them by value,
resulting in much better object code. The majority of the patch
was done using:

sed -i 's:\(rt2x00mmio_register_read(.*, .*\), &\(.*\));:\2 = \1);:' \
    -i 's:_rt2x00mmio_register_read:rt2x00mmio_register_read:' \
	drivers/net/wireless/ralink/rt2x00/*.c

The function itself was modified manually along with the one remaining
caller that was not covered automatically.
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
parent aea8baa1
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 252 additions and 259 deletions
drivers/net/wireless/ralink/rt2x00/rt2800mmio.c
View file @ 3954b4e3
...@@ -331,7 +331,7 @@ static inline void rt2800mmio_enable_interrupt(struct rt2x00_dev *rt2x00dev, ...@@ -331,7 +331,7 @@ static inline void rt2800mmio_enable_interrupt(struct rt2x00_dev *rt2x00dev,
* access needs locking. * access needs locking.
*/ */
spin_lock_irq(&rt2x00dev->irqmask_lock); spin_lock_irq(&rt2x00dev->irqmask_lock);
rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg); reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR);
rt2x00_set_field32(&reg, irq_field, 1); rt2x00_set_field32(&reg, irq_field, 1);
rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
spin_unlock_irq(&rt2x00dev->irqmask_lock); spin_unlock_irq(&rt2x00dev->irqmask_lock);
...@@ -376,12 +376,12 @@ void rt2800mmio_tbtt_tasklet(unsigned long data) ...@@ -376,12 +376,12 @@ void rt2800mmio_tbtt_tasklet(unsigned long data)
* interval every 64 beacons by 64us to mitigate this effect. * interval every 64 beacons by 64us to mitigate this effect.
*/ */
if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 2)) { if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 2)) {
rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg); reg = rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG);
rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
(rt2x00dev->beacon_int * 16) - 1); (rt2x00dev->beacon_int * 16) - 1);
rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg); rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
} else if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 1)) { } else if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 1)) {
rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg); reg = rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG);
rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
(rt2x00dev->beacon_int * 16)); (rt2x00dev->beacon_int * 16));
rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg); rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
...@@ -439,7 +439,7 @@ static void rt2800mmio_txstatus_interrupt(struct rt2x00_dev *rt2x00dev) ...@@ -439,7 +439,7 @@ static void rt2800mmio_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
* need to lock the kfifo. * need to lock the kfifo.
*/ */
for (i = 0; i < rt2x00dev->tx->limit; i++) { for (i = 0; i < rt2x00dev->tx->limit; i++) {
rt2x00mmio_register_read(rt2x00dev, TX_STA_FIFO, &status); status = rt2x00mmio_register_read(rt2x00dev, TX_STA_FIFO);
if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID)) if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
break; break;
...@@ -460,7 +460,7 @@ irqreturn_t rt2800mmio_interrupt(int irq, void *dev_instance) ...@@ -460,7 +460,7 @@ irqreturn_t rt2800mmio_interrupt(int irq, void *dev_instance)
u32 reg, mask; u32 reg, mask;
/* Read status and ACK all interrupts */ /* Read status and ACK all interrupts */
rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, &reg); reg = rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR);
rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
if (!reg) if (!reg)
...@@ -501,7 +501,7 @@ irqreturn_t rt2800mmio_interrupt(int irq, void *dev_instance) ...@@ -501,7 +501,7 @@ irqreturn_t rt2800mmio_interrupt(int irq, void *dev_instance)
* the tasklet will reenable the appropriate interrupts. * the tasklet will reenable the appropriate interrupts.
*/ */
spin_lock(&rt2x00dev->irqmask_lock); spin_lock(&rt2x00dev->irqmask_lock);
rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg); reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR);
reg &= mask; reg &= mask;
rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
spin_unlock(&rt2x00dev->irqmask_lock); spin_unlock(&rt2x00dev->irqmask_lock);
...@@ -521,7 +521,7 @@ void rt2800mmio_toggle_irq(struct rt2x00_dev *rt2x00dev, ...@@ -521,7 +521,7 @@ void rt2800mmio_toggle_irq(struct rt2x00_dev *rt2x00dev,
* should clear the register to assure a clean state. * should clear the register to assure a clean state.
*/ */
if (state == STATE_RADIO_IRQ_ON) { if (state == STATE_RADIO_IRQ_ON) {
rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, &reg); reg = rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR);
rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
} }
...@@ -560,18 +560,18 @@ void rt2800mmio_start_queue(struct data_queue *queue) ...@@ -560,18 +560,18 @@ void rt2800mmio_start_queue(struct data_queue *queue)
switch (queue->qid) { switch (queue->qid) {
case QID_RX: case QID_RX:
rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); reg = rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL);
rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1); rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg); rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
break; break;
case QID_BEACON: case QID_BEACON:
rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg); reg = rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG);
rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1); rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1); rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1); rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg); rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN, &reg); reg = rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN);
rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1); rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
rt2x00mmio_register_write(rt2x00dev, INT_TIMER_EN, reg); rt2x00mmio_register_write(rt2x00dev, INT_TIMER_EN, reg);
break; break;
...@@ -613,18 +613,18 @@ void rt2800mmio_stop_queue(struct data_queue *queue) ...@@ -613,18 +613,18 @@ void rt2800mmio_stop_queue(struct data_queue *queue)
switch (queue->qid) { switch (queue->qid) {
case QID_RX: case QID_RX:
rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); reg = rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL);
rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0); rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg); rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
break; break;
case QID_BEACON: case QID_BEACON:
rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg); reg = rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG);
rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0); rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0); rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0); rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg); rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN, &reg); reg = rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN);
rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0); rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
rt2x00mmio_register_write(rt2x00dev, INT_TIMER_EN, reg); rt2x00mmio_register_write(rt2x00dev, INT_TIMER_EN, reg);
...@@ -810,7 +810,7 @@ int rt2800mmio_init_registers(struct rt2x00_dev *rt2x00dev) ...@@ -810,7 +810,7 @@ int rt2800mmio_init_registers(struct rt2x00_dev *rt2x00dev)
/* /*
* Reset DMA indexes * Reset DMA indexes
*/ */
rt2x00mmio_register_read(rt2x00dev, WPDMA_RST_IDX, &reg); reg = rt2x00mmio_register_read(rt2x00dev, WPDMA_RST_IDX);
rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1); rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1); rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1); rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
...@@ -831,7 +831,7 @@ int rt2800mmio_init_registers(struct rt2x00_dev *rt2x00dev) ...@@ -831,7 +831,7 @@ int rt2800mmio_init_registers(struct rt2x00_dev *rt2x00dev)
rt2x00_rt(rt2x00dev, RT5390) || rt2x00_rt(rt2x00dev, RT5390) ||
rt2x00_rt(rt2x00dev, RT5392) || rt2x00_rt(rt2x00dev, RT5392) ||
rt2x00_rt(rt2x00dev, RT5592))) { rt2x00_rt(rt2x00dev, RT5592))) {
rt2x00mmio_register_read(rt2x00dev, AUX_CTRL, &reg); reg = rt2x00mmio_register_read(rt2x00dev, AUX_CTRL);
rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1); rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1); rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
rt2x00mmio_register_write(rt2x00dev, AUX_CTRL, reg); rt2x00mmio_register_write(rt2x00dev, AUX_CTRL, reg);
......
drivers/net/wireless/ralink/rt2x00/rt2800pci.c
View file @ 3954b4e3
...@@ -69,7 +69,7 @@ static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token) ...@@ -69,7 +69,7 @@ static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
return; return;
for (i = 0; i < 200; i++) { for (i = 0; i < 200; i++) {
rt2x00mmio_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg); reg = rt2x00mmio_register_read(rt2x00dev, H2M_MAILBOX_CID);
if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) || if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
(rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) || (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
...@@ -92,7 +92,7 @@ static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom) ...@@ -92,7 +92,7 @@ static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
struct rt2x00_dev *rt2x00dev = eeprom->data; struct rt2x00_dev *rt2x00dev = eeprom->data;
u32 reg; u32 reg;
rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg); reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR);
eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN); eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT); eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
...@@ -122,7 +122,7 @@ static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev) ...@@ -122,7 +122,7 @@ static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
struct eeprom_93cx6 eeprom; struct eeprom_93cx6 eeprom;
u32 reg; u32 reg;
rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg); reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR);
eeprom.data = rt2x00dev; eeprom.data = rt2x00dev;
eeprom.register_read = rt2800pci_eepromregister_read; eeprom.register_read = rt2800pci_eepromregister_read;
...@@ -325,8 +325,8 @@ static const struct ieee80211_ops rt2800pci_mac80211_ops = { ...@@ -325,8 +325,8 @@ static const struct ieee80211_ops rt2800pci_mac80211_ops = {
}; };
static const struct rt2800_ops rt2800pci_rt2800_ops = { static const struct rt2800_ops rt2800pci_rt2800_ops = {
.register_read = _rt2x00mmio_register_read, .register_read = rt2x00mmio_register_read,
.register_read_lock = _rt2x00mmio_register_read, /* same for PCI */ .register_read_lock = rt2x00mmio_register_read, /* same for PCI */
.register_write = rt2x00mmio_register_write, .register_write = rt2x00mmio_register_write,
.register_write_lock = rt2x00mmio_register_write, /* same for PCI */ .register_write_lock = rt2x00mmio_register_write, /* same for PCI */
.register_multiread = rt2x00mmio_register_multiread, .register_multiread = rt2x00mmio_register_multiread,
......
drivers/net/wireless/ralink/rt2x00/rt2800soc.c
View file @ 3954b4e3
...@@ -164,8 +164,8 @@ static const struct ieee80211_ops rt2800soc_mac80211_ops = { ...@@ -164,8 +164,8 @@ static const struct ieee80211_ops rt2800soc_mac80211_ops = {
}; };
static const struct rt2800_ops rt2800soc_rt2800_ops = { static const struct rt2800_ops rt2800soc_rt2800_ops = {
.register_read = _rt2x00mmio_register_read, .register_read = rt2x00mmio_register_read,
.register_read_lock = _rt2x00mmio_register_read, /* same for SoCs */ .register_read_lock = rt2x00mmio_register_read, /* same for SoCs */
.register_write = rt2x00mmio_register_write, .register_write = rt2x00mmio_register_write,
.register_write_lock = rt2x00mmio_register_write, /* same for SoCs */ .register_write_lock = rt2x00mmio_register_write, /* same for SoCs */
.register_multiread = rt2x00mmio_register_multiread, .register_multiread = rt2x00mmio_register_multiread,
......
drivers/net/wireless/ralink/rt2x00/rt2x00mmio.c
View file @ 3954b4e3
...@@ -43,7 +43,7 @@ int rt2x00mmio_regbusy_read(struct rt2x00_dev *rt2x00dev, ...@@ -43,7 +43,7 @@ int rt2x00mmio_regbusy_read(struct rt2x00_dev *rt2x00dev,
return 0; return 0;
for (i = 0; i < REGISTER_BUSY_COUNT; i++) { for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
rt2x00mmio_register_read(rt2x00dev, offset, reg); *reg = rt2x00mmio_register_read(rt2x00dev, offset);
if (!rt2x00_get_field32(*reg, field)) if (!rt2x00_get_field32(*reg, field))
return 1; return 1;
udelay(REGISTER_BUSY_DELAY); udelay(REGISTER_BUSY_DELAY);
......
drivers/net/wireless/ralink/rt2x00/rt2x00mmio.h
View file @ 3954b4e3
...@@ -29,14 +29,7 @@ ...@@ -29,14 +29,7 @@
/* /*
* Register access. * Register access.
*/ */
static inline void rt2x00mmio_register_read(struct rt2x00_dev *rt2x00dev, static inline u32 rt2x00mmio_register_read(struct rt2x00_dev *rt2x00dev,
const unsigned int offset,
u32 *value)
{
*value = readl(rt2x00dev->csr.base + offset);
}
static inline u32 _rt2x00mmio_register_read(struct rt2x00_dev *rt2x00dev,
const unsigned int offset) const unsigned int offset)
{ {
return readl(rt2x00dev->csr.base + offset); return readl(rt2x00dev->csr.base + offset);
......
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