Commit 3b6b59b6 authored by Alex Deucher's avatar Alex Deucher

drm/radeon: add dma engine support for vm pt updates on ni (v5)

Async DMA has a special packet for contiguous pt updates
which saves overhead.

v2: leave the CP method enabled for now as doing the updates
in the DMA rings is not working properly yet.

v3: update for 2 level pts

v4: rebase

v5: drop pte/pde packet.  doesn't seem to work on NI.
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2d6cc729
...@@ -1795,30 +1795,57 @@ void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe, ...@@ -1795,30 +1795,57 @@ void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe,
{ {
struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index]; struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index];
uint32_t r600_flags = cayman_vm_page_flags(rdev, flags); uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
uint64_t value;
while (count) { unsigned ndw;
unsigned ndw = 1 + count * 2;
if (ndw > 0x3FFF) if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
ndw = 0x3FFF; while (count) {
ndw = 1 + count * 2;
radeon_ring_write(ring, PACKET3(PACKET3_ME_WRITE, ndw)); if (ndw > 0x3FFF)
radeon_ring_write(ring, pe); ndw = 0x3FFF;
radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
for (; ndw > 1; ndw -= 2, --count, pe += 8) { radeon_ring_write(ring, PACKET3(PACKET3_ME_WRITE, ndw));
uint64_t value = 0; radeon_ring_write(ring, pe);
if (flags & RADEON_VM_PAGE_SYSTEM) { radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
value = radeon_vm_map_gart(rdev, addr); for (; ndw > 1; ndw -= 2, --count, pe += 8) {
value &= 0xFFFFFFFFFFFFF000ULL; if (flags & RADEON_VM_PAGE_SYSTEM) {
value = radeon_vm_map_gart(rdev, addr);
value &= 0xFFFFFFFFFFFFF000ULL;
} else if (flags & RADEON_VM_PAGE_VALID) {
value = addr;
} else {
value = 0;
}
addr += incr; addr += incr;
value |= r600_flags;
} else if (flags & RADEON_VM_PAGE_VALID) { radeon_ring_write(ring, value);
value = addr; radeon_ring_write(ring, upper_32_bits(value));
}
}
} else {
while (count) {
ndw = count * 2;
if (ndw > 0xFFFFE)
ndw = 0xFFFFE;
/* for non-physically contiguous pages (system) */
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, ndw));
radeon_ring_write(ring, pe);
radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
for (; ndw > 0; ndw -= 2, --count, pe += 8) {
if (flags & RADEON_VM_PAGE_SYSTEM) {
value = radeon_vm_map_gart(rdev, addr);
value &= 0xFFFFFFFFFFFFF000ULL;
} else if (flags & RADEON_VM_PAGE_VALID) {
value = addr;
} else {
value = 0;
}
addr += incr; addr += incr;
value |= r600_flags;
radeon_ring_write(ring, value);
radeon_ring_write(ring, upper_32_bits(value));
} }
value |= r600_flags;
radeon_ring_write(ring, value);
radeon_ring_write(ring, upper_32_bits(value));
} }
} }
} }
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment