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Commit 3b7faeb4 authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt
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Merge commit 'kumar/next' into next

parents 82a0a1cc 96a8bac5
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arch/powerpc/boot/dts/mpc8572ds.dts
View file @ 3b7faeb4
/*
* MPC8572 DS Device Tree Source
*
* Copyright 2007, 2008 Freescale Semiconductor Inc.
* Copyright 2007-2009 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -643,7 +643,7 @@ pcie@0 {
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
0x0 0x10000>;
uli1575@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
......@@ -654,7 +654,7 @@ uli1575@0 {
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
0x0 0x10000>;
isa@1e {
device_type = "isa";
#interrupt-cells = <2>;
......@@ -744,7 +744,7 @@ pcie@0 {
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
0x0 0x10000>;
};
};
......@@ -781,7 +781,7 @@ pcie@0 {
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
0x0 0x10000>;
};
};
};
arch/powerpc/boot/dts/mpc8572ds_36b.dts 0 → 100644
View file @ 3b7faeb4
/*
* MPC8572 DS Device Tree Source
*
* Copyright 2007-2009 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
model = "fsl,MPC8572DS";
compatible = "fsl,MPC8572DS";
#address-cells = <2>;
#size-cells = <2>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
ethernet2 = &enet2;
ethernet3 = &enet3;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
pci1 = &pci1;
pci2 = &pci2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8572@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
PowerPC,8572@1 {
device_type = "cpu";
reg = <0x1>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};
memory {
device_type = "memory";
};
localbus@fffe05000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
reg = <0xf 0xffe05000 0 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
0x1 0x0 0xf 0xe0000000 0x08000000
0x2 0x0 0xf 0xffa00000 0x00040000
0x3 0x0 0xf 0xffdf0000 0x00008000
0x4 0x0 0xf 0xffa40000 0x00040000
0x5 0x0 0xf 0xffa80000 0x00040000
0x6 0x0 0xf 0xffac0000 0x00040000>;
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
ramdisk@0 {
reg = <0x0 0x03000000>;
read-only;
};
diagnostic@3000000 {
reg = <0x03000000 0x00e00000>;
read-only;
};
dink@3e00000 {
reg = <0x03e00000 0x00200000>;
read-only;
};
kernel@4000000 {
reg = <0x04000000 0x00400000>;
read-only;
};
jffs2@4400000 {
reg = <0x04400000 0x03b00000>;
};
dtb@7f00000 {
reg = <0x07f00000 0x00080000>;
read-only;
};
u-boot@7f80000 {
reg = <0x07f80000 0x00080000>;
read-only;
};
};
nand@2,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8572-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <0x2 0x0 0x40000>;
u-boot@0 {
reg = <0x0 0x02000000>;
read-only;
};
jffs2@2000000 {
reg = <0x02000000 0x10000000>;
};
ramdisk@12000000 {
reg = <0x12000000 0x08000000>;
read-only;
};
kernel@1a000000 {
reg = <0x1a000000 0x04000000>;
};
dtb@1e000000 {
reg = <0x1e000000 0x01000000>;
read-only;
};
empty@1f000000 {
reg = <0x1f000000 0x21000000>;
};
};
nand@4,0 {
compatible = "fsl,mpc8572-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <0x4 0x0 0x40000>;
};
nand@5,0 {
compatible = "fsl,mpc8572-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <0x5 0x0 0x40000>;
};
nand@6,0 {
compatible = "fsl,mpc8572-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <0x6 0x0 0x40000>;
};
};
soc8572@fffe00000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
ranges = <0x0 0xf 0xffe00000 0x100000>;
reg = <0xf 0xffe00000 0 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
bus-frequency = <0>; // Filled out by uboot.
memory-controller@2000 {
compatible = "fsl,mpc8572-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
memory-controller@6000 {
compatible = "fsl,mpc8572-memory-controller";
reg = <0x6000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,mpc8572-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x100000>; // L2, 1M
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
dma@c300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
reg = <0xc300 0x4>;
ranges = <0x0 0xc100 0x200>;
cell-index = <1>;
dma-channel@0 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <76 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <77 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <78 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <79 2>;
};
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8572-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
mdio@24520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x24520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <10 1>;
reg = <0x0>;
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <10 1>;
reg = <0x1>;
};
phy2: ethernet-phy@2 {
interrupt-parent = <&mpic>;
interrupts = <10 1>;
reg = <0x2>;
};
phy3: ethernet-phy@3 {
interrupt-parent = <&mpic>;
interrupts = <10 1>;
reg = <0x3>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
mdio@25520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x25520 0x20>;
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
mdio@26520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x26520 0x20>;
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
mdio@27520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x27520 0x20>;
tbi3: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet0: ethernet@24000 {
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
};
enet1: ethernet@25000 {
cell-index = <1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi1>;
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
};
enet2: ethernet@26000 {
cell-index = <2>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi2>;
phy-handle = <&phy2>;
phy-connection-type = "rgmii-id";
};
enet3: ethernet@27000 {
cell-index = <3>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x27000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <37 2 38 2 39 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi3>;
phy-handle = <&phy3>;
phy-connection-type = "rgmii-id";
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { //global utilities block
compatible = "fsl,mpc8572-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
msi@41600 {
compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
reg = <0x41600 0x80>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xe0 0
0xe1 0
0xe2 0
0xe3 0
0xe4 0
0xe5 0
0xe6 0
0xe7 0>;
interrupt-parent = <&mpic>;
};
crypto@30000 {
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
"fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <45 2 58 2>;
interrupt-parent = <&mpic>;
fsl,num-channels = <4>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x9fe>;
fsl,descriptor-types-mask = <0x3ab0ebf>;
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
};
};
pci0: pcie@fffe08000 {
cell-index = <0>;
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xf 0xffe08000 0 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0xc0000000 0xc 0x00000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <24 2>;
interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x11 func 0 - PCI slot 1 */
0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 1 - PCI slot 1 */
0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 2 - PCI slot 1 */
0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 3 - PCI slot 1 */
0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 4 - PCI slot 1 */
0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 5 - PCI slot 1 */
0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 6 - PCI slot 1 */
0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x11 func 7 - PCI slot 1 */
0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
/* IDSEL 0x12 func 0 - PCI slot 2 */
0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 1 - PCI slot 2 */
0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 2 - PCI slot 2 */
0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 3 - PCI slot 2 */
0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 4 - PCI slot 2 */
0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 5 - PCI slot 2 */
0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 6 - PCI slot 2 */
0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
/* IDSEL 0x12 func 7 - PCI slot 2 */
0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
// IDSEL 0x1c USB
0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
// IDSEL 0x1d Audio
0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
// IDSEL 0x1e Legacy
0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
// IDSEL 0x1f IDE/SATA
0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x2000000 0x0 0xc0000000
0x2000000 0x0 0xc0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x10000>;
uli1575@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
ranges = <0x2000000 0x0 0xc0000000
0x2000000 0x0 0xc0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x10000>;
isa@1e {
device_type = "isa";
#interrupt-cells = <2>;
#size-cells = <1>;
#address-cells = <2>;
reg = <0xf000 0x0 0x0 0x0 0x0>;
ranges = <0x1 0x0 0x1000000 0x0 0x0
0x1000>;
interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 {
reg = <0x1 0x20 0x2
0x1 0xa0 0x2
0x1 0x4d0 0x2>;
interrupt-controller;
device_type = "interrupt-controller";
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "chrp,iic";
interrupts = <9 2>;
interrupt-parent = <&mpic>;
};
i8042@60 {
#size-cells = <0>;
#address-cells = <1>;
reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
interrupts = <1 3 12 3>;
interrupt-parent =
<&i8259>;
keyboard@0 {
reg = <0x0>;
compatible = "pnpPNP,303";
};
mouse@1 {
reg = <0x1>;
compatible = "pnpPNP,f03";
};
};
rtc@70 {
compatible = "pnpPNP,b00";
reg = <0x1 0x70 0x2>;
};
gpio@400 {
reg = <0x1 0x400 0x80>;
};
};
};
};
};
pci1: pcie@fffe09000 {
cell-index = <1>;
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xf 0xffe09000 0 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <25 2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0x0 0x0 0x1 &mpic 0x4 0x1
0000 0x0 0x0 0x2 &mpic 0x5 0x1
0000 0x0 0x0 0x3 &mpic 0x6 0x1
0000 0x0 0x0 0x4 &mpic 0x7 0x1
>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x2000000 0x0 0xc0000000
0x2000000 0x0 0xc0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x10000>;
};
};
pci2: pcie@fffe0a000 {
cell-index = <2>;
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xf 0xffe0a000 0 0x1000>;
bus-range = <0 255>;
ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x00010000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <26 2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0x0 0x0 0x1 &mpic 0x0 0x1
0000 0x0 0x0 0x2 &mpic 0x1 0x1
0000 0x0 0x0 0x3 &mpic 0x2 0x1
0000 0x0 0x0 0x4 &mpic 0x3 0x1
>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x2000000 0x0 0xc0000000
0x2000000 0x0 0xc0000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x10000>;
};
};
};
arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
View file @ 3b7faeb4
......@@ -6,7 +6,7 @@
* This dts file allows core0 to have memory, l2, i2c, dma1, global-util, eth0,
* eth1, crypto, pci0, pci1.
*
* Copyright 2007, 2008 Freescale Semiconductor Inc.
* Copyright 2007-2009 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -376,7 +376,7 @@ pcie@0 {
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
0x0 0x10000>;
uli1575@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
......@@ -387,7 +387,7 @@ uli1575@0 {
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
0x0 0x10000>;
isa@1e {
device_type = "isa";
#interrupt-cells = <2>;
......@@ -477,7 +477,7 @@ pcie@0 {
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
0x0 0x10000>;
};
};
};
arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
View file @ 3b7faeb4
......@@ -7,7 +7,7 @@
*
* Please note to add "-b 1" for core1's dts compiling.
*
* Copyright 2007, 2008 Freescale Semiconductor Inc.
* Copyright 2007-2009 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
......@@ -228,7 +228,7 @@ pcie@0 {
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x100000>;
0x0 0x10000>;
};
};
};
arch/powerpc/include/asm/mmu-fsl-booke.h → arch/powerpc/include/asm/mmu-book3e.h
View file @ 3b7faeb4
#ifndef _ASM_POWERPC_MMU_FSL_BOOKE_H_
#define _ASM_POWERPC_MMU_FSL_BOOKE_H_
#ifndef _ASM_POWERPC_MMU_BOOK3E_H_
#define _ASM_POWERPC_MMU_BOOK3E_H_
/*
* Freescale Book-E MMU support
* Freescale Book-E/Book-3e (ISA 2.06+) MMU support
*/
/* Book-E defined page sizes */
#define BOOKE_PAGESZ_1K 0
#define BOOKE_PAGESZ_4K 1
#define BOOKE_PAGESZ_16K 2
#define BOOKE_PAGESZ_64K 3
#define BOOKE_PAGESZ_256K 4
#define BOOKE_PAGESZ_1M 5
#define BOOKE_PAGESZ_4M 6
#define BOOKE_PAGESZ_16M 7
#define BOOKE_PAGESZ_64M 8
#define BOOKE_PAGESZ_256M 9
#define BOOKE_PAGESZ_1GB 10
#define BOOKE_PAGESZ_4GB 11
#define BOOKE_PAGESZ_16GB 12
#define BOOKE_PAGESZ_64GB 13
#define BOOKE_PAGESZ_256GB 14
#define BOOKE_PAGESZ_1TB 15
/* Book-3e defined page sizes */
#define BOOK3E_PAGESZ_1K 0
#define BOOK3E_PAGESZ_2K 1
#define BOOK3E_PAGESZ_4K 2
#define BOOK3E_PAGESZ_8K 3
#define BOOK3E_PAGESZ_16K 4
#define BOOK3E_PAGESZ_32K 5
#define BOOK3E_PAGESZ_64K 6
#define BOOK3E_PAGESZ_128K 7
#define BOOK3E_PAGESZ_256K 8
#define BOOK3E_PAGESZ_512K 9
#define BOOK3E_PAGESZ_1M 10
#define BOOK3E_PAGESZ_2M 11
#define BOOK3E_PAGESZ_4M 12
#define BOOK3E_PAGESZ_8M 13
#define BOOK3E_PAGESZ_16M 14
#define BOOK3E_PAGESZ_32M 15
#define BOOK3E_PAGESZ_64M 16
#define BOOK3E_PAGESZ_128M 17
#define BOOK3E_PAGESZ_256M 18
#define BOOK3E_PAGESZ_512M 19
#define BOOK3E_PAGESZ_1GB 20
#define BOOK3E_PAGESZ_2GB 21
#define BOOK3E_PAGESZ_4GB 22
#define BOOK3E_PAGESZ_8GB 23
#define BOOK3E_PAGESZ_16GB 24
#define BOOK3E_PAGESZ_32GB 25
#define BOOK3E_PAGESZ_64GB 26
#define BOOK3E_PAGESZ_128GB 27
#define BOOK3E_PAGESZ_256GB 28
#define BOOK3E_PAGESZ_512GB 29
#define BOOK3E_PAGESZ_1TB 30
#define BOOK3E_PAGESZ_2TB 31
#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000)
#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000)
......@@ -29,8 +45,9 @@
#define MAS1_VALID 0x80000000
#define MAS1_IPROT 0x40000000
#define MAS1_TID(x) ((x << 16) & 0x3FFF0000)
#define MAS1_IND 0x00002000
#define MAS1_TS 0x00001000
#define MAS1_TSIZE(x) ((x << 8) & 0x00000F00)
#define MAS1_TSIZE(x) ((x << 7) & 0x00000F80)
#define MAS2_EPN 0xFFFFF000
#define MAS2_X0 0x00000040
......@@ -40,7 +57,7 @@
#define MAS2_M 0x00000004
#define MAS2_G 0x00000002
#define MAS2_E 0x00000001
#define MAS2_EPN_MASK(size) (~0 << (2*(size) + 10))
#define MAS2_EPN_MASK(size) (~0 << (size + 10))
#define MAS2_VAL(addr, size, flags) ((addr) & MAS2_EPN_MASK(size) | (flags))
#define MAS3_RPN 0xFFFFF000
......@@ -56,7 +73,7 @@
#define MAS3_SR 0x00000001
#define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
#define MAS4_TIDDSEL 0x000F0000
#define MAS4_INDD 0x00008000
#define MAS4_TSIZED(x) MAS1_TSIZE(x)
#define MAS4_X0D 0x00000040
#define MAS4_X1D 0x00000020
......@@ -68,6 +85,7 @@
#define MAS6_SPID0 0x3FFF0000
#define MAS6_SPID1 0x00007FFE
#define MAS6_ISIZE(x) MAS1_TSIZE(x)
#define MAS6_SAS 0x00000001
#define MAS6_SPID MAS6_SPID0
......@@ -82,4 +100,4 @@ typedef struct {
} mm_context_t;
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_POWERPC_MMU_FSL_BOOKE_H_ */
#endif /* _ASM_POWERPC_MMU_BOOK3E_H_ */
arch/powerpc/include/asm/mmu.h
View file @ 3b7faeb4
......@@ -71,9 +71,9 @@ extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
#elif defined(CONFIG_44x)
/* 44x-style software loaded TLB */
# include <asm/mmu-44x.h>
#elif defined(CONFIG_FSL_BOOKE)
/* Freescale Book-E software loaded TLB */
# include <asm/mmu-fsl-booke.h>
#elif defined(CONFIG_PPC_BOOK3E_MMU)
/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
# include <asm/mmu-book3e.h>
#elif defined (CONFIG_PPC_8xx)
/* Motorola/Freescale 8xx software loaded TLB */
# include <asm/mmu-8xx.h>
......
arch/powerpc/kernel/entry_32.S
View file @ 3b7faeb4
......@@ -63,7 +63,7 @@ debug_transfer_to_handler:
.globl crit_transfer_to_handler
crit_transfer_to_handler:
#ifdef CONFIG_FSL_BOOKE
#ifdef CONFIG_PPC_BOOK3E_MMU
mfspr r0,SPRN_MAS0
stw r0,MAS0(r11)
mfspr r0,SPRN_MAS1
......@@ -78,7 +78,7 @@ crit_transfer_to_handler:
mfspr r0,SPRN_MAS7
stw r0,MAS7(r11)
#endif /* CONFIG_PHYS_64BIT */
#endif /* CONFIG_FSL_BOOKE */
#endif /* CONFIG_PPC_BOOK3E_MMU */
#ifdef CONFIG_44x
mfspr r0,SPRN_MMUCR
stw r0,MMUCR(r11)
......@@ -914,7 +914,7 @@ exc_exit_restart_end:
mtspr SPRN_##exc_lvl_srr0,r9; \
mtspr SPRN_##exc_lvl_srr1,r10;
#if defined(CONFIG_FSL_BOOKE)
#if defined(CONFIG_PPC_BOOK3E_MMU)
#ifdef CONFIG_PHYS_64BIT
#define RESTORE_MAS7 \
lwz r11,MAS7(r1); \
......
arch/powerpc/kernel/head_fsl_booke.S
View file @ 3b7faeb4
......@@ -173,7 +173,7 @@ skpinv: addi r6,r6,1 /* Increment */
/* grab and fixup the RPN */
mfspr r6,SPRN_MAS1 /* extract MAS1[SIZE] */
rlwinm r6,r6,25,27,30
rlwinm r6,r6,25,27,31
li r8,-1
addi r6,r6,10
slw r6,r8,r6 /* convert to mask */
......@@ -199,7 +199,7 @@ skpinv: addi r6,r6,1 /* Increment */
xori r6,r4,1 /* Setup TMP mapping in the other Address space */
slwi r6,r6,12
oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h
ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_4K))@l
mtspr SPRN_MAS1,r6
mfspr r6,SPRN_MAS2
li r7,0 /* temp EPN = 0 */
......@@ -257,10 +257,10 @@ skpinv: addi r6,r6,1 /* Increment */
lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
mtspr SPRN_MAS0,r6
lis r6,(MAS1_VALID|MAS1_IPROT)@h
ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l
mtspr SPRN_MAS1,r6
lis r6,MAS2_VAL(PAGE_OFFSET, BOOKE_PAGESZ_64M, M_IF_SMP)@h
ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOKE_PAGESZ_64M, M_IF_SMP)@l
lis r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@h
ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@l
mtspr SPRN_MAS2,r6
mtspr SPRN_MAS3,r8
tlbwe
......@@ -315,7 +315,7 @@ skpinv: addi r6,r6,1 /* Increment */
mtspr SPRN_IVPR,r4
/* Setup the defaults for TLB entries */
li r2,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l
li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
#ifdef CONFIG_E200
oris r2,r2,MAS4_TLBSELD(1)@h
#endif
......@@ -1116,7 +1116,7 @@ __secondary_start:
mtspr SPRN_SPRG3,r4
/* Setup the defaults for TLB entries */
li r4,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l
li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
mtspr SPRN_MAS4,r4
/* Jump to start_secondary */
......
arch/powerpc/mm/fsl_booke_mmu.c
View file @ 3b7faeb4
......@@ -111,7 +111,7 @@ void settlbcam(int index, unsigned long virt, phys_addr_t phys,
unsigned int tsize, lz;
asm ("cntlzw %0,%1" : "=r" (lz) : "r" (size));
tsize = (21 - lz) / 2;
tsize = 21 - lz;
#ifdef CONFIG_SMP
if ((flags & _PAGE_NO_CACHE) == 0)
......@@ -218,7 +218,7 @@ adjust_total_lowmem(void)
p += sprintf(p, "0/");
p[-1] = '\0';
pr_info("Memory CAM mapping: %s Mb, residual: %ldMb\n", buf,
(total_lowmem - __max_low_memory) >> 20);
pr_info("Memory CAM mapping: %s Mb, residual: %dMb\n", buf,
(unsigned int)((total_lowmem - __max_low_memory) >> 20));
__initial_memory_limit_addr = memstart_addr + __max_low_memory;
}
arch/powerpc/platforms/Kconfig.cputype
View file @ 3b7faeb4
......@@ -210,6 +210,10 @@ config PPC_MMU_NOHASH
def_bool y
depends on !PPC_STD_MMU
config PPC_BOOK3E_MMU
def_bool y
depends on FSL_BOOKE
config PPC_MM_SLICES
bool
default y if HUGETLB_PAGE || (PPC_STD_MMU_64 && PPC_64K_PAGES)
......
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