Commit 3b921832 authored by Krzysztof Helt's avatar Krzysztof Helt Committed by Linus Torvalds

cirrusfb: fix 16bpp modes

The 16bpp mode did not work on the Cirrus cards as the visual type was set
to DIRECTCOLOR instead of TRUECOLOR.  The Alpine family used one incorrect
register setting so this 16bpp modes generated wrong horizontal frequency.
Signed-off-by: default avatarKrzysztof Helt <krzysztof.h1@wp.pl>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 55a0dd83
...@@ -657,7 +657,7 @@ static int cirrusfb_decode_var(const struct fb_var_screeninfo *var, ...@@ -657,7 +657,7 @@ static int cirrusfb_decode_var(const struct fb_var_screeninfo *var,
case 16: case 16:
case 32: case 32:
info->fix.line_length = var->xres_virtual * maxclockidx; info->fix.line_length = var->xres_virtual * maxclockidx;
info->fix.visual = FB_VISUAL_DIRECTCOLOR; info->fix.visual = FB_VISUAL_TRUECOLOR;
break; break;
default: default:
...@@ -1178,10 +1178,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info) ...@@ -1178,10 +1178,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
case BT_ALPINE: case BT_ALPINE:
DPRINTK(" (for GD543x)\n"); DPRINTK(" (for GD543x)\n");
if (var->xres >= 1024) vga_wseq(regbase, CL_SEQR7, 0xa7);
vga_wseq(regbase, CL_SEQR7, 0xa7);
else
vga_wseq(regbase, CL_SEQR7, 0xa3);
cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK); cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
break; break;
......
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