Commit 3bd44d99 authored by Arend van Spriel's avatar Arend van Spriel Committed by John W. Linville

brcmfmac: correct detection of save&restore device capability

The detection of the save&restore capability in brcmf_sdio_sr_capable()
is only valid for certain chipsets. This patch should cover it for all
chipsets currently supported.
Reviewed-by: default avatarHante Meuleman <meuleman@broadcom.com>
Reviewed-by: default avatarFranky Lin <frankyl@broadcom.com>
Reviewed-by: default avatarPieter-Paul Giesberts <pieterpg@broadcom.com>
Signed-off-by: default avatarArend van Spriel <arend@broadcom.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent af35f55f
...@@ -3384,7 +3384,8 @@ static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus) ...@@ -3384,7 +3384,8 @@ static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus)
static bool brcmf_sdio_sr_capable(struct brcmf_sdio *bus) static bool brcmf_sdio_sr_capable(struct brcmf_sdio *bus)
{ {
u32 addr, reg; u32 addr, reg, pmu_cc3_mask = ~0;
int err;
brcmf_dbg(TRACE, "Enter\n"); brcmf_dbg(TRACE, "Enter\n");
...@@ -3392,13 +3393,27 @@ static bool brcmf_sdio_sr_capable(struct brcmf_sdio *bus) ...@@ -3392,13 +3393,27 @@ static bool brcmf_sdio_sr_capable(struct brcmf_sdio *bus)
if (bus->ci->pmurev < 17) if (bus->ci->pmurev < 17)
return false; return false;
/* read PMU chipcontrol register 3*/ switch (bus->ci->chip) {
addr = CORE_CC_REG(bus->ci->c_inf[0].base, chipcontrol_addr); case BCM43241_CHIP_ID:
brcmf_sdiod_regwl(bus->sdiodev, addr, 3, NULL); case BCM4335_CHIP_ID:
addr = CORE_CC_REG(bus->ci->c_inf[0].base, chipcontrol_data); case BCM4339_CHIP_ID:
reg = brcmf_sdiod_regrl(bus->sdiodev, addr, NULL); /* read PMU chipcontrol register 3 */
addr = CORE_CC_REG(bus->ci->c_inf[0].base, chipcontrol_addr);
brcmf_sdiod_regwl(bus->sdiodev, addr, 3, NULL);
addr = CORE_CC_REG(bus->ci->c_inf[0].base, chipcontrol_data);
reg = brcmf_sdiod_regrl(bus->sdiodev, addr, NULL);
return (reg & pmu_cc3_mask) != 0;
default:
addr = CORE_CC_REG(bus->ci->c_inf[0].base, pmucapabilities_ext);
reg = brcmf_sdiod_regrl(bus->sdiodev, addr, &err);
if ((reg & PCAPEXT_SR_SUPPORTED_MASK) == 0)
return false;
return (bool)reg; addr = CORE_CC_REG(bus->ci->c_inf[0].base, retention_ctl);
reg = brcmf_sdiod_regrl(bus->sdiodev, addr, NULL);
return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK |
PMU_RCTL_LOGIC_DISABLE_MASK)) == 0;
}
} }
static void brcmf_sdio_sr_init(struct brcmf_sdio *bus) static void brcmf_sdio_sr_init(struct brcmf_sdio *bus)
......
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