Commit 3c2ee2d9 authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt

Merge commit 'kumar/next' into next

parents 67764263 1dcd8ffc
...@@ -173,6 +173,14 @@ scc4: serial@11a60 { ...@@ -173,6 +173,14 @@ scc4: serial@11a60 {
fsl,cpm-command = <0xce00000>; fsl,cpm-command = <0xce00000>;
}; };
usb@11b60 {
compatible = "fsl,mpc8272-cpm-usb";
reg = <0x11b60 0x40 0x8b00 0x100>;
interrupts = <11 8>;
interrupt-parent = <&PIC>;
mode = "peripheral";
};
mdio@10d40 { mdio@10d40 {
device_type = "mdio"; device_type = "mdio";
compatible = "fsl,mpc8272ads-mdio-bitbang", compatible = "fsl,mpc8272ads-mdio-bitbang",
......
...@@ -250,6 +250,14 @@ usb@2b000 { ...@@ -250,6 +250,14 @@ usb@2b000 {
phy_type = "ulpi"; phy_type = "ulpi";
}; };
sdhci@2e000 {
compatible = "fsl,mpc8536-esdhc", "fsl,esdhc";
reg = <0x2e000 0x1000>;
interrupts = <72 0x2>;
interrupt-parent = <&mpic>;
clock-frequency = <250000000>;
};
serial0: serial@4500 { serial0: serial@4500 {
cell-index = <0>; cell-index = <0>;
device_type = "serial"; device_type = "serial";
......
...@@ -250,6 +250,14 @@ usb@2b000 { ...@@ -250,6 +250,14 @@ usb@2b000 {
phy_type = "ulpi"; phy_type = "ulpi";
}; };
sdhci@2e000 {
compatible = "fsl,mpc8536-esdhc", "fsl,esdhc";
reg = <0x2e000 0x1000>;
interrupts = <72 0x2>;
interrupt-parent = <&mpic>;
clock-frequency = <250000000>;
};
serial0: serial@4500 { serial0: serial@4500 {
cell-index = <0>; cell-index = <0>;
device_type = "serial"; device_type = "serial";
......
...@@ -99,8 +99,18 @@ partition@1f80000 { ...@@ -99,8 +99,18 @@ partition@1f80000 {
}; };
bcsr@1,0 { bcsr@1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8569mds-bcsr"; compatible = "fsl,mpc8569mds-bcsr";
reg = <1 0 0x8000>; reg = <1 0 0x8000>;
ranges = <0 1 0 0x8000>;
bcsr17: gpio-controller@11 {
#gpio-cells = <2>;
compatible = "fsl,mpc8569mds-bcsr-gpio";
reg = <0x11 0x1>;
gpio-controller;
};
}; };
nand@3,0 { nand@3,0 {
...@@ -315,6 +325,14 @@ qe_pio_e: gpio-controller@80 { ...@@ -315,6 +325,14 @@ qe_pio_e: gpio-controller@80 {
gpio-controller; gpio-controller;
}; };
qe_pio_f: gpio-controller@a0 {
#gpio-cells = <2>;
compatible = "fsl,mpc8569-qe-pario-bank",
"fsl,mpc8323-qe-pario-bank";
reg = <0xa0 0x18>;
gpio-controller;
};
pio1: ucc_pin@01 { pio1: ucc_pin@01 {
pio-map = < pio-map = <
/* port pin dir open_drain assignment has_irq */ /* port pin dir open_drain assignment has_irq */
...@@ -419,6 +437,16 @@ qeic: interrupt-controller@80 { ...@@ -419,6 +437,16 @@ qeic: interrupt-controller@80 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
}; };
timer@440 {
compatible = "fsl,mpc8569-qe-gtm",
"fsl,qe-gtm", "fsl,gtm";
reg = <0x440 0x40>;
interrupts = <12 13 14 15>;
interrupt-parent = <&qeic>;
/* Filled in by U-Boot */
clock-frequency = <0>;
};
spi@4c0 { spi@4c0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
...@@ -446,6 +474,23 @@ spi@500 { ...@@ -446,6 +474,23 @@ spi@500 {
mode = "cpu"; mode = "cpu";
}; };
usb@6c0 {
compatible = "fsl,mpc8569-qe-usb",
"fsl,mpc8323-qe-usb";
reg = <0x6c0 0x40 0x8b00 0x100>;
interrupts = <11>;
interrupt-parent = <&qeic>;
fsl,fullspeed-clock = "clk5";
fsl,lowspeed-clock = "brg10";
gpios = <&qe_pio_f 3 0 /* USBOE */
&qe_pio_f 4 0 /* USBTP */
&qe_pio_f 5 0 /* USBTN */
&qe_pio_f 6 0 /* USBRP */
&qe_pio_f 8 0 /* USBRN */
&bcsr17 6 0 /* SPEED */
&bcsr17 5 1>; /* POWER */
};
enet0: ucc@2000 { enet0: ucc@2000 {
device_type = "network"; device_type = "network";
compatible = "ucc_geth"; compatible = "ucc_geth";
......
This diff is collapsed.
...@@ -146,18 +146,6 @@ usb@22000 { ...@@ -146,18 +146,6 @@ usb@22000 {
phy_type = "ulpi"; phy_type = "ulpi";
port0; port0;
}; };
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
usb@23000 {
device_type = "usb";
compatible = "fsl-usb2-dr";
reg = <0x23000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&ipic>;
interrupts = <38 0x8>;
dr_mode = "otg";
phy_type = "ulpi";
};
enet0: ethernet@24000 { enet0: ethernet@24000 {
#address-cells = <1>; #address-cells = <1>;
...@@ -277,15 +265,55 @@ ipic: pic@700 { ...@@ -277,15 +265,55 @@ ipic: pic@700 {
}; };
}; };
localbus@e0005000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8349-localbus", "simple-bus";
reg = <0xe0005000 0x1000>;
interrupts = <77 0x8>;
interrupt-parent = <&ipic>;
ranges = <0x0 0x0 0xff800000 0x00800000 /* 8MB Flash */
0x1 0x0 0xf8000000 0x00002000 /* 8KB EEPROM */
0x2 0x0 0x10000000 0x04000000 /* 64MB SDRAM */
0x3 0x0 0x10000000 0x04000000>; /* 64MB SDRAM */
flash@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "intel,28F640J3A", "cfi-flash";
reg = <0x0 0x0 0x800000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
label = "u-boot";
reg = <0x00000000 0x00040000>;
read-only;
};
partition@40000 {
label = "user";
reg = <0x00040000 0x006c0000>;
};
partition@700000 {
label = "legacy u-boot";
reg = <0x00700000 0x00100000>;
read-only;
};
};
};
pci0: pci@e0008500 { pci0: pci@e0008500 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>; interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x11 */ /* IDSEL 0x11 */
0x8800 0x0 0x0 0x1 &ipic 20 0x8 0x8800 0x0 0x0 0x1 &ipic 48 0x8
0x8800 0x0 0x0 0x2 &ipic 21 0x8 0x8800 0x0 0x0 0x2 &ipic 17 0x8
0x8800 0x0 0x0 0x3 &ipic 22 0x8 0x8800 0x0 0x0 0x3 &ipic 18 0x8
0x8800 0x0 0x0 0x4 &ipic 23 0x8>; 0x8800 0x0 0x0 0x4 &ipic 19 0x8>;
interrupt-parent = <&ipic>; interrupt-parent = <&ipic>;
interrupts = <0x42 0x8>; interrupts = <0x42 0x8>;
......
...@@ -303,7 +303,6 @@ enet3: ethernet@91340 { ...@@ -303,7 +303,6 @@ enet3: ethernet@91340 {
global-utilities@e0000 { global-utilities@e0000 {
compatible = "fsl,mpc8560-guts"; compatible = "fsl,mpc8560-guts";
reg = <0xe0000 0x1000>; reg = <0xe0000 0x1000>;
fsl,has-rstcr;
}; };
}; };
......
This diff is collapsed.
# #
# Automatically generated make config: don't edit # Automatically generated make config: don't edit
# Linux kernel version: 2.6.31-rc4 # Linux kernel version: 2.6.31-rc5
# Wed Jul 29 23:31:51 2009 # Fri Aug 7 08:19:15 2009
# #
# CONFIG_PPC64 is not set # CONFIG_PPC64 is not set
...@@ -158,6 +158,7 @@ CONFIG_BASE_SMALL=0 ...@@ -158,6 +158,7 @@ CONFIG_BASE_SMALL=0
# CONFIG_MODULES is not set # CONFIG_MODULES is not set
CONFIG_BLOCK=y CONFIG_BLOCK=y
CONFIG_LBDAF=y CONFIG_LBDAF=y
CONFIG_BLK_DEV_BSG=y
# CONFIG_BLK_DEV_INTEGRITY is not set # CONFIG_BLK_DEV_INTEGRITY is not set
# #
...@@ -506,6 +507,7 @@ CONFIG_MTD_PHYSMAP_OF=y ...@@ -506,6 +507,7 @@ CONFIG_MTD_PHYSMAP_OF=y
# CONFIG_MTD_UBI is not set # CONFIG_MTD_UBI is not set
CONFIG_OF_DEVICE=y CONFIG_OF_DEVICE=y
CONFIG_OF_GPIO=y CONFIG_OF_GPIO=y
CONFIG_OF_I2C=y
CONFIG_OF_MDIO=y CONFIG_OF_MDIO=y
# CONFIG_PARPORT is not set # CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y CONFIG_BLK_DEV=y
...@@ -582,7 +584,8 @@ CONFIG_PHYLIB=y ...@@ -582,7 +584,8 @@ CONFIG_PHYLIB=y
# CONFIG_STE10XP is not set # CONFIG_STE10XP is not set
# CONFIG_LSI_ET1011C_PHY is not set # CONFIG_LSI_ET1011C_PHY is not set
CONFIG_FIXED_PHY=y CONFIG_FIXED_PHY=y
# CONFIG_MDIO_BITBANG is not set CONFIG_MDIO_BITBANG=y
# CONFIG_MDIO_GPIO is not set
CONFIG_NET_ETHERNET=y CONFIG_NET_ETHERNET=y
CONFIG_MII=y CONFIG_MII=y
# CONFIG_MACE is not set # CONFIG_MACE is not set
...@@ -608,8 +611,8 @@ CONFIG_MII=y ...@@ -608,8 +611,8 @@ CONFIG_MII=y
# CONFIG_ATL2 is not set # CONFIG_ATL2 is not set
CONFIG_FS_ENET=y CONFIG_FS_ENET=y
CONFIG_FS_ENET_HAS_SCC=y CONFIG_FS_ENET_HAS_SCC=y
# CONFIG_FS_ENET_HAS_FCC is not set CONFIG_FS_ENET_HAS_FCC=y
# CONFIG_FS_ENET_MDIO_FCC is not set CONFIG_FS_ENET_MDIO_FCC=y
# CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set # CONFIG_NETDEV_10000 is not set
# CONFIG_TR is not set # CONFIG_TR is not set
...@@ -680,7 +683,68 @@ CONFIG_HW_RANDOM=y ...@@ -680,7 +683,68 @@ CONFIG_HW_RANDOM=y
# CONFIG_APPLICOM is not set # CONFIG_APPLICOM is not set
# CONFIG_RAW_DRIVER is not set # CONFIG_RAW_DRIVER is not set
CONFIG_DEVPORT=y CONFIG_DEVPORT=y
# CONFIG_I2C is not set CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_HELPER_AUTO=y
#
# I2C Hardware Bus support
#
#
# PC SMBus host controller drivers
#
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_I801 is not set
# CONFIG_I2C_ISCH is not set
# CONFIG_I2C_PIIX4 is not set
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_SIS5595 is not set
# CONFIG_I2C_SIS630 is not set
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_VIAPRO is not set
#
# Mac SMBus host controller drivers
#
# CONFIG_I2C_POWERMAC is not set
#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
CONFIG_I2C_CPM=y
# CONFIG_I2C_DESIGNWARE is not set
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_MPC is not set
# CONFIG_I2C_SIMTEC is not set
#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_PARPORT_LIGHT is not set
#
# Graphics adapter I2C/DDC channel drivers
#
# CONFIG_I2C_VOODOO3 is not set
#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_PCA_PLATFORM is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_PCF8575 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
# CONFIG_SPI is not set # CONFIG_SPI is not set
# #
...@@ -699,6 +763,9 @@ CONFIG_GPIOLIB=y ...@@ -699,6 +763,9 @@ CONFIG_GPIOLIB=y
# #
# I2C GPIO expanders: # I2C GPIO expanders:
# #
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
# #
# PCI GPIO expanders: # PCI GPIO expanders:
...@@ -727,7 +794,14 @@ CONFIG_SSB_POSSIBLE=y ...@@ -727,7 +794,14 @@ CONFIG_SSB_POSSIBLE=y
# CONFIG_MFD_CORE is not set # CONFIG_MFD_CORE is not set
# CONFIG_MFD_SM501 is not set # CONFIG_MFD_SM501 is not set
# CONFIG_HTC_PASIC3 is not set # CONFIG_HTC_PASIC3 is not set
# CONFIG_TPS65010 is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_MFD_TMIO is not set # CONFIG_MFD_TMIO is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_AB3100_CORE is not set
# CONFIG_REGULATOR is not set # CONFIG_REGULATOR is not set
# CONFIG_MEDIA_SUPPORT is not set # CONFIG_MEDIA_SUPPORT is not set
......
...@@ -203,6 +203,7 @@ CONFIG_MPC85xx_CDS=y ...@@ -203,6 +203,7 @@ CONFIG_MPC85xx_CDS=y
CONFIG_MPC85xx_MDS=y CONFIG_MPC85xx_MDS=y
CONFIG_MPC8536_DS=y CONFIG_MPC8536_DS=y
CONFIG_MPC85xx_DS=y CONFIG_MPC85xx_DS=y
CONFIG_MPC85xx_RDB=y
CONFIG_SOCRATES=y CONFIG_SOCRATES=y
CONFIG_KSI8560=y CONFIG_KSI8560=y
# CONFIG_XES_MPC85xx is not set # CONFIG_XES_MPC85xx is not set
......
...@@ -114,6 +114,18 @@ ...@@ -114,6 +114,18 @@
#define MAS7_RPN 0xFFFFFFFF #define MAS7_RPN 0xFFFFFFFF
/* Bit definitions for MMUCSR0 */
#define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
#define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
#define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
#define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
#define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
#define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
#define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
#define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
/* TLBnCFG encoding */ /* TLBnCFG encoding */
#define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */ #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
#define TLBnCFG_HES 0x00002000 /* HW select supported */ #define TLBnCFG_HES 0x00002000 /* HW select supported */
......
...@@ -430,12 +430,6 @@ ...@@ -430,12 +430,6 @@
#define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */ #define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */
#define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */ #define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */
/* Bit definitions for MMUCSR0 */
#define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
#define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
#define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
#define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
/* Bit definitions for SGR. */ /* Bit definitions for SGR. */
#define SGR_NORMAL 0 /* Speculative fetching allowed. */ #define SGR_NORMAL 0 /* Speculative fetching allowed. */
#define SGR_GUARDED 1 /* Speculative fetching disallowed. */ #define SGR_GUARDED 1 /* Speculative fetching disallowed. */
......
...@@ -124,8 +124,6 @@ _GLOBAL(_tlbil_pid) ...@@ -124,8 +124,6 @@ _GLOBAL(_tlbil_pid)
* to have the larger code path before the _SECTION_ELSE * to have the larger code path before the _SECTION_ELSE
*/ */
#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
/* /*
* Flush MMU TLB on the local processor * Flush MMU TLB on the local processor
*/ */
......
...@@ -29,7 +29,6 @@ ...@@ -29,7 +29,6 @@
#include <sysdev/fsl_soc.h> #include <sysdev/fsl_soc.h>
#include <sysdev/cpm2_pic.h> #include <sysdev/cpm2_pic.h>
#include "pq2ads.h"
#include "pq2.h" #include "pq2.h"
static void __init mpc8272_ads_pic_init(void) static void __init mpc8272_ads_pic_init(void)
...@@ -100,6 +99,15 @@ static struct cpm_pin mpc8272_ads_pins[] = { ...@@ -100,6 +99,15 @@ static struct cpm_pin mpc8272_ads_pins[] = {
/* I2C */ /* I2C */
{3, 14, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN}, {3, 14, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN},
{3, 15, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN}, {3, 15, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN},
/* USB */
{2, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
{2, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
{2, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
{2, 24, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
{3, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
{3, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
{3, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
}; };
static void __init init_ioports(void) static void __init init_ioports(void)
...@@ -113,6 +121,8 @@ static void __init init_ioports(void) ...@@ -113,6 +121,8 @@ static void __init init_ioports(void)
cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX); cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX); cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
cpm2_clk_setup(CPM_CLK_SCC3, CPM_CLK8, CPM_CLK_RX);
cpm2_clk_setup(CPM_CLK_SCC3, CPM_CLK8, CPM_CLK_TX);
cpm2_clk_setup(CPM_CLK_SCC4, CPM_BRG4, CPM_CLK_RX); cpm2_clk_setup(CPM_CLK_SCC4, CPM_BRG4, CPM_CLK_RX);
cpm2_clk_setup(CPM_CLK_SCC4, CPM_BRG4, CPM_CLK_TX); cpm2_clk_setup(CPM_CLK_SCC4, CPM_BRG4, CPM_CLK_TX);
cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK11, CPM_CLK_RX); cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK11, CPM_CLK_RX);
...@@ -144,12 +154,22 @@ static void __init mpc8272_ads_setup_arch(void) ...@@ -144,12 +154,22 @@ static void __init mpc8272_ads_setup_arch(void)
return; return;
} }
#define BCSR1_FETHIEN 0x08000000
#define BCSR1_FETH_RST 0x04000000
#define BCSR1_RS232_EN1 0x02000000
#define BCSR1_RS232_EN2 0x01000000
#define BCSR3_USB_nEN 0x80000000
#define BCSR3_FETHIEN2 0x10000000
#define BCSR3_FETH2_RST 0x08000000
clrbits32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN); clrbits32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN);
setbits32(&bcsr[1], BCSR1_FETH_RST); setbits32(&bcsr[1], BCSR1_FETH_RST);
clrbits32(&bcsr[3], BCSR3_FETHIEN2); clrbits32(&bcsr[3], BCSR3_FETHIEN2);
setbits32(&bcsr[3], BCSR3_FETH2_RST); setbits32(&bcsr[3], BCSR3_FETH2_RST);
clrbits32(&bcsr[3], BCSR3_USB_nEN);
iounmap(bcsr); iounmap(bcsr);
init_ioports(); init_ioports();
......
...@@ -55,6 +55,15 @@ config MPC85xx_DS ...@@ -55,6 +55,15 @@ config MPC85xx_DS
help help
This option enables support for the MPC85xx DS (MPC8544 DS) board This option enables support for the MPC85xx DS (MPC8544 DS) board
config MPC85xx_RDB
bool "Freescale MPC85xx RDB"
select PPC_I8259
select DEFAULT_UIMAGE
select FSL_ULI1575
select SWIOTLB
help
This option enables support for the MPC85xx RDB (P2020 RDB) board
config SOCRATES config SOCRATES
bool "Socrates" bool "Socrates"
select DEFAULT_UIMAGE select DEFAULT_UIMAGE
......
...@@ -9,6 +9,7 @@ obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o ...@@ -9,6 +9,7 @@ obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
obj-$(CONFIG_MPC8536_DS) += mpc8536_ds.o obj-$(CONFIG_MPC8536_DS) += mpc8536_ds.o
obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o
obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
obj-$(CONFIG_STX_GP3) += stx_gp3.o obj-$(CONFIG_STX_GP3) += stx_gp3.o
obj-$(CONFIG_TQM85xx) += tqm85xx.o obj-$(CONFIG_TQM85xx) += tqm85xx.o
obj-$(CONFIG_SBC8560) += sbc8560.o obj-$(CONFIG_SBC8560) += sbc8560.o
......
...@@ -47,6 +47,7 @@ ...@@ -47,6 +47,7 @@
#include <asm/udbg.h> #include <asm/udbg.h>
#include <sysdev/fsl_soc.h> #include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h> #include <sysdev/fsl_pci.h>
#include <sysdev/simple_gpio.h>
#include <asm/qe.h> #include <asm/qe.h>
#include <asm/qe_ic.h> #include <asm/qe_ic.h>
#include <asm/mpic.h> #include <asm/mpic.h>
...@@ -304,6 +305,9 @@ static struct of_device_id mpc85xx_ids[] = { ...@@ -304,6 +305,9 @@ static struct of_device_id mpc85xx_ids[] = {
static int __init mpc85xx_publish_devices(void) static int __init mpc85xx_publish_devices(void)
{ {
if (machine_is(mpc8569_mds))
simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
/* Publish the QE devices */ /* Publish the QE devices */
of_platform_bus_probe(NULL, mpc85xx_ids, NULL); of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
......
/*
* MPC85xx RDB Board Setup
*
* Copyright 2009 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/of_platform.h>
#include <asm/system.h>
#include <asm/time.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <mm/mmu_decl.h>
#include <asm/prom.h>
#include <asm/udbg.h>
#include <asm/mpic.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#undef DEBUG
#ifdef DEBUG
#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
#else
#define DBG(fmt, args...)
#endif
void __init mpc85xx_rdb_pic_init(void)
{
struct mpic *mpic;
struct resource r;
struct device_node *np;
np = of_find_node_by_type(NULL, "open-pic");
if (np == NULL) {
printk(KERN_ERR "Could not find open-pic node\n");
return;
}
if (of_address_to_resource(np, 0, &r)) {
printk(KERN_ERR "Failed to map mpic register space\n");
of_node_put(np);
return;
}
mpic = mpic_alloc(np, r.start,
MPIC_PRIMARY | MPIC_WANTS_RESET |
MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
MPIC_SINGLE_DEST_CPU,
0, 256, " OpenPIC ");
BUG_ON(mpic == NULL);
of_node_put(np);
mpic_init(mpic);
}
/*
* Setup the architecture
*/
#ifdef CONFIG_SMP
extern void __init mpc85xx_smp_init(void);
#endif
static void __init mpc85xx_rdb_setup_arch(void)
{
#ifdef CONFIG_PCI
struct device_node *np;
#endif
if (ppc_md.progress)
ppc_md.progress("mpc85xx_rdb_setup_arch()", 0);
#ifdef CONFIG_PCI
for_each_node_by_type(np, "pci") {
if (of_device_is_compatible(np, "fsl,mpc8548-pcie"))
fsl_add_bridge(np, 0);
}
#endif
#ifdef CONFIG_SMP
mpc85xx_smp_init();
#endif
printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n");
}
static struct of_device_id __initdata mpc85xxrdb_ids[] = {
{ .type = "soc", },
{ .compatible = "soc", },
{ .compatible = "simple-bus", },
{ .compatible = "gianfar", },
{},
};
static int __init mpc85xxrdb_publish_devices(void)
{
return of_platform_bus_probe(NULL, mpc85xxrdb_ids, NULL);
}
machine_device_initcall(p2020_rdb, mpc85xxrdb_publish_devices);
/*
* Called very early, device-tree isn't unflattened
*/
static int __init p2020_rdb_probe(void)
{
unsigned long root = of_get_flat_dt_root();
if (of_flat_dt_is_compatible(root, "fsl,P2020RDB"))
return 1;
return 0;
}
define_machine(p2020_rdb) {
.name = "P2020 RDB",
.probe = p2020_rdb_probe,
.setup_arch = mpc85xx_rdb_setup_arch,
.init_IRQ = mpc85xx_rdb_pic_init,
#ifdef CONFIG_PCI
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
#endif
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
...@@ -267,6 +267,43 @@ arch_initcall(sbc8560_rtc_init); ...@@ -267,6 +267,43 @@ arch_initcall(sbc8560_rtc_init);
#endif /* M48T59 */ #endif /* M48T59 */
static __u8 __iomem *brstcr;
static int __init sbc8560_bdrstcr_init(void)
{
struct device_node *np;
struct resource res;
np = of_find_compatible_node(NULL, NULL, "wrs,sbc8560-brstcr");
if (np == NULL) {
printk(KERN_WARNING "sbc8560: No board specific RSTCR in DTB.\n");
return -ENODEV;
}
of_address_to_resource(np, 0, &res);
printk(KERN_INFO "sbc8560: Found BRSTCR at i/o 0x%x\n", res.start);
brstcr = ioremap(res.start, res.end - res.start);
if(!brstcr)
printk(KERN_WARNING "sbc8560: ioremap of brstcr failed.\n");
of_node_put(np);
return 0;
}
arch_initcall(sbc8560_bdrstcr_init);
void sbc8560_rstcr_restart(char * cmd)
{
local_irq_disable();
if(brstcr)
clrbits8(brstcr, 0x80);
while(1);
}
define_machine(sbc8560) { define_machine(sbc8560) {
.name = "SBC8560", .name = "SBC8560",
.probe = sbc8560_probe, .probe = sbc8560_probe,
...@@ -274,7 +311,7 @@ define_machine(sbc8560) { ...@@ -274,7 +311,7 @@ define_machine(sbc8560) {
.init_IRQ = sbc8560_pic_init, .init_IRQ = sbc8560_pic_init,
.show_cpuinfo = sbc8560_show_cpuinfo, .show_cpuinfo = sbc8560_show_cpuinfo,
.get_irq = mpic_get_irq, .get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart, .restart = sbc8560_rstcr_restart,
.calibrate_decr = generic_calibrate_decr, .calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress, .progress = udbg_progress,
}; };
...@@ -37,6 +37,7 @@ ...@@ -37,6 +37,7 @@
#include <asm/irq.h> #include <asm/irq.h>
#include <asm/time.h> #include <asm/time.h>
#include <asm/prom.h> #include <asm/prom.h>
#include <asm/machdep.h>
#include <sysdev/fsl_soc.h> #include <sysdev/fsl_soc.h>
#include <mm/mmu_decl.h> #include <mm/mmu_decl.h>
#include <asm/cpm2.h> #include <asm/cpm2.h>
...@@ -383,8 +384,9 @@ static int __init setup_rstcr(void) ...@@ -383,8 +384,9 @@ static int __init setup_rstcr(void)
if (!rstcr) if (!rstcr)
printk (KERN_EMERG "Error: reset control register " printk (KERN_EMERG "Error: reset control register "
"not mapped!\n"); "not mapped!\n");
} else } else if (ppc_md.restart == fsl_rstcr_restart)
printk (KERN_INFO "rstcr compatible register does not exist!\n"); printk(KERN_ERR "No RSTCR register, warm reboot won't work\n");
if (np) if (np)
of_node_put(np); of_node_put(np);
return 0; return 0;
......
...@@ -105,14 +105,14 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) ...@@ -105,14 +105,14 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc); struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
unsigned long flags; unsigned long flags;
qe_gpio_set(gc, gpio, val);
spin_lock_irqsave(&qe_gc->lock, flags); spin_lock_irqsave(&qe_gc->lock, flags);
__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0); __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);
spin_unlock_irqrestore(&qe_gc->lock, flags); spin_unlock_irqrestore(&qe_gc->lock, flags);
qe_gpio_set(gc, gpio, val);
return 0; return 0;
} }
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment