Merge samba.org:/scratch/anton/linux-2.5

into samba.org:/scratch/anton/sfr

drivers/char/agp/Kconfig

@@ -61,16 +61,6 @@ config AGP_VIA
 	  You should say Y here if you use XFree86 3.3.6 or 4.x and want to
 	  use GLX or DRI.  If unsure, say N.
 
-config AGP_VIA_KT400
-	tristate "VIA KT400 chipset support"
-	depends on AGP3
-	help
-	  This option gives you AGP support for the GLX component of the
-	  XFree86 4.x on VIA KT400 AGP 3.0 chipsets.
-
-	  You should say Y here if you use XFree86 3.3.6 or 4.x and want to
-	  use GLX or DRI.  If unsure, say N.
-
 config AGP_AMD
 	tristate "AMD Irongate, 761, and 762 support"
 	depends on AGP
@@ -141,6 +131,11 @@ config AGP_HP_ZX1
 	  This option gives you AGP GART support for the HP ZX1 chipset
 	  for IA64 processors.
 
+config AGP_ALPHA_CORE
+	tristate
+	depends on AGP && (ALPHA_GENERIC || ALPHA_TITAN || ALPHA_MARVEL)
+	default AGP
+
 # Put AGP 3.0 entries below here.
 
 config AGP_I7505

drivers/char/agp/Makefile

@@ -10,7 +10,6 @@ obj-$(CONFIG_AGP) += agpgart.o
 
 obj-$(CONFIG_AGP_INTEL)		+= intel-agp.o
 obj-$(CONFIG_AGP_VIA)		+= via-agp.o
-obj-$(CONFIG_AGP_VIA_KT400)	+= via-kt400.o
 obj-$(CONFIG_AGP_AMD)		+= amd-k7-agp.o
 obj-$(CONFIG_AGP_SIS)		+= sis-agp.o
 obj-$(CONFIG_AGP_ALI)		+= ali-agp.o
@@ -18,6 +17,7 @@ obj-$(CONFIG_AGP_SWORKS)	+= sworks-agp.o
 obj-$(CONFIG_AGP_I460)		+= i460-agp.o
 obj-$(CONFIG_AGP_HP_ZX1)	+= hp-agp.o
 obj-$(CONFIG_AGP_AMD_8151)	+= amd-k8-agp.o
+obj-$(CONFIG_AGP_ALPHA_CORE)	+= alpha-agp.o
 
 obj-$(CONFIG_AGP_I7x05)		+= i7x05-agp.o
 

drivers/char/agp/agp.h

@@ -30,7 +30,7 @@
 
 #include <asm/agp.h>	/* for flush_agp_cache() */
 
-extern struct agp_bridge_data agp_bridge;
+extern struct agp_bridge_data *agp_bridge;
 
 #define PFX "agpgart: "
 
@@ -128,6 +128,7 @@ struct agp_bridge_data {
 	int num_aperture_sizes;
 	int capndx;
 	int cant_use_aperture;
+	struct vm_operations_struct *vm_ops;
 
 	/* Links to driver specific functions */
 
@@ -165,20 +166,20 @@ struct agp_bridge_data {
 #define MB(x)	(KB (KB (x)))
 #define GB(x)	(MB (KB (x)))
 
-#define CACHE_FLUSH	agp_bridge.cache_flush
+#define CACHE_FLUSH	agp_bridge->cache_flush
 #define A_SIZE_8(x)	((struct aper_size_info_8 *) x)
 #define A_SIZE_16(x)	((struct aper_size_info_16 *) x)
 #define A_SIZE_32(x)	((struct aper_size_info_32 *) x)
 #define A_SIZE_LVL2(x)	((struct aper_size_info_lvl2 *) x)
 #define A_SIZE_FIX(x)	((struct aper_size_info_fixed *) x)
-#define A_IDX8()	(A_SIZE_8(agp_bridge.aperture_sizes) + i)
-#define A_IDX16()	(A_SIZE_16(agp_bridge.aperture_sizes) + i)
-#define A_IDX32()	(A_SIZE_32(agp_bridge.aperture_sizes) + i)
-#define A_IDXLVL2()	(A_SIZE_LVL2(agp_bridge.aperture_sizes) + i)
-#define A_IDXFIX()	(A_SIZE_FIX(agp_bridge.aperture_sizes) + i)
+#define A_IDX8()	(A_SIZE_8(agp_bridge->aperture_sizes) + i)
+#define A_IDX16()	(A_SIZE_16(agp_bridge->aperture_sizes) + i)
+#define A_IDX32()	(A_SIZE_32(agp_bridge->aperture_sizes) + i)
+#define A_IDXLVL2()	(A_SIZE_LVL2(agp_bridge->aperture_sizes) + i)
+#define A_IDXFIX()	(A_SIZE_FIX(agp_bridge->aperture_sizes) + i)
 #define MAXKEY		(4096 * 32)
 
-#define PGE_EMPTY(p)	(!(p) || (p) == (unsigned long) agp_bridge.scratch_page)
+#define PGE_EMPTY(p)	(!(p) || (p) == (unsigned long) agp_bridge->scratch_page)
 
 /* intel register */
 #define INTEL_APBASE	0x10
@@ -366,7 +367,7 @@ struct agp_driver {
 
 /* Generic routines. */
 void agp_generic_agp_enable(u32 mode);
-int agp_generic_agp_3_0_enable(u32 mode);
+void agp_generic_agp_3_0_enable(u32 mode);
 int agp_generic_create_gatt_table(void);
 int agp_generic_free_gatt_table(void);
 agp_memory *agp_create_memory(int scratch_pages);

drivers/char/agp/ali-agp.c

@@ -17,15 +17,15 @@ static int ali_fetch_size(void)
 	u32 temp;
 	struct aper_size_info_32 *values;
 
-	pci_read_config_dword(agp_bridge.dev, ALI_ATTBASE, &temp);
+	pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp);
 	temp &= ~(0xfffffff0);
-	values = A_SIZE_32(agp_bridge.aperture_sizes);
+	values = A_SIZE_32(agp_bridge->aperture_sizes);
 
-	for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+	for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
 		if (temp == values[i].size_value) {
-			agp_bridge.previous_size =
-			    agp_bridge.current_size = (void *) (values + i);
-			agp_bridge.aperture_size_idx = i;
+			agp_bridge->previous_size =
+			    agp_bridge->current_size = (void *) (values + i);
+			agp_bridge->aperture_size_idx = i;
 			return values[i].size;
 		}
 	}
@@ -37,9 +37,9 @@ static void ali_tlbflush(agp_memory * mem)
 {
 	u32 temp;
 
-	pci_read_config_dword(agp_bridge.dev, ALI_TLBCTRL, &temp);
+	pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
 // clear tag
-	pci_write_config_dword(agp_bridge.dev, ALI_TAGCTRL,
+	pci_write_config_dword(agp_bridge->dev, ALI_TAGCTRL,
 			((temp & 0xfffffff0) | 0x00000001|0x00000002));
 }
 
@@ -48,15 +48,15 @@ static void ali_cleanup(void)
 	struct aper_size_info_32 *previous_size;
 	u32 temp;
 
-	previous_size = A_SIZE_32(agp_bridge.previous_size);
+	previous_size = A_SIZE_32(agp_bridge->previous_size);
 
-	pci_read_config_dword(agp_bridge.dev, ALI_TLBCTRL, &temp);
+	pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
 // clear tag
-	pci_write_config_dword(agp_bridge.dev, ALI_TAGCTRL,
+	pci_write_config_dword(agp_bridge->dev, ALI_TAGCTRL,
 			((temp & 0xffffff00) | 0x00000001|0x00000002));
 
-	pci_read_config_dword(agp_bridge.dev,  ALI_ATTBASE, &temp);
-	pci_write_config_dword(agp_bridge.dev, ALI_ATTBASE,
+	pci_read_config_dword(agp_bridge->dev,  ALI_ATTBASE, &temp);
+	pci_write_config_dword(agp_bridge->dev, ALI_ATTBASE,
 			((temp & 0x00000ff0) | previous_size->size_value));
 }
 
@@ -65,24 +65,24 @@ static int ali_configure(void)
 	u32 temp;
 	struct aper_size_info_32 *current_size;
 
-	current_size = A_SIZE_32(agp_bridge.current_size);
+	current_size = A_SIZE_32(agp_bridge->current_size);
 
 	/* aperture size and gatt addr */
-	pci_read_config_dword(agp_bridge.dev, ALI_ATTBASE, &temp);
-	temp = (((temp & 0x00000ff0) | (agp_bridge.gatt_bus_addr & 0xfffff000))
+	pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp);
+	temp = (((temp & 0x00000ff0) | (agp_bridge->gatt_bus_addr & 0xfffff000))
 			| (current_size->size_value & 0xf));
-	pci_write_config_dword(agp_bridge.dev, ALI_ATTBASE, temp);
+	pci_write_config_dword(agp_bridge->dev, ALI_ATTBASE, temp);
 
 	/* tlb control */
-	pci_read_config_dword(agp_bridge.dev, ALI_TLBCTRL, &temp);
-	pci_write_config_dword(agp_bridge.dev, ALI_TLBCTRL, ((temp & 0xffffff00) | 0x00000010));
+	pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
+	pci_write_config_dword(agp_bridge->dev, ALI_TLBCTRL, ((temp & 0xffffff00) | 0x00000010));
 
 	/* address to map to */
-	pci_read_config_dword(agp_bridge.dev, ALI_APBASE, &temp);
-	agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+	pci_read_config_dword(agp_bridge->dev, ALI_APBASE, &temp);
+	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 
 #if 0
-	if (agp_bridge.type == ALI_M1541) {
+	if (agp_bridge->type == ALI_M1541) {
 		u32 nlvm_addr = 0;
 
 		switch (current_size->size_value) {
@@ -101,15 +101,15 @@ static int ali_configure(void)
 		nlvm_addr--;
 		nlvm_addr&=0xfff00000;
 
-		nlvm_addr+= agp_bridge.gart_bus_addr;
-		nlvm_addr|=(agp_bridge.gart_bus_addr>>12);
+		nlvm_addr+= agp_bridge->gart_bus_addr;
+		nlvm_addr|=(agp_bridge->gart_bus_addr>>12);
 		printk(KERN_INFO PFX "nlvm top &base = %8x\n",nlvm_addr);
 	}
 #endif
 
-	pci_read_config_dword(agp_bridge.dev, ALI_TLBCTRL, &temp);
+	pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
 	temp &= 0xffffff7f;		//enable TLB
-	pci_write_config_dword(agp_bridge.dev, ALI_TLBCTRL, temp);
+	pci_write_config_dword(agp_bridge->dev, ALI_TLBCTRL, temp);
 
 	return 0;
 }
@@ -118,23 +118,23 @@ static unsigned long ali_mask_memory(unsigned long addr, int type)
 {
 	/* Memory type is ignored */
 
-	return addr | agp_bridge.masks[0].mask;
+	return addr | agp_bridge->masks[0].mask;
 }
 
 static void ali_cache_flush(void)
 {
 	global_cache_flush();
 
-	if (agp_bridge.type == ALI_M1541) {
+	if (agp_bridge->type == ALI_M1541) {
 		int i, page_count;
 		u32 temp;
 
-		page_count = 1 << A_SIZE_32(agp_bridge.current_size)->page_order;
+		page_count = 1 << A_SIZE_32(agp_bridge->current_size)->page_order;
 		for (i = 0; i < PAGE_SIZE * page_count; i += PAGE_SIZE) {
-			pci_read_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL, &temp);
-			pci_write_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL,
+			pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, &temp);
+			pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL,
 					(((temp & ALI_CACHE_FLUSH_ADDR_MASK) |
-					  (agp_bridge.gatt_bus_addr + i)) |
+					  (agp_bridge->gatt_bus_addr + i)) |
 					    ALI_CACHE_FLUSH_EN));
 		}
 	}
@@ -148,9 +148,9 @@ static void *ali_alloc_page(void)
 	if (adr == 0)
 		return 0;
 
-	if (agp_bridge.type == ALI_M1541) {
-		pci_read_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL, &temp);
-		pci_write_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL,
+	if (agp_bridge->type == ALI_M1541) {
+		pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, &temp);
+		pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL,
 				(((temp & ALI_CACHE_FLUSH_ADDR_MASK) |
 				  virt_to_phys(adr)) |
 				    ALI_CACHE_FLUSH_EN ));
@@ -167,9 +167,9 @@ static void ali_destroy_page(void * addr)
 
 	global_cache_flush();
 
-	if (agp_bridge.type == ALI_M1541) {
-		pci_read_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL, &temp);
-		pci_write_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL,
+	if (agp_bridge->type == ALI_M1541) {
+		pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, &temp);
+		pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL,
 				(((temp & ALI_CACHE_FLUSH_ADDR_MASK) |
 				  virt_to_phys(addr)) |
 				    ALI_CACHE_FLUSH_EN));
@@ -197,30 +197,30 @@ static struct aper_size_info_32 ali_generic_sizes[7] =
 
 static int __init ali_generic_setup (struct pci_dev *pdev)
 {
-	agp_bridge.masks = ali_generic_masks;
-	agp_bridge.aperture_sizes = (void *) ali_generic_sizes;
-	agp_bridge.size_type = U32_APER_SIZE;
-	agp_bridge.num_aperture_sizes = 7;
-	agp_bridge.dev_private_data = NULL;
-	agp_bridge.needs_scratch_page = FALSE;
-	agp_bridge.configure = ali_configure;
-	agp_bridge.fetch_size = ali_fetch_size;
-	agp_bridge.cleanup = ali_cleanup;
-	agp_bridge.tlb_flush = ali_tlbflush;
-	agp_bridge.mask_memory = ali_mask_memory;
-	agp_bridge.agp_enable = agp_generic_agp_enable;
-	agp_bridge.cache_flush = ali_cache_flush;
-	agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
-	agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
-	agp_bridge.insert_memory = agp_generic_insert_memory;
-	agp_bridge.remove_memory = agp_generic_remove_memory;
-	agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
-	agp_bridge.free_by_type = agp_generic_free_by_type;
-	agp_bridge.agp_alloc_page = ali_alloc_page;
-	agp_bridge.agp_destroy_page = ali_destroy_page;
-	agp_bridge.suspend = agp_generic_suspend;
-	agp_bridge.resume = agp_generic_resume;
-	agp_bridge.cant_use_aperture = 0;
+	agp_bridge->masks = ali_generic_masks;
+	agp_bridge->aperture_sizes = (void *) ali_generic_sizes;
+	agp_bridge->size_type = U32_APER_SIZE;
+	agp_bridge->num_aperture_sizes = 7;
+	agp_bridge->dev_private_data = NULL;
+	agp_bridge->needs_scratch_page = FALSE;
+	agp_bridge->configure = ali_configure;
+	agp_bridge->fetch_size = ali_fetch_size;
+	agp_bridge->cleanup = ali_cleanup;
+	agp_bridge->tlb_flush = ali_tlbflush;
+	agp_bridge->mask_memory = ali_mask_memory;
+	agp_bridge->agp_enable = agp_generic_agp_enable;
+	agp_bridge->cache_flush = ali_cache_flush;
+	agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+	agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+	agp_bridge->insert_memory = agp_generic_insert_memory;
+	agp_bridge->remove_memory = agp_generic_remove_memory;
+	agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+	agp_bridge->free_by_type = agp_generic_free_by_type;
+	agp_bridge->agp_alloc_page = ali_alloc_page;
+	agp_bridge->agp_destroy_page = ali_destroy_page;
+	agp_bridge->suspend = agp_generic_suspend;
+	agp_bridge->resume = agp_generic_resume;
+	agp_bridge->cant_use_aperture = 0;
 	return 0;
 }
 
@@ -313,7 +313,7 @@ static int __init agp_lookup_host_bridge (struct pci_dev *pdev)
 
 			printk (KERN_INFO PFX "Detected ALi %s chipset\n",
 				devs[j].chipset_name);
-			agp_bridge.type = devs[j].chipset;
+			agp_bridge->type = devs[j].chipset;
 
 			if (devs[j].chipset_setup != NULL)
 				return devs[j].chipset_setup(pdev);
@@ -327,7 +327,7 @@ static int __init agp_lookup_host_bridge (struct pci_dev *pdev)
 	if (agp_try_unsupported) {
 		printk(KERN_WARNING PFX "Trying generic ALi routines"
 		       " for device id: %04x\n", pdev->device);
-		agp_bridge.type = ALI_GENERIC;
+		agp_bridge->type = ALI_GENERIC;
 		return ali_generic_setup(pdev);
 	}
 
@@ -350,10 +350,10 @@ static int __init agp_ali_probe (struct pci_dev *dev, const struct pci_device_id
 
 	/* probe for known chipsets */
 	if (agp_lookup_host_bridge(dev) != -ENODEV) {
-		agp_bridge.dev = dev;
-		agp_bridge.capndx = cap_ptr;
+		agp_bridge->dev = dev;
+		agp_bridge->capndx = cap_ptr;
 		/* Fill in the mode register */
-		pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
+		pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
 		ali_agp_driver.dev = dev;
 		agp_register_driver(&ali_agp_driver);
 		return 0;
@@ -387,7 +387,7 @@ static int __init agp_ali_init(void)
 
 	ret_val = pci_module_init(&agp_ali_pci_driver);
 	if (ret_val)
-		agp_bridge.type = NOT_SUPPORTED;
+		agp_bridge->type = NOT_SUPPORTED;
 
 	return ret_val;
 }

drivers/char/agp/alpha-agp.c

+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/agp_backend.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+
+#include <asm/machvec.h>
+#include <asm/agp_backend.h>
+#include "../../../arch/alpha/kernel/pci_impl.h"
+
+#include "agp.h"
+
+static struct page *alpha_core_agp_vm_nopage(struct vm_area_struct *vma,
+					     unsigned long address,
+					     int write_access)
+{
+	alpha_agp_info *agp = agp_bridge->dev_private_data;
+	dma_addr_t dma_addr;
+	unsigned long pa;
+	struct page *page;
+
+	dma_addr = address - vma->vm_start + agp->aperture.bus_base;
+	pa = agp->ops->translate(agp, dma_addr);
+
+	if (pa == (unsigned long)-EINVAL) return NULL;	/* no translation */
+	
+	/*
+	 * Get the page, inc the use count, and return it
+	 */
+	page = virt_to_page(__va(pa));
+	get_page(page);
+	return page;
+}
+
+static struct aper_size_info_fixed alpha_core_agp_sizes[] =
+{
+	{ 0, 0, 0 }, /* filled in by alpha_core_agp_setup */
+};
+
+static struct gatt_mask alpha_core_agp_masks[] = {
+	{ .mask = 0, .type = 0 },
+};
+
+struct vm_operations_struct alpha_core_agp_vm_ops = {
+	.nopage = alpha_core_agp_vm_nopage,
+};
+
+
+static int alpha_core_agp_nop(void)
+{
+	/* just return success */
+	return 0;
+}
+
+static int alpha_core_agp_fetch_size(void)
+{
+	return alpha_core_agp_sizes[0].size;
+}
+
+static int alpha_core_agp_configure(void)
+{
+	alpha_agp_info *agp = agp_bridge->dev_private_data;
+	agp_bridge->gart_bus_addr = agp->aperture.bus_base;
+	return 0;
+}
+
+static void alpha_core_agp_cleanup(void)
+{
+	alpha_agp_info *agp = agp_bridge->dev_private_data;
+
+	agp->ops->cleanup(agp);
+}
+
+static void alpha_core_agp_tlbflush(agp_memory *mem)
+{
+	alpha_agp_info *agp = agp_bridge->dev_private_data;
+	alpha_mv.mv_pci_tbi(agp->hose, 0, -1);
+}
+
+static unsigned long alpha_core_agp_mask_memory(unsigned long addr, int type)
+{
+	/* Memory type is ignored */
+	return addr | agp_bridge->masks[0].mask;
+}
+
+static void alpha_core_agp_enable(u32 mode)
+{
+	alpha_agp_info *agp = agp_bridge->dev_private_data;
+
+	agp->mode.lw = agp_collect_device_status(mode, agp->capability.lw);
+
+	agp->mode.bits.enable = 1;
+	agp->ops->configure(agp);
+
+	agp_device_command(agp->mode.lw, 0);
+}
+
+static int alpha_core_agp_insert_memory(agp_memory *mem, off_t pg_start, 
+					int type)
+{
+	alpha_agp_info *agp = agp_bridge->dev_private_data;
+	int num_entries, status;
+	void *temp;
+
+	temp = agp_bridge->current_size;
+	num_entries = A_SIZE_FIX(temp)->num_entries;
+	if ((pg_start + mem->page_count) > num_entries) return -EINVAL;
+
+	status = agp->ops->bind(agp, pg_start, mem);
+	mb();
+	agp_bridge->tlb_flush(mem);
+
+	return status;
+}
+
+static int alpha_core_agp_remove_memory(agp_memory *mem, off_t pg_start, 
+					int type)
+{
+	alpha_agp_info *agp = agp_bridge->dev_private_data;
+	int status;
+
+	status = agp->ops->unbind(agp, pg_start, mem);
+	agp_bridge->tlb_flush(mem);
+	return status;
+}
+
+
+static struct agp_driver alpha_core_agp_driver = {
+	.owner = THIS_MODULE,
+};
+
+int __init
+alpha_core_agp_setup(void)
+{
+	alpha_agp_info *agp = alpha_mv.agp_info();
+	struct aper_size_info_fixed *aper_size;
+
+	if (!agp) return -ENODEV;
+	if (agp->ops->setup(agp)) return -ENODEV;
+
+	/*
+	 * Build the aperture size descriptor
+	 */
+	aper_size = alpha_core_agp_sizes;
+	if (!aper_size) return -ENOMEM;
+	aper_size->size = agp->aperture.size / (1024 * 1024);
+	aper_size->num_entries = agp->aperture.size / PAGE_SIZE;
+	aper_size->page_order = ffs(aper_size->num_entries / 1024) - 1;
+
+	/*
+	 * Build a fake pci_dev struct
+	 */
+	if (!(agp_bridge->dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL))) {
+		return -ENOMEM;
+	}
+	agp_bridge->dev->vendor = 0xffff;
+	agp_bridge->dev->device = 0xffff;
+	agp_bridge->dev->sysdata = agp->hose;
+
+	/*
+	 * Fill in the rest of the agp_bridge struct
+	 */
+	agp_bridge->masks = alpha_core_agp_masks;
+	agp_bridge->aperture_sizes = aper_size;
+	agp_bridge->current_size = aper_size;	/* only one entry */
+	agp_bridge->size_type = FIXED_APER_SIZE;
+	agp_bridge->num_aperture_sizes = 1;
+	agp_bridge->dev_private_data = agp;
+	agp_bridge->needs_scratch_page = FALSE;
+	agp_bridge->configure = alpha_core_agp_configure;
+	agp_bridge->fetch_size = alpha_core_agp_fetch_size;
+	agp_bridge->cleanup = alpha_core_agp_cleanup;
+	agp_bridge->tlb_flush = alpha_core_agp_tlbflush;
+	agp_bridge->mask_memory = alpha_core_agp_mask_memory;
+	agp_bridge->agp_enable = alpha_core_agp_enable;
+	agp_bridge->cache_flush = global_cache_flush;
+	agp_bridge->create_gatt_table = alpha_core_agp_nop;
+	agp_bridge->free_gatt_table = alpha_core_agp_nop;
+	agp_bridge->insert_memory = alpha_core_agp_insert_memory;
+	agp_bridge->remove_memory = alpha_core_agp_remove_memory;
+	agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+	agp_bridge->free_by_type = agp_generic_free_by_type;
+	agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+	agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+	agp_bridge->mode = agp->capability.lw;
+	agp_bridge->cant_use_aperture = 1;
+	agp_bridgevm_ops =  &alpha_core_agp_vm_ops;
+
+	alpha_core_agp_driver.dev = agp_bridge->dev;
+	agp_register_driver(&alpha_core_agp_driver);
+	printk(KERN_INFO "Detected AGP on hose %d\n", agp->hose->index);
+	return 0;
+}
+
+static int __init agp_alpha_core_init(void)
+{
+	int ret_val = -ENODEV;
+	if (alpha_mv.agp_info) {
+		agp_bridge->type = ALPHA_CORE_AGP;
+		ret_val = alpha_core_agp_setup();
+	}
+
+	return ret_val;
+}
+
+static void __exit agp_alpha_core_cleanup(void)
+{
+	agp_unregister_driver(&alpha_core_agp_driver);
+	/* no pci driver for core */
+}
+
+module_init(agp_alpha_core_init);
+module_exit(agp_alpha_core_cleanup);
+
+MODULE_AUTHOR("Jeff Wiedemeier <Jeff.Wiedemeier@hp.com>");
+MODULE_LICENSE("GPL and additional rights");

drivers/char/agp/amd-k8-agp.c

@@ -70,7 +70,7 @@ static int x86_64_insert_memory(agp_memory * mem, off_t pg_start, int type)
 
 	/* gatt table should be empty. */
 	while (j < (pg_start + mem->page_count)) {
-		if (!PGE_EMPTY(agp_bridge.gatt_table[j]))
+		if (!PGE_EMPTY(agp_bridge->gatt_table[j]))
 			return -EBUSY;
 		j++;
 	}
@@ -81,7 +81,7 @@ static int x86_64_insert_memory(agp_memory * mem, off_t pg_start, int type)
 	}
 
 	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
-		addr = agp_bridge.mask_memory(mem->memory[i], mem->type);
+		addr = agp_bridge->mask_memory(mem->memory[i], mem->type);
 
 		tmp = addr;
 		BUG_ON(tmp & 0xffffff0000000ffc);
@@ -89,9 +89,9 @@ static int x86_64_insert_memory(agp_memory * mem, off_t pg_start, int type)
 		pte |=(tmp & 0x00000000fffff000);
 		pte |= 1<<1|1<<0;
 
-		agp_bridge.gatt_table[j] = pte;
+		agp_bridge->gatt_table[j] = pte;
 	}
-	agp_bridge.tlb_flush(mem);
+	agp_bridge->tlb_flush(mem);
 	return 0;
 }
 
@@ -134,12 +134,12 @@ static int amd_x86_64_fetch_size(void)
 			temp = (temp & 0xe);
 			values = A_SIZE_32(x86_64_aperture_sizes);
 
-			for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+			for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
 				if (temp == values[i].size_value) {
-					agp_bridge.previous_size =
-					    agp_bridge.current_size = (void *) (values + i);
+					agp_bridge->previous_size =
+					    agp_bridge->current_size = (void *) (values + i);
 
-					agp_bridge.aperture_size_idx = i;
+					agp_bridge->aperture_size_idx = i;
 					return values[i].size;
 				}
 			}
@@ -225,14 +225,14 @@ static int amd_8151_configure(void)
 	int current_size;
 	int tmp, tmp2, i;
 	u64 aperbar;
-	unsigned long gatt_bus = virt_to_phys(agp_bridge.gatt_table_real);
+	unsigned long gatt_bus = virt_to_phys(agp_bridge->gatt_table_real);
 
 	/* Configure AGP regs in each x86-64 host bridge. */
 	pci_for_each_dev(dev) {
 		if (dev->bus->number==0 &&
 			PCI_FUNC(dev->devfn)==3 &&
 			PCI_SLOT(dev->devfn)>=24 && PCI_SLOT(dev->devfn)<=31) {
-			agp_bridge.gart_bus_addr = amd_x86_64_configure(dev,gatt_bus);
+			agp_bridge->gart_bus_addr = amd_x86_64_configure(dev,gatt_bus);
 			hammer = dev;
 
 			/*
@@ -248,7 +248,7 @@ static int amd_8151_configure(void)
 
 	/* Shadow x86-64 registers into 8151 registers. */
 
-	dev = agp_bridge.dev;
+	dev = agp_bridge->dev;
 	if (!dev) 
 		return -ENODEV;
 
@@ -315,7 +315,7 @@ static void amd_8151_cleanup(void)
 
 static unsigned long amd_8151_mask_memory(unsigned long addr, int type)
 {
-	return addr | agp_bridge.masks[0].mask;
+	return addr | agp_bridge->masks[0].mask;
 }
 
 
@@ -368,12 +368,12 @@ static void agp_x86_64_agp_enable(u32 mode)
 	}
 
 
-	pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &command);
+	pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &command);
 
 	command = agp_collect_device_status(mode, command);
 	command |= 0x100;
 
-	pci_write_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_COMMAND, command);
+	pci_write_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_COMMAND, command);
 
 	agp_device_command(command, 1);
 }
@@ -381,30 +381,30 @@ static void agp_x86_64_agp_enable(u32 mode)
 
 static int __init amd_8151_setup (struct pci_dev *pdev)
 {
-	agp_bridge.masks = amd_8151_masks;
-	agp_bridge.aperture_sizes = (void *) amd_8151_sizes;
-	agp_bridge.size_type = U32_APER_SIZE;
-	agp_bridge.num_aperture_sizes = 7;
-	agp_bridge.dev_private_data = NULL;
-	agp_bridge.needs_scratch_page = FALSE;
-	agp_bridge.configure = amd_8151_configure;
-	agp_bridge.fetch_size = amd_x86_64_fetch_size;
-	agp_bridge.cleanup = amd_8151_cleanup;
-	agp_bridge.tlb_flush = amd_x86_64_tlbflush;
-	agp_bridge.mask_memory = amd_8151_mask_memory;
-	agp_bridge.agp_enable = agp_x86_64_agp_enable;
-	agp_bridge.cache_flush = global_cache_flush;
-	agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
-	agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
-	agp_bridge.insert_memory = x86_64_insert_memory;
-	agp_bridge.remove_memory = agp_generic_remove_memory;
-	agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
-	agp_bridge.free_by_type = agp_generic_free_by_type;
-	agp_bridge.agp_alloc_page = agp_generic_alloc_page;
-	agp_bridge.agp_destroy_page = agp_generic_destroy_page;
-	agp_bridge.suspend = agp_generic_suspend;
-	agp_bridge.resume = agp_generic_resume;
-	agp_bridge.cant_use_aperture = 0;
+	agp_bridge->masks = amd_8151_masks;
+	agp_bridge->aperture_sizes = (void *) amd_8151_sizes;
+	agp_bridge->size_type = U32_APER_SIZE;
+	agp_bridge->num_aperture_sizes = 7;
+	agp_bridge->dev_private_data = NULL;
+	agp_bridge->needs_scratch_page = FALSE;
+	agp_bridge->configure = amd_8151_configure;
+	agp_bridge->fetch_size = amd_x86_64_fetch_size;
+	agp_bridge->cleanup = amd_8151_cleanup;
+	agp_bridge->tlb_flush = amd_x86_64_tlbflush;
+	agp_bridge->mask_memory = amd_8151_mask_memory;
+	agp_bridge->agp_enable = agp_x86_64_agp_enable;
+	agp_bridge->cache_flush = global_cache_flush;
+	agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+	agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+	agp_bridge->insert_memory = x86_64_insert_memory;
+	agp_bridge->remove_memory = agp_generic_remove_memory;
+	agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+	agp_bridge->free_by_type = agp_generic_free_by_type;
+	agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+	agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+	agp_bridge->suspend = agp_generic_suspend;
+	agp_bridge->resume = agp_generic_resume;
+	agp_bridge->cant_use_aperture = 0;
 	return 0;
 }
 
@@ -420,11 +420,11 @@ static int __init agp_amdk8_probe (struct pci_dev *dev, const struct pci_device_
 	if (cap_ptr == 0)
 		return -ENODEV;
 
-	agp_bridge.dev = dev;
-	agp_bridge.capndx = cap_ptr;
+	agp_bridge->dev = dev;
+	agp_bridge->capndx = cap_ptr;
 
 	/* Fill in the mode register */
-	pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
+	pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
 	amd_8151_setup(dev);
 	amd_k8_agp_driver.dev = dev;
 	agp_register_driver(&amd_k8_agp_driver);
@@ -458,9 +458,9 @@ int __init agp_amdk8_init(void)
 
 	ret_val = pci_module_init(&agp_amdk8_pci_driver);
 	if (ret_val)
-		agp_bridge.type = NOT_SUPPORTED;
+		agp_bridge->type = NOT_SUPPORTED;
 
-	agp_bridge.type = AMD_8151;
+	agp_bridge->type = AMD_8151;
 
 	return ret_val;
 }

drivers/char/agp/backend.c

@@ -44,26 +44,27 @@
 #define AGPGART_VERSION_MAJOR 0
 #define AGPGART_VERSION_MINOR 100
 
-struct agp_bridge_data agp_bridge = { .type = NOT_SUPPORTED };
+struct agp_bridge_data agp_bridge_dummy = { .type = NOT_SUPPORTED };
+struct agp_bridge_data *agp_bridge = &agp_bridge_dummy;
 
 int agp_backend_acquire(void)
 {
-	if (agp_bridge.type == NOT_SUPPORTED)
+	if (agp_bridge->type == NOT_SUPPORTED)
 		return -EINVAL;
 
-	if (atomic_read(&agp_bridge.agp_in_use) != 0)
+	if (atomic_read(&agp_bridge->agp_in_use) != 0)
 		return -EBUSY;
 
-	atomic_inc(&agp_bridge.agp_in_use);
+	atomic_inc(&agp_bridge->agp_in_use);
 	return 0;
 }
 
 void agp_backend_release(void)
 {
-	if (agp_bridge.type == NOT_SUPPORTED)
+	if (agp_bridge->type == NOT_SUPPORTED)
 		return;
 
-	atomic_dec(&agp_bridge.agp_in_use);
+	atomic_dec(&agp_bridge->agp_in_use);
 }
 
 struct agp_max_table {
@@ -114,38 +115,38 @@ static int agp_backend_initialize(struct pci_dev *dev)
 {
 	int size_value, rc, got_gatt=0, got_keylist=0;
 
-	agp_bridge.max_memory_agp = agp_find_max();
-	agp_bridge.version = &agp_current_version;
+	agp_bridge->max_memory_agp = agp_find_max();
+	agp_bridge->version = &agp_current_version;
 
-	if (agp_bridge.needs_scratch_page == TRUE) {
+	if (agp_bridge->needs_scratch_page == TRUE) {
 		void *addr;
-		addr = agp_bridge.agp_alloc_page();
+		addr = agp_bridge->agp_alloc_page();
 
 		if (addr == NULL) {
 			printk(KERN_ERR PFX "unable to get memory for scratch page.\n");
 			return -ENOMEM;
 		}
-		agp_bridge.scratch_page_real = virt_to_phys(addr);
-		agp_bridge.scratch_page =
-			agp_bridge.mask_memory(agp_bridge.scratch_page_real, 0);
+		agp_bridge->scratch_page_real = virt_to_phys(addr);
+		agp_bridge->scratch_page =
+			agp_bridge->mask_memory(agp_bridge->scratch_page_real, 0);
 	}
 
-	size_value = agp_bridge.fetch_size();
+	size_value = agp_bridge->fetch_size();
 
 	if (size_value == 0) {
 		printk(KERN_ERR PFX "unable to determine aperture size.\n");
 		rc = -EINVAL;
 		goto err_out;
 	}
-	if (agp_bridge.create_gatt_table()) {
+	if (agp_bridge->create_gatt_table()) {
 		printk(KERN_ERR PFX "unable to get memory for graphics translation table.\n");
 		rc = -ENOMEM;
 		goto err_out;
 	}
 	got_gatt = 1;
 	
-	agp_bridge.key_list = vmalloc(PAGE_SIZE * 4);
-	if (agp_bridge.key_list == NULL) {
+	agp_bridge->key_list = vmalloc(PAGE_SIZE * 4);
+	if (agp_bridge->key_list == NULL) {
 		printk(KERN_ERR PFX "error allocating memory for key lists.\n");
 		rc = -ENOMEM;
 		goto err_out;
@@ -153,27 +154,27 @@ static int agp_backend_initialize(struct pci_dev *dev)
 	got_keylist = 1;
 	
 	/* FIXME vmalloc'd memory not guaranteed contiguous */
-	memset(agp_bridge.key_list, 0, PAGE_SIZE * 4);
+	memset(agp_bridge->key_list, 0, PAGE_SIZE * 4);
 
-	if (agp_bridge.configure()) {
+	if (agp_bridge->configure()) {
 		printk(KERN_ERR PFX "error configuring host chipset.\n");
 		rc = -EINVAL;
 		goto err_out;
 	}
 
 	printk(KERN_INFO PFX "AGP aperture is %dM @ 0x%lx\n",
-	       size_value, agp_bridge.gart_bus_addr);
+	       size_value, agp_bridge->gart_bus_addr);
 
 	return 0;
 
 err_out:
-	if (agp_bridge.needs_scratch_page == TRUE) {
-		agp_bridge.agp_destroy_page(phys_to_virt(agp_bridge.scratch_page_real));
+	if (agp_bridge->needs_scratch_page == TRUE) {
+		agp_bridge->agp_destroy_page(phys_to_virt(agp_bridge->scratch_page_real));
 	}
 	if (got_gatt)
-		agp_bridge.free_gatt_table();
+		agp_bridge->free_gatt_table();
 	if (got_keylist)
-		vfree(agp_bridge.key_list);
+		vfree(agp_bridge->key_list);
 	return rc;
 }
 
@@ -181,13 +182,16 @@ static int agp_backend_initialize(struct pci_dev *dev)
 /* cannot be __exit b/c as it could be called from __init code */
 static void agp_backend_cleanup(void)
 {
-	agp_bridge.cleanup();
-	agp_bridge.free_gatt_table();
-	vfree(agp_bridge.key_list);
-
-	if (agp_bridge.needs_scratch_page == TRUE) {
-		agp_bridge.agp_destroy_page(phys_to_virt(agp_bridge.scratch_page_real));
-	}
+	if (agp_bridge->cleanup != NULL)
+		agp_bridge->cleanup();
+	if (agp_bridge->free_gatt_table != NULL)
+		agp_bridge->free_gatt_table();
+	if (agp_bridge->key_list)
+		vfree(agp_bridge->key_list);
+
+	if ((agp_bridge->agp_destroy_page!=NULL) &&
+			(agp_bridge->needs_scratch_page == TRUE))
+		agp_bridge->agp_destroy_page(phys_to_virt(agp_bridge->scratch_page_real));
 }
 
 static int agp_power(struct pm_dev *dev, pm_request_t rq, void *data)
@@ -195,9 +199,9 @@ static int agp_power(struct pm_dev *dev, pm_request_t rq, void *data)
 	switch(rq)
 	{
 		case PM_SUSPEND:
-			return agp_bridge.suspend();
+			return agp_bridge->suspend();
 		case PM_RESUME:
-			agp_bridge.resume();
+			agp_bridge->resume();
 			return 0;
 	}		
 	return 0;
@@ -248,21 +252,25 @@ int agp_register_driver (struct agp_driver *drv)
 	/* FIXME: What to do with this? */
 	inter_module_register("drm_agp", THIS_MODULE, &drm_agp);
 
-	pm_register(PM_PCI_DEV, PM_PCI_ID(agp_bridge.dev), agp_power);
+	pm_register(PM_PCI_DEV, PM_PCI_ID(agp_bridge->dev), agp_power);
 	agp_count++;
 	return 0;
 
 frontend_err:
 	agp_backend_cleanup();
 err_out:
-	agp_bridge.type = NOT_SUPPORTED;
+	agp_bridge->type = NOT_SUPPORTED;
 	module_put(drv->owner);
+	drv->dev = NULL;
 	return ret_val;
 }
 
 int agp_unregister_driver(struct agp_driver *drv)
 {
-	agp_bridge.type = NOT_SUPPORTED;
+	if (drv->dev==NULL)
+		return -ENODEV;
+
+	agp_bridge->type = NOT_SUPPORTED;
 	pm_unregister_all(agp_power);
 	agp_frontend_cleanup();
 	agp_backend_cleanup();
@@ -282,8 +290,8 @@ int __init agp_init(void)
 
 	already_initialised = 1;
 
-	memset(&agp_bridge, 0, sizeof(struct agp_bridge_data));
-	agp_bridge.type = NOT_SUPPORTED;
+	memset(agp_bridge, 0, sizeof(struct agp_bridge_data));
+	agp_bridge->type = NOT_SUPPORTED;
 
 	printk(KERN_INFO "Linux agpgart interface v%d.%d (c) Dave Jones\n",
 	       AGPGART_VERSION_MAJOR, AGPGART_VERSION_MINOR);

drivers/char/agp/frontend.c

@@ -97,7 +97,9 @@ static agp_segment_priv *agp_find_seg_in_client(const agp_client * client,
 					    int size, pgprot_t page_prot)
 {
 	agp_segment_priv *seg;
-	int num_segments, pg_start, pg_count, i;
+	int num_segments, i;
+	off_t pg_start;
+	size_t pg_count;
 
 	pg_start = offset / 4096;
 	pg_count = size / 4096;
@@ -174,7 +176,7 @@ static int agp_create_segment(agp_client * client, agp_region * region)
 	agp_segment_priv **ret_seg;
 	agp_segment_priv *seg;
 	agp_segment *user_seg;
-	int i;
+	size_t i;
 
 	seg = kmalloc((sizeof(agp_segment_priv) * region->seg_count), GFP_KERNEL);
 	if (seg == NULL) {
@@ -578,8 +580,7 @@ static int agp_remove_client(pid_t id)
 
 static int agp_mmap(struct file *file, struct vm_area_struct *vma)
 {
-	int size;
-	int current_size;
+	unsigned int size, current_size;
 	unsigned long offset;
 	agp_client *client;
 	agp_file_private *priv = (agp_file_private *) file->private_data;
@@ -611,7 +612,10 @@ static int agp_mmap(struct file *file, struct vm_area_struct *vma)
 		if (!agp_find_seg_in_client(client, offset, size, vma->vm_page_prot))
 			goto out_inval;
 
-		if (remap_page_range(vma, vma->vm_start, (kerninfo.aper_base + offset),
+		if (kerninfo.vm_ops) {
+			vma->vm_ops = kerninfo.vm_ops;
+		} else if (remap_page_range(vma, vma->vm_start, 
+					    (kerninfo.aper_base + offset),
 					    size, vma->vm_page_prot)) {
 			goto out_again;
 		}
@@ -623,7 +627,10 @@ static int agp_mmap(struct file *file, struct vm_area_struct *vma)
 		if (size != current_size)
 			goto out_inval;
 
-		if (remap_page_range(vma, vma->vm_start, kerninfo.aper_base,
+		if (kerninfo.vm_ops) {
+			vma->vm_ops = kerninfo.vm_ops;
+		} else if (remap_page_range(vma, vma->vm_start, 
+					    kerninfo.aper_base,
 					    size, vma->vm_page_prot)) {
 			goto out_again;
 		}

drivers/char/agp/generic-3.0.c

@@ -77,7 +77,7 @@ static int agp_3_0_isochronous_node_enable(struct agp_3_0_dev *dev_list, unsigne
 		struct agp_3_0_dev *dev;
 	};
 
-	struct pci_dev *td = agp_bridge.dev, *dev;
+	struct pci_dev *td = agp_bridge->dev, *dev;
 	struct list_head *head = &dev_list->list, *pos;
 	struct agp_3_0_dev *cur;
 	struct isoch_data *master, target;
@@ -117,8 +117,8 @@ static int agp_3_0_isochronous_node_enable(struct agp_3_0_dev *dev_list, unsigne
 	if((ret = agp_3_0_dev_list_sort(dev_list, ndevs)) != 0)
 		goto free_and_exit;
 
-	pci_read_config_dword(td, agp_bridge.capndx + 0x0c, &tnistat);
-	pci_read_config_dword(td, agp_bridge.capndx + 0x04, &tstatus);
+	pci_read_config_dword(td, agp_bridge->capndx + 0x0c, &tnistat);
+	pci_read_config_dword(td, agp_bridge->capndx + 0x04, &tstatus);
 
 	/* Extract power-on defaults from the target */
 	target.maxbw = (tnistat >> 16) & 0xff;
@@ -170,13 +170,13 @@ static int agp_3_0_isochronous_node_enable(struct agp_3_0_dev *dev_list, unsigne
 	 * in the target's NISTAT register, so we need to do this now
 	 * to get an accurate value for ISOCH_N later.
 	 */
-	pci_read_config_word(td, agp_bridge.capndx + 0x20, &tnicmd);
+	pci_read_config_word(td, agp_bridge->capndx + 0x20, &tnicmd);
 	tnicmd &= ~(0x3 << 6);
 	tnicmd |= target.y << 6;
-	pci_write_config_word(td, agp_bridge.capndx + 0x20, tnicmd);
+	pci_write_config_word(td, agp_bridge->capndx + 0x20, tnicmd);
 
 	/* Reread the target's ISOCH_N */
-	pci_read_config_dword(td, agp_bridge.capndx + 0x0c, &tnistat);
+	pci_read_config_dword(td, agp_bridge->capndx + 0x0c, &tnistat);
 	target.n = (tnistat >> 8) & 0xff;
 
 	/* Calculate the minimum ISOCH_N needed by each master */
@@ -296,7 +296,7 @@ static int agp_3_0_nonisochronous_node_enable(struct agp_3_0_dev *dev_list, unsi
 	u32 trq, mrq, rem;
 	unsigned int cdev = 0;
 
-	pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx + 0x04, &tstatus);
+	pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx + 0x04, &tstatus);
 
 	trq = (tstatus >> 24) & 0xff;
 	mrq = trq / ndevs;
@@ -321,7 +321,7 @@ static int agp_3_0_nonisochronous_node_enable(struct agp_3_0_dev *dev_list, unsi
  */
 static int agp_3_0_node_enable(u32 mode, u32 minor)
 {
-	struct pci_dev *td = agp_bridge.dev, *dev;
+	struct pci_dev *td = agp_bridge->dev, *dev;
 	u8 bus_num, mcapndx;
 	u32 isoch, arqsz, cal_cycle, tmp, rate;
 	u32 tstatus, tcmd, mcmd, mstatus, ncapid;
@@ -364,7 +364,7 @@ static int agp_3_0_node_enable(u32 mode, u32 minor)
 	}
 
 	/* Extract some power-on defaults from the target */
-	pci_read_config_dword(td, agp_bridge.capndx + 0x04, &tstatus);
+	pci_read_config_dword(td, agp_bridge->capndx + 0x04, &tstatus);
 	isoch     = (tstatus >> 17) & 0x1;
 	arqsz     = (tstatus >> 13) & 0x7;
 	cal_cycle = (tstatus >> 10) & 0x7;
@@ -470,7 +470,7 @@ static int agp_3_0_node_enable(u32 mode, u32 minor)
 	 * Also set the AGP_ENABLE bit, effectively 'turning on' the
 	 * target (this has to be done _before_ turning on the masters).
 	 */
-	pci_read_config_dword(td, agp_bridge.capndx + 0x08, &tcmd);
+	pci_read_config_dword(td, agp_bridge->capndx + 0x08, &tcmd);
 
 	tcmd &= ~(0x7 << 10);
 	tcmd &= ~0x7;
@@ -479,7 +479,7 @@ static int agp_3_0_node_enable(u32 mode, u32 minor)
 	tcmd |= 0x1 << 8;
 	tcmd |= rate;
 
-	pci_write_config_dword(td, agp_bridge.capndx + 0x08, tcmd);
+	pci_write_config_dword(td, agp_bridge->capndx + 0x08, tcmd);
 
 	/*
 	 * Set the target's advertised arqsz value, the minimum supported
@@ -525,11 +525,11 @@ static int agp_3_0_node_enable(u32 mode, u32 minor)
  * (AGP 3.0 devices are required to operate as AGP 2.0 devices 
  * when not using 3.0 electricals.
  */
-int agp_generic_agp_3_0_enable(u32 mode)
+void agp_generic_agp_3_0_enable(u32 mode)
 {
 	u32 ncapid, major, minor, agp_3_0;
 
-	pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx, &ncapid);
+	pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx, &ncapid);
 
 	major = (ncapid >> 20) & 0xf;
 	minor = (ncapid >> 16) & 0xf;
@@ -537,16 +537,13 @@ int agp_generic_agp_3_0_enable(u32 mode)
 	printk(KERN_INFO PFX "Found an AGP %d.%d compliant device.\n",major, minor);
 
 	if(major >= 3) {
-		pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx + 0x4, &agp_3_0);
+		pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx + 0x4, &agp_3_0);
 		/* 
 		 * Check to see if we are operating in 3.0 mode 
 		 */
-		if((agp_3_0 >> 3) & 0x1) {
+		if((agp_3_0 >> 3) & 0x1)
 			agp_3_0_node_enable(mode, minor);
-			return TRUE;
 	}
-	}
-	return FALSE;
 }
 
 EXPORT_SYMBOL(agp_generic_agp_3_0_enable);

drivers/char/agp/hp-agp.c

@@ -176,7 +176,7 @@ static int hp_zx1_fetch_size(void)
 
 	size = hp_private.gart_size / MB(1);
 	hp_zx1_sizes[0].size = size;
-	agp_bridge.current_size = (void *) &hp_zx1_sizes[0];
+	agp_bridge->current_size = (void *) &hp_zx1_sizes[0];
 	return size;
 }
 
@@ -184,10 +184,10 @@ static int hp_zx1_configure(void)
 {
 	struct _hp_private *hp = &hp_private;
 
-	agp_bridge.gart_bus_addr = hp->gart_base;
-	agp_bridge.capndx = pci_find_capability(agp_bridge.dev, PCI_CAP_ID_AGP);
-	pci_read_config_dword(agp_bridge.dev,
-		agp_bridge.capndx + PCI_AGP_STATUS, &agp_bridge.mode);
+	agp_bridge->gart_bus_addr = hp->gart_base;
+	agp_bridge->capndx = pci_find_capability(agp_bridge->dev, PCI_CAP_ID_AGP);
+	pci_read_config_dword(agp_bridge->dev,
+		agp_bridge->capndx + PCI_AGP_STATUS, &agp_bridge->mode);
 
 	if (hp->io_pdir_owner) {
 		OUTREG64(hp->registers, HP_ZX1_PDIR_BASE,
@@ -241,7 +241,7 @@ static int hp_zx1_create_gatt_table(void)
 	}
 
 	for (i = 0; i < hp->gatt_entries; i++) {
-		hp->gatt[i] = (unsigned long) agp_bridge.scratch_page;
+		hp->gatt[i] = (unsigned long) agp_bridge->scratch_page;
 	}
 
 	return 0;
@@ -296,11 +296,11 @@ static int hp_zx1_insert_memory(agp_memory * mem, off_t pg_start, int type)
 		for (k = 0;
 		     k < hp->io_pages_per_kpage;
 		     k++, j++, paddr += hp->io_page_size) {
-			hp->gatt[j] = agp_bridge.mask_memory(paddr, type);
+			hp->gatt[j] = agp_bridge->mask_memory(paddr, type);
 		}
 	}
 
-	agp_bridge.tlb_flush(mem);
+	agp_bridge->tlb_flush(mem);
 	return 0;
 }
 
@@ -316,10 +316,10 @@ static int hp_zx1_remove_memory(agp_memory * mem, off_t pg_start, int type)
 	io_pg_start = hp->io_pages_per_kpage * pg_start;
 	io_pg_count = hp->io_pages_per_kpage * mem->page_count;
 	for (i = io_pg_start; i < io_pg_count + io_pg_start; i++) {
-		hp->gatt[i] = agp_bridge.scratch_page;
+		hp->gatt[i] = agp_bridge->scratch_page;
 	}
 
-	agp_bridge.tlb_flush(mem);
+	agp_bridge->tlb_flush(mem);
 	return 0;
 }
 
@@ -330,39 +330,39 @@ static unsigned long hp_zx1_mask_memory(unsigned long addr, int type)
 
 static int __init hp_zx1_setup (struct pci_dev *pdev __attribute__((unused)))
 {
-	agp_bridge.masks = hp_zx1_masks;
-	agp_bridge.dev_private_data = NULL;
-	agp_bridge.size_type = FIXED_APER_SIZE;
-	agp_bridge.needs_scratch_page = FALSE;
-	agp_bridge.configure = hp_zx1_configure;
-	agp_bridge.fetch_size = hp_zx1_fetch_size;
-	agp_bridge.cleanup = hp_zx1_cleanup;
-	agp_bridge.tlb_flush = hp_zx1_tlbflush;
-	agp_bridge.mask_memory = hp_zx1_mask_memory;
-	agp_bridge.agp_enable = agp_generic_agp_enable;
-	agp_bridge.cache_flush = global_cache_flush;
-	agp_bridge.create_gatt_table = hp_zx1_create_gatt_table;
-	agp_bridge.free_gatt_table = hp_zx1_free_gatt_table;
-	agp_bridge.insert_memory = hp_zx1_insert_memory;
-	agp_bridge.remove_memory = hp_zx1_remove_memory;
-	agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
-	agp_bridge.free_by_type = agp_generic_free_by_type;
-	agp_bridge.agp_alloc_page = agp_generic_alloc_page;
-	agp_bridge.agp_destroy_page = agp_generic_destroy_page;
-	agp_bridge.cant_use_aperture = 1;
+	agp_bridge->masks = hp_zx1_masks;
+	agp_bridge->dev_private_data = NULL;
+	agp_bridge->size_type = FIXED_APER_SIZE;
+	agp_bridge->needs_scratch_page = FALSE;
+	agp_bridge->configure = hp_zx1_configure;
+	agp_bridge->fetch_size = hp_zx1_fetch_size;
+	agp_bridge->cleanup = hp_zx1_cleanup;
+	agp_bridge->tlb_flush = hp_zx1_tlbflush;
+	agp_bridge->mask_memory = hp_zx1_mask_memory;
+	agp_bridge->agp_enable = agp_generic_agp_enable;
+	agp_bridge->cache_flush = global_cache_flush;
+	agp_bridge->create_gatt_table = hp_zx1_create_gatt_table;
+	agp_bridge->free_gatt_table = hp_zx1_free_gatt_table;
+	agp_bridge->insert_memory = hp_zx1_insert_memory;
+	agp_bridge->remove_memory = hp_zx1_remove_memory;
+	agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+	agp_bridge->free_by_type = agp_generic_free_by_type;
+	agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+	agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+	agp_bridge->cant_use_aperture = 1;
 	return hp_zx1_ioc_init();
 }
 
 static int __init agp_find_supported_device(struct pci_dev *dev)
 {
-	agp_bridge.dev = dev;
+	agp_bridge->dev = dev;
 
 	/* ZX1 LBAs can be either PCI or AGP bridges */
 	if (pci_find_capability(dev, PCI_CAP_ID_AGP)) {
 		printk(KERN_INFO PFX "Detected HP ZX1 AGP chipset at %s\n",
 			dev->slot_name);
-		agp_bridge.type = HP_ZX1;
-		agp_bridge.dev = dev;
+		agp_bridge->type = HP_ZX1;
+		agp_bridge->dev = dev;
 		return hp_zx1_setup(dev);
 	}
 	return -ENODEV;
@@ -408,7 +408,7 @@ static int __init agp_hp_init(void)
 
 	ret_val = pci_module_init(&agp_hp_pci_driver);
 	if (ret_val)
-		agp_bridge.type = NOT_SUPPORTED;
+		agp_bridge->type = NOT_SUPPORTED;
 
 	return ret_val;
 }

drivers/char/agp/i7x05-agp.c

@@ -13,16 +13,16 @@ static int intel_7505_fetch_size(void)
 	/* 
 	 * For AGP 3.0 APSIZE is now 16 bits
 	 */
-	pci_read_config_word (agp_bridge.dev, INTEL_I7505_APSIZE, &tmp);
+	pci_read_config_word (agp_bridge->dev, INTEL_I7505_APSIZE, &tmp);
 	tmp = (tmp & 0xfff);
 	
-	values = A_SIZE_16(agp_bridge.aperture_sizes);
+	values = A_SIZE_16(agp_bridge->aperture_sizes);
 
-	for (i=0; i < agp_bridge.num_aperture_sizes; i++) {
+	for (i=0; i < agp_bridge->num_aperture_sizes; i++) {
 		if (tmp == values[i].size_value) {
-			agp_bridge.previous_size = agp_bridge.current_size =
+			agp_bridge->previous_size = agp_bridge->current_size =
 					(void *)(values + i);
-			agp_bridge.aperture_size_idx = i;
+			agp_bridge->aperture_size_idx = i;
 			return values[i].size;
 		}
 	}
@@ -33,18 +33,18 @@ static int intel_7505_fetch_size(void)
 static void intel_7505_tlbflush(agp_memory *mem)
 {
 	u32 temp;
-	pci_read_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, &temp);
-	pci_write_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, temp & ~(1 << 7));
-	pci_read_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, &temp);
-	pci_write_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, temp | (1 << 7));
+	pci_read_config_dword(agp_bridge->dev, INTEL_I7505_AGPCTRL, &temp);
+	pci_write_config_dword(agp_bridge->dev, INTEL_I7505_AGPCTRL, temp & ~(1 << 7));
+	pci_read_config_dword(agp_bridge->dev, INTEL_I7505_AGPCTRL, &temp);
+	pci_write_config_dword(agp_bridge->dev, INTEL_I7505_AGPCTRL, temp | (1 << 7));
 }
 
 static void intel_7505_cleanup(void)
 {
 	aper_size_info_16 *previous_size;
 
-	previous_size = A_SIZE_16(agp_bridge.previous_size);
-	pci_write_config_byte(agp_bridge.dev, INTEL_I7505_APSIZE,
+	previous_size = A_SIZE_16(agp_bridge->previous_size);
+	pci_write_config_byte(agp_bridge->dev, INTEL_I7505_APSIZE,
 			      previous_size->size_value);
 }
 
@@ -54,25 +54,25 @@ static int intel_7505_configure(void)
 	u32 temp;
 	aper_size_info_16 *current_size;
 	
-	current_size = A_SIZE_16(agp_bridge.current_size);
+	current_size = A_SIZE_16(agp_bridge->current_size);
 
 	/* aperture size */
-	pci_write_config_word(agp_bridge.dev, INTEL_I7505_APSIZE,
+	pci_write_config_word(agp_bridge->dev, INTEL_I7505_APSIZE,
 			      current_size->size_value);
 
 	/* address to map to */
-	pci_read_config_dword(agp_bridge.dev, INTEL_I7505_NAPBASELO, &temp);
-	agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+	pci_read_config_dword(agp_bridge->dev, INTEL_I7505_NAPBASELO, &temp);
+	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 
 	/* attbase */ 
-	pci_write_config_dword(agp_bridge.dev, INTEL_I7505_ATTBASE,
-			       agp_bridge.gatt_bus_addr);
+	pci_write_config_dword(agp_bridge->dev, INTEL_I7505_ATTBASE,
+			       agp_bridge->gatt_bus_addr);
 
 	/* agpctrl */
-	pci_write_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, 0x0000);
+	pci_write_config_dword(agp_bridge->dev, INTEL_I7505_AGPCTRL, 0x0000);
 
 	/* clear error registers */
-	pci_write_config_byte(agp_bridge.dev, INTEL_I7505_ERRSTS, 0xff);
+	pci_write_config_byte(agp_bridge->dev, INTEL_I7505_ERRSTS, 0xff);
 	return 0;
 }
 
@@ -95,30 +95,30 @@ static void i7505_setup (u32 mode)
 
 static int __init intel_7505_setup (struct pci_dev *pdev)
 {
-	agp_bridge.masks = intel_generic_masks;
-	agp_bridge.aperture_sizes = (void *) intel_7505_sizes;
-	agp_bridge.size_type = U16_APER_SIZE;
-	agp_bridge.num_aperture_sizes = 7;
-	agp_bridge.dev_private_data = NULL;
-	agp_bridge.needs_scratch_page = FALSE;
-	agp_bridge.configure = intel_7505_configure;
-	agp_bridge.fetch_size = intel_7505_fetch_size;
-	agp_bridge.cleanup = intel_7505_cleanup;
-	agp_bridge.tlb_flush = intel_7505_tlbflush;
-	agp_bridge.mask_memory = intel_mask_memory;
-	agp_bridge.agp_enable = i7505_enable;
-	agp_bridge.cache_flush = global_cache_flush;
-	agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
-	agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
-	agp_bridge.insert_memory = agp_generic_insert_memory;
-	agp_bridge.remove_memory = agp_generic_remove_memory;
-	agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
-	agp_bridge.free_by_type = agp_generic_free_by_type;
-	agp_bridge.agp_alloc_page = agp_generic_alloc_page;
-	agp_bridge.agp_destroy_page = agp_generic_destroy_page;
-	agp_bridge.suspend = agp_generic_suspend;
-	agp_bridge.resume = agp_generic_resume;
-	agp_bridge.cant_use_aperture = 0;
+	agp_bridge->masks = intel_generic_masks;
+	agp_bridge->aperture_sizes = (void *) intel_7505_sizes;
+	agp_bridge->size_type = U16_APER_SIZE;
+	agp_bridge->num_aperture_sizes = 7;
+	agp_bridge->dev_private_data = NULL;
+	agp_bridge->needs_scratch_page = FALSE;
+	agp_bridge->configure = intel_7505_configure;
+	agp_bridge->fetch_size = intel_7505_fetch_size;
+	agp_bridge->cleanup = intel_7505_cleanup;
+	agp_bridge->tlb_flush = intel_7505_tlbflush;
+	agp_bridge->mask_memory = intel_mask_memory;
+	agp_bridge->agp_enable = i7505_enable;
+	agp_bridge->cache_flush = global_cache_flush;
+	agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+	agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+	agp_bridge->insert_memory = agp_generic_insert_memory;
+	agp_bridge->remove_memory = agp_generic_remove_memory;
+	agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+	agp_bridge->free_by_type = agp_generic_free_by_type;
+	agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+	agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+	agp_bridge->suspend = agp_generic_suspend;
+	agp_bridge->resume = agp_generic_resume;
+	agp_bridge->cant_use_aperture = 0;
 	return 0;
 }
 
@@ -149,7 +149,7 @@ static int __init agp_lookup_host_bridge (struct pci_dev *pdev)
 		if (pdev->device == devs[j].device_id) {
 			printk (KERN_INFO PFX "Detected Intel %s chipset\n",
 				devs[j].chipset_name);
-			agp_bridge.type = devs[j].chipset;
+			agp_bridge->type = devs[j].chipset;
 
 			if (devs[j].chipset_setup != NULL)
 				return devs[j].chipset_setup(pdev);
@@ -177,10 +177,10 @@ static int __init agp_i7x05_probe (struct pci_dev *dev, const struct pci_device_
 		return -ENODEV;
 
 	if (agp_lookup_host_bridge(dev) != -ENODEV) {
-		agp_bridge.dev = dev;
-		agp_bridge.capndx = cap_ptr;
+		agp_bridge->dev = dev;
+		agp_bridge->capndx = cap_ptr;
 		/* Fill in the mode register */
-		pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode)
+		pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode)
 		i7x05_agp_driver.dev = dev;
 		agp_register_driver(&i7x05_agp_driver);
 		return 0;
@@ -215,7 +215,7 @@ int __init agp_i7x05_init(void)
 
 	ret_val = pci_module_init(&agp_i7x05_pci_driver);
 	if (ret_val)
-		agp_bridge.type = NOT_SUPPORTED;
+		agp_bridge->type = NOT_SUPPORTED;
 
 	return ret_val;
 }

drivers/char/agp/sis-agp.c

@@ -16,16 +16,16 @@ static int sis_fetch_size(void)
 	int i;
 	struct aper_size_info_8 *values;
 
-	pci_read_config_byte(agp_bridge.dev, SIS_APSIZE, &temp_size);
-	values = A_SIZE_8(agp_bridge.aperture_sizes);
-	for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+	pci_read_config_byte(agp_bridge->dev, SIS_APSIZE, &temp_size);
+	values = A_SIZE_8(agp_bridge->aperture_sizes);
+	for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
 		if ((temp_size == values[i].size_value) ||
 		    ((temp_size & ~(0x03)) ==
 		     (values[i].size_value & ~(0x03)))) {
-			agp_bridge.previous_size =
-			    agp_bridge.current_size = (void *) (values + i);
+			agp_bridge->previous_size =
+			    agp_bridge->current_size = (void *) (values + i);
 
-			agp_bridge.aperture_size_idx = i;
+			agp_bridge->aperture_size_idx = i;
 			return values[i].size;
 		}
 	}
@@ -35,7 +35,7 @@ static int sis_fetch_size(void)
 
 static void sis_tlbflush(agp_memory * mem)
 {
-	pci_write_config_byte(agp_bridge.dev, SIS_TLBFLUSH, 0x02);
+	pci_write_config_byte(agp_bridge->dev, SIS_TLBFLUSH, 0x02);
 }
 
 static int sis_configure(void)
@@ -43,13 +43,13 @@ static int sis_configure(void)
 	u32 temp;
 	struct aper_size_info_8 *current_size;
 
-	current_size = A_SIZE_8(agp_bridge.current_size);
-	pci_write_config_byte(agp_bridge.dev, SIS_TLBCNTRL, 0x05);
-	pci_read_config_dword(agp_bridge.dev, SIS_APBASE, &temp);
-	agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
-	pci_write_config_dword(agp_bridge.dev, SIS_ATTBASE,
-			       agp_bridge.gatt_bus_addr);
-	pci_write_config_byte(agp_bridge.dev, SIS_APSIZE,
+	current_size = A_SIZE_8(agp_bridge->current_size);
+	pci_write_config_byte(agp_bridge->dev, SIS_TLBCNTRL, 0x05);
+	pci_read_config_dword(agp_bridge->dev, SIS_APBASE, &temp);
+	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+	pci_write_config_dword(agp_bridge->dev, SIS_ATTBASE,
+			       agp_bridge->gatt_bus_addr);
+	pci_write_config_byte(agp_bridge->dev, SIS_APSIZE,
 			      current_size->size_value);
 	return 0;
 }
@@ -58,8 +58,8 @@ static void sis_cleanup(void)
 {
 	struct aper_size_info_8 *previous_size;
 
-	previous_size = A_SIZE_8(agp_bridge.previous_size);
-	pci_write_config_byte(agp_bridge.dev, SIS_APSIZE,
+	previous_size = A_SIZE_8(agp_bridge->previous_size);
+	pci_write_config_byte(agp_bridge->dev, SIS_APSIZE,
 			      (previous_size->size_value & ~(0x03)));
 }
 
@@ -67,7 +67,7 @@ static unsigned long sis_mask_memory(unsigned long addr, int type)
 {
 	/* Memory type is ignored */
 
-	return addr | agp_bridge.masks[0].mask;
+	return addr | agp_bridge->masks[0].mask;
 }
 
 static struct aper_size_info_8 sis_generic_sizes[7] =
@@ -88,30 +88,30 @@ static struct gatt_mask sis_generic_masks[] =
 
 static int __init sis_generic_setup (struct pci_dev *pdev)
 {
-	agp_bridge.masks = sis_generic_masks;
-	agp_bridge.aperture_sizes = (void *) sis_generic_sizes;
-	agp_bridge.size_type = U8_APER_SIZE;
-	agp_bridge.num_aperture_sizes = 7;
-	agp_bridge.dev_private_data = NULL;
-	agp_bridge.needs_scratch_page = FALSE;
-	agp_bridge.configure = sis_configure;
-	agp_bridge.fetch_size = sis_fetch_size;
-	agp_bridge.cleanup = sis_cleanup;
-	agp_bridge.tlb_flush = sis_tlbflush;
-	agp_bridge.mask_memory = sis_mask_memory;
-	agp_bridge.agp_enable = agp_generic_agp_enable;
-	agp_bridge.cache_flush = global_cache_flush;
-	agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
-	agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
-	agp_bridge.insert_memory = agp_generic_insert_memory;
-	agp_bridge.remove_memory = agp_generic_remove_memory;
-	agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
-	agp_bridge.free_by_type = agp_generic_free_by_type;
-	agp_bridge.agp_alloc_page = agp_generic_alloc_page;
-	agp_bridge.agp_destroy_page = agp_generic_destroy_page;
-	agp_bridge.suspend = agp_generic_suspend;
-	agp_bridge.resume = agp_generic_resume;
-	agp_bridge.cant_use_aperture = 0;
+	agp_bridge->masks = sis_generic_masks;
+	agp_bridge->aperture_sizes = (void *) sis_generic_sizes;
+	agp_bridge->size_type = U8_APER_SIZE;
+	agp_bridge->num_aperture_sizes = 7;
+	agp_bridge->dev_private_data = NULL;
+	agp_bridge->needs_scratch_page = FALSE;
+	agp_bridge->configure = sis_configure;
+	agp_bridge->fetch_size = sis_fetch_size;
+	agp_bridge->cleanup = sis_cleanup;
+	agp_bridge->tlb_flush = sis_tlbflush;
+	agp_bridge->mask_memory = sis_mask_memory;
+	agp_bridge->agp_enable = agp_generic_agp_enable;
+	agp_bridge->cache_flush = global_cache_flush;
+	agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+	agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+	agp_bridge->insert_memory = agp_generic_insert_memory;
+	agp_bridge->remove_memory = agp_generic_remove_memory;
+	agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+	agp_bridge->free_by_type = agp_generic_free_by_type;
+	agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+	agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+	agp_bridge->suspend = agp_generic_suspend;
+	agp_bridge->resume = agp_generic_resume;
+	agp_bridge->cant_use_aperture = 0;
 
 	return 0;
 }
@@ -198,7 +198,7 @@ static int __init agp_lookup_host_bridge (struct pci_dev *pdev)
 		if (pdev->device == devs[j].device_id) {
 			printk (KERN_INFO PFX "Detected SiS %s chipset\n",
 				devs[j].chipset_name);
-			agp_bridge.type = devs[j].chipset;
+			agp_bridge->type = devs[j].chipset;
 
 			if (devs[j].chipset_setup != NULL)
 				return devs[j].chipset_setup(pdev);
@@ -212,7 +212,7 @@ static int __init agp_lookup_host_bridge (struct pci_dev *pdev)
 	if (agp_try_unsupported) {
 		printk(KERN_WARNING PFX "Trying generic SiS routines"
 		       " for device id: %04x\n", pdev->device);
-		agp_bridge.type = SIS_GENERIC;
+		agp_bridge->type = SIS_GENERIC;
 		return sis_generic_setup(pdev);
 	}
 
@@ -235,10 +235,10 @@ static int __init agp_sis_probe (struct pci_dev *dev, const struct pci_device_id
 
 	/* probe for known chipsets */
 	if (agp_lookup_host_bridge(dev) != -ENODEV) {
-		agp_bridge.dev = dev;
-		agp_bridge.capndx = cap_ptr;
+		agp_bridge->dev = dev;
+		agp_bridge->capndx = cap_ptr;
 		/* Fill in the mode register */
-		pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
+		pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
 		sis_agp_driver.dev = dev;
 		agp_register_driver(&sis_agp_driver);
 		return 0;
@@ -272,7 +272,7 @@ static int __init agp_sis_init(void)
 
 	ret_val = pci_module_init(&agp_sis_pci_driver);
 	if (ret_val)
-		agp_bridge.type = NOT_SUPPORTED;
+		agp_bridge->type = NOT_SUPPORTED;
 
 	return ret_val;
 }

drivers/char/agp/via-kt400.c

-/*
- * VIA KT400 AGPGART routines. 
- *
- * The KT400 does magick to put the AGP bridge compliant with the same
- * standards version as the graphics card. If we haven't fallen into
- * 2.0 compatability mode, we run this code. Otherwise, we run the
- * code in via-agp.c
- */
-
-#include <linux/types.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-#include <linux/init.h>
-#include <linux/agp_backend.h>
-#include "agp.h"
-
-static int via_fetch_size(void)
-{
-	int i;
-	u8 temp;
-	struct aper_size_info_16 *values;
-
-	values = A_SIZE_16(agp_bridge.aperture_sizes);
-	pci_read_config_byte(agp_bridge.dev, VIA_AGP3_APSIZE, &temp);
-	for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
-		if (temp == values[i].size_value) {
-			agp_bridge.previous_size =
-			agp_bridge.current_size = (void *) (values + i);
-			agp_bridge.aperture_size_idx = i;
-			return values[i].size;
-		}
-	}
-	return 0;
-}
-
-static int via_configure(void)
-{
-	u32 temp;
-	struct aper_size_info_16 *current_size;
-    
-	current_size = A_SIZE_16(agp_bridge.current_size);
-
-	/* address to map too */
-	pci_read_config_dword(agp_bridge.dev, VIA_APBASE, &temp);
-	agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
-
-	/* attbase - aperture GATT base */
-	pci_write_config_dword(agp_bridge.dev, VIA_AGP3_ATTBASE,
-		agp_bridge.gatt_bus_addr & 0xfffff000);
-	return 0;
-}
-
-static void via_cleanup(void)
-{
-	struct aper_size_info_16 *previous_size;
-
-	previous_size = A_SIZE_16(agp_bridge.previous_size);
-	pci_write_config_byte(agp_bridge.dev, VIA_APSIZE, previous_size->size_value);
-}
-
-static void via_tlbflush(agp_memory * mem)
-{
-	u32 temp;
-
-	pci_read_config_dword(agp_bridge.dev, VIA_AGP3_GARTCTRL, &temp);
-	pci_write_config_dword(agp_bridge.dev, VIA_AGP3_GARTCTRL, temp & ~(1<<7));
-	pci_write_config_dword(agp_bridge.dev, VIA_AGP3_GARTCTRL, temp);
-}
-
-static unsigned long via_mask_memory(unsigned long addr, int type)
-{
-	/* Memory type is ignored */
-
-	return addr | agp_bridge.masks[0].mask;
-}
-
-static struct aper_size_info_16 via_generic_sizes[11] =
-{
-	{ 4,     1024,  0, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3|1<<2|1<<1|1<<0 },
-	{ 8,     2048,  1, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3|1<<2|1<<1},
-	{ 16,    4096,  2, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3|1<<2},
-	{ 32,    8192,  3, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3},
-	{ 64,   16384,  4, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4},
-	{ 128,  32768,  5, 1<<11|1<<10|1<<9|1<<8|1<<5},
-	{ 256,  65536,  6, 1<<11|1<<10|1<<9|1<<8},
-	{ 512,  131072, 7, 1<<11|1<<10|1<<9},
-	{ 1024, 262144, 8, 1<<11|1<<10},
-	{ 2048, 524288, 9, 1<<11}	/* 2GB <- Max supported */
-};
-
-static struct gatt_mask via_generic_masks[] =
-{
-	{.mask = 0x00000000, .type = 0}
-};
-
-
-static void __init via_kt400_enable(u32 mode)
-{
-	if ((agp_generic_agp_3_0_enable(mode))==FALSE)
-		printk (KERN_INFO PFX "agp_generic_agp_3_0_enable() failed\n");
-}
-
-static struct agp_driver via_kt400_agp_driver = {
-	.owner = THIS_MODULE,
-};
-
-static int __init agp_via_probe (struct pci_dev *dev, const struct pci_device_id *ent)
-{
-	u8 reg;
-	u8 cap_ptr = 0;
-
-	cap_ptr = pci_find_capability(dev, PCI_CAP_ID_AGP);
-	if (cap_ptr == 0)
-		return -ENODEV;
-
-	pci_read_config_byte(dev, VIA_AGPSEL, &reg);
-	/* Check if we are in AGP 2.0 compatability mode, if so it
-	 * will be picked up by via-agp.o */
-	if ((reg & (1<<1))==1)
-		return -ENODEV;
-
-	printk (KERN_INFO PFX "Detected VIA KT400 AGP3 chipset\n");
-
-	agp_bridge.dev = dev;
-	agp_bridge.type = VIA_APOLLO_KT400_3;
-	agp_bridge.capndx = cap_ptr;
-	agp_bridge.masks = via_generic_masks;
-	agp_bridge.aperture_sizes = (void *) via_generic_sizes;
-	agp_bridge.size_type = U8_APER_SIZE;
-	agp_bridge.num_aperture_sizes = 7;
-	agp_bridge.dev_private_data = NULL;
-	agp_bridge.needs_scratch_page = FALSE;
-	agp_bridge.agp_enable = via_kt400_enable;
-	agp_bridge.configure = via_configure;
-	agp_bridge.fetch_size = via_fetch_size;
-	agp_bridge.cleanup = via_cleanup;
-	agp_bridge.tlb_flush = via_tlbflush;
-	agp_bridge.mask_memory = via_mask_memory;
-	agp_bridge.cache_flush = global_cache_flush;
-	agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
-	agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
-	agp_bridge.insert_memory = agp_generic_insert_memory;
-	agp_bridge.remove_memory = agp_generic_remove_memory;
-	agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
-	agp_bridge.free_by_type = agp_generic_free_by_type;
-	agp_bridge.agp_alloc_page = agp_generic_alloc_page;
-	agp_bridge.agp_destroy_page = agp_generic_destroy_page;
-	agp_bridge.suspend = agp_generic_suspend;
-	agp_bridge.resume = agp_generic_resume;
-	agp_bridge.cant_use_aperture = 0;
-
-	/* Fill in the mode register */
-	pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
-
-	via_kt400_agp_driver.dev = dev;
-	agp_register_driver(&via_kt400_agp_driver);
-	return 0;
-}
-
-static struct pci_device_id agp_via_pci_table[] __initdata = {
-	{
-	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
-	.class_mask	= ~0,
-	.vendor		= PCI_VENDOR_ID_VIA,
-	.device		= PCI_DEVICE_ID_VIA_8377_0,
-	.subvendor	= PCI_ANY_ID,
-	.subdevice	= PCI_ANY_ID,
-	},
-	{ }
-};
-
-MODULE_DEVICE_TABLE(pci, agp_via_pci_table);
-
-static struct __initdata pci_driver agp_via_pci_driver = {
-	.name		= "agpgart-via",
-	.id_table	= agp_via_pci_table,
-	.probe		= agp_via_probe,
-};
-
-static int __init agp_via_init(void)
-{
-	int ret_val;
-
-	ret_val = pci_module_init(&agp_via_pci_driver);
-	if (ret_val)
-		agp_bridge.type = NOT_SUPPORTED;
-
-	return ret_val;
-}
-
-static void __exit agp_via_cleanup(void)
-{
-	agp_unregister_driver(&via_kt400_agp_driver);
-	pci_unregister_driver(&agp_via_pci_driver);
-}
-
-module_init(agp_via_init);
-module_exit(agp_via_cleanup);
-
-MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
-MODULE_LICENSE("GPL and additional rights");
-

drivers/char/rio/rioroute.c

@@ -763,7 +763,7 @@ uint UnitId;
 #endif
 	UnitId--;		/* this trick relies on the Unit Id being UNSIGNED! */
 
-	if ( UnitId > MAX_RUP )		/* dontcha just lurv unsigned maths! */
+	if ( UnitId >= MAX_RUP )	/* dontcha just lurv unsigned maths! */
 		return(0);
 
 	if ( HostP->Mapping[UnitId].Flags & BEEN_HERE )

drivers/char/specialix.c

@@ -1456,7 +1456,7 @@ static int sx_open(struct tty_struct * tty, struct file * filp)
 	
 	board = SX_BOARD(minor(tty->device));
 
-	if (board > SX_NBOARD || !(sx_board[board].flags & SX_BOARD_PRESENT))
+	if (board >= SX_NBOARD || !(sx_board[board].flags & SX_BOARD_PRESENT))
 		return -ENODEV;
 	
 	bp = &sx_board[board];
@@ -2363,7 +2363,7 @@ int specialix_init(void)
 		struct pci_dev *pdev = NULL;
 
 		i=0;
-		while (i <= SX_NBOARD) {
+		while (i < SX_NBOARD) {
 			if (sx_board[i].flags & SX_BOARD_PRESENT) {
 				i++;
 				continue;

drivers/net/tulip/de4x5.c

@@ -440,8 +440,6 @@
     =========================================================================
 */
 
-static char version[] __initdata = "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n";
-
 #include <linux/config.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
@@ -477,6 +475,8 @@ static char version[] __initdata = "de4x5.c:V0.546 2001/02/22 davies@maniac.ultr
 
 #include "de4x5.h"
 
+static char version[] __initdata = "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n";
+
 #define c_char const char
 #define TWIDDLE(a) (u_short)le16_to_cpu(get_unaligned((u_short *)(a)))
 

fs/buffer.c

@@ -2618,6 +2618,24 @@ void ll_rw_block(int rw, int nr, struct buffer_head *bhs[])
 	}
 }
 
+/*
+ * For a data-integrity writeout, we need to wait upon any in-progress I/O
+ * and then start new I/O and then wait upon it.
+ */
+void sync_dirty_buffer(struct buffer_head *bh)
+{
+	WARN_ON(atomic_read(&bh->b_count) < 1);
+	lock_buffer(bh);
+	if (test_clear_buffer_dirty(bh)) {
+		get_bh(bh);
+		bh->b_end_io = end_buffer_io_sync;
+		submit_bh(WRITE, bh);
+		wait_on_buffer(bh);
+	} else {
+		unlock_buffer(bh);
+	}
+}
+
 /*
  * Sanity checks for try_to_free_buffers.
  */

fs/ext2/balloc.c

@@ -233,10 +233,8 @@ void ext2_free_blocks (struct inode * inode, unsigned long block,
 	}
 
 	mark_buffer_dirty(bitmap_bh);
-	if (sb->s_flags & MS_SYNCHRONOUS) {
-		ll_rw_block(WRITE, 1, &bitmap_bh);
-		wait_on_buffer(bitmap_bh);
-	}
+	if (sb->s_flags & MS_SYNCHRONOUS)
+		sync_dirty_buffer(bitmap_bh);
 
 	group_release_blocks(desc, bh2, group_freed);
 	freed += group_freed;
@@ -466,10 +464,8 @@ int ext2_new_block (struct inode * inode, unsigned long goal,
 	write_unlock(&EXT2_I(inode)->i_meta_lock);
 
 	mark_buffer_dirty(bitmap_bh);
-	if (sb->s_flags & MS_SYNCHRONOUS) {
-		ll_rw_block(WRITE, 1, &bitmap_bh);
-		wait_on_buffer(bitmap_bh);
-	}
+	if (sb->s_flags & MS_SYNCHRONOUS)
+		sync_dirty_buffer(bitmap_bh);
 
 	ext2_debug ("allocating block %d. ", block);
 

fs/ext2/ialloc.c

@@ -146,10 +146,8 @@ void ext2_free_inode (struct inode * inode)
 		mark_buffer_dirty(EXT2_SB(sb)->s_sbh);
 	}
 	mark_buffer_dirty(bitmap_bh);
-	if (sb->s_flags & MS_SYNCHRONOUS) {
-		ll_rw_block(WRITE, 1, &bitmap_bh);
-		wait_on_buffer(bitmap_bh);
-	}
+	if (sb->s_flags & MS_SYNCHRONOUS)
+		sync_dirty_buffer(bitmap_bh);
 	sb->s_dirt = 1;
 error_return:
 	brelse(bitmap_bh);
@@ -485,10 +483,8 @@ struct inode * ext2_new_inode(struct inode * dir, int mode)
 	ext2_set_bit(i, bitmap_bh->b_data);
 
 	mark_buffer_dirty(bitmap_bh);
-	if (sb->s_flags & MS_SYNCHRONOUS) {
-		ll_rw_block(WRITE, 1, &bitmap_bh);
-		wait_on_buffer(bitmap_bh);
-	}
+	if (sb->s_flags & MS_SYNCHRONOUS)
+		sync_dirty_buffer(bitmap_bh);
 	brelse(bitmap_bh);
 
 	ino = group * EXT2_INODES_PER_GROUP(sb) + i + 1;

fs/ext2/inode.c

@@ -443,10 +443,8 @@ static int ext2_alloc_branch(struct inode *inode,
 		 * But we now rely upon generic_osync_inode()
 		 * and b_inode_buffers.  But not for directories.
 		 */
-		if (S_ISDIR(inode->i_mode) && IS_DIRSYNC(inode)) {
-			ll_rw_block(WRITE, 1, &bh);
-			wait_on_buffer(bh);
-		}
+		if (S_ISDIR(inode->i_mode) && IS_DIRSYNC(inode))
+			sync_dirty_buffer(bh);
 		parent = nr;
 	}
 	if (n == num)
@@ -1208,8 +1206,7 @@ static int ext2_update_inode(struct inode * inode, int do_sync)
 		raw_inode->i_block[n] = ei->i_data[n];
 	mark_buffer_dirty(bh);
 	if (do_sync) {
-		ll_rw_block (WRITE, 1, &bh);
-		wait_on_buffer (bh);
+		sync_dirty_buffer(bh);
 		if (buffer_req(bh) && !buffer_uptodate(bh)) {
 			printk ("IO error syncing ext2 inode [%s:%08lx]\n",
 				sb->s_id, (unsigned long) ino);

fs/ext2/super.c

@@ -842,8 +842,7 @@ static void ext2_sync_super(struct super_block *sb, struct ext2_super_block *es)
 {
 	es->s_wtime = cpu_to_le32(get_seconds());
 	mark_buffer_dirty(EXT2_SB(sb)->s_sbh);
-	ll_rw_block(WRITE, 1, &EXT2_SB(sb)->s_sbh);
-	wait_on_buffer(EXT2_SB(sb)->s_sbh);
+	sync_dirty_buffer(EXT2_SB(sb)->s_sbh);
 	sb->s_dirt = 0;
 }
 

fs/ext2/xattr.c

@@ -774,8 +774,7 @@ ext2_xattr_set2(struct inode *inode, struct buffer_head *old_bh,
 		}
 		mark_buffer_dirty(new_bh);
 		if (IS_SYNC(inode)) {
-			ll_rw_block(WRITE, 1, &new_bh);
-			wait_on_buffer(new_bh); 
+			sync_dirty_buffer(new_bh);
 			error = -EIO;
 			if (buffer_req(new_bh) && !buffer_uptodate(new_bh))
 				goto cleanup;
@@ -865,10 +864,8 @@ ext2_xattr_delete_inode(struct inode *inode)
 		HDR(bh)->h_refcount = cpu_to_le32(
 			le32_to_cpu(HDR(bh)->h_refcount) - 1);
 		mark_buffer_dirty(bh);
-		if (IS_SYNC(inode)) {
-			ll_rw_block(WRITE, 1, &bh);
-			wait_on_buffer(bh);
-		}
+		if (IS_SYNC(inode))
+			sync_dirty_buffer(bh);
 		DQUOT_FREE_BLOCK(inode, 1);
 	}
 	EXT2_I(inode)->i_file_acl = 0;