Commit 3f1dcc6a authored by Lucas Stach's avatar Lucas Stach Committed by David S. Miller

net: fec: add necessary defines to work on ARM64

The i.MX8 is a ARMv8 based SoC, that uses the same FEC IP as the
earlier, ARMv7 based, i.MX SoCs. Allow the driver to work on ARM64.
Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
Acked-by: default avatarFugang Duan <fugang.duan@nxp.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent d7dfc5cf
...@@ -20,7 +20,8 @@ ...@@ -20,7 +20,8 @@
#include <linux/timecounter.h> #include <linux/timecounter.h>
#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
defined(CONFIG_ARM64)
/* /*
* Just figures, Motorola would have to change the offsets for * Just figures, Motorola would have to change the offsets for
* registers in the same peripheral device on different models * registers in the same peripheral device on different models
...@@ -195,7 +196,7 @@ ...@@ -195,7 +196,7 @@
* Evidently, ARM SoCs have the FEC block generated in a * Evidently, ARM SoCs have the FEC block generated in a
* little endian mode so adjust endianness accordingly. * little endian mode so adjust endianness accordingly.
*/ */
#if defined(CONFIG_ARM) #if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
#define fec32_to_cpu le32_to_cpu #define fec32_to_cpu le32_to_cpu
#define fec16_to_cpu le16_to_cpu #define fec16_to_cpu le16_to_cpu
#define cpu_to_fec32 cpu_to_le32 #define cpu_to_fec32 cpu_to_le32
......
...@@ -195,7 +195,8 @@ MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); ...@@ -195,7 +195,8 @@ MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
* account when setting it. * account when setting it.
*/ */
#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
defined(CONFIG_ARM64)
#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
#else #else
#define OPT_FRAME_SIZE 0 #define OPT_FRAME_SIZE 0
...@@ -2109,7 +2110,8 @@ static int fec_enet_get_regs_len(struct net_device *ndev) ...@@ -2109,7 +2110,8 @@ static int fec_enet_get_regs_len(struct net_device *ndev)
/* List of registers that can be safety be read to dump them with ethtool */ /* List of registers that can be safety be read to dump them with ethtool */
#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
defined(CONFIG_ARM64)
static u32 fec_enet_register_offset[] = { static u32 fec_enet_register_offset[] = {
FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
...@@ -3139,7 +3141,7 @@ static int fec_enet_init(struct net_device *ndev) ...@@ -3139,7 +3141,7 @@ static int fec_enet_init(struct net_device *ndev)
unsigned dsize_log2 = __fls(dsize); unsigned dsize_log2 = __fls(dsize);
WARN_ON(dsize != (1 << dsize_log2)); WARN_ON(dsize != (1 << dsize_log2));
#if defined(CONFIG_ARM) #if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
fep->rx_align = 0xf; fep->rx_align = 0xf;
fep->tx_align = 0xf; fep->tx_align = 0xf;
#else #else
......
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