Commit 3f688f5d authored by David S. Miller's avatar David S. Miller

[TG3]: Fix 5788/5901, update TSO code.

- Do not set RDMAC_MODE_FIFO_LONG_BURST on 5788
- Do not set WDMAC_MODE_RX_ACCEL on 5788
- Note that 5788 cannot use tagged irq status.
- 5788 cannot do TSO
- 5788 cannot do NETIF_F_HIGHDMA.
- 5901 is 10/100 only.
- Update TSO firmware, add 5705 specific TSO firmware.
- Update TSO packet handling in ->hard_start_xmit() to
  match updated TSO firmware.
- TSO is still off by default until more perf analysis is done.
parent 417ec148
This diff is collapsed.
...@@ -678,6 +678,7 @@ ...@@ -678,6 +678,7 @@
#define RCVLPC_STATSCTRL_ENABLE 0x00000001 #define RCVLPC_STATSCTRL_ENABLE 0x00000001
#define RCVLPC_STATSCTRL_FASTUPD 0x00000002 #define RCVLPC_STATSCTRL_FASTUPD 0x00000002
#define RCVLPC_STATS_ENABLE 0x00002018 #define RCVLPC_STATS_ENABLE 0x00002018
#define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000
#define RCVLPC_STATS_INCMASK 0x0000201c #define RCVLPC_STATS_INCMASK 0x0000201c
/* 0x2020 --> 0x2100 unused */ /* 0x2020 --> 0x2100 unused */
#define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */ #define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */
...@@ -1225,6 +1226,8 @@ ...@@ -1225,6 +1226,8 @@
#define GRC_MISC_CFG_BOARD_ID_5704 0x00000000 #define GRC_MISC_CFG_BOARD_ID_5704 0x00000000
#define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000 #define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
#define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000 #define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000
#define GRC_MISC_CFG_BOARD_ID_5788 0x00010000
#define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000
#define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000 #define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
#define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000 #define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000
#define GRC_LOCAL_CTRL 0x00006808 #define GRC_LOCAL_CTRL 0x00006808
...@@ -1914,6 +1917,8 @@ struct tg3 { ...@@ -1914,6 +1917,8 @@ struct tg3 {
#define TG3_FLG2_RESTART_TIMER 0x00000001 #define TG3_FLG2_RESTART_TIMER 0x00000001
#define TG3_FLG2_SUN_5704 0x00000002 #define TG3_FLG2_SUN_5704 0x00000002
#define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004 #define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004
#define TG3_FLG2_IS_5788 0x00000008
#define TG3_FLG2_MAX_RXPEND_64 0x00000010
u32 split_mode_max_reqs; u32 split_mode_max_reqs;
#define SPLIT_MODE_5704_MAX_REQ 3 #define SPLIT_MODE_5704_MAX_REQ 3
......
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